Commit | Line | Data |
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85a7f0ac SAS |
1 | /* |
2 | * Support for Marvell's crypto engine which can be found on some Orion5X | |
3 | * boards. | |
4 | * | |
5 | * Author: Sebastian Andrzej Siewior < sebastian at breakpoint dot cc > | |
6 | * License: GPLv2 | |
7 | * | |
8 | */ | |
9 | #include <crypto/aes.h> | |
10 | #include <crypto/algapi.h> | |
11 | #include <linux/crypto.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/io.h> | |
14 | #include <linux/kthread.h> | |
15 | #include <linux/platform_device.h> | |
16 | #include <linux/scatterlist.h> | |
5a0e3ad6 | 17 | #include <linux/slab.h> |
4bb33cc8 | 18 | #include <linux/module.h> |
1f80b126 | 19 | #include <linux/clk.h> |
750052dd US |
20 | #include <crypto/internal/hash.h> |
21 | #include <crypto/sha.h> | |
85a7f0ac SAS |
22 | |
23 | #include "mv_cesa.h" | |
750052dd US |
24 | |
25 | #define MV_CESA "MV-CESA:" | |
26 | #define MAX_HW_HASH_SIZE 0xFFFF | |
27 | ||
85a7f0ac SAS |
28 | /* |
29 | * STM: | |
30 | * /---------------------------------------\ | |
31 | * | | request complete | |
32 | * \./ | | |
33 | * IDLE -> new request -> BUSY -> done -> DEQUEUE | |
34 | * /°\ | | |
35 | * | | more scatter entries | |
36 | * \________________/ | |
37 | */ | |
38 | enum engine_status { | |
39 | ENGINE_IDLE, | |
40 | ENGINE_BUSY, | |
41 | ENGINE_W_DEQUEUE, | |
42 | }; | |
43 | ||
44 | /** | |
45 | * struct req_progress - used for every crypt request | |
46 | * @src_sg_it: sg iterator for src | |
47 | * @dst_sg_it: sg iterator for dst | |
48 | * @sg_src_left: bytes left in src to process (scatter list) | |
49 | * @src_start: offset to add to src start position (scatter list) | |
750052dd | 50 | * @crypt_len: length of current hw crypt/hash process |
3b61a905 | 51 | * @hw_nbytes: total bytes to process in hw for this request |
f0d03dea | 52 | * @copy_back: whether to copy data back (crypt) or not (hash) |
85a7f0ac SAS |
53 | * @sg_dst_left: bytes left dst to process in this scatter list |
54 | * @dst_start: offset to add to dst start position (scatter list) | |
7a5f691e | 55 | * @hw_processed_bytes: number of bytes processed by hw (request). |
85a7f0ac SAS |
56 | * |
57 | * sg helper are used to iterate over the scatterlist. Since the size of the | |
58 | * SRAM may be less than the scatter size, this struct struct is used to keep | |
59 | * track of progress within current scatterlist. | |
60 | */ | |
61 | struct req_progress { | |
62 | struct sg_mapping_iter src_sg_it; | |
63 | struct sg_mapping_iter dst_sg_it; | |
a58094ac US |
64 | void (*complete) (void); |
65 | void (*process) (int is_first); | |
85a7f0ac SAS |
66 | |
67 | /* src mostly */ | |
68 | int sg_src_left; | |
69 | int src_start; | |
70 | int crypt_len; | |
3b61a905 | 71 | int hw_nbytes; |
85a7f0ac | 72 | /* dst mostly */ |
f0d03dea | 73 | int copy_back; |
85a7f0ac SAS |
74 | int sg_dst_left; |
75 | int dst_start; | |
7a5f691e | 76 | int hw_processed_bytes; |
85a7f0ac SAS |
77 | }; |
78 | ||
79 | struct crypto_priv { | |
80 | void __iomem *reg; | |
81 | void __iomem *sram; | |
82 | int irq; | |
1f80b126 | 83 | struct clk *clk; |
85a7f0ac SAS |
84 | struct task_struct *queue_th; |
85 | ||
86 | /* the lock protects queue and eng_st */ | |
87 | spinlock_t lock; | |
88 | struct crypto_queue queue; | |
89 | enum engine_status eng_st; | |
3b61a905 | 90 | struct crypto_async_request *cur_req; |
85a7f0ac SAS |
91 | struct req_progress p; |
92 | int max_req_size; | |
93 | int sram_size; | |
750052dd US |
94 | int has_sha1; |
95 | int has_hmac_sha1; | |
85a7f0ac SAS |
96 | }; |
97 | ||
98 | static struct crypto_priv *cpg; | |
99 | ||
100 | struct mv_ctx { | |
101 | u8 aes_enc_key[AES_KEY_LEN]; | |
102 | u32 aes_dec_key[8]; | |
103 | int key_len; | |
104 | u32 need_calc_aes_dkey; | |
105 | }; | |
106 | ||
107 | enum crypto_op { | |
108 | COP_AES_ECB, | |
109 | COP_AES_CBC, | |
110 | }; | |
111 | ||
112 | struct mv_req_ctx { | |
113 | enum crypto_op op; | |
114 | int decrypt; | |
115 | }; | |
116 | ||
750052dd US |
117 | enum hash_op { |
118 | COP_SHA1, | |
119 | COP_HMAC_SHA1 | |
120 | }; | |
121 | ||
122 | struct mv_tfm_hash_ctx { | |
123 | struct crypto_shash *fallback; | |
124 | struct crypto_shash *base_hash; | |
125 | u32 ivs[2 * SHA1_DIGEST_SIZE / 4]; | |
126 | int count_add; | |
127 | enum hash_op op; | |
128 | }; | |
129 | ||
130 | struct mv_req_hash_ctx { | |
131 | u64 count; | |
132 | u32 state[SHA1_DIGEST_SIZE / 4]; | |
133 | u8 buffer[SHA1_BLOCK_SIZE]; | |
134 | int first_hash; /* marks that we don't have previous state */ | |
135 | int last_chunk; /* marks that this is the 'final' request */ | |
136 | int extra_bytes; /* unprocessed bytes in buffer */ | |
137 | enum hash_op op; | |
138 | int count_add; | |
750052dd US |
139 | }; |
140 | ||
85a7f0ac SAS |
141 | static void compute_aes_dec_key(struct mv_ctx *ctx) |
142 | { | |
143 | struct crypto_aes_ctx gen_aes_key; | |
144 | int key_pos; | |
145 | ||
146 | if (!ctx->need_calc_aes_dkey) | |
147 | return; | |
148 | ||
149 | crypto_aes_expand_key(&gen_aes_key, ctx->aes_enc_key, ctx->key_len); | |
150 | ||
151 | key_pos = ctx->key_len + 24; | |
152 | memcpy(ctx->aes_dec_key, &gen_aes_key.key_enc[key_pos], 4 * 4); | |
153 | switch (ctx->key_len) { | |
154 | case AES_KEYSIZE_256: | |
155 | key_pos -= 2; | |
156 | /* fall */ | |
157 | case AES_KEYSIZE_192: | |
158 | key_pos -= 2; | |
159 | memcpy(&ctx->aes_dec_key[4], &gen_aes_key.key_enc[key_pos], | |
160 | 4 * 4); | |
161 | break; | |
162 | } | |
163 | ctx->need_calc_aes_dkey = 0; | |
164 | } | |
165 | ||
166 | static int mv_setkey_aes(struct crypto_ablkcipher *cipher, const u8 *key, | |
167 | unsigned int len) | |
168 | { | |
169 | struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher); | |
170 | struct mv_ctx *ctx = crypto_tfm_ctx(tfm); | |
171 | ||
172 | switch (len) { | |
173 | case AES_KEYSIZE_128: | |
174 | case AES_KEYSIZE_192: | |
175 | case AES_KEYSIZE_256: | |
176 | break; | |
177 | default: | |
178 | crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN); | |
179 | return -EINVAL; | |
180 | } | |
181 | ctx->key_len = len; | |
182 | ctx->need_calc_aes_dkey = 1; | |
183 | ||
184 | memcpy(ctx->aes_enc_key, key, AES_KEY_LEN); | |
185 | return 0; | |
186 | } | |
187 | ||
15d4dd35 | 188 | static void copy_src_to_buf(struct req_progress *p, char *dbuf, int len) |
85a7f0ac SAS |
189 | { |
190 | int ret; | |
15d4dd35 | 191 | void *sbuf; |
6677a776 | 192 | int copy_len; |
85a7f0ac | 193 | |
6677a776 | 194 | while (len) { |
15d4dd35 US |
195 | if (!p->sg_src_left) { |
196 | ret = sg_miter_next(&p->src_sg_it); | |
197 | BUG_ON(!ret); | |
198 | p->sg_src_left = p->src_sg_it.length; | |
199 | p->src_start = 0; | |
200 | } | |
85a7f0ac | 201 | |
15d4dd35 US |
202 | sbuf = p->src_sg_it.addr + p->src_start; |
203 | ||
6677a776 PS |
204 | copy_len = min(p->sg_src_left, len); |
205 | memcpy(dbuf, sbuf, copy_len); | |
206 | ||
207 | p->src_start += copy_len; | |
208 | p->sg_src_left -= copy_len; | |
209 | ||
210 | len -= copy_len; | |
211 | dbuf += copy_len; | |
15d4dd35 US |
212 | } |
213 | } | |
85a7f0ac | 214 | |
3b61a905 | 215 | static void setup_data_in(void) |
15d4dd35 US |
216 | { |
217 | struct req_progress *p = &cpg->p; | |
0c5c6c4b | 218 | int data_in_sram = |
7a5f691e | 219 | min(p->hw_nbytes - p->hw_processed_bytes, cpg->max_req_size); |
0c5c6c4b US |
220 | copy_src_to_buf(p, cpg->sram + SRAM_DATA_IN_START + p->crypt_len, |
221 | data_in_sram - p->crypt_len); | |
222 | p->crypt_len = data_in_sram; | |
85a7f0ac SAS |
223 | } |
224 | ||
225 | static void mv_process_current_q(int first_block) | |
226 | { | |
3b61a905 | 227 | struct ablkcipher_request *req = ablkcipher_request_cast(cpg->cur_req); |
85a7f0ac SAS |
228 | struct mv_ctx *ctx = crypto_tfm_ctx(req->base.tfm); |
229 | struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req); | |
230 | struct sec_accel_config op; | |
231 | ||
232 | switch (req_ctx->op) { | |
233 | case COP_AES_ECB: | |
234 | op.config = CFG_OP_CRYPT_ONLY | CFG_ENCM_AES | CFG_ENC_MODE_ECB; | |
235 | break; | |
236 | case COP_AES_CBC: | |
6bc6fcd6 | 237 | default: |
85a7f0ac SAS |
238 | op.config = CFG_OP_CRYPT_ONLY | CFG_ENCM_AES | CFG_ENC_MODE_CBC; |
239 | op.enc_iv = ENC_IV_POINT(SRAM_DATA_IV) | | |
240 | ENC_IV_BUF_POINT(SRAM_DATA_IV_BUF); | |
241 | if (first_block) | |
242 | memcpy(cpg->sram + SRAM_DATA_IV, req->info, 16); | |
243 | break; | |
244 | } | |
245 | if (req_ctx->decrypt) { | |
246 | op.config |= CFG_DIR_DEC; | |
247 | memcpy(cpg->sram + SRAM_DATA_KEY_P, ctx->aes_dec_key, | |
248 | AES_KEY_LEN); | |
249 | } else { | |
250 | op.config |= CFG_DIR_ENC; | |
251 | memcpy(cpg->sram + SRAM_DATA_KEY_P, ctx->aes_enc_key, | |
252 | AES_KEY_LEN); | |
253 | } | |
254 | ||
255 | switch (ctx->key_len) { | |
256 | case AES_KEYSIZE_128: | |
257 | op.config |= CFG_AES_LEN_128; | |
258 | break; | |
259 | case AES_KEYSIZE_192: | |
260 | op.config |= CFG_AES_LEN_192; | |
261 | break; | |
262 | case AES_KEYSIZE_256: | |
263 | op.config |= CFG_AES_LEN_256; | |
264 | break; | |
265 | } | |
266 | op.enc_p = ENC_P_SRC(SRAM_DATA_IN_START) | | |
267 | ENC_P_DST(SRAM_DATA_OUT_START); | |
268 | op.enc_key_p = SRAM_DATA_KEY_P; | |
269 | ||
3b61a905 | 270 | setup_data_in(); |
85a7f0ac SAS |
271 | op.enc_len = cpg->p.crypt_len; |
272 | memcpy(cpg->sram + SRAM_CONFIG, &op, | |
273 | sizeof(struct sec_accel_config)); | |
274 | ||
85a7f0ac SAS |
275 | /* GO */ |
276 | writel(SEC_CMD_EN_SEC_ACCL0, cpg->reg + SEC_ACCEL_CMD); | |
277 | ||
278 | /* | |
279 | * XXX: add timer if the interrupt does not occur for some mystery | |
280 | * reason | |
281 | */ | |
282 | } | |
283 | ||
284 | static void mv_crypto_algo_completion(void) | |
285 | { | |
3b61a905 | 286 | struct ablkcipher_request *req = ablkcipher_request_cast(cpg->cur_req); |
85a7f0ac SAS |
287 | struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req); |
288 | ||
a58094ac US |
289 | sg_miter_stop(&cpg->p.src_sg_it); |
290 | sg_miter_stop(&cpg->p.dst_sg_it); | |
291 | ||
85a7f0ac SAS |
292 | if (req_ctx->op != COP_AES_CBC) |
293 | return ; | |
294 | ||
295 | memcpy(req->info, cpg->sram + SRAM_DATA_IV_BUF, 16); | |
296 | } | |
297 | ||
750052dd US |
298 | static void mv_process_hash_current(int first_block) |
299 | { | |
300 | struct ahash_request *req = ahash_request_cast(cpg->cur_req); | |
cc8d3505 | 301 | const struct mv_tfm_hash_ctx *tfm_ctx = crypto_tfm_ctx(req->base.tfm); |
750052dd US |
302 | struct mv_req_hash_ctx *req_ctx = ahash_request_ctx(req); |
303 | struct req_progress *p = &cpg->p; | |
304 | struct sec_accel_config op = { 0 }; | |
305 | int is_last; | |
306 | ||
307 | switch (req_ctx->op) { | |
308 | case COP_SHA1: | |
309 | default: | |
310 | op.config = CFG_OP_MAC_ONLY | CFG_MACM_SHA1; | |
311 | break; | |
312 | case COP_HMAC_SHA1: | |
313 | op.config = CFG_OP_MAC_ONLY | CFG_MACM_HMAC_SHA1; | |
cc8d3505 PS |
314 | memcpy(cpg->sram + SRAM_HMAC_IV_IN, |
315 | tfm_ctx->ivs, sizeof(tfm_ctx->ivs)); | |
750052dd US |
316 | break; |
317 | } | |
318 | ||
319 | op.mac_src_p = | |
320 | MAC_SRC_DATA_P(SRAM_DATA_IN_START) | MAC_SRC_TOTAL_LEN((u32) | |
321 | req_ctx-> | |
322 | count); | |
323 | ||
324 | setup_data_in(); | |
325 | ||
326 | op.mac_digest = | |
327 | MAC_DIGEST_P(SRAM_DIGEST_BUF) | MAC_FRAG_LEN(p->crypt_len); | |
328 | op.mac_iv = | |
329 | MAC_INNER_IV_P(SRAM_HMAC_IV_IN) | | |
330 | MAC_OUTER_IV_P(SRAM_HMAC_IV_OUT); | |
331 | ||
332 | is_last = req_ctx->last_chunk | |
333 | && (p->hw_processed_bytes + p->crypt_len >= p->hw_nbytes) | |
334 | && (req_ctx->count <= MAX_HW_HASH_SIZE); | |
335 | if (req_ctx->first_hash) { | |
336 | if (is_last) | |
337 | op.config |= CFG_NOT_FRAG; | |
338 | else | |
339 | op.config |= CFG_FIRST_FRAG; | |
340 | ||
341 | req_ctx->first_hash = 0; | |
342 | } else { | |
343 | if (is_last) | |
344 | op.config |= CFG_LAST_FRAG; | |
345 | else | |
346 | op.config |= CFG_MID_FRAG; | |
86523487 | 347 | |
27425286 PS |
348 | if (first_block) { |
349 | writel(req_ctx->state[0], cpg->reg + DIGEST_INITIAL_VAL_A); | |
350 | writel(req_ctx->state[1], cpg->reg + DIGEST_INITIAL_VAL_B); | |
351 | writel(req_ctx->state[2], cpg->reg + DIGEST_INITIAL_VAL_C); | |
352 | writel(req_ctx->state[3], cpg->reg + DIGEST_INITIAL_VAL_D); | |
353 | writel(req_ctx->state[4], cpg->reg + DIGEST_INITIAL_VAL_E); | |
354 | } | |
750052dd US |
355 | } |
356 | ||
357 | memcpy(cpg->sram + SRAM_CONFIG, &op, sizeof(struct sec_accel_config)); | |
358 | ||
750052dd US |
359 | /* GO */ |
360 | writel(SEC_CMD_EN_SEC_ACCL0, cpg->reg + SEC_ACCEL_CMD); | |
361 | ||
362 | /* | |
363 | * XXX: add timer if the interrupt does not occur for some mystery | |
364 | * reason | |
365 | */ | |
366 | } | |
367 | ||
368 | static inline int mv_hash_import_sha1_ctx(const struct mv_req_hash_ctx *ctx, | |
369 | struct shash_desc *desc) | |
370 | { | |
371 | int i; | |
372 | struct sha1_state shash_state; | |
373 | ||
374 | shash_state.count = ctx->count + ctx->count_add; | |
375 | for (i = 0; i < 5; i++) | |
376 | shash_state.state[i] = ctx->state[i]; | |
377 | memcpy(shash_state.buffer, ctx->buffer, sizeof(shash_state.buffer)); | |
378 | return crypto_shash_import(desc, &shash_state); | |
379 | } | |
380 | ||
381 | static int mv_hash_final_fallback(struct ahash_request *req) | |
382 | { | |
383 | const struct mv_tfm_hash_ctx *tfm_ctx = crypto_tfm_ctx(req->base.tfm); | |
384 | struct mv_req_hash_ctx *req_ctx = ahash_request_ctx(req); | |
385 | struct { | |
386 | struct shash_desc shash; | |
387 | char ctx[crypto_shash_descsize(tfm_ctx->fallback)]; | |
388 | } desc; | |
389 | int rc; | |
390 | ||
391 | desc.shash.tfm = tfm_ctx->fallback; | |
392 | desc.shash.flags = CRYPTO_TFM_REQ_MAY_SLEEP; | |
393 | if (unlikely(req_ctx->first_hash)) { | |
394 | crypto_shash_init(&desc.shash); | |
395 | crypto_shash_update(&desc.shash, req_ctx->buffer, | |
396 | req_ctx->extra_bytes); | |
397 | } else { | |
398 | /* only SHA1 for now.... | |
399 | */ | |
400 | rc = mv_hash_import_sha1_ctx(req_ctx, &desc.shash); | |
401 | if (rc) | |
402 | goto out; | |
403 | } | |
404 | rc = crypto_shash_final(&desc.shash, req->result); | |
405 | out: | |
406 | return rc; | |
407 | } | |
408 | ||
409 | static void mv_hash_algo_completion(void) | |
410 | { | |
411 | struct ahash_request *req = ahash_request_cast(cpg->cur_req); | |
412 | struct mv_req_hash_ctx *ctx = ahash_request_ctx(req); | |
413 | ||
414 | if (ctx->extra_bytes) | |
415 | copy_src_to_buf(&cpg->p, ctx->buffer, ctx->extra_bytes); | |
416 | sg_miter_stop(&cpg->p.src_sg_it); | |
417 | ||
750052dd US |
418 | if (likely(ctx->last_chunk)) { |
419 | if (likely(ctx->count <= MAX_HW_HASH_SIZE)) { | |
420 | memcpy(req->result, cpg->sram + SRAM_DIGEST_BUF, | |
421 | crypto_ahash_digestsize(crypto_ahash_reqtfm | |
422 | (req))); | |
423 | } else | |
424 | mv_hash_final_fallback(req); | |
7a1c6bcf PS |
425 | } else { |
426 | ctx->state[0] = readl(cpg->reg + DIGEST_INITIAL_VAL_A); | |
427 | ctx->state[1] = readl(cpg->reg + DIGEST_INITIAL_VAL_B); | |
428 | ctx->state[2] = readl(cpg->reg + DIGEST_INITIAL_VAL_C); | |
429 | ctx->state[3] = readl(cpg->reg + DIGEST_INITIAL_VAL_D); | |
430 | ctx->state[4] = readl(cpg->reg + DIGEST_INITIAL_VAL_E); | |
750052dd US |
431 | } |
432 | } | |
433 | ||
85a7f0ac SAS |
434 | static void dequeue_complete_req(void) |
435 | { | |
3b61a905 | 436 | struct crypto_async_request *req = cpg->cur_req; |
85a7f0ac SAS |
437 | void *buf; |
438 | int ret; | |
7a5f691e | 439 | cpg->p.hw_processed_bytes += cpg->p.crypt_len; |
f0d03dea US |
440 | if (cpg->p.copy_back) { |
441 | int need_copy_len = cpg->p.crypt_len; | |
442 | int sram_offset = 0; | |
443 | do { | |
444 | int dst_copy; | |
445 | ||
446 | if (!cpg->p.sg_dst_left) { | |
447 | ret = sg_miter_next(&cpg->p.dst_sg_it); | |
448 | BUG_ON(!ret); | |
449 | cpg->p.sg_dst_left = cpg->p.dst_sg_it.length; | |
450 | cpg->p.dst_start = 0; | |
451 | } | |
452 | ||
453 | buf = cpg->p.dst_sg_it.addr; | |
454 | buf += cpg->p.dst_start; | |
455 | ||
456 | dst_copy = min(need_copy_len, cpg->p.sg_dst_left); | |
457 | ||
458 | memcpy(buf, | |
459 | cpg->sram + SRAM_DATA_OUT_START + sram_offset, | |
460 | dst_copy); | |
461 | sram_offset += dst_copy; | |
462 | cpg->p.sg_dst_left -= dst_copy; | |
463 | need_copy_len -= dst_copy; | |
464 | cpg->p.dst_start += dst_copy; | |
465 | } while (need_copy_len > 0); | |
466 | } | |
85a7f0ac | 467 | |
0c5c6c4b | 468 | cpg->p.crypt_len = 0; |
85a7f0ac SAS |
469 | |
470 | BUG_ON(cpg->eng_st != ENGINE_W_DEQUEUE); | |
7a5f691e | 471 | if (cpg->p.hw_processed_bytes < cpg->p.hw_nbytes) { |
85a7f0ac SAS |
472 | /* process next scatter list entry */ |
473 | cpg->eng_st = ENGINE_BUSY; | |
a58094ac | 474 | cpg->p.process(0); |
85a7f0ac | 475 | } else { |
a58094ac | 476 | cpg->p.complete(); |
85a7f0ac | 477 | cpg->eng_st = ENGINE_IDLE; |
0328ac26 | 478 | local_bh_disable(); |
3b61a905 | 479 | req->complete(req, 0); |
0328ac26 | 480 | local_bh_enable(); |
85a7f0ac SAS |
481 | } |
482 | } | |
483 | ||
484 | static int count_sgs(struct scatterlist *sl, unsigned int total_bytes) | |
485 | { | |
486 | int i = 0; | |
15d4dd35 US |
487 | size_t cur_len; |
488 | ||
6ef84509 | 489 | while (sl) { |
15d4dd35 US |
490 | cur_len = sl[i].length; |
491 | ++i; | |
492 | if (total_bytes > cur_len) | |
493 | total_bytes -= cur_len; | |
494 | else | |
495 | break; | |
496 | } | |
85a7f0ac SAS |
497 | |
498 | return i; | |
499 | } | |
500 | ||
750052dd | 501 | static void mv_start_new_crypt_req(struct ablkcipher_request *req) |
85a7f0ac | 502 | { |
3b61a905 | 503 | struct req_progress *p = &cpg->p; |
85a7f0ac SAS |
504 | int num_sgs; |
505 | ||
3b61a905 US |
506 | cpg->cur_req = &req->base; |
507 | memset(p, 0, sizeof(struct req_progress)); | |
508 | p->hw_nbytes = req->nbytes; | |
a58094ac US |
509 | p->complete = mv_crypto_algo_completion; |
510 | p->process = mv_process_current_q; | |
f0d03dea | 511 | p->copy_back = 1; |
85a7f0ac SAS |
512 | |
513 | num_sgs = count_sgs(req->src, req->nbytes); | |
3b61a905 | 514 | sg_miter_start(&p->src_sg_it, req->src, num_sgs, SG_MITER_FROM_SG); |
85a7f0ac SAS |
515 | |
516 | num_sgs = count_sgs(req->dst, req->nbytes); | |
3b61a905 US |
517 | sg_miter_start(&p->dst_sg_it, req->dst, num_sgs, SG_MITER_TO_SG); |
518 | ||
85a7f0ac SAS |
519 | mv_process_current_q(1); |
520 | } | |
521 | ||
750052dd US |
522 | static void mv_start_new_hash_req(struct ahash_request *req) |
523 | { | |
524 | struct req_progress *p = &cpg->p; | |
525 | struct mv_req_hash_ctx *ctx = ahash_request_ctx(req); | |
750052dd US |
526 | int num_sgs, hw_bytes, old_extra_bytes, rc; |
527 | cpg->cur_req = &req->base; | |
528 | memset(p, 0, sizeof(struct req_progress)); | |
529 | hw_bytes = req->nbytes + ctx->extra_bytes; | |
530 | old_extra_bytes = ctx->extra_bytes; | |
531 | ||
750052dd US |
532 | ctx->extra_bytes = hw_bytes % SHA1_BLOCK_SIZE; |
533 | if (ctx->extra_bytes != 0 | |
534 | && (!ctx->last_chunk || ctx->count > MAX_HW_HASH_SIZE)) | |
535 | hw_bytes -= ctx->extra_bytes; | |
536 | else | |
537 | ctx->extra_bytes = 0; | |
538 | ||
539 | num_sgs = count_sgs(req->src, req->nbytes); | |
540 | sg_miter_start(&p->src_sg_it, req->src, num_sgs, SG_MITER_FROM_SG); | |
541 | ||
542 | if (hw_bytes) { | |
543 | p->hw_nbytes = hw_bytes; | |
544 | p->complete = mv_hash_algo_completion; | |
545 | p->process = mv_process_hash_current; | |
546 | ||
7759995c PS |
547 | if (unlikely(old_extra_bytes)) { |
548 | memcpy(cpg->sram + SRAM_DATA_IN_START, ctx->buffer, | |
549 | old_extra_bytes); | |
550 | p->crypt_len = old_extra_bytes; | |
551 | } | |
552 | ||
750052dd US |
553 | mv_process_hash_current(1); |
554 | } else { | |
555 | copy_src_to_buf(p, ctx->buffer + old_extra_bytes, | |
556 | ctx->extra_bytes - old_extra_bytes); | |
557 | sg_miter_stop(&p->src_sg_it); | |
558 | if (ctx->last_chunk) | |
559 | rc = mv_hash_final_fallback(req); | |
560 | else | |
561 | rc = 0; | |
562 | cpg->eng_st = ENGINE_IDLE; | |
563 | local_bh_disable(); | |
564 | req->base.complete(&req->base, rc); | |
565 | local_bh_enable(); | |
566 | } | |
567 | } | |
568 | ||
85a7f0ac SAS |
569 | static int queue_manag(void *data) |
570 | { | |
571 | cpg->eng_st = ENGINE_IDLE; | |
572 | do { | |
85a7f0ac SAS |
573 | struct crypto_async_request *async_req = NULL; |
574 | struct crypto_async_request *backlog; | |
575 | ||
576 | __set_current_state(TASK_INTERRUPTIBLE); | |
577 | ||
578 | if (cpg->eng_st == ENGINE_W_DEQUEUE) | |
579 | dequeue_complete_req(); | |
580 | ||
581 | spin_lock_irq(&cpg->lock); | |
582 | if (cpg->eng_st == ENGINE_IDLE) { | |
583 | backlog = crypto_get_backlog(&cpg->queue); | |
584 | async_req = crypto_dequeue_request(&cpg->queue); | |
585 | if (async_req) { | |
586 | BUG_ON(cpg->eng_st != ENGINE_IDLE); | |
587 | cpg->eng_st = ENGINE_BUSY; | |
588 | } | |
589 | } | |
590 | spin_unlock_irq(&cpg->lock); | |
591 | ||
592 | if (backlog) { | |
593 | backlog->complete(backlog, -EINPROGRESS); | |
594 | backlog = NULL; | |
595 | } | |
596 | ||
597 | if (async_req) { | |
750052dd US |
598 | if (async_req->tfm->__crt_alg->cra_type != |
599 | &crypto_ahash_type) { | |
600 | struct ablkcipher_request *req = | |
042e9e73 | 601 | ablkcipher_request_cast(async_req); |
750052dd US |
602 | mv_start_new_crypt_req(req); |
603 | } else { | |
604 | struct ahash_request *req = | |
605 | ahash_request_cast(async_req); | |
606 | mv_start_new_hash_req(req); | |
607 | } | |
85a7f0ac SAS |
608 | async_req = NULL; |
609 | } | |
610 | ||
611 | schedule(); | |
612 | ||
613 | } while (!kthread_should_stop()); | |
614 | return 0; | |
615 | } | |
616 | ||
3b61a905 | 617 | static int mv_handle_req(struct crypto_async_request *req) |
85a7f0ac SAS |
618 | { |
619 | unsigned long flags; | |
620 | int ret; | |
621 | ||
622 | spin_lock_irqsave(&cpg->lock, flags); | |
3b61a905 | 623 | ret = crypto_enqueue_request(&cpg->queue, req); |
85a7f0ac SAS |
624 | spin_unlock_irqrestore(&cpg->lock, flags); |
625 | wake_up_process(cpg->queue_th); | |
626 | return ret; | |
627 | } | |
628 | ||
629 | static int mv_enc_aes_ecb(struct ablkcipher_request *req) | |
630 | { | |
631 | struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req); | |
632 | ||
633 | req_ctx->op = COP_AES_ECB; | |
634 | req_ctx->decrypt = 0; | |
635 | ||
3b61a905 | 636 | return mv_handle_req(&req->base); |
85a7f0ac SAS |
637 | } |
638 | ||
639 | static int mv_dec_aes_ecb(struct ablkcipher_request *req) | |
640 | { | |
641 | struct mv_ctx *ctx = crypto_tfm_ctx(req->base.tfm); | |
642 | struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req); | |
643 | ||
644 | req_ctx->op = COP_AES_ECB; | |
645 | req_ctx->decrypt = 1; | |
646 | ||
647 | compute_aes_dec_key(ctx); | |
3b61a905 | 648 | return mv_handle_req(&req->base); |
85a7f0ac SAS |
649 | } |
650 | ||
651 | static int mv_enc_aes_cbc(struct ablkcipher_request *req) | |
652 | { | |
653 | struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req); | |
654 | ||
655 | req_ctx->op = COP_AES_CBC; | |
656 | req_ctx->decrypt = 0; | |
657 | ||
3b61a905 | 658 | return mv_handle_req(&req->base); |
85a7f0ac SAS |
659 | } |
660 | ||
661 | static int mv_dec_aes_cbc(struct ablkcipher_request *req) | |
662 | { | |
663 | struct mv_ctx *ctx = crypto_tfm_ctx(req->base.tfm); | |
664 | struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req); | |
665 | ||
666 | req_ctx->op = COP_AES_CBC; | |
667 | req_ctx->decrypt = 1; | |
668 | ||
669 | compute_aes_dec_key(ctx); | |
3b61a905 | 670 | return mv_handle_req(&req->base); |
85a7f0ac SAS |
671 | } |
672 | ||
673 | static int mv_cra_init(struct crypto_tfm *tfm) | |
674 | { | |
675 | tfm->crt_ablkcipher.reqsize = sizeof(struct mv_req_ctx); | |
676 | return 0; | |
677 | } | |
678 | ||
750052dd US |
679 | static void mv_init_hash_req_ctx(struct mv_req_hash_ctx *ctx, int op, |
680 | int is_last, unsigned int req_len, | |
681 | int count_add) | |
682 | { | |
683 | memset(ctx, 0, sizeof(*ctx)); | |
684 | ctx->op = op; | |
685 | ctx->count = req_len; | |
686 | ctx->first_hash = 1; | |
687 | ctx->last_chunk = is_last; | |
688 | ctx->count_add = count_add; | |
689 | } | |
690 | ||
691 | static void mv_update_hash_req_ctx(struct mv_req_hash_ctx *ctx, int is_last, | |
692 | unsigned req_len) | |
693 | { | |
694 | ctx->last_chunk = is_last; | |
695 | ctx->count += req_len; | |
696 | } | |
697 | ||
698 | static int mv_hash_init(struct ahash_request *req) | |
699 | { | |
700 | const struct mv_tfm_hash_ctx *tfm_ctx = crypto_tfm_ctx(req->base.tfm); | |
701 | mv_init_hash_req_ctx(ahash_request_ctx(req), tfm_ctx->op, 0, 0, | |
702 | tfm_ctx->count_add); | |
703 | return 0; | |
704 | } | |
705 | ||
706 | static int mv_hash_update(struct ahash_request *req) | |
707 | { | |
708 | if (!req->nbytes) | |
709 | return 0; | |
710 | ||
711 | mv_update_hash_req_ctx(ahash_request_ctx(req), 0, req->nbytes); | |
712 | return mv_handle_req(&req->base); | |
713 | } | |
714 | ||
715 | static int mv_hash_final(struct ahash_request *req) | |
716 | { | |
717 | struct mv_req_hash_ctx *ctx = ahash_request_ctx(req); | |
6ef84509 | 718 | |
f8f54e19 | 719 | ahash_request_set_crypt(req, NULL, req->result, 0); |
750052dd US |
720 | mv_update_hash_req_ctx(ctx, 1, 0); |
721 | return mv_handle_req(&req->base); | |
722 | } | |
723 | ||
724 | static int mv_hash_finup(struct ahash_request *req) | |
725 | { | |
750052dd US |
726 | mv_update_hash_req_ctx(ahash_request_ctx(req), 1, req->nbytes); |
727 | return mv_handle_req(&req->base); | |
728 | } | |
729 | ||
730 | static int mv_hash_digest(struct ahash_request *req) | |
731 | { | |
732 | const struct mv_tfm_hash_ctx *tfm_ctx = crypto_tfm_ctx(req->base.tfm); | |
733 | mv_init_hash_req_ctx(ahash_request_ctx(req), tfm_ctx->op, 1, | |
734 | req->nbytes, tfm_ctx->count_add); | |
735 | return mv_handle_req(&req->base); | |
736 | } | |
737 | ||
738 | static void mv_hash_init_ivs(struct mv_tfm_hash_ctx *ctx, const void *istate, | |
739 | const void *ostate) | |
740 | { | |
741 | const struct sha1_state *isha1_state = istate, *osha1_state = ostate; | |
742 | int i; | |
743 | for (i = 0; i < 5; i++) { | |
744 | ctx->ivs[i] = cpu_to_be32(isha1_state->state[i]); | |
745 | ctx->ivs[i + 5] = cpu_to_be32(osha1_state->state[i]); | |
746 | } | |
747 | } | |
748 | ||
749 | static int mv_hash_setkey(struct crypto_ahash *tfm, const u8 * key, | |
750 | unsigned int keylen) | |
751 | { | |
752 | int rc; | |
753 | struct mv_tfm_hash_ctx *ctx = crypto_tfm_ctx(&tfm->base); | |
754 | int bs, ds, ss; | |
755 | ||
756 | if (!ctx->base_hash) | |
757 | return 0; | |
758 | ||
759 | rc = crypto_shash_setkey(ctx->fallback, key, keylen); | |
760 | if (rc) | |
761 | return rc; | |
762 | ||
763 | /* Can't see a way to extract the ipad/opad from the fallback tfm | |
764 | so I'm basically copying code from the hmac module */ | |
765 | bs = crypto_shash_blocksize(ctx->base_hash); | |
766 | ds = crypto_shash_digestsize(ctx->base_hash); | |
767 | ss = crypto_shash_statesize(ctx->base_hash); | |
768 | ||
769 | { | |
770 | struct { | |
771 | struct shash_desc shash; | |
772 | char ctx[crypto_shash_descsize(ctx->base_hash)]; | |
773 | } desc; | |
774 | unsigned int i; | |
775 | char ipad[ss]; | |
776 | char opad[ss]; | |
777 | ||
778 | desc.shash.tfm = ctx->base_hash; | |
779 | desc.shash.flags = crypto_shash_get_flags(ctx->base_hash) & | |
780 | CRYPTO_TFM_REQ_MAY_SLEEP; | |
781 | ||
782 | if (keylen > bs) { | |
783 | int err; | |
784 | ||
785 | err = | |
786 | crypto_shash_digest(&desc.shash, key, keylen, ipad); | |
787 | if (err) | |
788 | return err; | |
789 | ||
790 | keylen = ds; | |
791 | } else | |
792 | memcpy(ipad, key, keylen); | |
793 | ||
794 | memset(ipad + keylen, 0, bs - keylen); | |
795 | memcpy(opad, ipad, bs); | |
796 | ||
797 | for (i = 0; i < bs; i++) { | |
798 | ipad[i] ^= 0x36; | |
799 | opad[i] ^= 0x5c; | |
800 | } | |
801 | ||
802 | rc = crypto_shash_init(&desc.shash) ? : | |
803 | crypto_shash_update(&desc.shash, ipad, bs) ? : | |
804 | crypto_shash_export(&desc.shash, ipad) ? : | |
805 | crypto_shash_init(&desc.shash) ? : | |
806 | crypto_shash_update(&desc.shash, opad, bs) ? : | |
807 | crypto_shash_export(&desc.shash, opad); | |
808 | ||
809 | if (rc == 0) | |
810 | mv_hash_init_ivs(ctx, ipad, opad); | |
811 | ||
812 | return rc; | |
813 | } | |
814 | } | |
815 | ||
816 | static int mv_cra_hash_init(struct crypto_tfm *tfm, const char *base_hash_name, | |
817 | enum hash_op op, int count_add) | |
818 | { | |
819 | const char *fallback_driver_name = tfm->__crt_alg->cra_name; | |
820 | struct mv_tfm_hash_ctx *ctx = crypto_tfm_ctx(tfm); | |
821 | struct crypto_shash *fallback_tfm = NULL; | |
822 | struct crypto_shash *base_hash = NULL; | |
823 | int err = -ENOMEM; | |
824 | ||
825 | ctx->op = op; | |
826 | ctx->count_add = count_add; | |
827 | ||
828 | /* Allocate a fallback and abort if it failed. */ | |
829 | fallback_tfm = crypto_alloc_shash(fallback_driver_name, 0, | |
830 | CRYPTO_ALG_NEED_FALLBACK); | |
831 | if (IS_ERR(fallback_tfm)) { | |
832 | printk(KERN_WARNING MV_CESA | |
833 | "Fallback driver '%s' could not be loaded!\n", | |
834 | fallback_driver_name); | |
835 | err = PTR_ERR(fallback_tfm); | |
836 | goto out; | |
837 | } | |
838 | ctx->fallback = fallback_tfm; | |
839 | ||
840 | if (base_hash_name) { | |
841 | /* Allocate a hash to compute the ipad/opad of hmac. */ | |
842 | base_hash = crypto_alloc_shash(base_hash_name, 0, | |
843 | CRYPTO_ALG_NEED_FALLBACK); | |
844 | if (IS_ERR(base_hash)) { | |
845 | printk(KERN_WARNING MV_CESA | |
846 | "Base driver '%s' could not be loaded!\n", | |
847 | base_hash_name); | |
41f2977d | 848 | err = PTR_ERR(base_hash); |
750052dd US |
849 | goto err_bad_base; |
850 | } | |
851 | } | |
852 | ctx->base_hash = base_hash; | |
853 | ||
854 | crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), | |
855 | sizeof(struct mv_req_hash_ctx) + | |
856 | crypto_shash_descsize(ctx->fallback)); | |
857 | return 0; | |
858 | err_bad_base: | |
859 | crypto_free_shash(fallback_tfm); | |
860 | out: | |
861 | return err; | |
862 | } | |
863 | ||
864 | static void mv_cra_hash_exit(struct crypto_tfm *tfm) | |
865 | { | |
866 | struct mv_tfm_hash_ctx *ctx = crypto_tfm_ctx(tfm); | |
867 | ||
868 | crypto_free_shash(ctx->fallback); | |
869 | if (ctx->base_hash) | |
870 | crypto_free_shash(ctx->base_hash); | |
871 | } | |
872 | ||
873 | static int mv_cra_hash_sha1_init(struct crypto_tfm *tfm) | |
874 | { | |
875 | return mv_cra_hash_init(tfm, NULL, COP_SHA1, 0); | |
876 | } | |
877 | ||
878 | static int mv_cra_hash_hmac_sha1_init(struct crypto_tfm *tfm) | |
879 | { | |
880 | return mv_cra_hash_init(tfm, "sha1", COP_HMAC_SHA1, SHA1_BLOCK_SIZE); | |
881 | } | |
882 | ||
85a7f0ac SAS |
883 | irqreturn_t crypto_int(int irq, void *priv) |
884 | { | |
885 | u32 val; | |
886 | ||
887 | val = readl(cpg->reg + SEC_ACCEL_INT_STATUS); | |
888 | if (!(val & SEC_INT_ACCEL0_DONE)) | |
889 | return IRQ_NONE; | |
890 | ||
891 | val &= ~SEC_INT_ACCEL0_DONE; | |
892 | writel(val, cpg->reg + FPGA_INT_STATUS); | |
893 | writel(val, cpg->reg + SEC_ACCEL_INT_STATUS); | |
894 | BUG_ON(cpg->eng_st != ENGINE_BUSY); | |
895 | cpg->eng_st = ENGINE_W_DEQUEUE; | |
896 | wake_up_process(cpg->queue_th); | |
897 | return IRQ_HANDLED; | |
898 | } | |
899 | ||
900 | struct crypto_alg mv_aes_alg_ecb = { | |
901 | .cra_name = "ecb(aes)", | |
902 | .cra_driver_name = "mv-ecb-aes", | |
903 | .cra_priority = 300, | |
d912bb76 NM |
904 | .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | |
905 | CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC, | |
85a7f0ac SAS |
906 | .cra_blocksize = 16, |
907 | .cra_ctxsize = sizeof(struct mv_ctx), | |
908 | .cra_alignmask = 0, | |
909 | .cra_type = &crypto_ablkcipher_type, | |
910 | .cra_module = THIS_MODULE, | |
911 | .cra_init = mv_cra_init, | |
912 | .cra_u = { | |
913 | .ablkcipher = { | |
914 | .min_keysize = AES_MIN_KEY_SIZE, | |
915 | .max_keysize = AES_MAX_KEY_SIZE, | |
916 | .setkey = mv_setkey_aes, | |
917 | .encrypt = mv_enc_aes_ecb, | |
918 | .decrypt = mv_dec_aes_ecb, | |
919 | }, | |
920 | }, | |
921 | }; | |
922 | ||
923 | struct crypto_alg mv_aes_alg_cbc = { | |
924 | .cra_name = "cbc(aes)", | |
925 | .cra_driver_name = "mv-cbc-aes", | |
926 | .cra_priority = 300, | |
d912bb76 NM |
927 | .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | |
928 | CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC, | |
85a7f0ac SAS |
929 | .cra_blocksize = AES_BLOCK_SIZE, |
930 | .cra_ctxsize = sizeof(struct mv_ctx), | |
931 | .cra_alignmask = 0, | |
932 | .cra_type = &crypto_ablkcipher_type, | |
933 | .cra_module = THIS_MODULE, | |
934 | .cra_init = mv_cra_init, | |
935 | .cra_u = { | |
936 | .ablkcipher = { | |
937 | .ivsize = AES_BLOCK_SIZE, | |
938 | .min_keysize = AES_MIN_KEY_SIZE, | |
939 | .max_keysize = AES_MAX_KEY_SIZE, | |
940 | .setkey = mv_setkey_aes, | |
941 | .encrypt = mv_enc_aes_cbc, | |
942 | .decrypt = mv_dec_aes_cbc, | |
943 | }, | |
944 | }, | |
945 | }; | |
946 | ||
750052dd US |
947 | struct ahash_alg mv_sha1_alg = { |
948 | .init = mv_hash_init, | |
949 | .update = mv_hash_update, | |
950 | .final = mv_hash_final, | |
951 | .finup = mv_hash_finup, | |
952 | .digest = mv_hash_digest, | |
953 | .halg = { | |
954 | .digestsize = SHA1_DIGEST_SIZE, | |
955 | .base = { | |
956 | .cra_name = "sha1", | |
957 | .cra_driver_name = "mv-sha1", | |
958 | .cra_priority = 300, | |
959 | .cra_flags = | |
d912bb76 NM |
960 | CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY | |
961 | CRYPTO_ALG_NEED_FALLBACK, | |
750052dd US |
962 | .cra_blocksize = SHA1_BLOCK_SIZE, |
963 | .cra_ctxsize = sizeof(struct mv_tfm_hash_ctx), | |
964 | .cra_init = mv_cra_hash_sha1_init, | |
965 | .cra_exit = mv_cra_hash_exit, | |
966 | .cra_module = THIS_MODULE, | |
967 | } | |
968 | } | |
969 | }; | |
970 | ||
971 | struct ahash_alg mv_hmac_sha1_alg = { | |
972 | .init = mv_hash_init, | |
973 | .update = mv_hash_update, | |
974 | .final = mv_hash_final, | |
975 | .finup = mv_hash_finup, | |
976 | .digest = mv_hash_digest, | |
977 | .setkey = mv_hash_setkey, | |
978 | .halg = { | |
979 | .digestsize = SHA1_DIGEST_SIZE, | |
980 | .base = { | |
981 | .cra_name = "hmac(sha1)", | |
982 | .cra_driver_name = "mv-hmac-sha1", | |
983 | .cra_priority = 300, | |
984 | .cra_flags = | |
d912bb76 NM |
985 | CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY | |
986 | CRYPTO_ALG_NEED_FALLBACK, | |
750052dd US |
987 | .cra_blocksize = SHA1_BLOCK_SIZE, |
988 | .cra_ctxsize = sizeof(struct mv_tfm_hash_ctx), | |
989 | .cra_init = mv_cra_hash_hmac_sha1_init, | |
990 | .cra_exit = mv_cra_hash_exit, | |
991 | .cra_module = THIS_MODULE, | |
992 | } | |
993 | } | |
994 | }; | |
995 | ||
85a7f0ac SAS |
996 | static int mv_probe(struct platform_device *pdev) |
997 | { | |
998 | struct crypto_priv *cp; | |
999 | struct resource *res; | |
1000 | int irq; | |
1001 | int ret; | |
1002 | ||
1003 | if (cpg) { | |
750052dd | 1004 | printk(KERN_ERR MV_CESA "Second crypto dev?\n"); |
85a7f0ac SAS |
1005 | return -EEXIST; |
1006 | } | |
1007 | ||
1008 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); | |
1009 | if (!res) | |
1010 | return -ENXIO; | |
1011 | ||
1012 | cp = kzalloc(sizeof(*cp), GFP_KERNEL); | |
1013 | if (!cp) | |
1014 | return -ENOMEM; | |
1015 | ||
1016 | spin_lock_init(&cp->lock); | |
1017 | crypto_init_queue(&cp->queue, 50); | |
5bdd5ded | 1018 | cp->reg = ioremap(res->start, resource_size(res)); |
85a7f0ac SAS |
1019 | if (!cp->reg) { |
1020 | ret = -ENOMEM; | |
1021 | goto err; | |
1022 | } | |
1023 | ||
1024 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram"); | |
1025 | if (!res) { | |
1026 | ret = -ENXIO; | |
1027 | goto err_unmap_reg; | |
1028 | } | |
5bdd5ded | 1029 | cp->sram_size = resource_size(res); |
85a7f0ac SAS |
1030 | cp->max_req_size = cp->sram_size - SRAM_CFG_SPACE; |
1031 | cp->sram = ioremap(res->start, cp->sram_size); | |
1032 | if (!cp->sram) { | |
1033 | ret = -ENOMEM; | |
1034 | goto err_unmap_reg; | |
1035 | } | |
1036 | ||
1037 | irq = platform_get_irq(pdev, 0); | |
1038 | if (irq < 0 || irq == NO_IRQ) { | |
1039 | ret = irq; | |
1040 | goto err_unmap_sram; | |
1041 | } | |
1042 | cp->irq = irq; | |
1043 | ||
1044 | platform_set_drvdata(pdev, cp); | |
1045 | cpg = cp; | |
1046 | ||
1047 | cp->queue_th = kthread_run(queue_manag, cp, "mv_crypto"); | |
1048 | if (IS_ERR(cp->queue_th)) { | |
1049 | ret = PTR_ERR(cp->queue_th); | |
7cc28350 | 1050 | goto err_unmap_sram; |
85a7f0ac SAS |
1051 | } |
1052 | ||
1053 | ret = request_irq(irq, crypto_int, IRQF_DISABLED, dev_name(&pdev->dev), | |
1054 | cp); | |
1055 | if (ret) | |
7cc28350 | 1056 | goto err_thread; |
85a7f0ac | 1057 | |
1f80b126 AL |
1058 | /* Not all platforms can gate the clock, so it is not |
1059 | an error if the clock does not exists. */ | |
1060 | cp->clk = clk_get(&pdev->dev, NULL); | |
1061 | if (!IS_ERR(cp->clk)) | |
1062 | clk_prepare_enable(cp->clk); | |
1063 | ||
85a7f0ac SAS |
1064 | writel(SEC_INT_ACCEL0_DONE, cpg->reg + SEC_ACCEL_INT_MASK); |
1065 | writel(SEC_CFG_STOP_DIG_ERR, cpg->reg + SEC_ACCEL_CFG); | |
99db3eac | 1066 | writel(SRAM_CONFIG, cpg->reg + SEC_ACCEL_DESC_P0); |
85a7f0ac SAS |
1067 | |
1068 | ret = crypto_register_alg(&mv_aes_alg_ecb); | |
2a025f5d PS |
1069 | if (ret) { |
1070 | printk(KERN_WARNING MV_CESA | |
1071 | "Could not register aes-ecb driver\n"); | |
7cc28350 | 1072 | goto err_irq; |
2a025f5d | 1073 | } |
85a7f0ac SAS |
1074 | |
1075 | ret = crypto_register_alg(&mv_aes_alg_cbc); | |
2a025f5d PS |
1076 | if (ret) { |
1077 | printk(KERN_WARNING MV_CESA | |
1078 | "Could not register aes-cbc driver\n"); | |
85a7f0ac | 1079 | goto err_unreg_ecb; |
2a025f5d | 1080 | } |
750052dd US |
1081 | |
1082 | ret = crypto_register_ahash(&mv_sha1_alg); | |
1083 | if (ret == 0) | |
1084 | cpg->has_sha1 = 1; | |
1085 | else | |
1086 | printk(KERN_WARNING MV_CESA "Could not register sha1 driver\n"); | |
1087 | ||
1088 | ret = crypto_register_ahash(&mv_hmac_sha1_alg); | |
1089 | if (ret == 0) { | |
1090 | cpg->has_hmac_sha1 = 1; | |
1091 | } else { | |
1092 | printk(KERN_WARNING MV_CESA | |
1093 | "Could not register hmac-sha1 driver\n"); | |
1094 | } | |
1095 | ||
85a7f0ac SAS |
1096 | return 0; |
1097 | err_unreg_ecb: | |
1098 | crypto_unregister_alg(&mv_aes_alg_ecb); | |
7cc28350 | 1099 | err_irq: |
85a7f0ac | 1100 | free_irq(irq, cp); |
7cc28350 | 1101 | err_thread: |
85a7f0ac SAS |
1102 | kthread_stop(cp->queue_th); |
1103 | err_unmap_sram: | |
1104 | iounmap(cp->sram); | |
1105 | err_unmap_reg: | |
1106 | iounmap(cp->reg); | |
1107 | err: | |
1108 | kfree(cp); | |
1109 | cpg = NULL; | |
1110 | platform_set_drvdata(pdev, NULL); | |
1111 | return ret; | |
1112 | } | |
1113 | ||
1114 | static int mv_remove(struct platform_device *pdev) | |
1115 | { | |
1116 | struct crypto_priv *cp = platform_get_drvdata(pdev); | |
1117 | ||
1118 | crypto_unregister_alg(&mv_aes_alg_ecb); | |
1119 | crypto_unregister_alg(&mv_aes_alg_cbc); | |
750052dd US |
1120 | if (cp->has_sha1) |
1121 | crypto_unregister_ahash(&mv_sha1_alg); | |
1122 | if (cp->has_hmac_sha1) | |
1123 | crypto_unregister_ahash(&mv_hmac_sha1_alg); | |
85a7f0ac SAS |
1124 | kthread_stop(cp->queue_th); |
1125 | free_irq(cp->irq, cp); | |
1126 | memset(cp->sram, 0, cp->sram_size); | |
1127 | iounmap(cp->sram); | |
1128 | iounmap(cp->reg); | |
1f80b126 AL |
1129 | |
1130 | if (!IS_ERR(cp->clk)) { | |
1131 | clk_disable_unprepare(cp->clk); | |
1132 | clk_put(cp->clk); | |
1133 | } | |
1134 | ||
85a7f0ac SAS |
1135 | kfree(cp); |
1136 | cpg = NULL; | |
1137 | return 0; | |
1138 | } | |
1139 | ||
1140 | static struct platform_driver marvell_crypto = { | |
1141 | .probe = mv_probe, | |
1142 | .remove = mv_remove, | |
1143 | .driver = { | |
1144 | .owner = THIS_MODULE, | |
1145 | .name = "mv_crypto", | |
1146 | }, | |
1147 | }; | |
1148 | MODULE_ALIAS("platform:mv_crypto"); | |
1149 | ||
741e8c2d | 1150 | module_platform_driver(marvell_crypto); |
85a7f0ac SAS |
1151 | |
1152 | MODULE_AUTHOR("Sebastian Andrzej Siewior <sebastian@breakpoint.cc>"); | |
1153 | MODULE_DESCRIPTION("Support for Marvell's cryptographic engine"); | |
1154 | MODULE_LICENSE("GPL"); |