[deliverable/linux.git] / drivers / crypto / nx / nx-sha512.c

/**
 * SHA-512 routines supporting the Power 7+ Nest Accelerators driver
 *
 * Copyright (C) 2011-2012 International Business Machines Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 only.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 * Author: Kent Yoder <yoder1@us.ibm.com>
 */

#include <crypto/internal/hash.h>
#include <crypto/sha.h>
#include <linux/module.h>
#include <asm/vio.h>

#include "nx_csbcpb.h"
#include "nx.h"


static int nx_sha512_init(struct shash_desc *desc)
{
	struct sha512_state *sctx = shash_desc_ctx(desc);
	struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base);
	int len;
	int rc;

	nx_ctx_init(nx_ctx, HCOP_FC_SHA);

	memset(sctx, 0, sizeof *sctx);

	nx_ctx->ap = &nx_ctx->props[NX_PROPS_SHA512];

	NX_CPB_SET_DIGEST_SIZE(nx_ctx->csbcpb, NX_DS_SHA512);

	len = SHA512_DIGEST_SIZE;
	rc = nx_sha_build_sg_list(nx_ctx, nx_ctx->out_sg,
				  &nx_ctx->op.outlen,
				  &len,
				  (u8 *)sctx->state,
				  NX_DS_SHA512);

	if (rc || len != SHA512_DIGEST_SIZE)
		goto out;

	sctx->state[0] = __cpu_to_be64(SHA512_H0);
	sctx->state[1] = __cpu_to_be64(SHA512_H1);
	sctx->state[2] = __cpu_to_be64(SHA512_H2);
	sctx->state[3] = __cpu_to_be64(SHA512_H3);
	sctx->state[4] = __cpu_to_be64(SHA512_H4);
	sctx->state[5] = __cpu_to_be64(SHA512_H5);
	sctx->state[6] = __cpu_to_be64(SHA512_H6);
	sctx->state[7] = __cpu_to_be64(SHA512_H7);
	sctx->count[0] = 0;

out:
	return 0;
}

static int nx_sha512_update(struct shash_desc *desc, const u8 *data,
			    unsigned int len)
{
	struct sha512_state *sctx = shash_desc_ctx(desc);
	struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base);
	struct nx_csbcpb *csbcpb = (struct nx_csbcpb *)nx_ctx->csbcpb;
	u64 to_process, leftover = 0, total;
	unsigned long irq_flags;
	int rc = 0;
	int data_len;
	u64 buf_len = (sctx->count[0] % SHA512_BLOCK_SIZE);

	spin_lock_irqsave(&nx_ctx->lock, irq_flags);

	/* 2 cases for total data len:
	 *  1: < SHA512_BLOCK_SIZE: copy into state, return 0
	 *  2: >= SHA512_BLOCK_SIZE: process X blocks, copy in leftover
	 */
	total = (sctx->count[0] % SHA512_BLOCK_SIZE) + len;
	if (total < SHA512_BLOCK_SIZE) {
		memcpy(sctx->buf + buf_len, data, len);
		sctx->count[0] += len;
		goto out;
	}

	memcpy(csbcpb->cpb.sha512.message_digest, sctx->state, SHA512_DIGEST_SIZE);
	NX_CPB_FDM(csbcpb) |= NX_FDM_INTERMEDIATE;
	NX_CPB_FDM(csbcpb) |= NX_FDM_CONTINUATION;

	do {
		/*
		 * to_process: the SHA512_BLOCK_SIZE data chunk to process in
		 * this update. This value is also restricted by the sg list
		 * limits.
		 */
		to_process = total - leftover;
		to_process = to_process & ~(SHA512_BLOCK_SIZE - 1);
		leftover = total - to_process;

		if (buf_len) {
			data_len = buf_len;
			rc = nx_sha_build_sg_list(nx_ctx, nx_ctx->in_sg,
						  &nx_ctx->op.inlen,
						  &data_len,
						  (u8 *) sctx->buf,
						  NX_DS_SHA512);

			if (rc || data_len != buf_len)
				goto out;
		}

		data_len = to_process - buf_len;
		rc = nx_sha_build_sg_list(nx_ctx, nx_ctx->in_sg,
					  &nx_ctx->op.inlen,
					  &data_len,
					  (u8 *) data,
					  NX_DS_SHA512);

		if (rc || data_len != (to_process - buf_len))
			goto out;

		to_process = (data_len + buf_len);
		leftover = total - to_process;

		/*
		 * we've hit the nx chip previously and we're updating
		 * again, so copy over the partial digest.
		 */
		memcpy(csbcpb->cpb.sha512.input_partial_digest,
			       csbcpb->cpb.sha512.message_digest,
			       SHA512_DIGEST_SIZE);

		if (!nx_ctx->op.inlen || !nx_ctx->op.outlen) {
			rc = -EINVAL;
			goto out;
		}

		rc = nx_hcall_sync(nx_ctx, &nx_ctx->op,
				   desc->flags & CRYPTO_TFM_REQ_MAY_SLEEP);
		if (rc)
			goto out;

		atomic_inc(&(nx_ctx->stats->sha512_ops));

		total -= to_process;
		data += to_process - buf_len;
		buf_len = 0;

	} while (leftover >= SHA512_BLOCK_SIZE);

	/* copy the leftover back into the state struct */
	if (leftover)
		memcpy(sctx->buf, data, leftover);
	sctx->count[0] += len;
	memcpy(sctx->state, csbcpb->cpb.sha512.message_digest, SHA512_DIGEST_SIZE);
out:
	spin_unlock_irqrestore(&nx_ctx->lock, irq_flags);
	return rc;
}

static int nx_sha512_final(struct shash_desc *desc, u8 *out)
{
	struct sha512_state *sctx = shash_desc_ctx(desc);
	struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base);
	struct nx_csbcpb *csbcpb = (struct nx_csbcpb *)nx_ctx->csbcpb;
	u64 count0;
	unsigned long irq_flags;
	int rc;
	int len;

	spin_lock_irqsave(&nx_ctx->lock, irq_flags);

	/* final is represented by continuing the operation and indicating that
	 * this is not an intermediate operation */
	if (sctx->count[0] >= SHA512_BLOCK_SIZE) {
		/* we've hit the nx chip previously, now we're finalizing,
		 * so copy over the partial digest */
		memcpy(csbcpb->cpb.sha512.input_partial_digest, sctx->state,
							SHA512_DIGEST_SIZE);
		NX_CPB_FDM(csbcpb) &= ~NX_FDM_INTERMEDIATE;
		NX_CPB_FDM(csbcpb) |= NX_FDM_CONTINUATION;
	} else {
		NX_CPB_FDM(csbcpb) &= ~NX_FDM_INTERMEDIATE;
		NX_CPB_FDM(csbcpb) &= ~NX_FDM_CONTINUATION;
	}

	NX_CPB_FDM(csbcpb) &= ~NX_FDM_INTERMEDIATE;

	count0 = sctx->count[0] * 8;

	csbcpb->cpb.sha512.message_bit_length_lo = count0;

	len = sctx->count[0] & (SHA512_BLOCK_SIZE - 1);
	rc = nx_sha_build_sg_list(nx_ctx, nx_ctx->in_sg,
				  &nx_ctx->op.inlen,
				  &len,
				  (u8 *)sctx->buf,
				  NX_DS_SHA512);

	if (rc || len != (sctx->count[0] & (SHA512_BLOCK_SIZE - 1)))
		goto out;

	len = SHA512_DIGEST_SIZE;
	rc = nx_sha_build_sg_list(nx_ctx, nx_ctx->out_sg,
				  &nx_ctx->op.outlen,
				  &len,
				  out,
				  NX_DS_SHA512);

	if (rc)
		goto out;

	if (!nx_ctx->op.outlen) {
		rc = -EINVAL;
		goto out;
	}

	rc = nx_hcall_sync(nx_ctx, &nx_ctx->op,
			   desc->flags & CRYPTO_TFM_REQ_MAY_SLEEP);
	if (rc)
		goto out;

	atomic_inc(&(nx_ctx->stats->sha512_ops));
	atomic64_add(sctx->count[0], &(nx_ctx->stats->sha512_bytes));

	memcpy(out, csbcpb->cpb.sha512.message_digest, SHA512_DIGEST_SIZE);
out:
	spin_unlock_irqrestore(&nx_ctx->lock, irq_flags);
	return rc;
}

static int nx_sha512_export(struct shash_desc *desc, void *out)
{
	struct sha512_state *sctx = shash_desc_ctx(desc);

	memcpy(out, sctx, sizeof(*sctx));

	return 0;
}

static int nx_sha512_import(struct shash_desc *desc, const void *in)
{
	struct sha512_state *sctx = shash_desc_ctx(desc);

	memcpy(sctx, in, sizeof(*sctx));

	return 0;
}

struct shash_alg nx_shash_sha512_alg = {
	.digestsize = SHA512_DIGEST_SIZE,
	.init       = nx_sha512_init,
	.update     = nx_sha512_update,
	.final      = nx_sha512_final,
	.export     = nx_sha512_export,
	.import     = nx_sha512_import,
	.descsize   = sizeof(struct sha512_state),
	.statesize  = sizeof(struct sha512_state),
	.base       = {
		.cra_name        = "sha512",
		.cra_driver_name = "sha512-nx",
		.cra_priority    = 300,
		.cra_flags       = CRYPTO_ALG_TYPE_SHASH,
		.cra_blocksize   = SHA512_BLOCK_SIZE,
		.cra_module      = THIS_MODULE,
		.cra_ctxsize     = sizeof(struct nx_crypto_ctx),
		.cra_init        = nx_crypto_ctx_sha_init,
		.cra_exit        = nx_crypto_ctx_exit,
	}
};
Commit	Line	Data
fc482a86 KY	1	/**
	2	* SHA-512 routines supporting the Power 7+ Nest Accelerators driver
	3	*
	4	* Copyright (C) 2011-2012 International Business Machines Inc.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; version 2 only.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	18	*
	19	* Author: Kent Yoder <yoder1@us.ibm.com>
	20	*/
	21
	22	#include <crypto/internal/hash.h>
	23	#include <crypto/sha.h>
	24	#include <linux/module.h>
	25	#include <asm/vio.h>
	26
	27	#include "nx_csbcpb.h"
	28	#include "nx.h"
	29
	30
	31	static int nx_sha512_init(struct shash_desc *desc)
	32	{
	33	struct sha512_state *sctx = shash_desc_ctx(desc);
	34	struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base);
00085111 LB	35	int len;
00085111 LB	36	int rc;
fc482a86 KY	37
	38	nx_ctx_init(nx_ctx, HCOP_FC_SHA);
	39
	40	memset(sctx, 0, sizeof *sctx);
	41
	42	nx_ctx->ap = &nx_ctx->props[NX_PROPS_SHA512];
	43
	44	NX_CPB_SET_DIGEST_SIZE(nx_ctx->csbcpb, NX_DS_SHA512);
fc482a86	45
00085111 LB	46	len = SHA512_DIGEST_SIZE;
	47	rc = nx_sha_build_sg_list(nx_ctx, nx_ctx->out_sg,
	48	&nx_ctx->op.outlen,
	49	&len,
	50	(u8 *)sctx->state,
	51	NX_DS_SHA512);
	52
	53	if (rc \|\| len != SHA512_DIGEST_SIZE)
	54	goto out;
	55
	56	sctx->state[0] = __cpu_to_be64(SHA512_H0);
	57	sctx->state[1] = __cpu_to_be64(SHA512_H1);
	58	sctx->state[2] = __cpu_to_be64(SHA512_H2);
	59	sctx->state[3] = __cpu_to_be64(SHA512_H3);
	60	sctx->state[4] = __cpu_to_be64(SHA512_H4);
	61	sctx->state[5] = __cpu_to_be64(SHA512_H5);
	62	sctx->state[6] = __cpu_to_be64(SHA512_H6);
	63	sctx->state[7] = __cpu_to_be64(SHA512_H7);
	64	sctx->count[0] = 0;
	65
	66	out:
fc482a86 KY	67	return 0;
	68	}
	69
	70	static int nx_sha512_update(struct shash_desc desc, const u8 data,
	71	unsigned int len)
	72	{
	73	struct sha512_state *sctx = shash_desc_ctx(desc);
	74	struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base);
	75	struct nx_csbcpb csbcpb = (struct nx_csbcpb )nx_ctx->csbcpb;
00085111	76	u64 to_process, leftover = 0, total;
c849163b	77	unsigned long irq_flags;
fc482a86	78	int rc = 0;
00085111 LB	79	int data_len;
00085111 LB	80	u64 buf_len = (sctx->count[0] % SHA512_BLOCK_SIZE);
fc482a86	81
c849163b MC	82	spin_lock_irqsave(&nx_ctx->lock, irq_flags);
c849163b MC	83
fc482a86	84	/* 2 cases for total data len:
d3111493 MC	85	* 1: < SHA512_BLOCK_SIZE: copy into state, return 0
d3111493 MC	86	* 2: >= SHA512_BLOCK_SIZE: process X blocks, copy in leftover
fc482a86	87	*/
00085111	88	total = (sctx->count[0] % SHA512_BLOCK_SIZE) + len;
d3111493	89	if (total < SHA512_BLOCK_SIZE) {
00085111	90	memcpy(sctx->buf + buf_len, data, len);
fc482a86 KY	91	sctx->count[0] += len;
	92	goto out;
	93	}
	94
00085111 LB	95	memcpy(csbcpb->cpb.sha512.message_digest, sctx->state, SHA512_DIGEST_SIZE);
	96	NX_CPB_FDM(csbcpb) \|= NX_FDM_INTERMEDIATE;
	97	NX_CPB_FDM(csbcpb) \|= NX_FDM_CONTINUATION;
d3111493 MC	98
	99	do {
	100	/*
	101	* to_process: the SHA512_BLOCK_SIZE data chunk to process in
	102	* this update. This value is also restricted by the sg list
	103	* limits.
	104	*/
00085111	105	to_process = total - leftover;
d3111493 MC	106	to_process = to_process & ~(SHA512_BLOCK_SIZE - 1);
	107	leftover = total - to_process;
	108
00085111 LB	109	if (buf_len) {
	110	data_len = buf_len;
	111	rc = nx_sha_build_sg_list(nx_ctx, nx_ctx->in_sg,
	112	&nx_ctx->op.inlen,
	113	&data_len,
	114	(u8 *) sctx->buf,
	115	NX_DS_SHA512);
	116
	117	if (rc \|\| data_len != buf_len)
	118	goto out;
d3111493	119	}
00085111 LB	120
	121	data_len = to_process - buf_len;
	122	rc = nx_sha_build_sg_list(nx_ctx, nx_ctx->in_sg,
	123	&nx_ctx->op.inlen,
	124	&data_len,
	125	(u8 *) data,
	126	NX_DS_SHA512);
	127
	128	if (rc \|\| data_len != (to_process - buf_len))
	129	goto out;
	130
	131	to_process = (data_len + buf_len);
	132	leftover = total - to_process;
	133
	134	/*
	135	* we've hit the nx chip previously and we're updating
	136	* again, so copy over the partial digest.
	137	*/
	138	memcpy(csbcpb->cpb.sha512.input_partial_digest,
d3111493 MC	139	csbcpb->cpb.sha512.message_digest,
d3111493 MC	140	SHA512_DIGEST_SIZE);
d3111493	141
d3111493 MC	142	if (!nx_ctx->op.inlen \|\| !nx_ctx->op.outlen) {
	143	rc = -EINVAL;
	144	goto out;
	145	}
	146
	147	rc = nx_hcall_sync(nx_ctx, &nx_ctx->op,
	148	desc->flags & CRYPTO_TFM_REQ_MAY_SLEEP);
	149	if (rc)
	150	goto out;
	151
	152	atomic_inc(&(nx_ctx->stats->sha512_ops));
d3111493 MC	153
d3111493 MC	154	total -= to_process;
00085111 LB	155	data += to_process - buf_len;
	156	buf_len = 0;
	157
d3111493	158	} while (leftover >= SHA512_BLOCK_SIZE);
fc482a86 KY	159
fc482a86 KY	160	/* copy the leftover back into the state struct */
1ad936e8	161	if (leftover)
d3111493	162	memcpy(sctx->buf, data, leftover);
00085111 LB	163	sctx->count[0] += len;
00085111 LB	164	memcpy(sctx->state, csbcpb->cpb.sha512.message_digest, SHA512_DIGEST_SIZE);
fc482a86	165	out:
c849163b	166	spin_unlock_irqrestore(&nx_ctx->lock, irq_flags);
fc482a86 KY	167	return rc;
	168	}
	169
	170	static int nx_sha512_final(struct shash_desc desc, u8 out)
	171	{
	172	struct sha512_state *sctx = shash_desc_ctx(desc);
	173	struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(&desc->tfm->base);
	174	struct nx_csbcpb csbcpb = (struct nx_csbcpb )nx_ctx->csbcpb;
fc482a86	175	u64 count0;
c849163b	176	unsigned long irq_flags;
fc482a86	177	int rc;
00085111	178	int len;
fc482a86	179
c849163b MC	180	spin_lock_irqsave(&nx_ctx->lock, irq_flags);
c849163b MC	181
00085111 LB	182	/* final is represented by continuing the operation and indicating that
	183	* this is not an intermediate operation */
	184	if (sctx->count[0] >= SHA512_BLOCK_SIZE) {
fc482a86 KY	185	/* we've hit the nx chip previously, now we're finalizing,
fc482a86 KY	186	* so copy over the partial digest */
00085111 LB	187	memcpy(csbcpb->cpb.sha512.input_partial_digest, sctx->state,
	188	SHA512_DIGEST_SIZE);
	189	NX_CPB_FDM(csbcpb) &= ~NX_FDM_INTERMEDIATE;
	190	NX_CPB_FDM(csbcpb) \|= NX_FDM_CONTINUATION;
	191	} else {
	192	NX_CPB_FDM(csbcpb) &= ~NX_FDM_INTERMEDIATE;
	193	NX_CPB_FDM(csbcpb) &= ~NX_FDM_CONTINUATION;
fc482a86 KY	194	}
fc482a86 KY	195
fc482a86 KY	196	NX_CPB_FDM(csbcpb) &= ~NX_FDM_INTERMEDIATE;
	197
	198	count0 = sctx->count[0] * 8;
	199
00085111	200	csbcpb->cpb.sha512.message_bit_length_lo = count0;
fc482a86	201
00085111 LB	202	len = sctx->count[0] & (SHA512_BLOCK_SIZE - 1);
	203	rc = nx_sha_build_sg_list(nx_ctx, nx_ctx->in_sg,
	204	&nx_ctx->op.inlen,
	205	&len,
	206	(u8 *)sctx->buf,
	207	NX_DS_SHA512);
	208
	209	if (rc \|\| len != (sctx->count[0] & (SHA512_BLOCK_SIZE - 1)))
	210	goto out;
	211
	212	len = SHA512_DIGEST_SIZE;
	213	rc = nx_sha_build_sg_list(nx_ctx, nx_ctx->out_sg,
	214	&nx_ctx->op.outlen,
	215	&len,
	216	out,
	217	NX_DS_SHA512);
	218
	219	if (rc)
	220	goto out;
fc482a86 KY	221
	222	if (!nx_ctx->op.outlen) {
	223	rc = -EINVAL;
	224	goto out;
	225	}
	226
	227	rc = nx_hcall_sync(nx_ctx, &nx_ctx->op,
	228	desc->flags & CRYPTO_TFM_REQ_MAY_SLEEP);
	229	if (rc)
	230	goto out;
	231
	232	atomic_inc(&(nx_ctx->stats->sha512_ops));
00085111	233	atomic64_add(sctx->count[0], &(nx_ctx->stats->sha512_bytes));
fc482a86 KY	234
	235	memcpy(out, csbcpb->cpb.sha512.message_digest, SHA512_DIGEST_SIZE);
	236	out:
c849163b	237	spin_unlock_irqrestore(&nx_ctx->lock, irq_flags);
fc482a86 KY	238	return rc;
	239	}
	240
	241	static int nx_sha512_export(struct shash_desc desc, void out)
	242	{
	243	struct sha512_state *sctx = shash_desc_ctx(desc);
c849163b	244
00085111	245	memcpy(out, sctx, sizeof(*sctx));
fc482a86	246
fc482a86 KY	247	return 0;
	248	}
	249
	250	static int nx_sha512_import(struct shash_desc desc, const void in)
	251	{
	252	struct sha512_state *sctx = shash_desc_ctx(desc);
fc482a86	253
00085111	254	memcpy(sctx, in, sizeof(*sctx));
fc482a86 KY	255
	256	return 0;
	257	}
	258
	259	struct shash_alg nx_shash_sha512_alg = {
	260	.digestsize = SHA512_DIGEST_SIZE,
	261	.init = nx_sha512_init,
	262	.update = nx_sha512_update,
	263	.final = nx_sha512_final,
	264	.export = nx_sha512_export,
	265	.import = nx_sha512_import,
	266	.descsize = sizeof(struct sha512_state),
	267	.statesize = sizeof(struct sha512_state),
	268	.base = {
	269	.cra_name = "sha512",
	270	.cra_driver_name = "sha512-nx",
	271	.cra_priority = 300,
	272	.cra_flags = CRYPTO_ALG_TYPE_SHASH,
	273	.cra_blocksize = SHA512_BLOCK_SIZE,
	274	.cra_module = THIS_MODULE,
	275	.cra_ctxsize = sizeof(struct nx_crypto_ctx),
	276	.cra_init = nx_crypto_ctx_sha_init,
	277	.cra_exit = nx_crypto_ctx_exit,
	278	}
	279	};