Commit | Line | Data |
---|---|---|
537559a5 DK |
1 | /* |
2 | * Cryptographic API. | |
3 | * | |
4 | * Support for OMAP AES HW acceleration. | |
5 | * | |
6 | * Copyright (c) 2010 Nokia Corporation | |
7 | * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com> | |
0d35583a | 8 | * Copyright (c) 2011 Texas Instruments Incorporated |
537559a5 DK |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as published | |
12 | * by the Free Software Foundation. | |
13 | * | |
14 | */ | |
15 | ||
016af9b5 JF |
16 | #define pr_fmt(fmt) "%20s: " fmt, __func__ |
17 | #define prn(num) pr_debug(#num "=%d\n", num) | |
18 | #define prx(num) pr_debug(#num "=%x\n", num) | |
537559a5 DK |
19 | |
20 | #include <linux/err.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/errno.h> | |
24 | #include <linux/kernel.h> | |
537559a5 DK |
25 | #include <linux/platform_device.h> |
26 | #include <linux/scatterlist.h> | |
27 | #include <linux/dma-mapping.h> | |
ebedbf79 MG |
28 | #include <linux/dmaengine.h> |
29 | #include <linux/omap-dma.h> | |
5946c4a5 | 30 | #include <linux/pm_runtime.h> |
bc69d124 MG |
31 | #include <linux/of.h> |
32 | #include <linux/of_device.h> | |
33 | #include <linux/of_address.h> | |
537559a5 DK |
34 | #include <linux/io.h> |
35 | #include <linux/crypto.h> | |
36 | #include <linux/interrupt.h> | |
37 | #include <crypto/scatterwalk.h> | |
38 | #include <crypto/aes.h> | |
39 | ||
ebedbf79 MG |
40 | #define DST_MAXBURST 4 |
41 | #define DMA_MIN (DST_MAXBURST * sizeof(u32)) | |
537559a5 DK |
42 | |
43 | /* OMAP TRM gives bitfields as start:end, where start is the higher bit | |
44 | number. For example 7:0 */ | |
45 | #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end)) | |
46 | #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end)) | |
47 | ||
0d35583a MG |
48 | #define AES_REG_KEY(dd, x) ((dd)->pdata->key_ofs - \ |
49 | ((x ^ 0x01) * 0x04)) | |
50 | #define AES_REG_IV(dd, x) ((dd)->pdata->iv_ofs + ((x) * 0x04)) | |
537559a5 | 51 | |
0d35583a | 52 | #define AES_REG_CTRL(dd) ((dd)->pdata->ctrl_ofs) |
f9fb69e7 MG |
53 | #define AES_REG_CTRL_CTR_WIDTH_MASK (3 << 7) |
54 | #define AES_REG_CTRL_CTR_WIDTH_32 (0 << 7) | |
55 | #define AES_REG_CTRL_CTR_WIDTH_64 (1 << 7) | |
56 | #define AES_REG_CTRL_CTR_WIDTH_96 (2 << 7) | |
57 | #define AES_REG_CTRL_CTR_WIDTH_128 (3 << 7) | |
537559a5 DK |
58 | #define AES_REG_CTRL_CTR (1 << 6) |
59 | #define AES_REG_CTRL_CBC (1 << 5) | |
60 | #define AES_REG_CTRL_KEY_SIZE (3 << 3) | |
61 | #define AES_REG_CTRL_DIRECTION (1 << 2) | |
62 | #define AES_REG_CTRL_INPUT_READY (1 << 1) | |
63 | #define AES_REG_CTRL_OUTPUT_READY (1 << 0) | |
64 | ||
0d35583a | 65 | #define AES_REG_DATA_N(dd, x) ((dd)->pdata->data_ofs + ((x) * 0x04)) |
537559a5 | 66 | |
0d35583a | 67 | #define AES_REG_REV(dd) ((dd)->pdata->rev_ofs) |
537559a5 | 68 | |
0d35583a | 69 | #define AES_REG_MASK(dd) ((dd)->pdata->mask_ofs) |
537559a5 DK |
70 | #define AES_REG_MASK_SIDLE (1 << 6) |
71 | #define AES_REG_MASK_START (1 << 5) | |
72 | #define AES_REG_MASK_DMA_OUT_EN (1 << 3) | |
73 | #define AES_REG_MASK_DMA_IN_EN (1 << 2) | |
74 | #define AES_REG_MASK_SOFTRESET (1 << 1) | |
75 | #define AES_REG_AUTOIDLE (1 << 0) | |
76 | ||
0d35583a | 77 | #define AES_REG_LENGTH_N(x) (0x54 + ((x) * 0x04)) |
537559a5 | 78 | |
67216756 JF |
79 | #define AES_REG_IRQ_STATUS(dd) ((dd)->pdata->irq_status_ofs) |
80 | #define AES_REG_IRQ_ENABLE(dd) ((dd)->pdata->irq_enable_ofs) | |
81 | #define AES_REG_IRQ_DATA_IN BIT(1) | |
82 | #define AES_REG_IRQ_DATA_OUT BIT(2) | |
537559a5 DK |
83 | #define DEFAULT_TIMEOUT (5*HZ) |
84 | ||
85 | #define FLAGS_MODE_MASK 0x000f | |
86 | #define FLAGS_ENCRYPT BIT(0) | |
87 | #define FLAGS_CBC BIT(1) | |
88 | #define FLAGS_GIV BIT(2) | |
f9fb69e7 | 89 | #define FLAGS_CTR BIT(3) |
537559a5 | 90 | |
67a730ce DK |
91 | #define FLAGS_INIT BIT(4) |
92 | #define FLAGS_FAST BIT(5) | |
93 | #define FLAGS_BUSY BIT(6) | |
537559a5 DK |
94 | |
95 | struct omap_aes_ctx { | |
96 | struct omap_aes_dev *dd; | |
97 | ||
98 | int keylen; | |
99 | u32 key[AES_KEYSIZE_256 / sizeof(u32)]; | |
100 | unsigned long flags; | |
101 | }; | |
102 | ||
103 | struct omap_aes_reqctx { | |
104 | unsigned long mode; | |
105 | }; | |
106 | ||
107 | #define OMAP_AES_QUEUE_LENGTH 1 | |
108 | #define OMAP_AES_CACHE_SIZE 0 | |
109 | ||
f9fb69e7 MG |
110 | struct omap_aes_algs_info { |
111 | struct crypto_alg *algs_list; | |
112 | unsigned int size; | |
113 | unsigned int registered; | |
114 | }; | |
115 | ||
0d35583a | 116 | struct omap_aes_pdata { |
f9fb69e7 MG |
117 | struct omap_aes_algs_info *algs_info; |
118 | unsigned int algs_info_size; | |
119 | ||
0d35583a MG |
120 | void (*trigger)(struct omap_aes_dev *dd, int length); |
121 | ||
122 | u32 key_ofs; | |
123 | u32 iv_ofs; | |
124 | u32 ctrl_ofs; | |
125 | u32 data_ofs; | |
126 | u32 rev_ofs; | |
127 | u32 mask_ofs; | |
67216756 JF |
128 | u32 irq_enable_ofs; |
129 | u32 irq_status_ofs; | |
0d35583a MG |
130 | |
131 | u32 dma_enable_in; | |
132 | u32 dma_enable_out; | |
133 | u32 dma_start; | |
134 | ||
135 | u32 major_mask; | |
136 | u32 major_shift; | |
137 | u32 minor_mask; | |
138 | u32 minor_shift; | |
139 | }; | |
140 | ||
537559a5 DK |
141 | struct omap_aes_dev { |
142 | struct list_head list; | |
143 | unsigned long phys_base; | |
efce41b6 | 144 | void __iomem *io_base; |
537559a5 DK |
145 | struct omap_aes_ctx *ctx; |
146 | struct device *dev; | |
147 | unsigned long flags; | |
21fe9767 | 148 | int err; |
537559a5 | 149 | |
21fe9767 DK |
150 | spinlock_t lock; |
151 | struct crypto_queue queue; | |
537559a5 | 152 | |
21fe9767 DK |
153 | struct tasklet_struct done_task; |
154 | struct tasklet_struct queue_task; | |
537559a5 DK |
155 | |
156 | struct ablkcipher_request *req; | |
157 | size_t total; | |
158 | struct scatterlist *in_sg; | |
537559a5 | 159 | struct scatterlist *out_sg; |
537559a5 | 160 | int dma_in; |
ebedbf79 | 161 | struct dma_chan *dma_lch_in; |
537559a5 | 162 | int dma_out; |
ebedbf79 | 163 | struct dma_chan *dma_lch_out; |
e77c756e JF |
164 | int in_sg_len; |
165 | int out_sg_len; | |
0d35583a | 166 | const struct omap_aes_pdata *pdata; |
537559a5 DK |
167 | }; |
168 | ||
169 | /* keep registered devices data here */ | |
170 | static LIST_HEAD(dev_list); | |
171 | static DEFINE_SPINLOCK(list_lock); | |
172 | ||
016af9b5 JF |
173 | #ifdef DEBUG |
174 | #define omap_aes_read(dd, offset) \ | |
175 | ({ \ | |
176 | int _read_ret; \ | |
177 | _read_ret = __raw_readl(dd->io_base + offset); \ | |
178 | pr_debug("omap_aes_read(" #offset "=%#x)= %#x\n", \ | |
179 | offset, _read_ret); \ | |
180 | _read_ret; \ | |
181 | }) | |
182 | #else | |
537559a5 DK |
183 | static inline u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset) |
184 | { | |
185 | return __raw_readl(dd->io_base + offset); | |
186 | } | |
016af9b5 JF |
187 | #endif |
188 | ||
189 | #ifdef DEBUG | |
190 | #define omap_aes_write(dd, offset, value) \ | |
191 | do { \ | |
192 | pr_debug("omap_aes_write(" #offset "=%#x) value=%#x\n", \ | |
193 | offset, value); \ | |
194 | __raw_writel(value, dd->io_base + offset); \ | |
195 | } while (0) | |
196 | #else | |
537559a5 DK |
197 | static inline void omap_aes_write(struct omap_aes_dev *dd, u32 offset, |
198 | u32 value) | |
199 | { | |
200 | __raw_writel(value, dd->io_base + offset); | |
201 | } | |
016af9b5 | 202 | #endif |
537559a5 DK |
203 | |
204 | static inline void omap_aes_write_mask(struct omap_aes_dev *dd, u32 offset, | |
205 | u32 value, u32 mask) | |
206 | { | |
207 | u32 val; | |
208 | ||
209 | val = omap_aes_read(dd, offset); | |
210 | val &= ~mask; | |
211 | val |= value; | |
212 | omap_aes_write(dd, offset, val); | |
213 | } | |
214 | ||
215 | static void omap_aes_write_n(struct omap_aes_dev *dd, u32 offset, | |
216 | u32 *value, int count) | |
217 | { | |
218 | for (; count--; value++, offset += 4) | |
219 | omap_aes_write(dd, offset, *value); | |
220 | } | |
221 | ||
537559a5 DK |
222 | static int omap_aes_hw_init(struct omap_aes_dev *dd) |
223 | { | |
537559a5 | 224 | if (!(dd->flags & FLAGS_INIT)) { |
eeb2b202 | 225 | dd->flags |= FLAGS_INIT; |
21fe9767 | 226 | dd->err = 0; |
537559a5 DK |
227 | } |
228 | ||
eeb2b202 | 229 | return 0; |
537559a5 DK |
230 | } |
231 | ||
21fe9767 | 232 | static int omap_aes_write_ctrl(struct omap_aes_dev *dd) |
537559a5 DK |
233 | { |
234 | unsigned int key32; | |
67a730ce | 235 | int i, err; |
f9fb69e7 | 236 | u32 val, mask = 0; |
537559a5 | 237 | |
21fe9767 DK |
238 | err = omap_aes_hw_init(dd); |
239 | if (err) | |
240 | return err; | |
241 | ||
537559a5 | 242 | key32 = dd->ctx->keylen / sizeof(u32); |
67a730ce DK |
243 | |
244 | /* it seems a key should always be set even if it has not changed */ | |
537559a5 | 245 | for (i = 0; i < key32; i++) { |
0d35583a | 246 | omap_aes_write(dd, AES_REG_KEY(dd, i), |
537559a5 DK |
247 | __le32_to_cpu(dd->ctx->key[i])); |
248 | } | |
537559a5 | 249 | |
f9fb69e7 | 250 | if ((dd->flags & (FLAGS_CBC | FLAGS_CTR)) && dd->req->info) |
0d35583a | 251 | omap_aes_write_n(dd, AES_REG_IV(dd, 0), dd->req->info, 4); |
67a730ce DK |
252 | |
253 | val = FLD_VAL(((dd->ctx->keylen >> 3) - 1), 4, 3); | |
254 | if (dd->flags & FLAGS_CBC) | |
255 | val |= AES_REG_CTRL_CBC; | |
f9fb69e7 MG |
256 | if (dd->flags & FLAGS_CTR) { |
257 | val |= AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_32; | |
258 | mask = AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_MASK; | |
259 | } | |
67a730ce DK |
260 | if (dd->flags & FLAGS_ENCRYPT) |
261 | val |= AES_REG_CTRL_DIRECTION; | |
537559a5 | 262 | |
f9fb69e7 | 263 | mask |= AES_REG_CTRL_CBC | AES_REG_CTRL_DIRECTION | |
537559a5 DK |
264 | AES_REG_CTRL_KEY_SIZE; |
265 | ||
0d35583a | 266 | omap_aes_write_mask(dd, AES_REG_CTRL(dd), val, mask); |
537559a5 | 267 | |
21fe9767 | 268 | return 0; |
537559a5 DK |
269 | } |
270 | ||
0d35583a MG |
271 | static void omap_aes_dma_trigger_omap2(struct omap_aes_dev *dd, int length) |
272 | { | |
273 | u32 mask, val; | |
274 | ||
275 | val = dd->pdata->dma_start; | |
276 | ||
277 | if (dd->dma_lch_out != NULL) | |
278 | val |= dd->pdata->dma_enable_out; | |
279 | if (dd->dma_lch_in != NULL) | |
280 | val |= dd->pdata->dma_enable_in; | |
281 | ||
282 | mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in | | |
283 | dd->pdata->dma_start; | |
284 | ||
285 | omap_aes_write_mask(dd, AES_REG_MASK(dd), val, mask); | |
286 | ||
287 | } | |
288 | ||
289 | static void omap_aes_dma_trigger_omap4(struct omap_aes_dev *dd, int length) | |
290 | { | |
291 | omap_aes_write(dd, AES_REG_LENGTH_N(0), length); | |
292 | omap_aes_write(dd, AES_REG_LENGTH_N(1), 0); | |
293 | ||
294 | omap_aes_dma_trigger_omap2(dd, length); | |
295 | } | |
296 | ||
297 | static void omap_aes_dma_stop(struct omap_aes_dev *dd) | |
298 | { | |
299 | u32 mask; | |
300 | ||
301 | mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in | | |
302 | dd->pdata->dma_start; | |
303 | ||
304 | omap_aes_write_mask(dd, AES_REG_MASK(dd), 0, mask); | |
305 | } | |
306 | ||
537559a5 DK |
307 | static struct omap_aes_dev *omap_aes_find_dev(struct omap_aes_ctx *ctx) |
308 | { | |
309 | struct omap_aes_dev *dd = NULL, *tmp; | |
310 | ||
311 | spin_lock_bh(&list_lock); | |
312 | if (!ctx->dd) { | |
313 | list_for_each_entry(tmp, &dev_list, list) { | |
314 | /* FIXME: take fist available aes core */ | |
315 | dd = tmp; | |
316 | break; | |
317 | } | |
318 | ctx->dd = dd; | |
319 | } else { | |
320 | /* already found before */ | |
321 | dd = ctx->dd; | |
322 | } | |
323 | spin_unlock_bh(&list_lock); | |
324 | ||
325 | return dd; | |
326 | } | |
327 | ||
ebedbf79 MG |
328 | static void omap_aes_dma_out_callback(void *data) |
329 | { | |
330 | struct omap_aes_dev *dd = data; | |
331 | ||
332 | /* dma_lch_out - completed */ | |
333 | tasklet_schedule(&dd->done_task); | |
334 | } | |
537559a5 DK |
335 | |
336 | static int omap_aes_dma_init(struct omap_aes_dev *dd) | |
337 | { | |
338 | int err = -ENOMEM; | |
ebedbf79 | 339 | dma_cap_mask_t mask; |
537559a5 | 340 | |
ebedbf79 MG |
341 | dd->dma_lch_out = NULL; |
342 | dd->dma_lch_in = NULL; | |
537559a5 | 343 | |
ebedbf79 MG |
344 | dma_cap_zero(mask); |
345 | dma_cap_set(DMA_SLAVE, mask); | |
346 | ||
b4b87a93 MG |
347 | dd->dma_lch_in = dma_request_slave_channel_compat(mask, |
348 | omap_dma_filter_fn, | |
349 | &dd->dma_in, | |
350 | dd->dev, "rx"); | |
ebedbf79 MG |
351 | if (!dd->dma_lch_in) { |
352 | dev_err(dd->dev, "Unable to request in DMA channel\n"); | |
353 | goto err_dma_in; | |
354 | } | |
355 | ||
b4b87a93 MG |
356 | dd->dma_lch_out = dma_request_slave_channel_compat(mask, |
357 | omap_dma_filter_fn, | |
358 | &dd->dma_out, | |
359 | dd->dev, "tx"); | |
ebedbf79 MG |
360 | if (!dd->dma_lch_out) { |
361 | dev_err(dd->dev, "Unable to request out DMA channel\n"); | |
362 | goto err_dma_out; | |
363 | } | |
537559a5 | 364 | |
537559a5 DK |
365 | return 0; |
366 | ||
367 | err_dma_out: | |
ebedbf79 | 368 | dma_release_channel(dd->dma_lch_in); |
537559a5 | 369 | err_dma_in: |
537559a5 DK |
370 | if (err) |
371 | pr_err("error: %d\n", err); | |
372 | return err; | |
373 | } | |
374 | ||
375 | static void omap_aes_dma_cleanup(struct omap_aes_dev *dd) | |
376 | { | |
ebedbf79 MG |
377 | dma_release_channel(dd->dma_lch_out); |
378 | dma_release_channel(dd->dma_lch_in); | |
537559a5 DK |
379 | } |
380 | ||
381 | static void sg_copy_buf(void *buf, struct scatterlist *sg, | |
382 | unsigned int start, unsigned int nbytes, int out) | |
383 | { | |
384 | struct scatter_walk walk; | |
385 | ||
386 | if (!nbytes) | |
387 | return; | |
388 | ||
389 | scatterwalk_start(&walk, sg); | |
390 | scatterwalk_advance(&walk, start); | |
391 | scatterwalk_copychunks(buf, &walk, nbytes, out); | |
392 | scatterwalk_done(&walk, out, 0); | |
393 | } | |
394 | ||
ebedbf79 | 395 | static int omap_aes_crypt_dma(struct crypto_tfm *tfm, |
4b645c94 JF |
396 | struct scatterlist *in_sg, struct scatterlist *out_sg, |
397 | int in_sg_len, int out_sg_len) | |
537559a5 DK |
398 | { |
399 | struct omap_aes_ctx *ctx = crypto_tfm_ctx(tfm); | |
400 | struct omap_aes_dev *dd = ctx->dd; | |
ebedbf79 MG |
401 | struct dma_async_tx_descriptor *tx_in, *tx_out; |
402 | struct dma_slave_config cfg; | |
4b645c94 | 403 | int ret; |
537559a5 | 404 | |
0a641712 JF |
405 | dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE); |
406 | ||
ebedbf79 MG |
407 | memset(&cfg, 0, sizeof(cfg)); |
408 | ||
0d35583a MG |
409 | cfg.src_addr = dd->phys_base + AES_REG_DATA_N(dd, 0); |
410 | cfg.dst_addr = dd->phys_base + AES_REG_DATA_N(dd, 0); | |
ebedbf79 MG |
411 | cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
412 | cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
413 | cfg.src_maxburst = DST_MAXBURST; | |
414 | cfg.dst_maxburst = DST_MAXBURST; | |
415 | ||
416 | /* IN */ | |
417 | ret = dmaengine_slave_config(dd->dma_lch_in, &cfg); | |
418 | if (ret) { | |
419 | dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n", | |
420 | ret); | |
421 | return ret; | |
422 | } | |
423 | ||
4b645c94 | 424 | tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len, |
ebedbf79 MG |
425 | DMA_MEM_TO_DEV, |
426 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
427 | if (!tx_in) { | |
428 | dev_err(dd->dev, "IN prep_slave_sg() failed\n"); | |
429 | return -EINVAL; | |
430 | } | |
431 | ||
432 | /* No callback necessary */ | |
433 | tx_in->callback_param = dd; | |
434 | ||
435 | /* OUT */ | |
436 | ret = dmaengine_slave_config(dd->dma_lch_out, &cfg); | |
437 | if (ret) { | |
438 | dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n", | |
439 | ret); | |
440 | return ret; | |
441 | } | |
442 | ||
4b645c94 | 443 | tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg, out_sg_len, |
ebedbf79 MG |
444 | DMA_DEV_TO_MEM, |
445 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
446 | if (!tx_out) { | |
447 | dev_err(dd->dev, "OUT prep_slave_sg() failed\n"); | |
448 | return -EINVAL; | |
449 | } | |
450 | ||
451 | tx_out->callback = omap_aes_dma_out_callback; | |
452 | tx_out->callback_param = dd; | |
453 | ||
454 | dmaengine_submit(tx_in); | |
455 | dmaengine_submit(tx_out); | |
456 | ||
457 | dma_async_issue_pending(dd->dma_lch_in); | |
458 | dma_async_issue_pending(dd->dma_lch_out); | |
537559a5 | 459 | |
0d35583a | 460 | /* start DMA */ |
4b645c94 | 461 | dd->pdata->trigger(dd, dd->total); |
83ea7e0f | 462 | |
537559a5 DK |
463 | return 0; |
464 | } | |
465 | ||
466 | static int omap_aes_crypt_dma_start(struct omap_aes_dev *dd) | |
467 | { | |
468 | struct crypto_tfm *tfm = crypto_ablkcipher_tfm( | |
469 | crypto_ablkcipher_reqtfm(dd->req)); | |
4b645c94 | 470 | int err; |
537559a5 DK |
471 | |
472 | pr_debug("total: %d\n", dd->total); | |
473 | ||
4b645c94 JF |
474 | err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE); |
475 | if (!err) { | |
476 | dev_err(dd->dev, "dma_map_sg() error\n"); | |
477 | return -EINVAL; | |
537559a5 DK |
478 | } |
479 | ||
4b645c94 JF |
480 | err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len, DMA_FROM_DEVICE); |
481 | if (!err) { | |
482 | dev_err(dd->dev, "dma_map_sg() error\n"); | |
483 | return -EINVAL; | |
537559a5 DK |
484 | } |
485 | ||
4b645c94 JF |
486 | err = omap_aes_crypt_dma(tfm, dd->in_sg, dd->out_sg, dd->in_sg_len, |
487 | dd->out_sg_len); | |
21fe9767 | 488 | if (err) { |
4b645c94 JF |
489 | dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE); |
490 | dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len, | |
491 | DMA_FROM_DEVICE); | |
21fe9767 | 492 | } |
537559a5 DK |
493 | |
494 | return err; | |
495 | } | |
496 | ||
497 | static void omap_aes_finish_req(struct omap_aes_dev *dd, int err) | |
498 | { | |
21fe9767 | 499 | struct ablkcipher_request *req = dd->req; |
537559a5 DK |
500 | |
501 | pr_debug("err: %d\n", err); | |
502 | ||
eeb2b202 DK |
503 | dd->flags &= ~FLAGS_BUSY; |
504 | ||
67a730ce | 505 | req->base.complete(&req->base, err); |
537559a5 DK |
506 | } |
507 | ||
508 | static int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd) | |
509 | { | |
510 | int err = 0; | |
537559a5 DK |
511 | |
512 | pr_debug("total: %d\n", dd->total); | |
513 | ||
0d35583a | 514 | omap_aes_dma_stop(dd); |
537559a5 | 515 | |
ebedbf79 MG |
516 | dmaengine_terminate_all(dd->dma_lch_in); |
517 | dmaengine_terminate_all(dd->dma_lch_out); | |
537559a5 | 518 | |
4b645c94 JF |
519 | dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE); |
520 | dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len, DMA_FROM_DEVICE); | |
537559a5 | 521 | |
537559a5 DK |
522 | return err; |
523 | } | |
524 | ||
21fe9767 | 525 | static int omap_aes_handle_queue(struct omap_aes_dev *dd, |
eeb2b202 | 526 | struct ablkcipher_request *req) |
537559a5 DK |
527 | { |
528 | struct crypto_async_request *async_req, *backlog; | |
529 | struct omap_aes_ctx *ctx; | |
530 | struct omap_aes_reqctx *rctx; | |
537559a5 | 531 | unsigned long flags; |
21fe9767 | 532 | int err, ret = 0; |
537559a5 DK |
533 | |
534 | spin_lock_irqsave(&dd->lock, flags); | |
eeb2b202 | 535 | if (req) |
21fe9767 | 536 | ret = ablkcipher_enqueue_request(&dd->queue, req); |
eeb2b202 DK |
537 | if (dd->flags & FLAGS_BUSY) { |
538 | spin_unlock_irqrestore(&dd->lock, flags); | |
21fe9767 | 539 | return ret; |
eeb2b202 | 540 | } |
537559a5 DK |
541 | backlog = crypto_get_backlog(&dd->queue); |
542 | async_req = crypto_dequeue_request(&dd->queue); | |
eeb2b202 DK |
543 | if (async_req) |
544 | dd->flags |= FLAGS_BUSY; | |
537559a5 DK |
545 | spin_unlock_irqrestore(&dd->lock, flags); |
546 | ||
547 | if (!async_req) | |
21fe9767 | 548 | return ret; |
537559a5 DK |
549 | |
550 | if (backlog) | |
551 | backlog->complete(backlog, -EINPROGRESS); | |
552 | ||
553 | req = ablkcipher_request_cast(async_req); | |
554 | ||
537559a5 DK |
555 | /* assign new request to device */ |
556 | dd->req = req; | |
557 | dd->total = req->nbytes; | |
537559a5 | 558 | dd->in_sg = req->src; |
537559a5 DK |
559 | dd->out_sg = req->dst; |
560 | ||
e77c756e JF |
561 | dd->in_sg_len = scatterwalk_bytes_sglen(dd->in_sg, dd->total); |
562 | dd->out_sg_len = scatterwalk_bytes_sglen(dd->out_sg, dd->total); | |
563 | BUG_ON(dd->in_sg_len < 0 || dd->out_sg_len < 0); | |
564 | ||
537559a5 DK |
565 | rctx = ablkcipher_request_ctx(req); |
566 | ctx = crypto_ablkcipher_ctx(crypto_ablkcipher_reqtfm(req)); | |
567 | rctx->mode &= FLAGS_MODE_MASK; | |
568 | dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode; | |
569 | ||
67a730ce | 570 | dd->ctx = ctx; |
537559a5 | 571 | ctx->dd = dd; |
537559a5 | 572 | |
83ea7e0f DK |
573 | err = omap_aes_write_ctrl(dd); |
574 | if (!err) | |
575 | err = omap_aes_crypt_dma_start(dd); | |
21fe9767 DK |
576 | if (err) { |
577 | /* aes_task will not finish it, so do it here */ | |
578 | omap_aes_finish_req(dd, err); | |
579 | tasklet_schedule(&dd->queue_task); | |
580 | } | |
eeb2b202 | 581 | |
21fe9767 | 582 | return ret; /* return ret, which is enqueue return value */ |
537559a5 DK |
583 | } |
584 | ||
21fe9767 | 585 | static void omap_aes_done_task(unsigned long data) |
537559a5 DK |
586 | { |
587 | struct omap_aes_dev *dd = (struct omap_aes_dev *)data; | |
537559a5 | 588 | |
4b645c94 | 589 | pr_debug("enter done_task\n"); |
21fe9767 | 590 | |
0a641712 JF |
591 | dma_sync_sg_for_cpu(dd->dev, dd->in_sg, dd->in_sg_len, DMA_FROM_DEVICE); |
592 | ||
4b645c94 JF |
593 | omap_aes_crypt_dma_stop(dd); |
594 | omap_aes_finish_req(dd, 0); | |
21fe9767 | 595 | omap_aes_handle_queue(dd, NULL); |
537559a5 DK |
596 | |
597 | pr_debug("exit\n"); | |
598 | } | |
599 | ||
21fe9767 DK |
600 | static void omap_aes_queue_task(unsigned long data) |
601 | { | |
602 | struct omap_aes_dev *dd = (struct omap_aes_dev *)data; | |
603 | ||
604 | omap_aes_handle_queue(dd, NULL); | |
605 | } | |
606 | ||
537559a5 DK |
607 | static int omap_aes_crypt(struct ablkcipher_request *req, unsigned long mode) |
608 | { | |
609 | struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx( | |
610 | crypto_ablkcipher_reqtfm(req)); | |
611 | struct omap_aes_reqctx *rctx = ablkcipher_request_ctx(req); | |
612 | struct omap_aes_dev *dd; | |
537559a5 DK |
613 | |
614 | pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->nbytes, | |
615 | !!(mode & FLAGS_ENCRYPT), | |
616 | !!(mode & FLAGS_CBC)); | |
617 | ||
21fe9767 DK |
618 | if (!IS_ALIGNED(req->nbytes, AES_BLOCK_SIZE)) { |
619 | pr_err("request size is not exact amount of AES blocks\n"); | |
620 | return -EINVAL; | |
621 | } | |
622 | ||
537559a5 DK |
623 | dd = omap_aes_find_dev(ctx); |
624 | if (!dd) | |
625 | return -ENODEV; | |
626 | ||
627 | rctx->mode = mode; | |
628 | ||
21fe9767 | 629 | return omap_aes_handle_queue(dd, req); |
537559a5 DK |
630 | } |
631 | ||
632 | /* ********************** ALG API ************************************ */ | |
633 | ||
634 | static int omap_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key, | |
635 | unsigned int keylen) | |
636 | { | |
637 | struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm); | |
638 | ||
639 | if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 && | |
640 | keylen != AES_KEYSIZE_256) | |
641 | return -EINVAL; | |
642 | ||
643 | pr_debug("enter, keylen: %d\n", keylen); | |
644 | ||
645 | memcpy(ctx->key, key, keylen); | |
646 | ctx->keylen = keylen; | |
537559a5 DK |
647 | |
648 | return 0; | |
649 | } | |
650 | ||
651 | static int omap_aes_ecb_encrypt(struct ablkcipher_request *req) | |
652 | { | |
653 | return omap_aes_crypt(req, FLAGS_ENCRYPT); | |
654 | } | |
655 | ||
656 | static int omap_aes_ecb_decrypt(struct ablkcipher_request *req) | |
657 | { | |
658 | return omap_aes_crypt(req, 0); | |
659 | } | |
660 | ||
661 | static int omap_aes_cbc_encrypt(struct ablkcipher_request *req) | |
662 | { | |
663 | return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC); | |
664 | } | |
665 | ||
666 | static int omap_aes_cbc_decrypt(struct ablkcipher_request *req) | |
667 | { | |
668 | return omap_aes_crypt(req, FLAGS_CBC); | |
669 | } | |
670 | ||
f9fb69e7 MG |
671 | static int omap_aes_ctr_encrypt(struct ablkcipher_request *req) |
672 | { | |
673 | return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CTR); | |
674 | } | |
675 | ||
676 | static int omap_aes_ctr_decrypt(struct ablkcipher_request *req) | |
677 | { | |
678 | return omap_aes_crypt(req, FLAGS_CTR); | |
679 | } | |
680 | ||
537559a5 DK |
681 | static int omap_aes_cra_init(struct crypto_tfm *tfm) |
682 | { | |
a3485e68 JF |
683 | struct omap_aes_dev *dd = NULL; |
684 | ||
685 | /* Find AES device, currently picks the first device */ | |
686 | spin_lock_bh(&list_lock); | |
687 | list_for_each_entry(dd, &dev_list, list) { | |
688 | break; | |
689 | } | |
690 | spin_unlock_bh(&list_lock); | |
537559a5 | 691 | |
a3485e68 | 692 | pm_runtime_get_sync(dd->dev); |
537559a5 DK |
693 | tfm->crt_ablkcipher.reqsize = sizeof(struct omap_aes_reqctx); |
694 | ||
695 | return 0; | |
696 | } | |
697 | ||
698 | static void omap_aes_cra_exit(struct crypto_tfm *tfm) | |
699 | { | |
a3485e68 JF |
700 | struct omap_aes_dev *dd = NULL; |
701 | ||
702 | /* Find AES device, currently picks the first device */ | |
703 | spin_lock_bh(&list_lock); | |
704 | list_for_each_entry(dd, &dev_list, list) { | |
705 | break; | |
706 | } | |
707 | spin_unlock_bh(&list_lock); | |
708 | ||
709 | pm_runtime_put_sync(dd->dev); | |
537559a5 DK |
710 | } |
711 | ||
712 | /* ********************** ALGS ************************************ */ | |
713 | ||
f9fb69e7 | 714 | static struct crypto_alg algs_ecb_cbc[] = { |
537559a5 DK |
715 | { |
716 | .cra_name = "ecb(aes)", | |
717 | .cra_driver_name = "ecb-aes-omap", | |
718 | .cra_priority = 100, | |
d912bb76 NM |
719 | .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | |
720 | CRYPTO_ALG_KERN_DRIVER_ONLY | | |
721 | CRYPTO_ALG_ASYNC, | |
537559a5 DK |
722 | .cra_blocksize = AES_BLOCK_SIZE, |
723 | .cra_ctxsize = sizeof(struct omap_aes_ctx), | |
efce41b6 | 724 | .cra_alignmask = 0, |
537559a5 DK |
725 | .cra_type = &crypto_ablkcipher_type, |
726 | .cra_module = THIS_MODULE, | |
727 | .cra_init = omap_aes_cra_init, | |
728 | .cra_exit = omap_aes_cra_exit, | |
729 | .cra_u.ablkcipher = { | |
730 | .min_keysize = AES_MIN_KEY_SIZE, | |
731 | .max_keysize = AES_MAX_KEY_SIZE, | |
732 | .setkey = omap_aes_setkey, | |
733 | .encrypt = omap_aes_ecb_encrypt, | |
734 | .decrypt = omap_aes_ecb_decrypt, | |
735 | } | |
736 | }, | |
737 | { | |
738 | .cra_name = "cbc(aes)", | |
739 | .cra_driver_name = "cbc-aes-omap", | |
740 | .cra_priority = 100, | |
d912bb76 NM |
741 | .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | |
742 | CRYPTO_ALG_KERN_DRIVER_ONLY | | |
743 | CRYPTO_ALG_ASYNC, | |
537559a5 DK |
744 | .cra_blocksize = AES_BLOCK_SIZE, |
745 | .cra_ctxsize = sizeof(struct omap_aes_ctx), | |
efce41b6 | 746 | .cra_alignmask = 0, |
537559a5 DK |
747 | .cra_type = &crypto_ablkcipher_type, |
748 | .cra_module = THIS_MODULE, | |
749 | .cra_init = omap_aes_cra_init, | |
750 | .cra_exit = omap_aes_cra_exit, | |
751 | .cra_u.ablkcipher = { | |
752 | .min_keysize = AES_MIN_KEY_SIZE, | |
753 | .max_keysize = AES_MAX_KEY_SIZE, | |
754 | .ivsize = AES_BLOCK_SIZE, | |
755 | .setkey = omap_aes_setkey, | |
756 | .encrypt = omap_aes_cbc_encrypt, | |
757 | .decrypt = omap_aes_cbc_decrypt, | |
758 | } | |
759 | } | |
760 | }; | |
761 | ||
f9fb69e7 MG |
762 | static struct crypto_alg algs_ctr[] = { |
763 | { | |
764 | .cra_name = "ctr(aes)", | |
765 | .cra_driver_name = "ctr-aes-omap", | |
766 | .cra_priority = 100, | |
767 | .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | | |
768 | CRYPTO_ALG_KERN_DRIVER_ONLY | | |
769 | CRYPTO_ALG_ASYNC, | |
770 | .cra_blocksize = AES_BLOCK_SIZE, | |
771 | .cra_ctxsize = sizeof(struct omap_aes_ctx), | |
772 | .cra_alignmask = 0, | |
773 | .cra_type = &crypto_ablkcipher_type, | |
774 | .cra_module = THIS_MODULE, | |
775 | .cra_init = omap_aes_cra_init, | |
776 | .cra_exit = omap_aes_cra_exit, | |
777 | .cra_u.ablkcipher = { | |
778 | .min_keysize = AES_MIN_KEY_SIZE, | |
779 | .max_keysize = AES_MAX_KEY_SIZE, | |
780 | .geniv = "eseqiv", | |
781 | .ivsize = AES_BLOCK_SIZE, | |
782 | .setkey = omap_aes_setkey, | |
783 | .encrypt = omap_aes_ctr_encrypt, | |
784 | .decrypt = omap_aes_ctr_decrypt, | |
785 | } | |
786 | } , | |
787 | }; | |
788 | ||
789 | static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc[] = { | |
790 | { | |
791 | .algs_list = algs_ecb_cbc, | |
792 | .size = ARRAY_SIZE(algs_ecb_cbc), | |
793 | }, | |
794 | }; | |
795 | ||
0d35583a | 796 | static const struct omap_aes_pdata omap_aes_pdata_omap2 = { |
f9fb69e7 MG |
797 | .algs_info = omap_aes_algs_info_ecb_cbc, |
798 | .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc), | |
0d35583a MG |
799 | .trigger = omap_aes_dma_trigger_omap2, |
800 | .key_ofs = 0x1c, | |
801 | .iv_ofs = 0x20, | |
802 | .ctrl_ofs = 0x30, | |
803 | .data_ofs = 0x34, | |
804 | .rev_ofs = 0x44, | |
805 | .mask_ofs = 0x48, | |
806 | .dma_enable_in = BIT(2), | |
807 | .dma_enable_out = BIT(3), | |
808 | .dma_start = BIT(5), | |
809 | .major_mask = 0xf0, | |
810 | .major_shift = 4, | |
811 | .minor_mask = 0x0f, | |
812 | .minor_shift = 0, | |
813 | }; | |
814 | ||
bc69d124 | 815 | #ifdef CONFIG_OF |
f9fb69e7 MG |
816 | static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc_ctr[] = { |
817 | { | |
818 | .algs_list = algs_ecb_cbc, | |
819 | .size = ARRAY_SIZE(algs_ecb_cbc), | |
820 | }, | |
821 | { | |
822 | .algs_list = algs_ctr, | |
823 | .size = ARRAY_SIZE(algs_ctr), | |
824 | }, | |
825 | }; | |
826 | ||
827 | static const struct omap_aes_pdata omap_aes_pdata_omap3 = { | |
828 | .algs_info = omap_aes_algs_info_ecb_cbc_ctr, | |
829 | .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr), | |
830 | .trigger = omap_aes_dma_trigger_omap2, | |
831 | .key_ofs = 0x1c, | |
832 | .iv_ofs = 0x20, | |
833 | .ctrl_ofs = 0x30, | |
834 | .data_ofs = 0x34, | |
835 | .rev_ofs = 0x44, | |
836 | .mask_ofs = 0x48, | |
837 | .dma_enable_in = BIT(2), | |
838 | .dma_enable_out = BIT(3), | |
839 | .dma_start = BIT(5), | |
840 | .major_mask = 0xf0, | |
841 | .major_shift = 4, | |
842 | .minor_mask = 0x0f, | |
843 | .minor_shift = 0, | |
844 | }; | |
845 | ||
0d35583a | 846 | static const struct omap_aes_pdata omap_aes_pdata_omap4 = { |
f9fb69e7 MG |
847 | .algs_info = omap_aes_algs_info_ecb_cbc_ctr, |
848 | .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr), | |
0d35583a MG |
849 | .trigger = omap_aes_dma_trigger_omap4, |
850 | .key_ofs = 0x3c, | |
851 | .iv_ofs = 0x40, | |
852 | .ctrl_ofs = 0x50, | |
853 | .data_ofs = 0x60, | |
854 | .rev_ofs = 0x80, | |
855 | .mask_ofs = 0x84, | |
67216756 JF |
856 | .irq_status_ofs = 0x8c, |
857 | .irq_enable_ofs = 0x90, | |
0d35583a MG |
858 | .dma_enable_in = BIT(5), |
859 | .dma_enable_out = BIT(6), | |
860 | .major_mask = 0x0700, | |
861 | .major_shift = 8, | |
862 | .minor_mask = 0x003f, | |
863 | .minor_shift = 0, | |
864 | }; | |
865 | ||
bc69d124 MG |
866 | static const struct of_device_id omap_aes_of_match[] = { |
867 | { | |
868 | .compatible = "ti,omap2-aes", | |
0d35583a MG |
869 | .data = &omap_aes_pdata_omap2, |
870 | }, | |
f9fb69e7 MG |
871 | { |
872 | .compatible = "ti,omap3-aes", | |
873 | .data = &omap_aes_pdata_omap3, | |
874 | }, | |
0d35583a MG |
875 | { |
876 | .compatible = "ti,omap4-aes", | |
877 | .data = &omap_aes_pdata_omap4, | |
bc69d124 MG |
878 | }, |
879 | {}, | |
880 | }; | |
881 | MODULE_DEVICE_TABLE(of, omap_aes_of_match); | |
882 | ||
883 | static int omap_aes_get_res_of(struct omap_aes_dev *dd, | |
884 | struct device *dev, struct resource *res) | |
885 | { | |
886 | struct device_node *node = dev->of_node; | |
887 | const struct of_device_id *match; | |
888 | int err = 0; | |
889 | ||
890 | match = of_match_device(of_match_ptr(omap_aes_of_match), dev); | |
891 | if (!match) { | |
892 | dev_err(dev, "no compatible OF match\n"); | |
893 | err = -EINVAL; | |
894 | goto err; | |
895 | } | |
896 | ||
897 | err = of_address_to_resource(node, 0, res); | |
898 | if (err < 0) { | |
899 | dev_err(dev, "can't translate OF node address\n"); | |
900 | err = -EINVAL; | |
901 | goto err; | |
902 | } | |
903 | ||
904 | dd->dma_out = -1; /* Dummy value that's unused */ | |
905 | dd->dma_in = -1; /* Dummy value that's unused */ | |
906 | ||
0d35583a MG |
907 | dd->pdata = match->data; |
908 | ||
bc69d124 MG |
909 | err: |
910 | return err; | |
911 | } | |
912 | #else | |
913 | static const struct of_device_id omap_aes_of_match[] = { | |
914 | {}, | |
915 | }; | |
916 | ||
917 | static int omap_aes_get_res_of(struct omap_aes_dev *dd, | |
918 | struct device *dev, struct resource *res) | |
919 | { | |
920 | return -EINVAL; | |
921 | } | |
922 | #endif | |
923 | ||
924 | static int omap_aes_get_res_pdev(struct omap_aes_dev *dd, | |
925 | struct platform_device *pdev, struct resource *res) | |
926 | { | |
927 | struct device *dev = &pdev->dev; | |
928 | struct resource *r; | |
929 | int err = 0; | |
930 | ||
931 | /* Get the base address */ | |
932 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
933 | if (!r) { | |
934 | dev_err(dev, "no MEM resource info\n"); | |
935 | err = -ENODEV; | |
936 | goto err; | |
937 | } | |
938 | memcpy(res, r, sizeof(*res)); | |
939 | ||
940 | /* Get the DMA out channel */ | |
941 | r = platform_get_resource(pdev, IORESOURCE_DMA, 0); | |
942 | if (!r) { | |
943 | dev_err(dev, "no DMA out resource info\n"); | |
944 | err = -ENODEV; | |
945 | goto err; | |
946 | } | |
947 | dd->dma_out = r->start; | |
948 | ||
949 | /* Get the DMA in channel */ | |
950 | r = platform_get_resource(pdev, IORESOURCE_DMA, 1); | |
951 | if (!r) { | |
952 | dev_err(dev, "no DMA in resource info\n"); | |
953 | err = -ENODEV; | |
954 | goto err; | |
955 | } | |
956 | dd->dma_in = r->start; | |
957 | ||
0d35583a MG |
958 | /* Only OMAP2/3 can be non-DT */ |
959 | dd->pdata = &omap_aes_pdata_omap2; | |
960 | ||
bc69d124 MG |
961 | err: |
962 | return err; | |
963 | } | |
964 | ||
537559a5 DK |
965 | static int omap_aes_probe(struct platform_device *pdev) |
966 | { | |
967 | struct device *dev = &pdev->dev; | |
968 | struct omap_aes_dev *dd; | |
f9fb69e7 | 969 | struct crypto_alg *algp; |
bc69d124 | 970 | struct resource res; |
537559a5 DK |
971 | int err = -ENOMEM, i, j; |
972 | u32 reg; | |
973 | ||
974 | dd = kzalloc(sizeof(struct omap_aes_dev), GFP_KERNEL); | |
975 | if (dd == NULL) { | |
976 | dev_err(dev, "unable to alloc data struct.\n"); | |
977 | goto err_data; | |
978 | } | |
979 | dd->dev = dev; | |
980 | platform_set_drvdata(pdev, dd); | |
981 | ||
982 | spin_lock_init(&dd->lock); | |
983 | crypto_init_queue(&dd->queue, OMAP_AES_QUEUE_LENGTH); | |
984 | ||
bc69d124 MG |
985 | err = (dev->of_node) ? omap_aes_get_res_of(dd, dev, &res) : |
986 | omap_aes_get_res_pdev(dd, pdev, &res); | |
987 | if (err) | |
537559a5 | 988 | goto err_res; |
bc69d124 | 989 | |
30862281 LN |
990 | dd->io_base = devm_ioremap_resource(dev, &res); |
991 | if (IS_ERR(dd->io_base)) { | |
992 | err = PTR_ERR(dd->io_base); | |
5946c4a5 | 993 | goto err_res; |
537559a5 | 994 | } |
bc69d124 | 995 | dd->phys_base = res.start; |
537559a5 | 996 | |
5946c4a5 MG |
997 | pm_runtime_enable(dev); |
998 | pm_runtime_get_sync(dev); | |
999 | ||
0d35583a MG |
1000 | omap_aes_dma_stop(dd); |
1001 | ||
1002 | reg = omap_aes_read(dd, AES_REG_REV(dd)); | |
5946c4a5 MG |
1003 | |
1004 | pm_runtime_put_sync(dev); | |
537559a5 | 1005 | |
0d35583a MG |
1006 | dev_info(dev, "OMAP AES hw accel rev: %u.%u\n", |
1007 | (reg & dd->pdata->major_mask) >> dd->pdata->major_shift, | |
1008 | (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift); | |
1009 | ||
21fe9767 DK |
1010 | tasklet_init(&dd->done_task, omap_aes_done_task, (unsigned long)dd); |
1011 | tasklet_init(&dd->queue_task, omap_aes_queue_task, (unsigned long)dd); | |
537559a5 DK |
1012 | |
1013 | err = omap_aes_dma_init(dd); | |
1014 | if (err) | |
1015 | goto err_dma; | |
1016 | ||
1017 | INIT_LIST_HEAD(&dd->list); | |
1018 | spin_lock(&list_lock); | |
1019 | list_add_tail(&dd->list, &dev_list); | |
1020 | spin_unlock(&list_lock); | |
1021 | ||
f9fb69e7 MG |
1022 | for (i = 0; i < dd->pdata->algs_info_size; i++) { |
1023 | for (j = 0; j < dd->pdata->algs_info[i].size; j++) { | |
1024 | algp = &dd->pdata->algs_info[i].algs_list[j]; | |
1025 | ||
1026 | pr_debug("reg alg: %s\n", algp->cra_name); | |
1027 | INIT_LIST_HEAD(&algp->cra_list); | |
1028 | ||
1029 | err = crypto_register_alg(algp); | |
1030 | if (err) | |
1031 | goto err_algs; | |
1032 | ||
1033 | dd->pdata->algs_info[i].registered++; | |
1034 | } | |
537559a5 DK |
1035 | } |
1036 | ||
537559a5 DK |
1037 | return 0; |
1038 | err_algs: | |
f9fb69e7 MG |
1039 | for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) |
1040 | for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) | |
1041 | crypto_unregister_alg( | |
1042 | &dd->pdata->algs_info[i].algs_list[j]); | |
537559a5 DK |
1043 | omap_aes_dma_cleanup(dd); |
1044 | err_dma: | |
21fe9767 DK |
1045 | tasklet_kill(&dd->done_task); |
1046 | tasklet_kill(&dd->queue_task); | |
5946c4a5 | 1047 | pm_runtime_disable(dev); |
537559a5 DK |
1048 | err_res: |
1049 | kfree(dd); | |
1050 | dd = NULL; | |
1051 | err_data: | |
1052 | dev_err(dev, "initialization failed.\n"); | |
1053 | return err; | |
1054 | } | |
1055 | ||
1056 | static int omap_aes_remove(struct platform_device *pdev) | |
1057 | { | |
1058 | struct omap_aes_dev *dd = platform_get_drvdata(pdev); | |
f9fb69e7 | 1059 | int i, j; |
537559a5 DK |
1060 | |
1061 | if (!dd) | |
1062 | return -ENODEV; | |
1063 | ||
1064 | spin_lock(&list_lock); | |
1065 | list_del(&dd->list); | |
1066 | spin_unlock(&list_lock); | |
1067 | ||
f9fb69e7 MG |
1068 | for (i = dd->pdata->algs_info_size - 1; i >= 0; i--) |
1069 | for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) | |
1070 | crypto_unregister_alg( | |
1071 | &dd->pdata->algs_info[i].algs_list[j]); | |
537559a5 | 1072 | |
21fe9767 DK |
1073 | tasklet_kill(&dd->done_task); |
1074 | tasklet_kill(&dd->queue_task); | |
537559a5 | 1075 | omap_aes_dma_cleanup(dd); |
5946c4a5 | 1076 | pm_runtime_disable(dd->dev); |
537559a5 DK |
1077 | kfree(dd); |
1078 | dd = NULL; | |
1079 | ||
1080 | return 0; | |
1081 | } | |
1082 | ||
0635fb3a MG |
1083 | #ifdef CONFIG_PM_SLEEP |
1084 | static int omap_aes_suspend(struct device *dev) | |
1085 | { | |
1086 | pm_runtime_put_sync(dev); | |
1087 | return 0; | |
1088 | } | |
1089 | ||
1090 | static int omap_aes_resume(struct device *dev) | |
1091 | { | |
1092 | pm_runtime_get_sync(dev); | |
1093 | return 0; | |
1094 | } | |
1095 | #endif | |
1096 | ||
1097 | static const struct dev_pm_ops omap_aes_pm_ops = { | |
1098 | SET_SYSTEM_SLEEP_PM_OPS(omap_aes_suspend, omap_aes_resume) | |
1099 | }; | |
1100 | ||
537559a5 DK |
1101 | static struct platform_driver omap_aes_driver = { |
1102 | .probe = omap_aes_probe, | |
1103 | .remove = omap_aes_remove, | |
1104 | .driver = { | |
1105 | .name = "omap-aes", | |
1106 | .owner = THIS_MODULE, | |
0635fb3a | 1107 | .pm = &omap_aes_pm_ops, |
bc69d124 | 1108 | .of_match_table = omap_aes_of_match, |
537559a5 DK |
1109 | }, |
1110 | }; | |
1111 | ||
94e51df9 | 1112 | module_platform_driver(omap_aes_driver); |
537559a5 DK |
1113 | |
1114 | MODULE_DESCRIPTION("OMAP AES hw acceleration support."); | |
1115 | MODULE_LICENSE("GPL v2"); | |
1116 | MODULE_AUTHOR("Dmitry Kasatkin"); | |
1117 |