Commit | Line | Data |
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8628e7c8 DK |
1 | /* |
2 | * Cryptographic API. | |
3 | * | |
4 | * Support for OMAP SHA1/MD5 HW acceleration. | |
5 | * | |
6 | * Copyright (c) 2010 Nokia Corporation | |
7 | * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com> | |
0d373d60 | 8 | * Copyright (c) 2011 Texas Instruments Incorporated |
8628e7c8 DK |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as published | |
12 | * by the Free Software Foundation. | |
13 | * | |
14 | * Some ideas are from old omap-sha1-md5.c driver. | |
15 | */ | |
16 | ||
17 | #define pr_fmt(fmt) "%s: " fmt, __func__ | |
18 | ||
8628e7c8 DK |
19 | #include <linux/err.h> |
20 | #include <linux/device.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/errno.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/kernel.h> | |
8628e7c8 DK |
26 | #include <linux/irq.h> |
27 | #include <linux/io.h> | |
28 | #include <linux/platform_device.h> | |
29 | #include <linux/scatterlist.h> | |
30 | #include <linux/dma-mapping.h> | |
dfd061d5 MG |
31 | #include <linux/dmaengine.h> |
32 | #include <linux/omap-dma.h> | |
b359f034 | 33 | #include <linux/pm_runtime.h> |
03feec9c MG |
34 | #include <linux/of.h> |
35 | #include <linux/of_device.h> | |
36 | #include <linux/of_address.h> | |
37 | #include <linux/of_irq.h> | |
8628e7c8 DK |
38 | #include <linux/delay.h> |
39 | #include <linux/crypto.h> | |
40 | #include <linux/cryptohash.h> | |
41 | #include <crypto/scatterwalk.h> | |
42 | #include <crypto/algapi.h> | |
43 | #include <crypto/sha.h> | |
44 | #include <crypto/hash.h> | |
45 | #include <crypto/internal/hash.h> | |
46 | ||
8628e7c8 DK |
47 | #define SHA1_MD5_BLOCK_SIZE SHA1_BLOCK_SIZE |
48 | #define MD5_DIGEST_SIZE 16 | |
49 | ||
dfd061d5 MG |
50 | #define DST_MAXBURST 16 |
51 | #define DMA_MIN (DST_MAXBURST * sizeof(u32)) | |
52 | ||
0d373d60 MG |
53 | #define SHA_REG_IDIGEST(dd, x) ((dd)->pdata->idigest_ofs + ((x)*0x04)) |
54 | #define SHA_REG_DIN(dd, x) ((dd)->pdata->din_ofs + ((x) * 0x04)) | |
55 | #define SHA_REG_DIGCNT(dd) ((dd)->pdata->digcnt_ofs) | |
56 | ||
57 | #define SHA_REG_ODIGEST(x) (0x00 + ((x) * 0x04)) | |
8628e7c8 DK |
58 | |
59 | #define SHA_REG_CTRL 0x18 | |
60 | #define SHA_REG_CTRL_LENGTH (0xFFFFFFFF << 5) | |
61 | #define SHA_REG_CTRL_CLOSE_HASH (1 << 4) | |
62 | #define SHA_REG_CTRL_ALGO_CONST (1 << 3) | |
63 | #define SHA_REG_CTRL_ALGO (1 << 2) | |
64 | #define SHA_REG_CTRL_INPUT_READY (1 << 1) | |
65 | #define SHA_REG_CTRL_OUTPUT_READY (1 << 0) | |
66 | ||
0d373d60 | 67 | #define SHA_REG_REV(dd) ((dd)->pdata->rev_ofs) |
8628e7c8 | 68 | |
0d373d60 | 69 | #define SHA_REG_MASK(dd) ((dd)->pdata->mask_ofs) |
8628e7c8 DK |
70 | #define SHA_REG_MASK_DMA_EN (1 << 3) |
71 | #define SHA_REG_MASK_IT_EN (1 << 2) | |
72 | #define SHA_REG_MASK_SOFTRESET (1 << 1) | |
73 | #define SHA_REG_AUTOIDLE (1 << 0) | |
74 | ||
0d373d60 | 75 | #define SHA_REG_SYSSTATUS(dd) ((dd)->pdata->sysstatus_ofs) |
8628e7c8 DK |
76 | #define SHA_REG_SYSSTATUS_RESETDONE (1 << 0) |
77 | ||
0d373d60 MG |
78 | #define SHA_REG_MODE 0x44 |
79 | #define SHA_REG_MODE_HMAC_OUTER_HASH (1 << 7) | |
80 | #define SHA_REG_MODE_HMAC_KEY_PROC (1 << 5) | |
81 | #define SHA_REG_MODE_CLOSE_HASH (1 << 4) | |
82 | #define SHA_REG_MODE_ALGO_CONSTANT (1 << 3) | |
83 | #define SHA_REG_MODE_ALGO_MASK (3 << 1) | |
84 | #define SHA_REG_MODE_ALGO_MD5_128 (0 << 1) | |
85 | #define SHA_REG_MODE_ALGO_SHA1_160 (1 << 1) | |
86 | ||
87 | #define SHA_REG_LENGTH 0x48 | |
88 | ||
89 | #define SHA_REG_IRQSTATUS 0x118 | |
90 | #define SHA_REG_IRQSTATUS_CTX_RDY (1 << 3) | |
91 | #define SHA_REG_IRQSTATUS_PARTHASH_RDY (1 << 2) | |
92 | #define SHA_REG_IRQSTATUS_INPUT_RDY (1 << 1) | |
93 | #define SHA_REG_IRQSTATUS_OUTPUT_RDY (1 << 0) | |
94 | ||
95 | #define SHA_REG_IRQENA 0x11C | |
96 | #define SHA_REG_IRQENA_CTX_RDY (1 << 3) | |
97 | #define SHA_REG_IRQENA_PARTHASH_RDY (1 << 2) | |
98 | #define SHA_REG_IRQENA_INPUT_RDY (1 << 1) | |
99 | #define SHA_REG_IRQENA_OUTPUT_RDY (1 << 0) | |
100 | ||
8628e7c8 DK |
101 | #define DEFAULT_TIMEOUT_INTERVAL HZ |
102 | ||
ea1fd224 DK |
103 | /* mostly device flags */ |
104 | #define FLAGS_BUSY 0 | |
105 | #define FLAGS_FINAL 1 | |
106 | #define FLAGS_DMA_ACTIVE 2 | |
107 | #define FLAGS_OUTPUT_READY 3 | |
108 | #define FLAGS_INIT 4 | |
109 | #define FLAGS_CPU 5 | |
6c63db82 | 110 | #define FLAGS_DMA_READY 6 |
0d373d60 MG |
111 | #define FLAGS_AUTO_XOR 7 |
112 | #define FLAGS_BE32_SHA1 8 | |
ea1fd224 DK |
113 | /* context flags */ |
114 | #define FLAGS_FINUP 16 | |
115 | #define FLAGS_SG 17 | |
8628e7c8 | 116 | |
0d373d60 MG |
117 | #define FLAGS_MODE_SHIFT 18 |
118 | #define FLAGS_MODE_MASK (SHA_REG_MODE_ALGO_MASK \ | |
119 | << (FLAGS_MODE_SHIFT - 1)) | |
120 | #define FLAGS_MODE_MD5 (SHA_REG_MODE_ALGO_MD5_128 \ | |
121 | << (FLAGS_MODE_SHIFT - 1)) | |
122 | #define FLAGS_MODE_SHA1 (SHA_REG_MODE_ALGO_SHA1_160 \ | |
123 | << (FLAGS_MODE_SHIFT - 1)) | |
124 | #define FLAGS_HMAC 20 | |
125 | #define FLAGS_ERROR 21 | |
126 | ||
127 | #define OP_UPDATE 1 | |
128 | #define OP_FINAL 2 | |
8628e7c8 | 129 | |
798eed5d DK |
130 | #define OMAP_ALIGN_MASK (sizeof(u32)-1) |
131 | #define OMAP_ALIGNED __attribute__((aligned(sizeof(u32)))) | |
132 | ||
0d373d60 | 133 | #define BUFLEN PAGE_SIZE |
798eed5d | 134 | |
8628e7c8 DK |
135 | struct omap_sham_dev; |
136 | ||
137 | struct omap_sham_reqctx { | |
138 | struct omap_sham_dev *dd; | |
139 | unsigned long flags; | |
140 | unsigned long op; | |
141 | ||
0d373d60 | 142 | u8 digest[SHA256_DIGEST_SIZE] OMAP_ALIGNED; |
8628e7c8 | 143 | size_t digcnt; |
8628e7c8 DK |
144 | size_t bufcnt; |
145 | size_t buflen; | |
146 | dma_addr_t dma_addr; | |
147 | ||
148 | /* walk state */ | |
149 | struct scatterlist *sg; | |
dfd061d5 | 150 | struct scatterlist sgl; |
8628e7c8 DK |
151 | unsigned int offset; /* offset in current sg */ |
152 | unsigned int total; /* total request */ | |
798eed5d DK |
153 | |
154 | u8 buffer[0] OMAP_ALIGNED; | |
8628e7c8 DK |
155 | }; |
156 | ||
157 | struct omap_sham_hmac_ctx { | |
158 | struct crypto_shash *shash; | |
0d373d60 MG |
159 | u8 ipad[SHA1_MD5_BLOCK_SIZE] OMAP_ALIGNED; |
160 | u8 opad[SHA1_MD5_BLOCK_SIZE] OMAP_ALIGNED; | |
8628e7c8 DK |
161 | }; |
162 | ||
163 | struct omap_sham_ctx { | |
164 | struct omap_sham_dev *dd; | |
165 | ||
166 | unsigned long flags; | |
167 | ||
168 | /* fallback stuff */ | |
169 | struct crypto_shash *fallback; | |
170 | ||
171 | struct omap_sham_hmac_ctx base[0]; | |
172 | }; | |
173 | ||
174 | #define OMAP_SHAM_QUEUE_LENGTH 1 | |
175 | ||
0d373d60 MG |
176 | struct omap_sham_pdata { |
177 | unsigned long flags; | |
178 | int digest_size; | |
179 | ||
180 | void (*copy_hash)(struct ahash_request *req, int out); | |
181 | void (*write_ctrl)(struct omap_sham_dev *dd, size_t length, | |
182 | int final, int dma); | |
183 | void (*trigger)(struct omap_sham_dev *dd, size_t length); | |
184 | int (*poll_irq)(struct omap_sham_dev *dd); | |
185 | irqreturn_t (*intr_hdlr)(int irq, void *dev_id); | |
186 | ||
187 | u32 odigest_ofs; | |
188 | u32 idigest_ofs; | |
189 | u32 din_ofs; | |
190 | u32 digcnt_ofs; | |
191 | u32 rev_ofs; | |
192 | u32 mask_ofs; | |
193 | u32 sysstatus_ofs; | |
194 | ||
195 | u32 major_mask; | |
196 | u32 major_shift; | |
197 | u32 minor_mask; | |
198 | u32 minor_shift; | |
199 | }; | |
200 | ||
8628e7c8 DK |
201 | struct omap_sham_dev { |
202 | struct list_head list; | |
203 | unsigned long phys_base; | |
204 | struct device *dev; | |
205 | void __iomem *io_base; | |
206 | int irq; | |
8628e7c8 | 207 | spinlock_t lock; |
3e133c8b | 208 | int err; |
03feec9c | 209 | unsigned int dma; |
dfd061d5 | 210 | struct dma_chan *dma_lch; |
8628e7c8 | 211 | struct tasklet_struct done_task; |
8628e7c8 DK |
212 | |
213 | unsigned long flags; | |
214 | struct crypto_queue queue; | |
215 | struct ahash_request *req; | |
0d373d60 MG |
216 | |
217 | const struct omap_sham_pdata *pdata; | |
8628e7c8 DK |
218 | }; |
219 | ||
220 | struct omap_sham_drv { | |
221 | struct list_head dev_list; | |
222 | spinlock_t lock; | |
223 | unsigned long flags; | |
224 | }; | |
225 | ||
226 | static struct omap_sham_drv sham = { | |
227 | .dev_list = LIST_HEAD_INIT(sham.dev_list), | |
228 | .lock = __SPIN_LOCK_UNLOCKED(sham.lock), | |
229 | }; | |
230 | ||
231 | static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset) | |
232 | { | |
233 | return __raw_readl(dd->io_base + offset); | |
234 | } | |
235 | ||
236 | static inline void omap_sham_write(struct omap_sham_dev *dd, | |
237 | u32 offset, u32 value) | |
238 | { | |
239 | __raw_writel(value, dd->io_base + offset); | |
240 | } | |
241 | ||
242 | static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address, | |
243 | u32 value, u32 mask) | |
244 | { | |
245 | u32 val; | |
246 | ||
247 | val = omap_sham_read(dd, address); | |
248 | val &= ~mask; | |
249 | val |= value; | |
250 | omap_sham_write(dd, address, val); | |
251 | } | |
252 | ||
253 | static inline int omap_sham_wait(struct omap_sham_dev *dd, u32 offset, u32 bit) | |
254 | { | |
255 | unsigned long timeout = jiffies + DEFAULT_TIMEOUT_INTERVAL; | |
256 | ||
257 | while (!(omap_sham_read(dd, offset) & bit)) { | |
258 | if (time_is_before_jiffies(timeout)) | |
259 | return -ETIMEDOUT; | |
260 | } | |
261 | ||
262 | return 0; | |
263 | } | |
264 | ||
0d373d60 | 265 | static void omap_sham_copy_hash_omap2(struct ahash_request *req, int out) |
8628e7c8 DK |
266 | { |
267 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
0d373d60 | 268 | struct omap_sham_dev *dd = ctx->dd; |
0c3cf4cc | 269 | u32 *hash = (u32 *)ctx->digest; |
8628e7c8 DK |
270 | int i; |
271 | ||
0d373d60 | 272 | for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) { |
3c8d758a | 273 | if (out) |
0d373d60 | 274 | hash[i] = omap_sham_read(dd, SHA_REG_IDIGEST(dd, i)); |
3c8d758a | 275 | else |
0d373d60 MG |
276 | omap_sham_write(dd, SHA_REG_IDIGEST(dd, i), hash[i]); |
277 | } | |
278 | } | |
279 | ||
280 | static void omap_sham_copy_hash_omap4(struct ahash_request *req, int out) | |
281 | { | |
282 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
283 | struct omap_sham_dev *dd = ctx->dd; | |
284 | int i; | |
285 | ||
286 | if (ctx->flags & BIT(FLAGS_HMAC)) { | |
287 | struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req); | |
288 | struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm); | |
289 | struct omap_sham_hmac_ctx *bctx = tctx->base; | |
290 | u32 *opad = (u32 *)bctx->opad; | |
291 | ||
292 | for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) { | |
293 | if (out) | |
294 | opad[i] = omap_sham_read(dd, | |
295 | SHA_REG_ODIGEST(i)); | |
296 | else | |
297 | omap_sham_write(dd, SHA_REG_ODIGEST(i), | |
298 | opad[i]); | |
299 | } | |
3c8d758a | 300 | } |
0d373d60 MG |
301 | |
302 | omap_sham_copy_hash_omap2(req, out); | |
3c8d758a DK |
303 | } |
304 | ||
305 | static void omap_sham_copy_ready_hash(struct ahash_request *req) | |
306 | { | |
307 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
308 | u32 *in = (u32 *)ctx->digest; | |
309 | u32 *hash = (u32 *)req->result; | |
0d373d60 | 310 | int i, d, big_endian = 0; |
3c8d758a DK |
311 | |
312 | if (!hash) | |
313 | return; | |
314 | ||
0d373d60 MG |
315 | switch (ctx->flags & FLAGS_MODE_MASK) { |
316 | case FLAGS_MODE_MD5: | |
317 | d = MD5_DIGEST_SIZE / sizeof(u32); | |
318 | break; | |
319 | case FLAGS_MODE_SHA1: | |
320 | /* OMAP2 SHA1 is big endian */ | |
321 | if (test_bit(FLAGS_BE32_SHA1, &ctx->dd->flags)) | |
322 | big_endian = 1; | |
323 | d = SHA1_DIGEST_SIZE / sizeof(u32); | |
324 | break; | |
325 | default: | |
326 | d = 0; | |
327 | } | |
328 | ||
329 | if (big_endian) | |
330 | for (i = 0; i < d; i++) | |
3c8d758a | 331 | hash[i] = be32_to_cpu(in[i]); |
0d373d60 MG |
332 | else |
333 | for (i = 0; i < d; i++) | |
3c8d758a | 334 | hash[i] = le32_to_cpu(in[i]); |
8628e7c8 DK |
335 | } |
336 | ||
798eed5d | 337 | static int omap_sham_hw_init(struct omap_sham_dev *dd) |
8628e7c8 | 338 | { |
b359f034 | 339 | pm_runtime_get_sync(dd->dev); |
8628e7c8 | 340 | |
a929cbee | 341 | if (!test_bit(FLAGS_INIT, &dd->flags)) { |
a929cbee | 342 | set_bit(FLAGS_INIT, &dd->flags); |
798eed5d DK |
343 | dd->err = 0; |
344 | } | |
8628e7c8 | 345 | |
798eed5d DK |
346 | return 0; |
347 | } | |
348 | ||
0d373d60 | 349 | static void omap_sham_write_ctrl_omap2(struct omap_sham_dev *dd, size_t length, |
798eed5d DK |
350 | int final, int dma) |
351 | { | |
352 | struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); | |
353 | u32 val = length << 5, mask; | |
354 | ||
355 | if (likely(ctx->digcnt)) | |
0d373d60 | 356 | omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt); |
8628e7c8 | 357 | |
0d373d60 | 358 | omap_sham_write_mask(dd, SHA_REG_MASK(dd), |
8628e7c8 DK |
359 | SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0), |
360 | SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN); | |
361 | /* | |
362 | * Setting ALGO_CONST only for the first iteration | |
363 | * and CLOSE_HASH only for the last one. | |
364 | */ | |
0d373d60 | 365 | if ((ctx->flags & FLAGS_MODE_MASK) == FLAGS_MODE_SHA1) |
8628e7c8 DK |
366 | val |= SHA_REG_CTRL_ALGO; |
367 | if (!ctx->digcnt) | |
368 | val |= SHA_REG_CTRL_ALGO_CONST; | |
369 | if (final) | |
370 | val |= SHA_REG_CTRL_CLOSE_HASH; | |
371 | ||
372 | mask = SHA_REG_CTRL_ALGO_CONST | SHA_REG_CTRL_CLOSE_HASH | | |
373 | SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH; | |
374 | ||
375 | omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask); | |
8628e7c8 DK |
376 | } |
377 | ||
0d373d60 MG |
378 | static void omap_sham_trigger_omap2(struct omap_sham_dev *dd, size_t length) |
379 | { | |
380 | } | |
381 | ||
382 | static int omap_sham_poll_irq_omap2(struct omap_sham_dev *dd) | |
383 | { | |
384 | return omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY); | |
385 | } | |
386 | ||
387 | static void omap_sham_write_n(struct omap_sham_dev *dd, u32 offset, | |
388 | u32 *value, int count) | |
389 | { | |
390 | for (; count--; value++, offset += 4) | |
391 | omap_sham_write(dd, offset, *value); | |
392 | } | |
393 | ||
394 | static void omap_sham_write_ctrl_omap4(struct omap_sham_dev *dd, size_t length, | |
395 | int final, int dma) | |
396 | { | |
397 | struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); | |
398 | u32 val, mask; | |
399 | ||
400 | /* | |
401 | * Setting ALGO_CONST only for the first iteration and | |
402 | * CLOSE_HASH only for the last one. Note that flags mode bits | |
403 | * correspond to algorithm encoding in mode register. | |
404 | */ | |
405 | val = (ctx->flags & FLAGS_MODE_MASK) >> (FLAGS_MODE_SHIFT - 1); | |
406 | if (!ctx->digcnt) { | |
407 | struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req); | |
408 | struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm); | |
409 | struct omap_sham_hmac_ctx *bctx = tctx->base; | |
410 | ||
411 | val |= SHA_REG_MODE_ALGO_CONSTANT; | |
412 | ||
413 | if (ctx->flags & BIT(FLAGS_HMAC)) { | |
414 | val |= SHA_REG_MODE_HMAC_KEY_PROC; | |
415 | omap_sham_write_n(dd, SHA_REG_ODIGEST(0), | |
416 | (u32 *)bctx->ipad, | |
417 | SHA1_BLOCK_SIZE / sizeof(u32)); | |
418 | ctx->digcnt += SHA1_BLOCK_SIZE; | |
419 | } | |
420 | } | |
421 | ||
422 | if (final) { | |
423 | val |= SHA_REG_MODE_CLOSE_HASH; | |
424 | ||
425 | if (ctx->flags & BIT(FLAGS_HMAC)) | |
426 | val |= SHA_REG_MODE_HMAC_OUTER_HASH; | |
427 | } | |
428 | ||
429 | mask = SHA_REG_MODE_ALGO_CONSTANT | SHA_REG_MODE_CLOSE_HASH | | |
430 | SHA_REG_MODE_ALGO_MASK | SHA_REG_MODE_HMAC_OUTER_HASH | | |
431 | SHA_REG_MODE_HMAC_KEY_PROC; | |
432 | ||
433 | dev_dbg(dd->dev, "ctrl: %08x, flags: %08lx\n", val, ctx->flags); | |
434 | omap_sham_write_mask(dd, SHA_REG_MODE, val, mask); | |
435 | omap_sham_write(dd, SHA_REG_IRQENA, SHA_REG_IRQENA_OUTPUT_RDY); | |
436 | omap_sham_write_mask(dd, SHA_REG_MASK(dd), | |
437 | SHA_REG_MASK_IT_EN | | |
438 | (dma ? SHA_REG_MASK_DMA_EN : 0), | |
439 | SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN); | |
440 | } | |
441 | ||
442 | static void omap_sham_trigger_omap4(struct omap_sham_dev *dd, size_t length) | |
443 | { | |
444 | omap_sham_write(dd, SHA_REG_LENGTH, length); | |
445 | } | |
446 | ||
447 | static int omap_sham_poll_irq_omap4(struct omap_sham_dev *dd) | |
448 | { | |
449 | return omap_sham_wait(dd, SHA_REG_IRQSTATUS, | |
450 | SHA_REG_IRQSTATUS_INPUT_RDY); | |
451 | } | |
452 | ||
8628e7c8 DK |
453 | static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, const u8 *buf, |
454 | size_t length, int final) | |
455 | { | |
456 | struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); | |
798eed5d | 457 | int count, len32; |
8628e7c8 DK |
458 | const u32 *buffer = (const u32 *)buf; |
459 | ||
460 | dev_dbg(dd->dev, "xmit_cpu: digcnt: %d, length: %d, final: %d\n", | |
461 | ctx->digcnt, length, final); | |
462 | ||
0d373d60 MG |
463 | dd->pdata->write_ctrl(dd, length, final, 0); |
464 | dd->pdata->trigger(dd, length); | |
8628e7c8 | 465 | |
3e133c8b DK |
466 | /* should be non-zero before next lines to disable clocks later */ |
467 | ctx->digcnt += length; | |
468 | ||
0d373d60 | 469 | if (dd->pdata->poll_irq(dd)) |
8628e7c8 DK |
470 | return -ETIMEDOUT; |
471 | ||
8628e7c8 | 472 | if (final) |
ed3ea9a8 | 473 | set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */ |
8628e7c8 | 474 | |
6c63db82 DK |
475 | set_bit(FLAGS_CPU, &dd->flags); |
476 | ||
8628e7c8 DK |
477 | len32 = DIV_ROUND_UP(length, sizeof(u32)); |
478 | ||
479 | for (count = 0; count < len32; count++) | |
0d373d60 | 480 | omap_sham_write(dd, SHA_REG_DIN(dd, count), buffer[count]); |
8628e7c8 DK |
481 | |
482 | return -EINPROGRESS; | |
483 | } | |
484 | ||
dfd061d5 MG |
485 | static void omap_sham_dma_callback(void *param) |
486 | { | |
487 | struct omap_sham_dev *dd = param; | |
488 | ||
489 | set_bit(FLAGS_DMA_READY, &dd->flags); | |
490 | tasklet_schedule(&dd->done_task); | |
491 | } | |
dfd061d5 | 492 | |
8628e7c8 | 493 | static int omap_sham_xmit_dma(struct omap_sham_dev *dd, dma_addr_t dma_addr, |
dfd061d5 | 494 | size_t length, int final, int is_sg) |
8628e7c8 DK |
495 | { |
496 | struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); | |
dfd061d5 MG |
497 | struct dma_async_tx_descriptor *tx; |
498 | struct dma_slave_config cfg; | |
499 | int len32, ret; | |
8628e7c8 DK |
500 | |
501 | dev_dbg(dd->dev, "xmit_dma: digcnt: %d, length: %d, final: %d\n", | |
502 | ctx->digcnt, length, final); | |
8628e7c8 | 503 | |
dfd061d5 MG |
504 | memset(&cfg, 0, sizeof(cfg)); |
505 | ||
0d373d60 | 506 | cfg.dst_addr = dd->phys_base + SHA_REG_DIN(dd, 0); |
dfd061d5 MG |
507 | cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
508 | cfg.dst_maxburst = DST_MAXBURST; | |
509 | ||
510 | ret = dmaengine_slave_config(dd->dma_lch, &cfg); | |
511 | if (ret) { | |
512 | pr_err("omap-sham: can't configure dmaengine slave: %d\n", ret); | |
513 | return ret; | |
514 | } | |
515 | ||
516 | len32 = DIV_ROUND_UP(length, DMA_MIN) * DMA_MIN; | |
517 | ||
518 | if (is_sg) { | |
519 | /* | |
520 | * The SG entry passed in may not have the 'length' member | |
521 | * set correctly so use a local SG entry (sgl) with the | |
522 | * proper value for 'length' instead. If this is not done, | |
523 | * the dmaengine may try to DMA the incorrect amount of data. | |
524 | */ | |
525 | sg_init_table(&ctx->sgl, 1); | |
526 | ctx->sgl.page_link = ctx->sg->page_link; | |
527 | ctx->sgl.offset = ctx->sg->offset; | |
528 | sg_dma_len(&ctx->sgl) = len32; | |
529 | sg_dma_address(&ctx->sgl) = sg_dma_address(ctx->sg); | |
530 | ||
531 | tx = dmaengine_prep_slave_sg(dd->dma_lch, &ctx->sgl, 1, | |
532 | DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
533 | } else { | |
534 | tx = dmaengine_prep_slave_single(dd->dma_lch, dma_addr, len32, | |
535 | DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
536 | } | |
537 | ||
538 | if (!tx) { | |
539 | dev_err(dd->dev, "prep_slave_sg/single() failed\n"); | |
540 | return -EINVAL; | |
541 | } | |
542 | ||
543 | tx->callback = omap_sham_dma_callback; | |
544 | tx->callback_param = dd; | |
dfd061d5 | 545 | |
0d373d60 | 546 | dd->pdata->write_ctrl(dd, length, final, 1); |
8628e7c8 DK |
547 | |
548 | ctx->digcnt += length; | |
549 | ||
550 | if (final) | |
ed3ea9a8 | 551 | set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */ |
8628e7c8 | 552 | |
a929cbee | 553 | set_bit(FLAGS_DMA_ACTIVE, &dd->flags); |
8628e7c8 | 554 | |
dfd061d5 MG |
555 | dmaengine_submit(tx); |
556 | dma_async_issue_pending(dd->dma_lch); | |
8628e7c8 | 557 | |
0d373d60 MG |
558 | dd->pdata->trigger(dd, length); |
559 | ||
8628e7c8 DK |
560 | return -EINPROGRESS; |
561 | } | |
562 | ||
563 | static size_t omap_sham_append_buffer(struct omap_sham_reqctx *ctx, | |
564 | const u8 *data, size_t length) | |
565 | { | |
566 | size_t count = min(length, ctx->buflen - ctx->bufcnt); | |
567 | ||
568 | count = min(count, ctx->total); | |
569 | if (count <= 0) | |
570 | return 0; | |
571 | memcpy(ctx->buffer + ctx->bufcnt, data, count); | |
572 | ctx->bufcnt += count; | |
573 | ||
574 | return count; | |
575 | } | |
576 | ||
577 | static size_t omap_sham_append_sg(struct omap_sham_reqctx *ctx) | |
578 | { | |
579 | size_t count; | |
580 | ||
581 | while (ctx->sg) { | |
582 | count = omap_sham_append_buffer(ctx, | |
583 | sg_virt(ctx->sg) + ctx->offset, | |
584 | ctx->sg->length - ctx->offset); | |
585 | if (!count) | |
586 | break; | |
587 | ctx->offset += count; | |
588 | ctx->total -= count; | |
589 | if (ctx->offset == ctx->sg->length) { | |
590 | ctx->sg = sg_next(ctx->sg); | |
591 | if (ctx->sg) | |
592 | ctx->offset = 0; | |
593 | else | |
594 | ctx->total = 0; | |
595 | } | |
596 | } | |
597 | ||
598 | return 0; | |
599 | } | |
600 | ||
798eed5d DK |
601 | static int omap_sham_xmit_dma_map(struct omap_sham_dev *dd, |
602 | struct omap_sham_reqctx *ctx, | |
603 | size_t length, int final) | |
604 | { | |
dfd061d5 MG |
605 | int ret; |
606 | ||
798eed5d DK |
607 | ctx->dma_addr = dma_map_single(dd->dev, ctx->buffer, ctx->buflen, |
608 | DMA_TO_DEVICE); | |
609 | if (dma_mapping_error(dd->dev, ctx->dma_addr)) { | |
610 | dev_err(dd->dev, "dma %u bytes error\n", ctx->buflen); | |
611 | return -EINVAL; | |
612 | } | |
613 | ||
ea1fd224 | 614 | ctx->flags &= ~BIT(FLAGS_SG); |
887c883e | 615 | |
dfd061d5 | 616 | ret = omap_sham_xmit_dma(dd, ctx->dma_addr, length, final, 0); |
0d373d60 | 617 | if (ret != -EINPROGRESS) |
dfd061d5 MG |
618 | dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen, |
619 | DMA_TO_DEVICE); | |
620 | ||
621 | return ret; | |
798eed5d DK |
622 | } |
623 | ||
8628e7c8 DK |
624 | static int omap_sham_update_dma_slow(struct omap_sham_dev *dd) |
625 | { | |
626 | struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); | |
627 | unsigned int final; | |
628 | size_t count; | |
629 | ||
8628e7c8 DK |
630 | omap_sham_append_sg(ctx); |
631 | ||
ea1fd224 | 632 | final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total; |
8628e7c8 DK |
633 | |
634 | dev_dbg(dd->dev, "slow: bufcnt: %u, digcnt: %d, final: %d\n", | |
635 | ctx->bufcnt, ctx->digcnt, final); | |
636 | ||
637 | if (final || (ctx->bufcnt == ctx->buflen && ctx->total)) { | |
638 | count = ctx->bufcnt; | |
639 | ctx->bufcnt = 0; | |
798eed5d | 640 | return omap_sham_xmit_dma_map(dd, ctx, count, final); |
8628e7c8 DK |
641 | } |
642 | ||
643 | return 0; | |
644 | } | |
645 | ||
887c883e DK |
646 | /* Start address alignment */ |
647 | #define SG_AA(sg) (IS_ALIGNED(sg->offset, sizeof(u32))) | |
648 | /* SHA1 block size alignment */ | |
649 | #define SG_SA(sg) (IS_ALIGNED(sg->length, SHA1_MD5_BLOCK_SIZE)) | |
650 | ||
651 | static int omap_sham_update_dma_start(struct omap_sham_dev *dd) | |
8628e7c8 DK |
652 | { |
653 | struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); | |
887c883e DK |
654 | unsigned int length, final, tail; |
655 | struct scatterlist *sg; | |
dfd061d5 | 656 | int ret; |
887c883e DK |
657 | |
658 | if (!ctx->total) | |
659 | return 0; | |
660 | ||
661 | if (ctx->bufcnt || ctx->offset) | |
662 | return omap_sham_update_dma_slow(dd); | |
663 | ||
dfd061d5 MG |
664 | /* |
665 | * Don't use the sg interface when the transfer size is less | |
666 | * than the number of elements in a DMA frame. Otherwise, | |
667 | * the dmaengine infrastructure will calculate that it needs | |
668 | * to transfer 0 frames which ultimately fails. | |
669 | */ | |
670 | if (ctx->total < (DST_MAXBURST * sizeof(u32))) | |
671 | return omap_sham_update_dma_slow(dd); | |
dfd061d5 | 672 | |
887c883e DK |
673 | dev_dbg(dd->dev, "fast: digcnt: %d, bufcnt: %u, total: %u\n", |
674 | ctx->digcnt, ctx->bufcnt, ctx->total); | |
675 | ||
676 | sg = ctx->sg; | |
8628e7c8 | 677 | |
887c883e DK |
678 | if (!SG_AA(sg)) |
679 | return omap_sham_update_dma_slow(dd); | |
8628e7c8 | 680 | |
887c883e DK |
681 | if (!sg_is_last(sg) && !SG_SA(sg)) |
682 | /* size is not SHA1_BLOCK_SIZE aligned */ | |
683 | return omap_sham_update_dma_slow(dd); | |
684 | ||
685 | length = min(ctx->total, sg->length); | |
686 | ||
687 | if (sg_is_last(sg)) { | |
ea1fd224 | 688 | if (!(ctx->flags & BIT(FLAGS_FINUP))) { |
887c883e DK |
689 | /* not last sg must be SHA1_MD5_BLOCK_SIZE aligned */ |
690 | tail = length & (SHA1_MD5_BLOCK_SIZE - 1); | |
691 | /* without finup() we need one block to close hash */ | |
692 | if (!tail) | |
693 | tail = SHA1_MD5_BLOCK_SIZE; | |
694 | length -= tail; | |
695 | } | |
696 | } | |
8628e7c8 DK |
697 | |
698 | if (!dma_map_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE)) { | |
699 | dev_err(dd->dev, "dma_map_sg error\n"); | |
700 | return -EINVAL; | |
701 | } | |
702 | ||
ea1fd224 | 703 | ctx->flags |= BIT(FLAGS_SG); |
887c883e | 704 | |
8628e7c8 | 705 | ctx->total -= length; |
887c883e DK |
706 | ctx->offset = length; /* offset where to start slow */ |
707 | ||
ea1fd224 | 708 | final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total; |
8628e7c8 | 709 | |
dfd061d5 | 710 | ret = omap_sham_xmit_dma(dd, sg_dma_address(ctx->sg), length, final, 1); |
0d373d60 | 711 | if (ret != -EINPROGRESS) |
dfd061d5 MG |
712 | dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE); |
713 | ||
714 | return ret; | |
8628e7c8 DK |
715 | } |
716 | ||
717 | static int omap_sham_update_cpu(struct omap_sham_dev *dd) | |
718 | { | |
719 | struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); | |
720 | int bufcnt; | |
721 | ||
722 | omap_sham_append_sg(ctx); | |
723 | bufcnt = ctx->bufcnt; | |
724 | ctx->bufcnt = 0; | |
725 | ||
726 | return omap_sham_xmit_cpu(dd, ctx->buffer, bufcnt, 1); | |
727 | } | |
728 | ||
729 | static int omap_sham_update_dma_stop(struct omap_sham_dev *dd) | |
730 | { | |
731 | struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req); | |
732 | ||
dfd061d5 | 733 | dmaengine_terminate_all(dd->dma_lch); |
dfd061d5 | 734 | |
ea1fd224 | 735 | if (ctx->flags & BIT(FLAGS_SG)) { |
8628e7c8 | 736 | dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE); |
887c883e DK |
737 | if (ctx->sg->length == ctx->offset) { |
738 | ctx->sg = sg_next(ctx->sg); | |
739 | if (ctx->sg) | |
740 | ctx->offset = 0; | |
741 | } | |
742 | } else { | |
798eed5d DK |
743 | dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen, |
744 | DMA_TO_DEVICE); | |
887c883e | 745 | } |
8628e7c8 DK |
746 | |
747 | return 0; | |
748 | } | |
749 | ||
8628e7c8 DK |
750 | static int omap_sham_init(struct ahash_request *req) |
751 | { | |
752 | struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); | |
753 | struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm); | |
754 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
755 | struct omap_sham_dev *dd = NULL, *tmp; | |
756 | ||
757 | spin_lock_bh(&sham.lock); | |
758 | if (!tctx->dd) { | |
759 | list_for_each_entry(tmp, &sham.dev_list, list) { | |
760 | dd = tmp; | |
761 | break; | |
762 | } | |
763 | tctx->dd = dd; | |
764 | } else { | |
765 | dd = tctx->dd; | |
766 | } | |
767 | spin_unlock_bh(&sham.lock); | |
768 | ||
769 | ctx->dd = dd; | |
770 | ||
771 | ctx->flags = 0; | |
772 | ||
8628e7c8 DK |
773 | dev_dbg(dd->dev, "init: digest size: %d\n", |
774 | crypto_ahash_digestsize(tfm)); | |
775 | ||
0d373d60 MG |
776 | switch (crypto_ahash_digestsize(tfm)) { |
777 | case MD5_DIGEST_SIZE: | |
778 | ctx->flags |= FLAGS_MODE_MD5; | |
779 | break; | |
780 | case SHA1_DIGEST_SIZE: | |
781 | ctx->flags |= FLAGS_MODE_SHA1; | |
782 | break; | |
783 | } | |
8628e7c8 DK |
784 | |
785 | ctx->bufcnt = 0; | |
786 | ctx->digcnt = 0; | |
798eed5d | 787 | ctx->buflen = BUFLEN; |
8628e7c8 | 788 | |
ea1fd224 | 789 | if (tctx->flags & BIT(FLAGS_HMAC)) { |
0d373d60 MG |
790 | if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) { |
791 | struct omap_sham_hmac_ctx *bctx = tctx->base; | |
792 | ||
793 | memcpy(ctx->buffer, bctx->ipad, SHA1_MD5_BLOCK_SIZE); | |
794 | ctx->bufcnt = SHA1_MD5_BLOCK_SIZE; | |
795 | } | |
8628e7c8 | 796 | |
ea1fd224 | 797 | ctx->flags |= BIT(FLAGS_HMAC); |
8628e7c8 DK |
798 | } |
799 | ||
800 | return 0; | |
801 | ||
802 | } | |
803 | ||
804 | static int omap_sham_update_req(struct omap_sham_dev *dd) | |
805 | { | |
806 | struct ahash_request *req = dd->req; | |
807 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
808 | int err; | |
809 | ||
810 | dev_dbg(dd->dev, "update_req: total: %u, digcnt: %d, finup: %d\n", | |
ea1fd224 | 811 | ctx->total, ctx->digcnt, (ctx->flags & BIT(FLAGS_FINUP)) != 0); |
8628e7c8 | 812 | |
ea1fd224 | 813 | if (ctx->flags & BIT(FLAGS_CPU)) |
8628e7c8 | 814 | err = omap_sham_update_cpu(dd); |
8628e7c8 | 815 | else |
887c883e | 816 | err = omap_sham_update_dma_start(dd); |
8628e7c8 DK |
817 | |
818 | /* wait for dma completion before can take more data */ | |
819 | dev_dbg(dd->dev, "update: err: %d, digcnt: %d\n", err, ctx->digcnt); | |
820 | ||
821 | return err; | |
822 | } | |
823 | ||
824 | static int omap_sham_final_req(struct omap_sham_dev *dd) | |
825 | { | |
826 | struct ahash_request *req = dd->req; | |
827 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
828 | int err = 0, use_dma = 1; | |
829 | ||
dfd061d5 | 830 | if (ctx->bufcnt <= DMA_MIN) |
8628e7c8 DK |
831 | /* faster to handle last block with cpu */ |
832 | use_dma = 0; | |
833 | ||
834 | if (use_dma) | |
798eed5d | 835 | err = omap_sham_xmit_dma_map(dd, ctx, ctx->bufcnt, 1); |
8628e7c8 DK |
836 | else |
837 | err = omap_sham_xmit_cpu(dd, ctx->buffer, ctx->bufcnt, 1); | |
838 | ||
839 | ctx->bufcnt = 0; | |
840 | ||
8628e7c8 DK |
841 | dev_dbg(dd->dev, "final_req: err: %d\n", err); |
842 | ||
843 | return err; | |
844 | } | |
845 | ||
bf362759 | 846 | static int omap_sham_finish_hmac(struct ahash_request *req) |
8628e7c8 DK |
847 | { |
848 | struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm); | |
849 | struct omap_sham_hmac_ctx *bctx = tctx->base; | |
850 | int bs = crypto_shash_blocksize(bctx->shash); | |
851 | int ds = crypto_shash_digestsize(bctx->shash); | |
852 | struct { | |
853 | struct shash_desc shash; | |
854 | char ctx[crypto_shash_descsize(bctx->shash)]; | |
855 | } desc; | |
856 | ||
857 | desc.shash.tfm = bctx->shash; | |
858 | desc.shash.flags = 0; /* not CRYPTO_TFM_REQ_MAY_SLEEP */ | |
859 | ||
860 | return crypto_shash_init(&desc.shash) ?: | |
861 | crypto_shash_update(&desc.shash, bctx->opad, bs) ?: | |
bf362759 DK |
862 | crypto_shash_finup(&desc.shash, req->result, ds, req->result); |
863 | } | |
864 | ||
865 | static int omap_sham_finish(struct ahash_request *req) | |
866 | { | |
867 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
868 | struct omap_sham_dev *dd = ctx->dd; | |
869 | int err = 0; | |
870 | ||
871 | if (ctx->digcnt) { | |
872 | omap_sham_copy_ready_hash(req); | |
0d373d60 MG |
873 | if ((ctx->flags & BIT(FLAGS_HMAC)) && |
874 | !test_bit(FLAGS_AUTO_XOR, &dd->flags)) | |
bf362759 DK |
875 | err = omap_sham_finish_hmac(req); |
876 | } | |
877 | ||
878 | dev_dbg(dd->dev, "digcnt: %d, bufcnt: %d\n", ctx->digcnt, ctx->bufcnt); | |
879 | ||
880 | return err; | |
8628e7c8 DK |
881 | } |
882 | ||
883 | static void omap_sham_finish_req(struct ahash_request *req, int err) | |
884 | { | |
885 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
798eed5d | 886 | struct omap_sham_dev *dd = ctx->dd; |
8628e7c8 DK |
887 | |
888 | if (!err) { | |
0d373d60 | 889 | dd->pdata->copy_hash(req, 1); |
ed3ea9a8 | 890 | if (test_bit(FLAGS_FINAL, &dd->flags)) |
bf362759 | 891 | err = omap_sham_finish(req); |
3e133c8b | 892 | } else { |
ea1fd224 | 893 | ctx->flags |= BIT(FLAGS_ERROR); |
8628e7c8 DK |
894 | } |
895 | ||
0efd4d8a DK |
896 | /* atomic operation is not needed here */ |
897 | dd->flags &= ~(BIT(FLAGS_BUSY) | BIT(FLAGS_FINAL) | BIT(FLAGS_CPU) | | |
898 | BIT(FLAGS_DMA_READY) | BIT(FLAGS_OUTPUT_READY)); | |
b359f034 MG |
899 | |
900 | pm_runtime_put_sync(dd->dev); | |
8628e7c8 DK |
901 | |
902 | if (req->base.complete) | |
903 | req->base.complete(&req->base, err); | |
6cb3ffe1 DK |
904 | |
905 | /* handle new request */ | |
906 | tasklet_schedule(&dd->done_task); | |
8628e7c8 DK |
907 | } |
908 | ||
a5d87237 DK |
909 | static int omap_sham_handle_queue(struct omap_sham_dev *dd, |
910 | struct ahash_request *req) | |
8628e7c8 | 911 | { |
6c39d116 | 912 | struct crypto_async_request *async_req, *backlog; |
8628e7c8 | 913 | struct omap_sham_reqctx *ctx; |
8628e7c8 | 914 | unsigned long flags; |
a5d87237 | 915 | int err = 0, ret = 0; |
8628e7c8 DK |
916 | |
917 | spin_lock_irqsave(&dd->lock, flags); | |
a5d87237 DK |
918 | if (req) |
919 | ret = ahash_enqueue_request(&dd->queue, req); | |
a929cbee | 920 | if (test_bit(FLAGS_BUSY, &dd->flags)) { |
a5d87237 DK |
921 | spin_unlock_irqrestore(&dd->lock, flags); |
922 | return ret; | |
923 | } | |
6c39d116 | 924 | backlog = crypto_get_backlog(&dd->queue); |
8628e7c8 | 925 | async_req = crypto_dequeue_request(&dd->queue); |
6c39d116 | 926 | if (async_req) |
a929cbee | 927 | set_bit(FLAGS_BUSY, &dd->flags); |
8628e7c8 DK |
928 | spin_unlock_irqrestore(&dd->lock, flags); |
929 | ||
930 | if (!async_req) | |
a5d87237 | 931 | return ret; |
8628e7c8 DK |
932 | |
933 | if (backlog) | |
934 | backlog->complete(backlog, -EINPROGRESS); | |
935 | ||
936 | req = ahash_request_cast(async_req); | |
8628e7c8 | 937 | dd->req = req; |
8628e7c8 DK |
938 | ctx = ahash_request_ctx(req); |
939 | ||
940 | dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n", | |
941 | ctx->op, req->nbytes); | |
942 | ||
798eed5d DK |
943 | err = omap_sham_hw_init(dd); |
944 | if (err) | |
945 | goto err1; | |
946 | ||
798eed5d | 947 | if (ctx->digcnt) |
8628e7c8 | 948 | /* request has changed - restore hash */ |
0d373d60 | 949 | dd->pdata->copy_hash(req, 0); |
8628e7c8 DK |
950 | |
951 | if (ctx->op == OP_UPDATE) { | |
952 | err = omap_sham_update_req(dd); | |
ea1fd224 | 953 | if (err != -EINPROGRESS && (ctx->flags & BIT(FLAGS_FINUP))) |
8628e7c8 DK |
954 | /* no final() after finup() */ |
955 | err = omap_sham_final_req(dd); | |
956 | } else if (ctx->op == OP_FINAL) { | |
957 | err = omap_sham_final_req(dd); | |
958 | } | |
798eed5d | 959 | err1: |
6cb3ffe1 | 960 | if (err != -EINPROGRESS) |
8628e7c8 DK |
961 | /* done_task will not finish it, so do it here */ |
962 | omap_sham_finish_req(req, err); | |
8628e7c8 DK |
963 | |
964 | dev_dbg(dd->dev, "exit, err: %d\n", err); | |
965 | ||
a5d87237 | 966 | return ret; |
8628e7c8 DK |
967 | } |
968 | ||
969 | static int omap_sham_enqueue(struct ahash_request *req, unsigned int op) | |
970 | { | |
971 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
972 | struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm); | |
973 | struct omap_sham_dev *dd = tctx->dd; | |
8628e7c8 DK |
974 | |
975 | ctx->op = op; | |
976 | ||
a5d87237 | 977 | return omap_sham_handle_queue(dd, req); |
8628e7c8 DK |
978 | } |
979 | ||
980 | static int omap_sham_update(struct ahash_request *req) | |
981 | { | |
982 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
983 | ||
984 | if (!req->nbytes) | |
985 | return 0; | |
986 | ||
987 | ctx->total = req->nbytes; | |
988 | ctx->sg = req->src; | |
989 | ctx->offset = 0; | |
990 | ||
ea1fd224 | 991 | if (ctx->flags & BIT(FLAGS_FINUP)) { |
8628e7c8 DK |
992 | if ((ctx->digcnt + ctx->bufcnt + ctx->total) < 9) { |
993 | /* | |
994 | * OMAP HW accel works only with buffers >= 9 | |
995 | * will switch to bypass in final() | |
996 | * final has the same request and data | |
997 | */ | |
998 | omap_sham_append_sg(ctx); | |
999 | return 0; | |
887c883e DK |
1000 | } else if (ctx->bufcnt + ctx->total <= SHA1_MD5_BLOCK_SIZE) { |
1001 | /* | |
1002 | * faster to use CPU for short transfers | |
1003 | */ | |
ea1fd224 | 1004 | ctx->flags |= BIT(FLAGS_CPU); |
8628e7c8 | 1005 | } |
887c883e | 1006 | } else if (ctx->bufcnt + ctx->total < ctx->buflen) { |
8628e7c8 DK |
1007 | omap_sham_append_sg(ctx); |
1008 | return 0; | |
1009 | } | |
1010 | ||
1011 | return omap_sham_enqueue(req, OP_UPDATE); | |
1012 | } | |
1013 | ||
1014 | static int omap_sham_shash_digest(struct crypto_shash *shash, u32 flags, | |
1015 | const u8 *data, unsigned int len, u8 *out) | |
1016 | { | |
1017 | struct { | |
1018 | struct shash_desc shash; | |
1019 | char ctx[crypto_shash_descsize(shash)]; | |
1020 | } desc; | |
1021 | ||
1022 | desc.shash.tfm = shash; | |
1023 | desc.shash.flags = flags & CRYPTO_TFM_REQ_MAY_SLEEP; | |
1024 | ||
1025 | return crypto_shash_digest(&desc.shash, data, len, out); | |
1026 | } | |
1027 | ||
1028 | static int omap_sham_final_shash(struct ahash_request *req) | |
1029 | { | |
1030 | struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm); | |
1031 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
1032 | ||
1033 | return omap_sham_shash_digest(tctx->fallback, req->base.flags, | |
1034 | ctx->buffer, ctx->bufcnt, req->result); | |
1035 | } | |
1036 | ||
1037 | static int omap_sham_final(struct ahash_request *req) | |
1038 | { | |
1039 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
8628e7c8 | 1040 | |
ea1fd224 | 1041 | ctx->flags |= BIT(FLAGS_FINUP); |
8628e7c8 | 1042 | |
ea1fd224 | 1043 | if (ctx->flags & BIT(FLAGS_ERROR)) |
bf362759 | 1044 | return 0; /* uncompleted hash is not needed */ |
8628e7c8 | 1045 | |
bf362759 DK |
1046 | /* OMAP HW accel works only with buffers >= 9 */ |
1047 | /* HMAC is always >= 9 because ipad == block size */ | |
1048 | if ((ctx->digcnt + ctx->bufcnt) < 9) | |
1049 | return omap_sham_final_shash(req); | |
1050 | else if (ctx->bufcnt) | |
1051 | return omap_sham_enqueue(req, OP_FINAL); | |
8628e7c8 | 1052 | |
bf362759 DK |
1053 | /* copy ready hash (+ finalize hmac) */ |
1054 | return omap_sham_finish(req); | |
8628e7c8 DK |
1055 | } |
1056 | ||
1057 | static int omap_sham_finup(struct ahash_request *req) | |
1058 | { | |
1059 | struct omap_sham_reqctx *ctx = ahash_request_ctx(req); | |
1060 | int err1, err2; | |
1061 | ||
ea1fd224 | 1062 | ctx->flags |= BIT(FLAGS_FINUP); |
8628e7c8 DK |
1063 | |
1064 | err1 = omap_sham_update(req); | |
455e3389 | 1065 | if (err1 == -EINPROGRESS || err1 == -EBUSY) |
8628e7c8 DK |
1066 | return err1; |
1067 | /* | |
1068 | * final() has to be always called to cleanup resources | |
1069 | * even if udpate() failed, except EINPROGRESS | |
1070 | */ | |
1071 | err2 = omap_sham_final(req); | |
1072 | ||
1073 | return err1 ?: err2; | |
1074 | } | |
1075 | ||
1076 | static int omap_sham_digest(struct ahash_request *req) | |
1077 | { | |
1078 | return omap_sham_init(req) ?: omap_sham_finup(req); | |
1079 | } | |
1080 | ||
1081 | static int omap_sham_setkey(struct crypto_ahash *tfm, const u8 *key, | |
1082 | unsigned int keylen) | |
1083 | { | |
1084 | struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm); | |
1085 | struct omap_sham_hmac_ctx *bctx = tctx->base; | |
1086 | int bs = crypto_shash_blocksize(bctx->shash); | |
1087 | int ds = crypto_shash_digestsize(bctx->shash); | |
0d373d60 | 1088 | struct omap_sham_dev *dd = NULL, *tmp; |
8628e7c8 | 1089 | int err, i; |
0d373d60 MG |
1090 | |
1091 | spin_lock_bh(&sham.lock); | |
1092 | if (!tctx->dd) { | |
1093 | list_for_each_entry(tmp, &sham.dev_list, list) { | |
1094 | dd = tmp; | |
1095 | break; | |
1096 | } | |
1097 | tctx->dd = dd; | |
1098 | } else { | |
1099 | dd = tctx->dd; | |
1100 | } | |
1101 | spin_unlock_bh(&sham.lock); | |
1102 | ||
8628e7c8 DK |
1103 | err = crypto_shash_setkey(tctx->fallback, key, keylen); |
1104 | if (err) | |
1105 | return err; | |
1106 | ||
1107 | if (keylen > bs) { | |
1108 | err = omap_sham_shash_digest(bctx->shash, | |
1109 | crypto_shash_get_flags(bctx->shash), | |
1110 | key, keylen, bctx->ipad); | |
1111 | if (err) | |
1112 | return err; | |
1113 | keylen = ds; | |
1114 | } else { | |
1115 | memcpy(bctx->ipad, key, keylen); | |
1116 | } | |
1117 | ||
1118 | memset(bctx->ipad + keylen, 0, bs - keylen); | |
8628e7c8 | 1119 | |
0d373d60 MG |
1120 | if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) { |
1121 | memcpy(bctx->opad, bctx->ipad, bs); | |
1122 | ||
1123 | for (i = 0; i < bs; i++) { | |
1124 | bctx->ipad[i] ^= 0x36; | |
1125 | bctx->opad[i] ^= 0x5c; | |
1126 | } | |
8628e7c8 DK |
1127 | } |
1128 | ||
1129 | return err; | |
1130 | } | |
1131 | ||
1132 | static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base) | |
1133 | { | |
1134 | struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm); | |
1135 | const char *alg_name = crypto_tfm_alg_name(tfm); | |
1136 | ||
1137 | /* Allocate a fallback and abort if it failed. */ | |
1138 | tctx->fallback = crypto_alloc_shash(alg_name, 0, | |
1139 | CRYPTO_ALG_NEED_FALLBACK); | |
1140 | if (IS_ERR(tctx->fallback)) { | |
1141 | pr_err("omap-sham: fallback driver '%s' " | |
1142 | "could not be loaded.\n", alg_name); | |
1143 | return PTR_ERR(tctx->fallback); | |
1144 | } | |
1145 | ||
1146 | crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), | |
798eed5d | 1147 | sizeof(struct omap_sham_reqctx) + BUFLEN); |
8628e7c8 DK |
1148 | |
1149 | if (alg_base) { | |
1150 | struct omap_sham_hmac_ctx *bctx = tctx->base; | |
ea1fd224 | 1151 | tctx->flags |= BIT(FLAGS_HMAC); |
8628e7c8 DK |
1152 | bctx->shash = crypto_alloc_shash(alg_base, 0, |
1153 | CRYPTO_ALG_NEED_FALLBACK); | |
1154 | if (IS_ERR(bctx->shash)) { | |
1155 | pr_err("omap-sham: base driver '%s' " | |
1156 | "could not be loaded.\n", alg_base); | |
1157 | crypto_free_shash(tctx->fallback); | |
1158 | return PTR_ERR(bctx->shash); | |
1159 | } | |
1160 | ||
1161 | } | |
1162 | ||
1163 | return 0; | |
1164 | } | |
1165 | ||
1166 | static int omap_sham_cra_init(struct crypto_tfm *tfm) | |
1167 | { | |
1168 | return omap_sham_cra_init_alg(tfm, NULL); | |
1169 | } | |
1170 | ||
1171 | static int omap_sham_cra_sha1_init(struct crypto_tfm *tfm) | |
1172 | { | |
1173 | return omap_sham_cra_init_alg(tfm, "sha1"); | |
1174 | } | |
1175 | ||
1176 | static int omap_sham_cra_md5_init(struct crypto_tfm *tfm) | |
1177 | { | |
1178 | return omap_sham_cra_init_alg(tfm, "md5"); | |
1179 | } | |
1180 | ||
1181 | static void omap_sham_cra_exit(struct crypto_tfm *tfm) | |
1182 | { | |
1183 | struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm); | |
1184 | ||
1185 | crypto_free_shash(tctx->fallback); | |
1186 | tctx->fallback = NULL; | |
1187 | ||
ea1fd224 | 1188 | if (tctx->flags & BIT(FLAGS_HMAC)) { |
8628e7c8 DK |
1189 | struct omap_sham_hmac_ctx *bctx = tctx->base; |
1190 | crypto_free_shash(bctx->shash); | |
1191 | } | |
1192 | } | |
1193 | ||
1194 | static struct ahash_alg algs[] = { | |
1195 | { | |
1196 | .init = omap_sham_init, | |
1197 | .update = omap_sham_update, | |
1198 | .final = omap_sham_final, | |
1199 | .finup = omap_sham_finup, | |
1200 | .digest = omap_sham_digest, | |
1201 | .halg.digestsize = SHA1_DIGEST_SIZE, | |
1202 | .halg.base = { | |
1203 | .cra_name = "sha1", | |
1204 | .cra_driver_name = "omap-sha1", | |
1205 | .cra_priority = 100, | |
1206 | .cra_flags = CRYPTO_ALG_TYPE_AHASH | | |
d912bb76 | 1207 | CRYPTO_ALG_KERN_DRIVER_ONLY | |
8628e7c8 DK |
1208 | CRYPTO_ALG_ASYNC | |
1209 | CRYPTO_ALG_NEED_FALLBACK, | |
1210 | .cra_blocksize = SHA1_BLOCK_SIZE, | |
1211 | .cra_ctxsize = sizeof(struct omap_sham_ctx), | |
1212 | .cra_alignmask = 0, | |
1213 | .cra_module = THIS_MODULE, | |
1214 | .cra_init = omap_sham_cra_init, | |
1215 | .cra_exit = omap_sham_cra_exit, | |
1216 | } | |
1217 | }, | |
1218 | { | |
1219 | .init = omap_sham_init, | |
1220 | .update = omap_sham_update, | |
1221 | .final = omap_sham_final, | |
1222 | .finup = omap_sham_finup, | |
1223 | .digest = omap_sham_digest, | |
1224 | .halg.digestsize = MD5_DIGEST_SIZE, | |
1225 | .halg.base = { | |
1226 | .cra_name = "md5", | |
1227 | .cra_driver_name = "omap-md5", | |
1228 | .cra_priority = 100, | |
1229 | .cra_flags = CRYPTO_ALG_TYPE_AHASH | | |
d912bb76 | 1230 | CRYPTO_ALG_KERN_DRIVER_ONLY | |
8628e7c8 DK |
1231 | CRYPTO_ALG_ASYNC | |
1232 | CRYPTO_ALG_NEED_FALLBACK, | |
1233 | .cra_blocksize = SHA1_BLOCK_SIZE, | |
1234 | .cra_ctxsize = sizeof(struct omap_sham_ctx), | |
798eed5d | 1235 | .cra_alignmask = OMAP_ALIGN_MASK, |
8628e7c8 DK |
1236 | .cra_module = THIS_MODULE, |
1237 | .cra_init = omap_sham_cra_init, | |
1238 | .cra_exit = omap_sham_cra_exit, | |
1239 | } | |
1240 | }, | |
1241 | { | |
1242 | .init = omap_sham_init, | |
1243 | .update = omap_sham_update, | |
1244 | .final = omap_sham_final, | |
1245 | .finup = omap_sham_finup, | |
1246 | .digest = omap_sham_digest, | |
1247 | .setkey = omap_sham_setkey, | |
1248 | .halg.digestsize = SHA1_DIGEST_SIZE, | |
1249 | .halg.base = { | |
1250 | .cra_name = "hmac(sha1)", | |
1251 | .cra_driver_name = "omap-hmac-sha1", | |
1252 | .cra_priority = 100, | |
1253 | .cra_flags = CRYPTO_ALG_TYPE_AHASH | | |
d912bb76 | 1254 | CRYPTO_ALG_KERN_DRIVER_ONLY | |
8628e7c8 DK |
1255 | CRYPTO_ALG_ASYNC | |
1256 | CRYPTO_ALG_NEED_FALLBACK, | |
1257 | .cra_blocksize = SHA1_BLOCK_SIZE, | |
1258 | .cra_ctxsize = sizeof(struct omap_sham_ctx) + | |
1259 | sizeof(struct omap_sham_hmac_ctx), | |
798eed5d | 1260 | .cra_alignmask = OMAP_ALIGN_MASK, |
8628e7c8 DK |
1261 | .cra_module = THIS_MODULE, |
1262 | .cra_init = omap_sham_cra_sha1_init, | |
1263 | .cra_exit = omap_sham_cra_exit, | |
1264 | } | |
1265 | }, | |
1266 | { | |
1267 | .init = omap_sham_init, | |
1268 | .update = omap_sham_update, | |
1269 | .final = omap_sham_final, | |
1270 | .finup = omap_sham_finup, | |
1271 | .digest = omap_sham_digest, | |
1272 | .setkey = omap_sham_setkey, | |
1273 | .halg.digestsize = MD5_DIGEST_SIZE, | |
1274 | .halg.base = { | |
1275 | .cra_name = "hmac(md5)", | |
1276 | .cra_driver_name = "omap-hmac-md5", | |
1277 | .cra_priority = 100, | |
1278 | .cra_flags = CRYPTO_ALG_TYPE_AHASH | | |
d912bb76 | 1279 | CRYPTO_ALG_KERN_DRIVER_ONLY | |
8628e7c8 DK |
1280 | CRYPTO_ALG_ASYNC | |
1281 | CRYPTO_ALG_NEED_FALLBACK, | |
1282 | .cra_blocksize = SHA1_BLOCK_SIZE, | |
1283 | .cra_ctxsize = sizeof(struct omap_sham_ctx) + | |
1284 | sizeof(struct omap_sham_hmac_ctx), | |
798eed5d | 1285 | .cra_alignmask = OMAP_ALIGN_MASK, |
8628e7c8 DK |
1286 | .cra_module = THIS_MODULE, |
1287 | .cra_init = omap_sham_cra_md5_init, | |
1288 | .cra_exit = omap_sham_cra_exit, | |
1289 | } | |
1290 | } | |
1291 | }; | |
1292 | ||
1293 | static void omap_sham_done_task(unsigned long data) | |
1294 | { | |
1295 | struct omap_sham_dev *dd = (struct omap_sham_dev *)data; | |
6c63db82 | 1296 | int err = 0; |
8628e7c8 | 1297 | |
6cb3ffe1 DK |
1298 | if (!test_bit(FLAGS_BUSY, &dd->flags)) { |
1299 | omap_sham_handle_queue(dd, NULL); | |
1300 | return; | |
1301 | } | |
1302 | ||
6c63db82 DK |
1303 | if (test_bit(FLAGS_CPU, &dd->flags)) { |
1304 | if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) | |
1305 | goto finish; | |
1306 | } else if (test_bit(FLAGS_DMA_READY, &dd->flags)) { | |
1307 | if (test_and_clear_bit(FLAGS_DMA_ACTIVE, &dd->flags)) { | |
1308 | omap_sham_update_dma_stop(dd); | |
1309 | if (dd->err) { | |
1310 | err = dd->err; | |
1311 | goto finish; | |
1312 | } | |
1313 | } | |
1314 | if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) { | |
1315 | /* hash or semi-hash ready */ | |
1316 | clear_bit(FLAGS_DMA_READY, &dd->flags); | |
887c883e | 1317 | err = omap_sham_update_dma_start(dd); |
6c63db82 DK |
1318 | if (err != -EINPROGRESS) |
1319 | goto finish; | |
1320 | } | |
8628e7c8 DK |
1321 | } |
1322 | ||
6c63db82 | 1323 | return; |
3e133c8b | 1324 | |
6c63db82 DK |
1325 | finish: |
1326 | dev_dbg(dd->dev, "update done: err: %d\n", err); | |
1327 | /* finish curent request */ | |
1328 | omap_sham_finish_req(dd->req, err); | |
8628e7c8 DK |
1329 | } |
1330 | ||
0d373d60 MG |
1331 | static irqreturn_t omap_sham_irq_common(struct omap_sham_dev *dd) |
1332 | { | |
1333 | if (!test_bit(FLAGS_BUSY, &dd->flags)) { | |
1334 | dev_warn(dd->dev, "Interrupt when no active requests.\n"); | |
1335 | } else { | |
1336 | set_bit(FLAGS_OUTPUT_READY, &dd->flags); | |
1337 | tasklet_schedule(&dd->done_task); | |
1338 | } | |
1339 | ||
1340 | return IRQ_HANDLED; | |
1341 | } | |
1342 | ||
1343 | static irqreturn_t omap_sham_irq_omap2(int irq, void *dev_id) | |
8628e7c8 DK |
1344 | { |
1345 | struct omap_sham_dev *dd = dev_id; | |
8628e7c8 | 1346 | |
ed3ea9a8 | 1347 | if (unlikely(test_bit(FLAGS_FINAL, &dd->flags))) |
8628e7c8 DK |
1348 | /* final -> allow device to go to power-saving mode */ |
1349 | omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH); | |
1350 | ||
1351 | omap_sham_write_mask(dd, SHA_REG_CTRL, SHA_REG_CTRL_OUTPUT_READY, | |
1352 | SHA_REG_CTRL_OUTPUT_READY); | |
1353 | omap_sham_read(dd, SHA_REG_CTRL); | |
1354 | ||
0d373d60 MG |
1355 | return omap_sham_irq_common(dd); |
1356 | } | |
cd3f1d54 | 1357 | |
0d373d60 MG |
1358 | static irqreturn_t omap_sham_irq_omap4(int irq, void *dev_id) |
1359 | { | |
1360 | struct omap_sham_dev *dd = dev_id; | |
8628e7c8 | 1361 | |
0d373d60 MG |
1362 | omap_sham_write_mask(dd, SHA_REG_MASK(dd), 0, SHA_REG_MASK_IT_EN); |
1363 | ||
1364 | return omap_sham_irq_common(dd); | |
8628e7c8 DK |
1365 | } |
1366 | ||
0d373d60 MG |
1367 | static const struct omap_sham_pdata omap_sham_pdata_omap2 = { |
1368 | .flags = BIT(FLAGS_BE32_SHA1), | |
1369 | .digest_size = SHA1_DIGEST_SIZE, | |
1370 | .copy_hash = omap_sham_copy_hash_omap2, | |
1371 | .write_ctrl = omap_sham_write_ctrl_omap2, | |
1372 | .trigger = omap_sham_trigger_omap2, | |
1373 | .poll_irq = omap_sham_poll_irq_omap2, | |
1374 | .intr_hdlr = omap_sham_irq_omap2, | |
1375 | .idigest_ofs = 0x00, | |
1376 | .din_ofs = 0x1c, | |
1377 | .digcnt_ofs = 0x14, | |
1378 | .rev_ofs = 0x5c, | |
1379 | .mask_ofs = 0x60, | |
1380 | .sysstatus_ofs = 0x64, | |
1381 | .major_mask = 0xf0, | |
1382 | .major_shift = 4, | |
1383 | .minor_mask = 0x0f, | |
1384 | .minor_shift = 0, | |
1385 | }; | |
1386 | ||
03feec9c | 1387 | #ifdef CONFIG_OF |
0d373d60 MG |
1388 | static const struct omap_sham_pdata omap_sham_pdata_omap4 = { |
1389 | .flags = BIT(FLAGS_AUTO_XOR), | |
1390 | .digest_size = SHA256_DIGEST_SIZE, | |
1391 | .copy_hash = omap_sham_copy_hash_omap4, | |
1392 | .write_ctrl = omap_sham_write_ctrl_omap4, | |
1393 | .trigger = omap_sham_trigger_omap4, | |
1394 | .poll_irq = omap_sham_poll_irq_omap4, | |
1395 | .intr_hdlr = omap_sham_irq_omap4, | |
1396 | .idigest_ofs = 0x020, | |
1397 | .din_ofs = 0x080, | |
1398 | .digcnt_ofs = 0x040, | |
1399 | .rev_ofs = 0x100, | |
1400 | .mask_ofs = 0x110, | |
1401 | .sysstatus_ofs = 0x114, | |
1402 | .major_mask = 0x0700, | |
1403 | .major_shift = 8, | |
1404 | .minor_mask = 0x003f, | |
1405 | .minor_shift = 0, | |
1406 | }; | |
1407 | ||
03feec9c MG |
1408 | static const struct of_device_id omap_sham_of_match[] = { |
1409 | { | |
1410 | .compatible = "ti,omap2-sham", | |
0d373d60 MG |
1411 | .data = &omap_sham_pdata_omap2, |
1412 | }, | |
1413 | { | |
1414 | .compatible = "ti,omap4-sham", | |
1415 | .data = &omap_sham_pdata_omap4, | |
03feec9c MG |
1416 | }, |
1417 | {}, | |
1418 | }; | |
1419 | MODULE_DEVICE_TABLE(of, omap_sham_of_match); | |
1420 | ||
1421 | static int omap_sham_get_res_of(struct omap_sham_dev *dd, | |
1422 | struct device *dev, struct resource *res) | |
1423 | { | |
1424 | struct device_node *node = dev->of_node; | |
1425 | const struct of_device_id *match; | |
1426 | int err = 0; | |
1427 | ||
1428 | match = of_match_device(of_match_ptr(omap_sham_of_match), dev); | |
1429 | if (!match) { | |
1430 | dev_err(dev, "no compatible OF match\n"); | |
1431 | err = -EINVAL; | |
1432 | goto err; | |
1433 | } | |
1434 | ||
1435 | err = of_address_to_resource(node, 0, res); | |
1436 | if (err < 0) { | |
1437 | dev_err(dev, "can't translate OF node address\n"); | |
1438 | err = -EINVAL; | |
1439 | goto err; | |
1440 | } | |
1441 | ||
1442 | dd->irq = of_irq_to_resource(node, 0, NULL); | |
1443 | if (!dd->irq) { | |
1444 | dev_err(dev, "can't translate OF irq value\n"); | |
1445 | err = -EINVAL; | |
1446 | goto err; | |
1447 | } | |
1448 | ||
1449 | dd->dma = -1; /* Dummy value that's unused */ | |
0d373d60 | 1450 | dd->pdata = match->data; |
03feec9c MG |
1451 | |
1452 | err: | |
1453 | return err; | |
1454 | } | |
1455 | #else | |
1456 | static int omap_sham_get_res_dev(struct omap_sham_dev *dd, | |
1457 | struct device *dev, struct resource *res) | |
1458 | { | |
1459 | return -EINVAL; | |
1460 | } | |
1461 | #endif | |
1462 | ||
1463 | static int omap_sham_get_res_pdev(struct omap_sham_dev *dd, | |
1464 | struct platform_device *pdev, struct resource *res) | |
1465 | { | |
1466 | struct device *dev = &pdev->dev; | |
1467 | struct resource *r; | |
1468 | int err = 0; | |
1469 | ||
1470 | /* Get the base address */ | |
1471 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1472 | if (!r) { | |
1473 | dev_err(dev, "no MEM resource info\n"); | |
1474 | err = -ENODEV; | |
1475 | goto err; | |
1476 | } | |
1477 | memcpy(res, r, sizeof(*res)); | |
1478 | ||
1479 | /* Get the IRQ */ | |
1480 | dd->irq = platform_get_irq(pdev, 0); | |
1481 | if (dd->irq < 0) { | |
1482 | dev_err(dev, "no IRQ resource info\n"); | |
1483 | err = dd->irq; | |
1484 | goto err; | |
1485 | } | |
1486 | ||
1487 | /* Get the DMA */ | |
1488 | r = platform_get_resource(pdev, IORESOURCE_DMA, 0); | |
1489 | if (!r) { | |
1490 | dev_err(dev, "no DMA resource info\n"); | |
1491 | err = -ENODEV; | |
1492 | goto err; | |
1493 | } | |
1494 | dd->dma = r->start; | |
1495 | ||
0d373d60 MG |
1496 | /* Only OMAP2/3 can be non-DT */ |
1497 | dd->pdata = &omap_sham_pdata_omap2; | |
1498 | ||
03feec9c MG |
1499 | err: |
1500 | return err; | |
1501 | } | |
1502 | ||
8628e7c8 DK |
1503 | static int __devinit omap_sham_probe(struct platform_device *pdev) |
1504 | { | |
1505 | struct omap_sham_dev *dd; | |
1506 | struct device *dev = &pdev->dev; | |
03feec9c | 1507 | struct resource res; |
dfd061d5 | 1508 | dma_cap_mask_t mask; |
8628e7c8 | 1509 | int err, i, j; |
0d373d60 | 1510 | u32 rev; |
8628e7c8 DK |
1511 | |
1512 | dd = kzalloc(sizeof(struct omap_sham_dev), GFP_KERNEL); | |
1513 | if (dd == NULL) { | |
1514 | dev_err(dev, "unable to alloc data struct.\n"); | |
1515 | err = -ENOMEM; | |
1516 | goto data_err; | |
1517 | } | |
1518 | dd->dev = dev; | |
1519 | platform_set_drvdata(pdev, dd); | |
1520 | ||
1521 | INIT_LIST_HEAD(&dd->list); | |
1522 | spin_lock_init(&dd->lock); | |
1523 | tasklet_init(&dd->done_task, omap_sham_done_task, (unsigned long)dd); | |
8628e7c8 DK |
1524 | crypto_init_queue(&dd->queue, OMAP_SHAM_QUEUE_LENGTH); |
1525 | ||
03feec9c MG |
1526 | err = (dev->of_node) ? omap_sham_get_res_of(dd, dev, &res) : |
1527 | omap_sham_get_res_pdev(dd, pdev, &res); | |
1528 | if (err) | |
8628e7c8 | 1529 | goto res_err; |
8628e7c8 | 1530 | |
03feec9c MG |
1531 | dd->io_base = devm_request_and_ioremap(dev, &res); |
1532 | if (!dd->io_base) { | |
1533 | dev_err(dev, "can't ioremap\n"); | |
1534 | err = -ENOMEM; | |
8628e7c8 DK |
1535 | goto res_err; |
1536 | } | |
03feec9c | 1537 | dd->phys_base = res.start; |
8628e7c8 | 1538 | |
0d373d60 MG |
1539 | err = request_irq(dd->irq, dd->pdata->intr_hdlr, IRQF_TRIGGER_LOW, |
1540 | dev_name(dev), dd); | |
8628e7c8 DK |
1541 | if (err) { |
1542 | dev_err(dev, "unable to request irq.\n"); | |
1543 | goto res_err; | |
1544 | } | |
1545 | ||
dfd061d5 MG |
1546 | dma_cap_zero(mask); |
1547 | dma_cap_set(DMA_SLAVE, mask); | |
1548 | ||
0e87e73f MG |
1549 | dd->dma_lch = dma_request_slave_channel_compat(mask, omap_dma_filter_fn, |
1550 | &dd->dma, dev, "rx"); | |
dfd061d5 MG |
1551 | if (!dd->dma_lch) { |
1552 | dev_err(dev, "unable to obtain RX DMA engine channel %u\n", | |
03feec9c | 1553 | dd->dma); |
dfd061d5 MG |
1554 | err = -ENXIO; |
1555 | goto dma_err; | |
1556 | } | |
8628e7c8 | 1557 | |
0d373d60 | 1558 | dd->flags |= dd->pdata->flags; |
8628e7c8 | 1559 | |
b359f034 MG |
1560 | pm_runtime_enable(dev); |
1561 | pm_runtime_get_sync(dev); | |
0d373d60 MG |
1562 | rev = omap_sham_read(dd, SHA_REG_REV(dd)); |
1563 | pm_runtime_put_sync(&pdev->dev); | |
b359f034 | 1564 | |
8628e7c8 | 1565 | dev_info(dev, "hw accel on OMAP rev %u.%u\n", |
0d373d60 MG |
1566 | (rev & dd->pdata->major_mask) >> dd->pdata->major_shift, |
1567 | (rev & dd->pdata->minor_mask) >> dd->pdata->minor_shift); | |
8628e7c8 DK |
1568 | |
1569 | spin_lock(&sham.lock); | |
1570 | list_add_tail(&dd->list, &sham.dev_list); | |
1571 | spin_unlock(&sham.lock); | |
1572 | ||
1573 | for (i = 0; i < ARRAY_SIZE(algs); i++) { | |
1574 | err = crypto_register_ahash(&algs[i]); | |
1575 | if (err) | |
1576 | goto err_algs; | |
1577 | } | |
1578 | ||
1579 | return 0; | |
1580 | ||
1581 | err_algs: | |
1582 | for (j = 0; j < i; j++) | |
1583 | crypto_unregister_ahash(&algs[j]); | |
b359f034 | 1584 | pm_runtime_disable(dev); |
dfd061d5 | 1585 | dma_release_channel(dd->dma_lch); |
8628e7c8 | 1586 | dma_err: |
03feec9c | 1587 | free_irq(dd->irq, dd); |
8628e7c8 DK |
1588 | res_err: |
1589 | kfree(dd); | |
1590 | dd = NULL; | |
1591 | data_err: | |
1592 | dev_err(dev, "initialization failed.\n"); | |
1593 | ||
1594 | return err; | |
1595 | } | |
1596 | ||
1597 | static int __devexit omap_sham_remove(struct platform_device *pdev) | |
1598 | { | |
1599 | static struct omap_sham_dev *dd; | |
1600 | int i; | |
1601 | ||
1602 | dd = platform_get_drvdata(pdev); | |
1603 | if (!dd) | |
1604 | return -ENODEV; | |
1605 | spin_lock(&sham.lock); | |
1606 | list_del(&dd->list); | |
1607 | spin_unlock(&sham.lock); | |
1608 | for (i = 0; i < ARRAY_SIZE(algs); i++) | |
1609 | crypto_unregister_ahash(&algs[i]); | |
1610 | tasklet_kill(&dd->done_task); | |
b359f034 | 1611 | pm_runtime_disable(&pdev->dev); |
dfd061d5 | 1612 | dma_release_channel(dd->dma_lch); |
03feec9c | 1613 | free_irq(dd->irq, dd); |
8628e7c8 DK |
1614 | kfree(dd); |
1615 | dd = NULL; | |
1616 | ||
1617 | return 0; | |
1618 | } | |
1619 | ||
3b3f4400 MG |
1620 | #ifdef CONFIG_PM_SLEEP |
1621 | static int omap_sham_suspend(struct device *dev) | |
1622 | { | |
1623 | pm_runtime_put_sync(dev); | |
1624 | return 0; | |
1625 | } | |
1626 | ||
1627 | static int omap_sham_resume(struct device *dev) | |
1628 | { | |
1629 | pm_runtime_get_sync(dev); | |
1630 | return 0; | |
1631 | } | |
1632 | #endif | |
1633 | ||
1634 | static const struct dev_pm_ops omap_sham_pm_ops = { | |
1635 | SET_SYSTEM_SLEEP_PM_OPS(omap_sham_suspend, omap_sham_resume) | |
1636 | }; | |
1637 | ||
8628e7c8 DK |
1638 | static struct platform_driver omap_sham_driver = { |
1639 | .probe = omap_sham_probe, | |
1640 | .remove = omap_sham_remove, | |
1641 | .driver = { | |
1642 | .name = "omap-sham", | |
1643 | .owner = THIS_MODULE, | |
3b3f4400 | 1644 | .pm = &omap_sham_pm_ops, |
03feec9c | 1645 | .of_match_table = omap_sham_of_match, |
8628e7c8 DK |
1646 | }, |
1647 | }; | |
1648 | ||
1649 | static int __init omap_sham_mod_init(void) | |
1650 | { | |
8628e7c8 DK |
1651 | return platform_driver_register(&omap_sham_driver); |
1652 | } | |
1653 | ||
1654 | static void __exit omap_sham_mod_exit(void) | |
1655 | { | |
1656 | platform_driver_unregister(&omap_sham_driver); | |
1657 | } | |
1658 | ||
1659 | module_init(omap_sham_mod_init); | |
1660 | module_exit(omap_sham_mod_exit); | |
1661 | ||
1662 | MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support."); | |
1663 | MODULE_LICENSE("GPL v2"); | |
1664 | MODULE_AUTHOR("Dmitry Kasatkin"); |