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crypto: omap-sham - DMA initialization fixes for off mode
[deliverable/linux.git] / drivers / crypto / omap-sham.c
CommitLineData
8628e7c8
DK		 1/*
2 * Cryptographic API.
3 *
4 * Support for OMAP SHA1/MD5 HW acceleration.
5 *
6 * Copyright (c) 2010 Nokia Corporation
7 * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 *
13 * Some ideas are from old omap-sha1-md5.c driver.
14 */
15
16#define pr_fmt(fmt) "%s: " fmt, __func__
17
8628e7c8
DK		 18#include <linux/err.h>
19#include <linux/device.h>
20#include <linux/module.h>
21#include <linux/init.h>
22#include <linux/errno.h>
23#include <linux/interrupt.h>
24#include <linux/kernel.h>
25#include <linux/clk.h>
26#include <linux/irq.h>
27#include <linux/io.h>
28#include <linux/platform_device.h>
29#include <linux/scatterlist.h>
30#include <linux/dma-mapping.h>
31#include <linux/delay.h>
32#include <linux/crypto.h>
33#include <linux/cryptohash.h>
34#include <crypto/scatterwalk.h>
35#include <crypto/algapi.h>
36#include <crypto/sha.h>
37#include <crypto/hash.h>
38#include <crypto/internal/hash.h>
39
40#include <plat/cpu.h>
41#include <plat/dma.h>
42#include <mach/irqs.h>
43
44#define SHA_REG_DIGEST(x) (0x00 + ((x) * 0x04))
45#define SHA_REG_DIN(x) (0x1C + ((x) * 0x04))
46
47#define SHA1_MD5_BLOCK_SIZE SHA1_BLOCK_SIZE
48#define MD5_DIGEST_SIZE 16
49
50#define SHA_REG_DIGCNT 0x14
51
52#define SHA_REG_CTRL 0x18
53#define SHA_REG_CTRL_LENGTH (0xFFFFFFFF << 5)
54#define SHA_REG_CTRL_CLOSE_HASH (1 << 4)
55#define SHA_REG_CTRL_ALGO_CONST (1 << 3)
56#define SHA_REG_CTRL_ALGO (1 << 2)
57#define SHA_REG_CTRL_INPUT_READY (1 << 1)
58#define SHA_REG_CTRL_OUTPUT_READY (1 << 0)
59
60#define SHA_REG_REV 0x5C
61#define SHA_REG_REV_MAJOR 0xF0
62#define SHA_REG_REV_MINOR 0x0F
63
64#define SHA_REG_MASK 0x60
65#define SHA_REG_MASK_DMA_EN (1 << 3)
66#define SHA_REG_MASK_IT_EN (1 << 2)
67#define SHA_REG_MASK_SOFTRESET (1 << 1)
68#define SHA_REG_AUTOIDLE (1 << 0)
69
70#define SHA_REG_SYSSTATUS 0x64
71#define SHA_REG_SYSSTATUS_RESETDONE (1 << 0)
72
73#define DEFAULT_TIMEOUT_INTERVAL HZ
74
75#define FLAGS_FIRST 0x0001
76#define FLAGS_FINUP 0x0002
77#define FLAGS_FINAL 0x0004
78#define FLAGS_FAST 0x0008
79#define FLAGS_SHA1 0x0010
80#define FLAGS_DMA_ACTIVE 0x0020
81#define FLAGS_OUTPUT_READY 0x0040
82#define FLAGS_CLEAN 0x0080
83#define FLAGS_INIT 0x0100
84#define FLAGS_CPU 0x0200
85#define FLAGS_HMAC 0x0400
86
87/* 3rd byte */
88#define FLAGS_BUSY 16
89
90#define OP_UPDATE 1
91#define OP_FINAL 2
92
93struct omap_sham_dev;
94
95struct omap_sham_reqctx {
96 struct omap_sham_dev *dd;
97 unsigned long flags;
98 unsigned long op;
99
0c3cf4cc 100 u8 digest[SHA1_DIGEST_SIZE];
8628e7c8
DK		 101 size_t digcnt;
102 u8 *buffer;
103 size_t bufcnt;
104 size_t buflen;
105 dma_addr_t dma_addr;
106
107 /* walk state */
108 struct scatterlist *sg;
109 unsigned int offset; /* offset in current sg */
110 unsigned int total; /* total request */
111};
112
113struct omap_sham_hmac_ctx {
114 struct crypto_shash *shash;
115 u8 ipad[SHA1_MD5_BLOCK_SIZE];
116 u8 opad[SHA1_MD5_BLOCK_SIZE];
117};
118
119struct omap_sham_ctx {
120 struct omap_sham_dev *dd;
121
122 unsigned long flags;
123
124 /* fallback stuff */
125 struct crypto_shash *fallback;
126
127 struct omap_sham_hmac_ctx base[0];
128};
129
130#define OMAP_SHAM_QUEUE_LENGTH 1
131
132struct omap_sham_dev {
133 struct list_head list;
134 unsigned long phys_base;
135 struct device *dev;
136 void __iomem *io_base;
137 int irq;
138 struct clk *iclk;
139 spinlock_t lock;
140 int dma;
141 int dma_lch;
142 struct tasklet_struct done_task;
143 struct tasklet_struct queue_task;
144
145 unsigned long flags;
146 struct crypto_queue queue;
147 struct ahash_request *req;
148};
149
150struct omap_sham_drv {
151 struct list_head dev_list;
152 spinlock_t lock;
153 unsigned long flags;
154};
155
156static struct omap_sham_drv sham = {
157 .dev_list = LIST_HEAD_INIT(sham.dev_list),
158 .lock = __SPIN_LOCK_UNLOCKED(sham.lock),
159};
160
161static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset)
162{
163 return __raw_readl(dd->io_base + offset);
164}
165
166static inline void omap_sham_write(struct omap_sham_dev *dd,
167 u32 offset, u32 value)
168{
169 __raw_writel(value, dd->io_base + offset);
170}
171
172static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address,
173 u32 value, u32 mask)
174{
175 u32 val;
176
177 val = omap_sham_read(dd, address);
178 val &= ~mask;
179 val |= value;
180 omap_sham_write(dd, address, val);
181}
182
183static inline int omap_sham_wait(struct omap_sham_dev *dd, u32 offset, u32 bit)
184{
185 unsigned long timeout = jiffies + DEFAULT_TIMEOUT_INTERVAL;
186
187 while (!(omap_sham_read(dd, offset) & bit)) {
188 if (time_is_before_jiffies(timeout))
189 return -ETIMEDOUT;
190 }
191
192 return 0;
193}
194
195static void omap_sham_copy_hash(struct ahash_request *req, int out)
196{
197 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
0c3cf4cc 198 u32 *hash = (u32 *)ctx->digest;
8628e7c8
DK		 199 int i;
200
201 if (likely(ctx->flags & FLAGS_SHA1)) {
202 /* SHA1 results are in big endian */
203 for (i = 0; i < SHA1_DIGEST_SIZE / sizeof(u32); i++)
204 if (out)
205 hash[i] = be32_to_cpu(omap_sham_read(ctx->dd,
206 SHA_REG_DIGEST(i)));
207 else
208 omap_sham_write(ctx->dd, SHA_REG_DIGEST(i),
209 cpu_to_be32(hash[i]));
210 } else {
211 /* MD5 results are in little endian */
212 for (i = 0; i < MD5_DIGEST_SIZE / sizeof(u32); i++)
213 if (out)
214 hash[i] = le32_to_cpu(omap_sham_read(ctx->dd,
215 SHA_REG_DIGEST(i)));
216 else
217 omap_sham_write(ctx->dd, SHA_REG_DIGEST(i),
218 cpu_to_le32(hash[i]));
219 }
220}
221
222static int omap_sham_write_ctrl(struct omap_sham_dev *dd, size_t length,
223 int final, int dma)
224{
225 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
226 u32 val = length << 5, mask;
227
228 if (unlikely(!ctx->digcnt)) {
229
230 clk_enable(dd->iclk);
231
232 if (!(dd->flags & FLAGS_INIT)) {
233 omap_sham_write_mask(dd, SHA_REG_MASK,
234 SHA_REG_MASK_SOFTRESET, SHA_REG_MASK_SOFTRESET);
235
236 if (omap_sham_wait(dd, SHA_REG_SYSSTATUS,
237 SHA_REG_SYSSTATUS_RESETDONE))
238 return -ETIMEDOUT;
239
240 dd->flags |= FLAGS_INIT;
241 }
242 } else {
243 omap_sham_write(dd, SHA_REG_DIGCNT, ctx->digcnt);
244 }
245
246 omap_sham_write_mask(dd, SHA_REG_MASK,
247 SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0),
248 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
249 /*
250 * Setting ALGO_CONST only for the first iteration
251 * and CLOSE_HASH only for the last one.
252 */
253 if (ctx->flags & FLAGS_SHA1)
254 val |= SHA_REG_CTRL_ALGO;
255 if (!ctx->digcnt)
256 val |= SHA_REG_CTRL_ALGO_CONST;
257 if (final)
258 val |= SHA_REG_CTRL_CLOSE_HASH;
259
260 mask = SHA_REG_CTRL_ALGO_CONST | SHA_REG_CTRL_CLOSE_HASH |
261 SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH;
262
263 omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask);
264
265 return 0;
266}
267
268static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, const u8 *buf,
269 size_t length, int final)
270{
271 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
272 int err, count, len32;
273 const u32 *buffer = (const u32 *)buf;
274
275 dev_dbg(dd->dev, "xmit_cpu: digcnt: %d, length: %d, final: %d\n",
276 ctx->digcnt, length, final);
277
278 err = omap_sham_write_ctrl(dd, length, final, 0);
279 if (err)
280 return err;
281
282 if (omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY))
283 return -ETIMEDOUT;
284
285 ctx->digcnt += length;
286
287 if (final)
288 ctx->flags |= FLAGS_FINAL; /* catch last interrupt */
289
290 len32 = DIV_ROUND_UP(length, sizeof(u32));
291
292 for (count = 0; count < len32; count++)
293 omap_sham_write(dd, SHA_REG_DIN(count), buffer[count]);
294
295 return -EINPROGRESS;
296}
297
298static int omap_sham_xmit_dma(struct omap_sham_dev *dd, dma_addr_t dma_addr,
299 size_t length, int final)
300{
301 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
302 int err, len32;
303
304 dev_dbg(dd->dev, "xmit_dma: digcnt: %d, length: %d, final: %d\n",
305 ctx->digcnt, length, final);
306
307 /* flush cache entries related to our page */
308 if (dma_addr == ctx->dma_addr)
309 dma_sync_single_for_device(dd->dev, dma_addr, length,
310 DMA_TO_DEVICE);
311
312 len32 = DIV_ROUND_UP(length, sizeof(u32));
313
314 omap_set_dma_transfer_params(dd->dma_lch, OMAP_DMA_DATA_TYPE_S32, len32,
584db6a1
SO		 315 1, OMAP_DMA_SYNC_PACKET, dd->dma,
316 OMAP_DMA_DST_SYNC_PREFETCH);
8628e7c8
DK		 317
318 omap_set_dma_src_params(dd->dma_lch, 0, OMAP_DMA_AMODE_POST_INC,
319 dma_addr, 0, 0);
320
c8eb5404
DK		 321 omap_set_dma_dest_params(dd->dma_lch, 0,
322 OMAP_DMA_AMODE_CONSTANT,
323 dd->phys_base + SHA_REG_DIN(0), 0, 16);
324
325 omap_set_dma_dest_burst_mode(dd->dma_lch,
326 OMAP_DMA_DATA_BURST_16);
327
328 omap_set_dma_src_burst_mode(dd->dma_lch,
329 OMAP_DMA_DATA_BURST_4);
330
8628e7c8
DK		 331 err = omap_sham_write_ctrl(dd, length, final, 1);
332 if (err)
333 return err;
334
335 ctx->digcnt += length;
336
337 if (final)
338 ctx->flags |= FLAGS_FINAL; /* catch last interrupt */
339
340 dd->flags |= FLAGS_DMA_ACTIVE;
341
342 omap_start_dma(dd->dma_lch);
343
344 return -EINPROGRESS;
345}
346
347static size_t omap_sham_append_buffer(struct omap_sham_reqctx *ctx,
348 const u8 *data, size_t length)
349{
350 size_t count = min(length, ctx->buflen - ctx->bufcnt);
351
352 count = min(count, ctx->total);
353 if (count <= 0)
354 return 0;
355 memcpy(ctx->buffer + ctx->bufcnt, data, count);
356 ctx->bufcnt += count;
357
358 return count;
359}
360
361static size_t omap_sham_append_sg(struct omap_sham_reqctx *ctx)
362{
363 size_t count;
364
365 while (ctx->sg) {
366 count = omap_sham_append_buffer(ctx,
367 sg_virt(ctx->sg) + ctx->offset,
368 ctx->sg->length - ctx->offset);
369 if (!count)
370 break;
371 ctx->offset += count;
372 ctx->total -= count;
373 if (ctx->offset == ctx->sg->length) {
374 ctx->sg = sg_next(ctx->sg);
375 if (ctx->sg)
376 ctx->offset = 0;
377 else
378 ctx->total = 0;
379 }
380 }
381
382 return 0;
383}
384
385static int omap_sham_update_dma_slow(struct omap_sham_dev *dd)
386{
387 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
388 unsigned int final;
389 size_t count;
390
391 if (!ctx->total)
392 return 0;
393
394 omap_sham_append_sg(ctx);
395
396 final = (ctx->flags & FLAGS_FINUP) && !ctx->total;
397
398 dev_dbg(dd->dev, "slow: bufcnt: %u, digcnt: %d, final: %d\n",
399 ctx->bufcnt, ctx->digcnt, final);
400
401 if (final || (ctx->bufcnt == ctx->buflen && ctx->total)) {
402 count = ctx->bufcnt;
403 ctx->bufcnt = 0;
404 return omap_sham_xmit_dma(dd, ctx->dma_addr, count, final);
405 }
406
407 return 0;
408}
409
410static int omap_sham_update_dma_fast(struct omap_sham_dev *dd)
411{
412 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
413 unsigned int length;
414
415 ctx->flags |= FLAGS_FAST;
416
417 length = min(ctx->total, sg_dma_len(ctx->sg));
418 ctx->total = length;
419
420 if (!dma_map_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE)) {
421 dev_err(dd->dev, "dma_map_sg error\n");
422 return -EINVAL;
423 }
424
425 ctx->total -= length;
426
427 return omap_sham_xmit_dma(dd, sg_dma_address(ctx->sg), length, 1);
428}
429
430static int omap_sham_update_cpu(struct omap_sham_dev *dd)
431{
432 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
433 int bufcnt;
434
435 omap_sham_append_sg(ctx);
436 bufcnt = ctx->bufcnt;
437 ctx->bufcnt = 0;
438
439 return omap_sham_xmit_cpu(dd, ctx->buffer, bufcnt, 1);
440}
441
442static int omap_sham_update_dma_stop(struct omap_sham_dev *dd)
443{
444 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
445
446 omap_stop_dma(dd->dma_lch);
447 if (ctx->flags & FLAGS_FAST)
448 dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE);
449
450 return 0;
451}
452
453static void omap_sham_cleanup(struct ahash_request *req)
454{
455 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
456 struct omap_sham_dev *dd = ctx->dd;
457 unsigned long flags;
458
459 spin_lock_irqsave(&dd->lock, flags);
460 if (ctx->flags & FLAGS_CLEAN) {
461 spin_unlock_irqrestore(&dd->lock, flags);
462 return;
463 }
464 ctx->flags |= FLAGS_CLEAN;
465 spin_unlock_irqrestore(&dd->lock, flags);
466
0c3cf4cc 467 if (ctx->digcnt) {
8628e7c8 468 clk_disable(dd->iclk);
0c3cf4cc
DK		 469 memcpy(req->result, ctx->digest, (ctx->flags & FLAGS_SHA1) ?
470 SHA1_DIGEST_SIZE : MD5_DIGEST_SIZE);
471 }
8628e7c8
DK		 472
473 if (ctx->dma_addr)
474 dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen,
475 DMA_TO_DEVICE);
476
477 if (ctx->buffer)
478 free_page((unsigned long)ctx->buffer);
479
480 dev_dbg(dd->dev, "digcnt: %d, bufcnt: %d\n", ctx->digcnt, ctx->bufcnt);
481}
482
483static int omap_sham_init(struct ahash_request *req)
484{
485 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
486 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
487 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
488 struct omap_sham_dev *dd = NULL, *tmp;
489
490 spin_lock_bh(&sham.lock);
491 if (!tctx->dd) {
492 list_for_each_entry(tmp, &sham.dev_list, list) {
493 dd = tmp;
494 break;
495 }
496 tctx->dd = dd;
497 } else {
498 dd = tctx->dd;
499 }
500 spin_unlock_bh(&sham.lock);
501
502 ctx->dd = dd;
503
504 ctx->flags = 0;
505
506 ctx->flags |= FLAGS_FIRST;
507
508 dev_dbg(dd->dev, "init: digest size: %d\n",
509 crypto_ahash_digestsize(tfm));
510
511 if (crypto_ahash_digestsize(tfm) == SHA1_DIGEST_SIZE)
512 ctx->flags |= FLAGS_SHA1;
513
514 ctx->bufcnt = 0;
515 ctx->digcnt = 0;
516
517 ctx->buflen = PAGE_SIZE;
518 ctx->buffer = (void *)__get_free_page(
519 (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
520 GFP_KERNEL : GFP_ATOMIC);
521 if (!ctx->buffer)
522 return -ENOMEM;
523
524 ctx->dma_addr = dma_map_single(dd->dev, ctx->buffer, ctx->buflen,
525 DMA_TO_DEVICE);
526 if (dma_mapping_error(dd->dev, ctx->dma_addr)) {
527 dev_err(dd->dev, "dma %u bytes error\n", ctx->buflen);
528 free_page((unsigned long)ctx->buffer);
529 return -EINVAL;
530 }
531
532 if (tctx->flags & FLAGS_HMAC) {
533 struct omap_sham_hmac_ctx *bctx = tctx->base;
534
535 memcpy(ctx->buffer, bctx->ipad, SHA1_MD5_BLOCK_SIZE);
536 ctx->bufcnt = SHA1_MD5_BLOCK_SIZE;
537 ctx->flags |= FLAGS_HMAC;
538 }
539
540 return 0;
541
542}
543
544static int omap_sham_update_req(struct omap_sham_dev *dd)
545{
546 struct ahash_request *req = dd->req;
547 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
548 int err;
549
550 dev_dbg(dd->dev, "update_req: total: %u, digcnt: %d, finup: %d\n",
551 ctx->total, ctx->digcnt, (ctx->flags & FLAGS_FINUP) != 0);
552
553 if (ctx->flags & FLAGS_CPU)
554 err = omap_sham_update_cpu(dd);
555 else if (ctx->flags & FLAGS_FAST)
556 err = omap_sham_update_dma_fast(dd);
557 else
558 err = omap_sham_update_dma_slow(dd);
559
560 /* wait for dma completion before can take more data */
561 dev_dbg(dd->dev, "update: err: %d, digcnt: %d\n", err, ctx->digcnt);
562
563 return err;
564}
565
566static int omap_sham_final_req(struct omap_sham_dev *dd)
567{
568 struct ahash_request *req = dd->req;
569 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
570 int err = 0, use_dma = 1;
571
572 if (ctx->bufcnt <= 64)
573 /* faster to handle last block with cpu */
574 use_dma = 0;
575
576 if (use_dma)
577 err = omap_sham_xmit_dma(dd, ctx->dma_addr, ctx->bufcnt, 1);
578 else
579 err = omap_sham_xmit_cpu(dd, ctx->buffer, ctx->bufcnt, 1);
580
581 ctx->bufcnt = 0;
582
583 if (err != -EINPROGRESS)
584 omap_sham_cleanup(req);
585
586 dev_dbg(dd->dev, "final_req: err: %d\n", err);
587
588 return err;
589}
590
591static int omap_sham_finish_req_hmac(struct ahash_request *req)
592{
0c3cf4cc 593 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
8628e7c8
DK		 594 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
595 struct omap_sham_hmac_ctx *bctx = tctx->base;
596 int bs = crypto_shash_blocksize(bctx->shash);
597 int ds = crypto_shash_digestsize(bctx->shash);
598 struct {
599 struct shash_desc shash;
600 char ctx[crypto_shash_descsize(bctx->shash)];
601 } desc;
602
603 desc.shash.tfm = bctx->shash;
604 desc.shash.flags = 0; /* not CRYPTO_TFM_REQ_MAY_SLEEP */
605
606 return crypto_shash_init(&desc.shash) ?:
607 crypto_shash_update(&desc.shash, bctx->opad, bs) ?:
0c3cf4cc 608 crypto_shash_finup(&desc.shash, ctx->digest, ds, ctx->digest);
8628e7c8
DK		 609}
610
611static void omap_sham_finish_req(struct ahash_request *req, int err)
612{
613 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
614
615 if (!err) {
616 omap_sham_copy_hash(ctx->dd->req, 1);
617 if (ctx->flags & FLAGS_HMAC)
618 err = omap_sham_finish_req_hmac(req);
619 }
620
621 if (ctx->flags & FLAGS_FINAL)
622 omap_sham_cleanup(req);
623
624 clear_bit(FLAGS_BUSY, &ctx->dd->flags);
625
626 if (req->base.complete)
627 req->base.complete(&req->base, err);
628}
629
630static int omap_sham_handle_queue(struct omap_sham_dev *dd)
631{
632 struct crypto_async_request *async_req, *backlog;
633 struct omap_sham_reqctx *ctx;
634 struct ahash_request *req, *prev_req;
635 unsigned long flags;
636 int err = 0;
637
638 if (test_and_set_bit(FLAGS_BUSY, &dd->flags))
639 return 0;
640
641 spin_lock_irqsave(&dd->lock, flags);
642 backlog = crypto_get_backlog(&dd->queue);
643 async_req = crypto_dequeue_request(&dd->queue);
644 if (!async_req)
645 clear_bit(FLAGS_BUSY, &dd->flags);
646 spin_unlock_irqrestore(&dd->lock, flags);
647
648 if (!async_req)
649 return 0;
650
651 if (backlog)
652 backlog->complete(backlog, -EINPROGRESS);
653
654 req = ahash_request_cast(async_req);
655
656 prev_req = dd->req;
657 dd->req = req;
658
659 ctx = ahash_request_ctx(req);
660
661 dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n",
662 ctx->op, req->nbytes);
663
664 if (req != prev_req && ctx->digcnt)
665 /* request has changed - restore hash */
666 omap_sham_copy_hash(req, 0);
667
668 if (ctx->op == OP_UPDATE) {
669 err = omap_sham_update_req(dd);
670 if (err != -EINPROGRESS && (ctx->flags & FLAGS_FINUP))
671 /* no final() after finup() */
672 err = omap_sham_final_req(dd);
673 } else if (ctx->op == OP_FINAL) {
674 err = omap_sham_final_req(dd);
675 }
676
677 if (err != -EINPROGRESS) {
678 /* done_task will not finish it, so do it here */
679 omap_sham_finish_req(req, err);
680 tasklet_schedule(&dd->queue_task);
681 }
682
683 dev_dbg(dd->dev, "exit, err: %d\n", err);
684
685 return err;
686}
687
688static int omap_sham_enqueue(struct ahash_request *req, unsigned int op)
689{
690 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
691 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
692 struct omap_sham_dev *dd = tctx->dd;
693 unsigned long flags;
694 int err;
695
696 ctx->op = op;
697
698 spin_lock_irqsave(&dd->lock, flags);
699 err = ahash_enqueue_request(&dd->queue, req);
700 spin_unlock_irqrestore(&dd->lock, flags);
701
702 omap_sham_handle_queue(dd);
703
704 return err;
705}
706
707static int omap_sham_update(struct ahash_request *req)
708{
709 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
710
711 if (!req->nbytes)
712 return 0;
713
714 ctx->total = req->nbytes;
715 ctx->sg = req->src;
716 ctx->offset = 0;
717
718 if (ctx->flags & FLAGS_FINUP) {
719 if ((ctx->digcnt + ctx->bufcnt + ctx->total) < 9) {
720 /*
721 * OMAP HW accel works only with buffers >= 9
722 * will switch to bypass in final()
723 * final has the same request and data
724 */
725 omap_sham_append_sg(ctx);
726 return 0;
727 } else if (ctx->bufcnt + ctx->total <= 64) {
728 ctx->flags |= FLAGS_CPU;
729 } else if (!ctx->bufcnt && sg_is_last(ctx->sg)) {
730 /* may be can use faster functions */
731 int aligned = IS_ALIGNED((u32)ctx->sg->offset,
732 sizeof(u32));
733
734 if (aligned && (ctx->flags & FLAGS_FIRST))
735 /* digest: first and final */
736 ctx->flags |= FLAGS_FAST;
737
738 ctx->flags &= ~FLAGS_FIRST;
739 }
740 } else if (ctx->bufcnt + ctx->total <= ctx->buflen) {
741 /* if not finaup -> not fast */
742 omap_sham_append_sg(ctx);
743 return 0;
744 }
745
746 return omap_sham_enqueue(req, OP_UPDATE);
747}
748
749static int omap_sham_shash_digest(struct crypto_shash *shash, u32 flags,
750 const u8 *data, unsigned int len, u8 *out)
751{
752 struct {
753 struct shash_desc shash;
754 char ctx[crypto_shash_descsize(shash)];
755 } desc;
756
757 desc.shash.tfm = shash;
758 desc.shash.flags = flags & CRYPTO_TFM_REQ_MAY_SLEEP;
759
760 return crypto_shash_digest(&desc.shash, data, len, out);
761}
762
763static int omap_sham_final_shash(struct ahash_request *req)
764{
765 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
766 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
767
768 return omap_sham_shash_digest(tctx->fallback, req->base.flags,
769 ctx->buffer, ctx->bufcnt, req->result);
770}
771
772static int omap_sham_final(struct ahash_request *req)
773{
774 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
775 int err = 0;
776
777 ctx->flags |= FLAGS_FINUP;
778
779 /* OMAP HW accel works only with buffers >= 9 */
780 /* HMAC is always >= 9 because of ipad */
781 if ((ctx->digcnt + ctx->bufcnt) < 9)
782 err = omap_sham_final_shash(req);
783 else if (ctx->bufcnt)
784 return omap_sham_enqueue(req, OP_FINAL);
785
786 omap_sham_cleanup(req);
787
788 return err;
789}
790
791static int omap_sham_finup(struct ahash_request *req)
792{
793 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
794 int err1, err2;
795
796 ctx->flags |= FLAGS_FINUP;
797
798 err1 = omap_sham_update(req);
799 if (err1 == -EINPROGRESS)
800 return err1;
801 /*
802 * final() has to be always called to cleanup resources
803 * even if udpate() failed, except EINPROGRESS
804 */
805 err2 = omap_sham_final(req);
806
807 return err1 ?: err2;
808}
809
810static int omap_sham_digest(struct ahash_request *req)
811{
812 return omap_sham_init(req) ?: omap_sham_finup(req);
813}
814
815static int omap_sham_setkey(struct crypto_ahash *tfm, const u8 *key,
816 unsigned int keylen)
817{
818 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
819 struct omap_sham_hmac_ctx *bctx = tctx->base;
820 int bs = crypto_shash_blocksize(bctx->shash);
821 int ds = crypto_shash_digestsize(bctx->shash);
822 int err, i;
823 err = crypto_shash_setkey(tctx->fallback, key, keylen);
824 if (err)
825 return err;
826
827 if (keylen > bs) {
828 err = omap_sham_shash_digest(bctx->shash,
829 crypto_shash_get_flags(bctx->shash),
830 key, keylen, bctx->ipad);
831 if (err)
832 return err;
833 keylen = ds;
834 } else {
835 memcpy(bctx->ipad, key, keylen);
836 }
837
838 memset(bctx->ipad + keylen, 0, bs - keylen);
839 memcpy(bctx->opad, bctx->ipad, bs);
840
841 for (i = 0; i < bs; i++) {
842 bctx->ipad[i] ^= 0x36;
843 bctx->opad[i] ^= 0x5c;
844 }
845
846 return err;
847}
848
849static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base)
850{
851 struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
852 const char *alg_name = crypto_tfm_alg_name(tfm);
853
854 /* Allocate a fallback and abort if it failed. */
855 tctx->fallback = crypto_alloc_shash(alg_name, 0,
856 CRYPTO_ALG_NEED_FALLBACK);
857 if (IS_ERR(tctx->fallback)) {
858 pr_err("omap-sham: fallback driver '%s' "
859 "could not be loaded.\n", alg_name);
860 return PTR_ERR(tctx->fallback);
861 }
862
863 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
864 sizeof(struct omap_sham_reqctx));
865
866 if (alg_base) {
867 struct omap_sham_hmac_ctx *bctx = tctx->base;
868 tctx->flags |= FLAGS_HMAC;
869 bctx->shash = crypto_alloc_shash(alg_base, 0,
870 CRYPTO_ALG_NEED_FALLBACK);
871 if (IS_ERR(bctx->shash)) {
872 pr_err("omap-sham: base driver '%s' "
873 "could not be loaded.\n", alg_base);
874 crypto_free_shash(tctx->fallback);
875 return PTR_ERR(bctx->shash);
876 }
877
878 }
879
880 return 0;
881}
882
883static int omap_sham_cra_init(struct crypto_tfm *tfm)
884{
885 return omap_sham_cra_init_alg(tfm, NULL);
886}
887
888static int omap_sham_cra_sha1_init(struct crypto_tfm *tfm)
889{
890 return omap_sham_cra_init_alg(tfm, "sha1");
891}
892
893static int omap_sham_cra_md5_init(struct crypto_tfm *tfm)
894{
895 return omap_sham_cra_init_alg(tfm, "md5");
896}
897
898static void omap_sham_cra_exit(struct crypto_tfm *tfm)
899{
900 struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
901
902 crypto_free_shash(tctx->fallback);
903 tctx->fallback = NULL;
904
905 if (tctx->flags & FLAGS_HMAC) {
906 struct omap_sham_hmac_ctx *bctx = tctx->base;
907 crypto_free_shash(bctx->shash);
908 }
909}
910
911static struct ahash_alg algs[] = {
912{
913 .init = omap_sham_init,
914 .update = omap_sham_update,
915 .final = omap_sham_final,
916 .finup = omap_sham_finup,
917 .digest = omap_sham_digest,
918 .halg.digestsize = SHA1_DIGEST_SIZE,
919 .halg.base = {
920 .cra_name = "sha1",
921 .cra_driver_name = "omap-sha1",
922 .cra_priority = 100,
923 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
924 CRYPTO_ALG_ASYNC |
925 CRYPTO_ALG_NEED_FALLBACK,
926 .cra_blocksize = SHA1_BLOCK_SIZE,
927 .cra_ctxsize = sizeof(struct omap_sham_ctx),
928 .cra_alignmask = 0,
929 .cra_module = THIS_MODULE,
930 .cra_init = omap_sham_cra_init,
931 .cra_exit = omap_sham_cra_exit,
932 }
933},
934{
935 .init = omap_sham_init,
936 .update = omap_sham_update,
937 .final = omap_sham_final,
938 .finup = omap_sham_finup,
939 .digest = omap_sham_digest,
940 .halg.digestsize = MD5_DIGEST_SIZE,
941 .halg.base = {
942 .cra_name = "md5",
943 .cra_driver_name = "omap-md5",
944 .cra_priority = 100,
945 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
946 CRYPTO_ALG_ASYNC |
947 CRYPTO_ALG_NEED_FALLBACK,
948 .cra_blocksize = SHA1_BLOCK_SIZE,
949 .cra_ctxsize = sizeof(struct omap_sham_ctx),
950 .cra_alignmask = 0,
951 .cra_module = THIS_MODULE,
952 .cra_init = omap_sham_cra_init,
953 .cra_exit = omap_sham_cra_exit,
954 }
955},
956{
957 .init = omap_sham_init,
958 .update = omap_sham_update,
959 .final = omap_sham_final,
960 .finup = omap_sham_finup,
961 .digest = omap_sham_digest,
962 .setkey = omap_sham_setkey,
963 .halg.digestsize = SHA1_DIGEST_SIZE,
964 .halg.base = {
965 .cra_name = "hmac(sha1)",
966 .cra_driver_name = "omap-hmac-sha1",
967 .cra_priority = 100,
968 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
969 CRYPTO_ALG_ASYNC |
970 CRYPTO_ALG_NEED_FALLBACK,
971 .cra_blocksize = SHA1_BLOCK_SIZE,
972 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
973 sizeof(struct omap_sham_hmac_ctx),
974 .cra_alignmask = 0,
975 .cra_module = THIS_MODULE,
976 .cra_init = omap_sham_cra_sha1_init,
977 .cra_exit = omap_sham_cra_exit,
978 }
979},
980{
981 .init = omap_sham_init,
982 .update = omap_sham_update,
983 .final = omap_sham_final,
984 .finup = omap_sham_finup,
985 .digest = omap_sham_digest,
986 .setkey = omap_sham_setkey,
987 .halg.digestsize = MD5_DIGEST_SIZE,
988 .halg.base = {
989 .cra_name = "hmac(md5)",
990 .cra_driver_name = "omap-hmac-md5",
991 .cra_priority = 100,
992 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
993 CRYPTO_ALG_ASYNC |
994 CRYPTO_ALG_NEED_FALLBACK,
995 .cra_blocksize = SHA1_BLOCK_SIZE,
996 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
997 sizeof(struct omap_sham_hmac_ctx),
998 .cra_alignmask = 0,
999 .cra_module = THIS_MODULE,
1000 .cra_init = omap_sham_cra_md5_init,
1001 .cra_exit = omap_sham_cra_exit,
1002 }
1003}
1004};
1005
1006static void omap_sham_done_task(unsigned long data)
1007{
1008 struct omap_sham_dev *dd = (struct omap_sham_dev *)data;
1009 struct ahash_request *req = dd->req;
1010 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1011 int ready = 1;
1012
1013 if (ctx->flags & FLAGS_OUTPUT_READY) {
1014 ctx->flags &= ~FLAGS_OUTPUT_READY;
1015 ready = 1;
1016 }
1017
1018 if (dd->flags & FLAGS_DMA_ACTIVE) {
1019 dd->flags &= ~FLAGS_DMA_ACTIVE;
1020 omap_sham_update_dma_stop(dd);
1021 omap_sham_update_dma_slow(dd);
1022 }
1023
1024 if (ready && !(dd->flags & FLAGS_DMA_ACTIVE)) {
1025 dev_dbg(dd->dev, "update done\n");
1026 /* finish curent request */
1027 omap_sham_finish_req(req, 0);
1028 /* start new request */
1029 omap_sham_handle_queue(dd);
1030 }
1031}
1032
1033static void omap_sham_queue_task(unsigned long data)
1034{
1035 struct omap_sham_dev *dd = (struct omap_sham_dev *)data;
1036
1037 omap_sham_handle_queue(dd);
1038}
1039
1040static irqreturn_t omap_sham_irq(int irq, void *dev_id)
1041{
1042 struct omap_sham_dev *dd = dev_id;
1043 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
1044
1045 if (!ctx) {
1046 dev_err(dd->dev, "unknown interrupt.\n");
1047 return IRQ_HANDLED;
1048 }
1049
1050 if (unlikely(ctx->flags & FLAGS_FINAL))
1051 /* final -> allow device to go to power-saving mode */
1052 omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH);
1053
1054 omap_sham_write_mask(dd, SHA_REG_CTRL, SHA_REG_CTRL_OUTPUT_READY,
1055 SHA_REG_CTRL_OUTPUT_READY);
1056 omap_sham_read(dd, SHA_REG_CTRL);
1057
1058 ctx->flags |= FLAGS_OUTPUT_READY;
1059 tasklet_schedule(&dd->done_task);
1060
1061 return IRQ_HANDLED;
1062}
1063
1064static void omap_sham_dma_callback(int lch, u16 ch_status, void *data)
1065{
1066 struct omap_sham_dev *dd = data;
1067
1068 if (likely(lch == dd->dma_lch))
1069 tasklet_schedule(&dd->done_task);
1070}
1071
1072static int omap_sham_dma_init(struct omap_sham_dev *dd)
1073{
1074 int err;
1075
1076 dd->dma_lch = -1;
1077
1078 err = omap_request_dma(dd->dma, dev_name(dd->dev),
1079 omap_sham_dma_callback, dd, &dd->dma_lch);
1080 if (err) {
1081 dev_err(dd->dev, "Unable to request DMA channel\n");
1082 return err;
1083 }
584db6a1 1084
8628e7c8
DK		 1085 return 0;
1086}
1087
1088static void omap_sham_dma_cleanup(struct omap_sham_dev *dd)
1089{
1090 if (dd->dma_lch >= 0) {
1091 omap_free_dma(dd->dma_lch);
1092 dd->dma_lch = -1;
1093 }
1094}
1095
1096static int __devinit omap_sham_probe(struct platform_device *pdev)
1097{
1098 struct omap_sham_dev *dd;
1099 struct device *dev = &pdev->dev;
1100 struct resource *res;
1101 int err, i, j;
1102
1103 dd = kzalloc(sizeof(struct omap_sham_dev), GFP_KERNEL);
1104 if (dd == NULL) {
1105 dev_err(dev, "unable to alloc data struct.\n");
1106 err = -ENOMEM;
1107 goto data_err;
1108 }
1109 dd->dev = dev;
1110 platform_set_drvdata(pdev, dd);
1111
1112 INIT_LIST_HEAD(&dd->list);
1113 spin_lock_init(&dd->lock);
1114 tasklet_init(&dd->done_task, omap_sham_done_task, (unsigned long)dd);
1115 tasklet_init(&dd->queue_task, omap_sham_queue_task, (unsigned long)dd);
1116 crypto_init_queue(&dd->queue, OMAP_SHAM_QUEUE_LENGTH);
1117
1118 dd->irq = -1;
1119
1120 /* Get the base address */
1121 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1122 if (!res) {
1123 dev_err(dev, "no MEM resource info\n");
1124 err = -ENODEV;
1125 goto res_err;
1126 }
1127 dd->phys_base = res->start;
1128
1129 /* Get the DMA */
1130 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1131 if (!res) {
1132 dev_err(dev, "no DMA resource info\n");
1133 err = -ENODEV;
1134 goto res_err;
1135 }
1136 dd->dma = res->start;
1137
1138 /* Get the IRQ */
1139 dd->irq = platform_get_irq(pdev, 0);
1140 if (dd->irq < 0) {
1141 dev_err(dev, "no IRQ resource info\n");
1142 err = dd->irq;
1143 goto res_err;
1144 }
1145
1146 err = request_irq(dd->irq, omap_sham_irq,
1147 IRQF_TRIGGER_LOW, dev_name(dev), dd);
1148 if (err) {
1149 dev_err(dev, "unable to request irq.\n");
1150 goto res_err;
1151 }
1152
1153 err = omap_sham_dma_init(dd);
1154 if (err)
1155 goto dma_err;
1156
1157 /* Initializing the clock */
1158 dd->iclk = clk_get(dev, "ick");
1159 if (!dd->iclk) {
1160 dev_err(dev, "clock intialization failed.\n");
1161 err = -ENODEV;
1162 goto clk_err;
1163 }
1164
1165 dd->io_base = ioremap(dd->phys_base, SZ_4K);
1166 if (!dd->io_base) {
1167 dev_err(dev, "can't ioremap\n");
1168 err = -ENOMEM;
1169 goto io_err;
1170 }
1171
1172 clk_enable(dd->iclk);
1173 dev_info(dev, "hw accel on OMAP rev %u.%u\n",
1174 (omap_sham_read(dd, SHA_REG_REV) & SHA_REG_REV_MAJOR) >> 4,
1175 omap_sham_read(dd, SHA_REG_REV) & SHA_REG_REV_MINOR);
1176 clk_disable(dd->iclk);
1177
1178 spin_lock(&sham.lock);
1179 list_add_tail(&dd->list, &sham.dev_list);
1180 spin_unlock(&sham.lock);
1181
1182 for (i = 0; i < ARRAY_SIZE(algs); i++) {
1183 err = crypto_register_ahash(&algs[i]);
1184 if (err)
1185 goto err_algs;
1186 }
1187
1188 return 0;
1189
1190err_algs:
1191 for (j = 0; j < i; j++)
1192 crypto_unregister_ahash(&algs[j]);
1193 iounmap(dd->io_base);
1194io_err:
1195 clk_put(dd->iclk);
1196clk_err:
1197 omap_sham_dma_cleanup(dd);
1198dma_err:
1199 if (dd->irq >= 0)
1200 free_irq(dd->irq, dd);
1201res_err:
1202 kfree(dd);
1203 dd = NULL;
1204data_err:
1205 dev_err(dev, "initialization failed.\n");
1206
1207 return err;
1208}
1209
1210static int __devexit omap_sham_remove(struct platform_device *pdev)
1211{
1212 static struct omap_sham_dev *dd;
1213 int i;
1214
1215 dd = platform_get_drvdata(pdev);
1216 if (!dd)
1217 return -ENODEV;
1218 spin_lock(&sham.lock);
1219 list_del(&dd->list);
1220 spin_unlock(&sham.lock);
1221 for (i = 0; i < ARRAY_SIZE(algs); i++)
1222 crypto_unregister_ahash(&algs[i]);
1223 tasklet_kill(&dd->done_task);
1224 tasklet_kill(&dd->queue_task);
1225 iounmap(dd->io_base);
1226 clk_put(dd->iclk);
1227 omap_sham_dma_cleanup(dd);
1228 if (dd->irq >= 0)
1229 free_irq(dd->irq, dd);
1230 kfree(dd);
1231 dd = NULL;
1232
1233 return 0;
1234}
1235
1236static struct platform_driver omap_sham_driver = {
1237 .probe = omap_sham_probe,
1238 .remove = omap_sham_remove,
1239 .driver = {
1240 .name = "omap-sham",
1241 .owner = THIS_MODULE,
1242 },
1243};
1244
1245static int __init omap_sham_mod_init(void)
1246{
1247 pr_info("loading %s driver\n", "omap-sham");
1248
1249 if (!cpu_class_is_omap2() ||
1250 omap_type() != OMAP2_DEVICE_TYPE_SEC) {
1251 pr_err("Unsupported cpu\n");
1252 return -ENODEV;
1253 }
1254
1255 return platform_driver_register(&omap_sham_driver);
1256}
1257
1258static void __exit omap_sham_mod_exit(void)
1259{
1260 platform_driver_unregister(&omap_sham_driver);
1261}
1262
1263module_init(omap_sham_mod_init);
1264module_exit(omap_sham_mod_exit);
1265
1266MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support.");
1267MODULE_LICENSE("GPL v2");
1268MODULE_AUTHOR("Dmitry Kasatkin");
Linux kernel - Deliverables
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