[deliverable/linux.git] / drivers / crypto / sunxi-ss / sun4i-ss.h

/*
 * sun4i-ss.h - hardware cryptographic accelerator for Allwinner A20 SoC
 *
 * Copyright (C) 2013-2015 Corentin LABBE <clabbe.montjoie@gmail.com>
 *
 * Support AES cipher with 128,192,256 bits keysize.
 * Support MD5 and SHA1 hash algorithms.
 * Support DES and 3DES
 *
 * You could find the datasheet in Documentation/arm/sunxi/README
 *
 * Licensed under the GPL-2.
 */

#include <linux/clk.h>
#include <linux/crypto.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/reset.h>
#include <crypto/scatterwalk.h>
#include <linux/scatterlist.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <crypto/md5.h>
#include <crypto/sha.h>
#include <crypto/hash.h>
#include <crypto/internal/hash.h>
#include <crypto/aes.h>
#include <crypto/des.h>
#include <crypto/internal/rng.h>

#define SS_CTL            0x00
#define SS_KEY0           0x04
#define SS_KEY1           0x08
#define SS_KEY2           0x0C
#define SS_KEY3           0x10
#define SS_KEY4           0x14
#define SS_KEY5           0x18
#define SS_KEY6           0x1C
#define SS_KEY7           0x20

#define SS_IV0            0x24
#define SS_IV1            0x28
#define SS_IV2            0x2C
#define SS_IV3            0x30

#define SS_FCSR           0x44

#define SS_MD0            0x4C
#define SS_MD1            0x50
#define SS_MD2            0x54
#define SS_MD3            0x58
#define SS_MD4            0x5C

#define SS_RXFIFO         0x200
#define SS_TXFIFO         0x204

/* SS_CTL configuration values */

/* PRNG generator mode - bit 15 */
#define SS_PRNG_ONESHOT		(0 << 15)
#define SS_PRNG_CONTINUE	(1 << 15)

/* IV mode for hash */
#define SS_IV_ARBITRARY		(1 << 14)

/* SS operation mode - bits 12-13 */
#define SS_ECB			(0 << 12)
#define SS_CBC			(1 << 12)
#define SS_CTS			(3 << 12)

/* Counter width for CNT mode - bits 10-11 */
#define SS_CNT_16BITS		(0 << 10)
#define SS_CNT_32BITS		(1 << 10)
#define SS_CNT_64BITS		(2 << 10)

/* Key size for AES - bits 8-9 */
#define SS_AES_128BITS		(0 << 8)
#define SS_AES_192BITS		(1 << 8)
#define SS_AES_256BITS		(2 << 8)

/* Operation direction - bit 7 */
#define SS_ENCRYPTION		(0 << 7)
#define SS_DECRYPTION		(1 << 7)

/* SS Method - bits 4-6 */
#define SS_OP_AES		(0 << 4)
#define SS_OP_DES		(1 << 4)
#define SS_OP_3DES		(2 << 4)
#define SS_OP_SHA1		(3 << 4)
#define SS_OP_MD5		(4 << 4)
#define SS_OP_PRNG		(5 << 4)

/* Data end bit - bit 2 */
#define SS_DATA_END		(1 << 2)

/* PRNG start bit - bit 1 */
#define SS_PRNG_START		(1 << 1)

/* SS Enable bit - bit 0 */
#define SS_DISABLED		(0 << 0)
#define SS_ENABLED		(1 << 0)

/* SS_FCSR configuration values */
/* RX FIFO status - bit 30 */
#define SS_RXFIFO_FREE		(1 << 30)

/* RX FIFO empty spaces - bits 24-29 */
#define SS_RXFIFO_SPACES(val)	(((val) >> 24) & 0x3f)

/* TX FIFO status - bit 22 */
#define SS_TXFIFO_AVAILABLE	(1 << 22)

/* TX FIFO available spaces - bits 16-21 */
#define SS_TXFIFO_SPACES(val)	(((val) >> 16) & 0x3f)

#define SS_RX_MAX	32
#define SS_RX_DEFAULT	SS_RX_MAX
#define SS_TX_MAX	33

#define SS_RXFIFO_EMP_INT_PENDING	(1 << 10)
#define SS_TXFIFO_AVA_INT_PENDING	(1 << 8)
#define SS_RXFIFO_EMP_INT_ENABLE	(1 << 2)
#define SS_TXFIFO_AVA_INT_ENABLE	(1 << 0)

struct sun4i_ss_ctx {
	void __iomem *base;
	int irq;
	struct clk *busclk;
	struct clk *ssclk;
	struct reset_control *reset;
	struct device *dev;
	struct resource *res;
	spinlock_t slock; /* control the use of the device */
};

struct sun4i_ss_alg_template {
	u32 type;
	u32 mode;
	union {
		struct crypto_alg crypto;
		struct ahash_alg hash;
	} alg;
	struct sun4i_ss_ctx *ss;
};

struct sun4i_tfm_ctx {
	u32 key[AES_MAX_KEY_SIZE / 4];/* divided by sizeof(u32) */
	u32 keylen;
	u32 keymode;
	struct sun4i_ss_ctx *ss;
};

struct sun4i_cipher_req_ctx {
	u32 mode;
};

struct sun4i_req_ctx {
	u32 mode;
	u64 byte_count; /* number of bytes "uploaded" to the device */
	u32 hash[5]; /* for storing SS_IVx register */
	char buf[64];
	unsigned int len;
	struct sun4i_ss_ctx *ss;
};

int sun4i_hash_crainit(struct crypto_tfm *tfm);
int sun4i_hash_init(struct ahash_request *areq);
int sun4i_hash_update(struct ahash_request *areq);
int sun4i_hash_final(struct ahash_request *areq);
int sun4i_hash_finup(struct ahash_request *areq);
int sun4i_hash_digest(struct ahash_request *areq);
int sun4i_hash_export_md5(struct ahash_request *areq, void *out);
int sun4i_hash_import_md5(struct ahash_request *areq, const void *in);
int sun4i_hash_export_sha1(struct ahash_request *areq, void *out);
int sun4i_hash_import_sha1(struct ahash_request *areq, const void *in);

int sun4i_ss_cbc_aes_encrypt(struct ablkcipher_request *areq);
int sun4i_ss_cbc_aes_decrypt(struct ablkcipher_request *areq);
int sun4i_ss_ecb_aes_encrypt(struct ablkcipher_request *areq);
int sun4i_ss_ecb_aes_decrypt(struct ablkcipher_request *areq);

int sun4i_ss_cbc_des_encrypt(struct ablkcipher_request *areq);
int sun4i_ss_cbc_des_decrypt(struct ablkcipher_request *areq);
int sun4i_ss_ecb_des_encrypt(struct ablkcipher_request *areq);
int sun4i_ss_ecb_des_decrypt(struct ablkcipher_request *areq);

int sun4i_ss_cbc_des3_encrypt(struct ablkcipher_request *areq);
int sun4i_ss_cbc_des3_decrypt(struct ablkcipher_request *areq);
int sun4i_ss_ecb_des3_encrypt(struct ablkcipher_request *areq);
int sun4i_ss_ecb_des3_decrypt(struct ablkcipher_request *areq);

int sun4i_ss_cipher_init(struct crypto_tfm *tfm);
int sun4i_ss_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
			unsigned int keylen);
int sun4i_ss_des_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
			unsigned int keylen);
int sun4i_ss_des3_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
			 unsigned int keylen);
Commit	Line	Data
6298e948 LC	1	/*
	2	* sun4i-ss.h - hardware cryptographic accelerator for Allwinner A20 SoC
	3	*
	4	* Copyright (C) 2013-2015 Corentin LABBE <clabbe.montjoie@gmail.com>
	5	*
	6	* Support AES cipher with 128,192,256 bits keysize.
	7	* Support MD5 and SHA1 hash algorithms.
	8	* Support DES and 3DES
	9	*
	10	* You could find the datasheet in Documentation/arm/sunxi/README
	11	*
	12	* Licensed under the GPL-2.
	13	*/
	14
	15	#include <linux/clk.h>
	16	#include <linux/crypto.h>
	17	#include <linux/io.h>
	18	#include <linux/module.h>
	19	#include <linux/of.h>
	20	#include <linux/platform_device.h>
7ab64628	21	#include <linux/reset.h>
6298e948 LC	22	#include <crypto/scatterwalk.h>
	23	#include <linux/scatterlist.h>
	24	#include <linux/interrupt.h>
	25	#include <linux/delay.h>
	26	#include <crypto/md5.h>
	27	#include <crypto/sha.h>
	28	#include <crypto/hash.h>
	29	#include <crypto/internal/hash.h>
	30	#include <crypto/aes.h>
	31	#include <crypto/des.h>
	32	#include <crypto/internal/rng.h>
	33
	34	#define SS_CTL 0x00
	35	#define SS_KEY0 0x04
	36	#define SS_KEY1 0x08
	37	#define SS_KEY2 0x0C
	38	#define SS_KEY3 0x10
	39	#define SS_KEY4 0x14
	40	#define SS_KEY5 0x18
	41	#define SS_KEY6 0x1C
	42	#define SS_KEY7 0x20
	43
	44	#define SS_IV0 0x24
	45	#define SS_IV1 0x28
	46	#define SS_IV2 0x2C
	47	#define SS_IV3 0x30
	48
	49	#define SS_FCSR 0x44
	50
	51	#define SS_MD0 0x4C
	52	#define SS_MD1 0x50
	53	#define SS_MD2 0x54
	54	#define SS_MD3 0x58
	55	#define SS_MD4 0x5C
	56
	57	#define SS_RXFIFO 0x200
	58	#define SS_TXFIFO 0x204
	59
	60	/* SS_CTL configuration values */
	61
	62	/* PRNG generator mode - bit 15 */
	63	#define SS_PRNG_ONESHOT (0 << 15)
	64	#define SS_PRNG_CONTINUE (1 << 15)
	65
	66	/* IV mode for hash */
	67	#define SS_IV_ARBITRARY (1 << 14)
	68
	69	/* SS operation mode - bits 12-13 */
	70	#define SS_ECB (0 << 12)
	71	#define SS_CBC (1 << 12)
	72	#define SS_CTS (3 << 12)
	73
	74	/* Counter width for CNT mode - bits 10-11 */
	75	#define SS_CNT_16BITS (0 << 10)
	76	#define SS_CNT_32BITS (1 << 10)
	77	#define SS_CNT_64BITS (2 << 10)
	78
	79	/* Key size for AES - bits 8-9 */
	80	#define SS_AES_128BITS (0 << 8)
	81	#define SS_AES_192BITS (1 << 8)
	82	#define SS_AES_256BITS (2 << 8)
	83
	84	/* Operation direction - bit 7 */
	85	#define SS_ENCRYPTION (0 << 7)
86	#define SS_DECRYPTION (1 << 7)
87
88	/* SS Method - bits 4-6 */
89	#define SS_OP_AES (0 << 4)
90	#define SS_OP_DES (1 << 4)
91	#define SS_OP_3DES (2 << 4)
92	#define SS_OP_SHA1 (3 << 4)
93	#define SS_OP_MD5 (4 << 4)
94	#define SS_OP_PRNG (5 << 4)
95
96	/* Data end bit - bit 2 */
97	#define SS_DATA_END (1 << 2)
98
99	/* PRNG start bit - bit 1 */
100	#define SS_PRNG_START (1 << 1)
101
102	/* SS Enable bit - bit 0 */
103	#define SS_DISABLED (0 << 0)
104	#define SS_ENABLED (1 << 0)
105
106	/* SS_FCSR configuration values */
107	/* RX FIFO status - bit 30 */
108	#define SS_RXFIFO_FREE (1 << 30)
109
110	/* RX FIFO empty spaces - bits 24-29 */
111	#define SS_RXFIFO_SPACES(val) (((val) >> 24) & 0x3f)
112
113	/* TX FIFO status - bit 22 */
114	#define SS_TXFIFO_AVAILABLE (1 << 22)
115
116	/* TX FIFO available spaces - bits 16-21 */
117	#define SS_TXFIFO_SPACES(val) (((val) >> 16) & 0x3f)
118
119	#define SS_RX_MAX 32
120	#define SS_RX_DEFAULT SS_RX_MAX
121	#define SS_TX_MAX 33
122
123	#define SS_RXFIFO_EMP_INT_PENDING (1 << 10)
124	#define SS_TXFIFO_AVA_INT_PENDING (1 << 8)
125	#define SS_RXFIFO_EMP_INT_ENABLE (1 << 2)
126	#define SS_TXFIFO_AVA_INT_ENABLE (1 << 0)
127
128	struct sun4i_ss_ctx {
129	void __iomem *base;
130	int irq;
131	struct clk *busclk;
132	struct clk *ssclk;
7ab64628	133	struct reset_control *reset;
6298e948 LC	134	struct device *dev;
	135	struct resource *res;
	136	spinlock_t slock; /* control the use of the device */
	137	};
	138
	139	struct sun4i_ss_alg_template {
	140	u32 type;
	141	u32 mode;
	142	union {
	143	struct crypto_alg crypto;
	144	struct ahash_alg hash;
	145	} alg;
	146	struct sun4i_ss_ctx *ss;
	147	};
	148
	149	struct sun4i_tfm_ctx {
	150	u32 key[AES_MAX_KEY_SIZE / 4];/* divided by sizeof(u32) */
	151	u32 keylen;
	152	u32 keymode;
	153	struct sun4i_ss_ctx *ss;
	154	};
	155
	156	struct sun4i_cipher_req_ctx {
	157	u32 mode;
	158	};
	159
	160	struct sun4i_req_ctx {
	161	u32 mode;
	162	u64 byte_count; /* number of bytes "uploaded" to the device */
	163	u32 hash[5]; /* for storing SS_IVx register */
	164	char buf[64];
	165	unsigned int len;
	166	struct sun4i_ss_ctx *ss;
	167	};
	168
	169	int sun4i_hash_crainit(struct crypto_tfm *tfm);
	170	int sun4i_hash_init(struct ahash_request *areq);
	171	int sun4i_hash_update(struct ahash_request *areq);
	172	int sun4i_hash_final(struct ahash_request *areq);
	173	int sun4i_hash_finup(struct ahash_request *areq);
	174	int sun4i_hash_digest(struct ahash_request *areq);
	175	int sun4i_hash_export_md5(struct ahash_request areq, void out);
	176	int sun4i_hash_import_md5(struct ahash_request areq, const void in);
	177	int sun4i_hash_export_sha1(struct ahash_request areq, void out);
	178	int sun4i_hash_import_sha1(struct ahash_request areq, const void in);
	179
	180	int sun4i_ss_cbc_aes_encrypt(struct ablkcipher_request *areq);
	181	int sun4i_ss_cbc_aes_decrypt(struct ablkcipher_request *areq);
	182	int sun4i_ss_ecb_aes_encrypt(struct ablkcipher_request *areq);
	183	int sun4i_ss_ecb_aes_decrypt(struct ablkcipher_request *areq);
	184
	185	int sun4i_ss_cbc_des_encrypt(struct ablkcipher_request *areq);
	186	int sun4i_ss_cbc_des_decrypt(struct ablkcipher_request *areq);
	187	int sun4i_ss_ecb_des_encrypt(struct ablkcipher_request *areq);
	188	int sun4i_ss_ecb_des_decrypt(struct ablkcipher_request *areq);
	189
	190	int sun4i_ss_cbc_des3_encrypt(struct ablkcipher_request *areq);
	191	int sun4i_ss_cbc_des3_decrypt(struct ablkcipher_request *areq);
	192	int sun4i_ss_ecb_des3_encrypt(struct ablkcipher_request *areq);
	193	int sun4i_ss_ecb_des3_decrypt(struct ablkcipher_request *areq);
	194
	195	int sun4i_ss_cipher_init(struct crypto_tfm *tfm);
	196	int sun4i_ss_aes_setkey(struct crypto_ablkcipher tfm, const u8 key,
	197	unsigned int keylen);
198	int sun4i_ss_des_setkey(struct crypto_ablkcipher tfm, const u8 key,
199	unsigned int keylen);
200	int sun4i_ss_des3_setkey(struct crypto_ablkcipher tfm, const u8 key,
201	unsigned int keylen);