projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
crypto: talitos - add hash algorithms
[deliverable/linux.git] / drivers / crypto / talitos.c
CommitLineData
9c4a7965
KP		 1/*
2 * talitos - Freescale Integrated Security Engine (SEC) device driver
3 *
4 * Copyright (c) 2008 Freescale Semiconductor, Inc.
5 *
6 * Scatterlist Crypto API glue code copied from files with the following:
7 * Copyright (c) 2006-2007 Herbert Xu <herbert@gondor.apana.org.au>
8 *
9 * Crypto algorithm registration code copied from hifn driver:
10 * 2007+ Copyright (c) Evgeniy Polyakov <johnpol@2ka.mipt.ru>
11 * All rights reserved.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 */
27
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/mod_devicetable.h>
31#include <linux/device.h>
32#include <linux/interrupt.h>
33#include <linux/crypto.h>
34#include <linux/hw_random.h>
35#include <linux/of_platform.h>
36#include <linux/dma-mapping.h>
37#include <linux/io.h>
38#include <linux/spinlock.h>
39#include <linux/rtnetlink.h>
5a0e3ad6 40#include <linux/slab.h>
9c4a7965
KP		 41
42#include <crypto/algapi.h>
43#include <crypto/aes.h>
3952f17e 44#include <crypto/des.h>
9c4a7965 45#include <crypto/sha.h>
497f2e6b 46#include <crypto/md5.h>
9c4a7965
KP		 47#include <crypto/aead.h>
48#include <crypto/authenc.h>
4de9d0b5 49#include <crypto/skcipher.h>
acbf7c62
LN		 50#include <crypto/hash.h>
51#include <crypto/internal/hash.h>
4de9d0b5 52#include <crypto/scatterwalk.h>
9c4a7965
KP		 53
54#include "talitos.h"
55
56#define TALITOS_TIMEOUT 100000
57#define TALITOS_MAX_DATA_LEN 65535
58
59#define DESC_TYPE(desc_hdr) ((be32_to_cpu(desc_hdr) >> 3) & 0x1f)
60#define PRIMARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 28) & 0xf)
61#define SECONDARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 16) & 0xf)
62
63/* descriptor pointer entry */
64struct talitos_ptr {
65 __be16 len; /* length */
66 u8 j_extent; /* jump to sg link table and/or extent */
67 u8 eptr; /* extended address */
68 __be32 ptr; /* address */
69};
70
497f2e6b
LN		 71static const struct talitos_ptr zero_entry = {
72 .len = 0,
73 .j_extent = 0,
74 .eptr = 0,
75 .ptr = 0
76};
77
9c4a7965
KP		 78/* descriptor */
79struct talitos_desc {
80 __be32 hdr; /* header high bits */
81 __be32 hdr_lo; /* header low bits */
82 struct talitos_ptr ptr[7]; /* ptr/len pair array */
83};
84
85/**
86 * talitos_request - descriptor submission request
87 * @desc: descriptor pointer (kernel virtual)
88 * @dma_desc: descriptor's physical bus address
89 * @callback: whom to call when descriptor processing is done
90 * @context: caller context (optional)
91 */
92struct talitos_request {
93 struct talitos_desc *desc;
94 dma_addr_t dma_desc;
95 void (*callback) (struct device *dev, struct talitos_desc *desc,
96 void *context, int error);
97 void *context;
98};
99
4b992628
KP		 100/* per-channel fifo management */
101struct talitos_channel {
102 /* request fifo */
103 struct talitos_request *fifo;
104
105 /* number of requests pending in channel h/w fifo */
106 atomic_t submit_count ____cacheline_aligned;
107
108 /* request submission (head) lock */
109 spinlock_t head_lock ____cacheline_aligned;
110 /* index to next free descriptor request */
111 int head;
112
113 /* request release (tail) lock */
114 spinlock_t tail_lock ____cacheline_aligned;
115 /* index to next in-progress/done descriptor request */
116 int tail;
117};
118
9c4a7965
KP		 119struct talitos_private {
120 struct device *dev;
121 struct of_device *ofdev;
122 void __iomem *reg;
123 int irq;
124
125 /* SEC version geometry (from device tree node) */
126 unsigned int num_channels;
127 unsigned int chfifo_len;
128 unsigned int exec_units;
129 unsigned int desc_types;
130
f3c85bc1
LN		 131 /* SEC Compatibility info */
132 unsigned long features;
133
9c4a7965
KP		 134 /*
135 * length of the request fifo
136 * fifo_len is chfifo_len rounded up to next power of 2
137 * so we can use bitwise ops to wrap
138 */
139 unsigned int fifo_len;
140
4b992628 141 struct talitos_channel *chan;
9c4a7965 142
4b992628
KP		 143 /* next channel to be assigned next incoming descriptor */
144 atomic_t last_chan ____cacheline_aligned;
9c4a7965
KP		 145
146 /* request callback tasklet */
147 struct tasklet_struct done_task;
9c4a7965
KP		 148
149 /* list of registered algorithms */
150 struct list_head alg_list;
151
152 /* hwrng device */
153 struct hwrng rng;
154};
155
f3c85bc1
LN		 156/* .features flag */
157#define TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT 0x00000001
fe5720e2 158#define TALITOS_FTR_HW_AUTH_CHECK 0x00000002
f3c85bc1 159
81eb024c
KP		 160static void to_talitos_ptr(struct talitos_ptr *talitos_ptr, dma_addr_t dma_addr)
161{
162 talitos_ptr->ptr = cpu_to_be32(lower_32_bits(dma_addr));
163 talitos_ptr->eptr = cpu_to_be32(upper_32_bits(dma_addr));
164}
165
9c4a7965
KP		 166/*
167 * map virtual single (contiguous) pointer to h/w descriptor pointer
168 */
169static void map_single_talitos_ptr(struct device *dev,
170 struct talitos_ptr *talitos_ptr,
171 unsigned short len, void *data,
172 unsigned char extent,
173 enum dma_data_direction dir)
174{
81eb024c
KP		 175 dma_addr_t dma_addr = dma_map_single(dev, data, len, dir);
176
9c4a7965 177 talitos_ptr->len = cpu_to_be16(len);
81eb024c 178 to_talitos_ptr(talitos_ptr, dma_addr);
9c4a7965
KP		 179 talitos_ptr->j_extent = extent;
180}
181
182/*
183 * unmap bus single (contiguous) h/w descriptor pointer
184 */
185static void unmap_single_talitos_ptr(struct device *dev,
186 struct talitos_ptr *talitos_ptr,
187 enum dma_data_direction dir)
188{
189 dma_unmap_single(dev, be32_to_cpu(talitos_ptr->ptr),
190 be16_to_cpu(talitos_ptr->len), dir);
191}
192
193static int reset_channel(struct device *dev, int ch)
194{
195 struct talitos_private *priv = dev_get_drvdata(dev);
196 unsigned int timeout = TALITOS_TIMEOUT;
197
198 setbits32(priv->reg + TALITOS_CCCR(ch), TALITOS_CCCR_RESET);
199
200 while ((in_be32(priv->reg + TALITOS_CCCR(ch)) & TALITOS_CCCR_RESET)
201 && --timeout)
202 cpu_relax();
203
204 if (timeout == 0) {
205 dev_err(dev, "failed to reset channel %d\n", ch);
206 return -EIO;
207 }
208
81eb024c
KP		 209 /* set 36-bit addressing, done writeback enable and done IRQ enable */
210 setbits32(priv->reg + TALITOS_CCCR_LO(ch), TALITOS_CCCR_LO_EAE |
211 TALITOS_CCCR_LO_CDWE | TALITOS_CCCR_LO_CDIE);
9c4a7965 212
fe5720e2
KP		 213 /* and ICCR writeback, if available */
214 if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
215 setbits32(priv->reg + TALITOS_CCCR_LO(ch),
216 TALITOS_CCCR_LO_IWSE);
217
9c4a7965
KP		 218 return 0;
219}
220
221static int reset_device(struct device *dev)
222{
223 struct talitos_private *priv = dev_get_drvdata(dev);
224 unsigned int timeout = TALITOS_TIMEOUT;
225
226 setbits32(priv->reg + TALITOS_MCR, TALITOS_MCR_SWR);
227
228 while ((in_be32(priv->reg + TALITOS_MCR) & TALITOS_MCR_SWR)
229 && --timeout)
230 cpu_relax();
231
232 if (timeout == 0) {
233 dev_err(dev, "failed to reset device\n");
234 return -EIO;
235 }
236
237 return 0;
238}
239
240/*
241 * Reset and initialize the device
242 */
243static int init_device(struct device *dev)
244{
245 struct talitos_private *priv = dev_get_drvdata(dev);
246 int ch, err;
247
248 /*
249 * Master reset
250 * errata documentation: warning: certain SEC interrupts
251 * are not fully cleared by writing the MCR:SWR bit,
252 * set bit twice to completely reset
253 */
254 err = reset_device(dev);
255 if (err)
256 return err;
257
258 err = reset_device(dev);
259 if (err)
260 return err;
261
262 /* reset channels */
263 for (ch = 0; ch < priv->num_channels; ch++) {
264 err = reset_channel(dev, ch);
265 if (err)
266 return err;
267 }
268
269 /* enable channel done and error interrupts */
270 setbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_INIT);
271 setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT);
272
fe5720e2
KP		 273 /* disable integrity check error interrupts (use writeback instead) */
274 if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
275 setbits32(priv->reg + TALITOS_MDEUICR_LO,
276 TALITOS_MDEUICR_LO_ICE);
277
9c4a7965
KP		 278 return 0;
279}
280
281/**
282 * talitos_submit - submits a descriptor to the device for processing
283 * @dev: the SEC device to be used
284 * @desc: the descriptor to be processed by the device
285 * @callback: whom to call when processing is complete
286 * @context: a handle for use by caller (optional)
287 *
288 * desc must contain valid dma-mapped (bus physical) address pointers.
289 * callback must check err and feedback in descriptor header
290 * for device processing status.
291 */
292static int talitos_submit(struct device *dev, struct talitos_desc *desc,
293 void (*callback)(struct device *dev,
294 struct talitos_desc *desc,
295 void *context, int error),
296 void *context)
297{
298 struct talitos_private *priv = dev_get_drvdata(dev);
299 struct talitos_request *request;
300 unsigned long flags, ch;
301 int head;
302
303 /* select done notification */
304 desc->hdr |= DESC_HDR_DONE_NOTIFY;
305
306 /* emulate SEC's round-robin channel fifo polling scheme */
307 ch = atomic_inc_return(&priv->last_chan) & (priv->num_channels - 1);
308
4b992628 309 spin_lock_irqsave(&priv->chan[ch].head_lock, flags);
9c4a7965 310
4b992628 311 if (!atomic_inc_not_zero(&priv->chan[ch].submit_count)) {
ec6644d6 312 /* h/w fifo is full */
4b992628 313 spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
9c4a7965
KP		 314 return -EAGAIN;
315 }
316
4b992628
KP		 317 head = priv->chan[ch].head;
318 request = &priv->chan[ch].fifo[head];
ec6644d6 319
9c4a7965
KP		 320 /* map descriptor and save caller data */
321 request->dma_desc = dma_map_single(dev, desc, sizeof(*desc),
322 DMA_BIDIRECTIONAL);
323 request->callback = callback;
324 request->context = context;
325
326 /* increment fifo head */
4b992628 327 priv->chan[ch].head = (priv->chan[ch].head + 1) & (priv->fifo_len - 1);
9c4a7965
KP		 328
329 smp_wmb();
330 request->desc = desc;
331
332 /* GO! */
333 wmb();
81eb024c
KP		 334 out_be32(priv->reg + TALITOS_FF(ch),
335 cpu_to_be32(upper_32_bits(request->dma_desc)));
336 out_be32(priv->reg + TALITOS_FF_LO(ch),
337 cpu_to_be32(lower_32_bits(request->dma_desc)));
9c4a7965 338
4b992628 339 spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
9c4a7965
KP		 340
341 return -EINPROGRESS;
342}
343
344/*
345 * process what was done, notify callback of error if not
346 */
347static void flush_channel(struct device *dev, int ch, int error, int reset_ch)
348{
349 struct talitos_private *priv = dev_get_drvdata(dev);
350 struct talitos_request *request, saved_req;
351 unsigned long flags;
352 int tail, status;
353
4b992628 354 spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
9c4a7965 355
4b992628
KP		 356 tail = priv->chan[ch].tail;
357 while (priv->chan[ch].fifo[tail].desc) {
358 request = &priv->chan[ch].fifo[tail];
9c4a7965
KP		 359
360 /* descriptors with their done bits set don't get the error */
361 rmb();
ca38a814 362 if ((request->desc->hdr & DESC_HDR_DONE) == DESC_HDR_DONE)
9c4a7965 363 status = 0;
ca38a814 364 else
9c4a7965
KP		 365 if (!error)
366 break;
367 else
368 status = error;
369
370 dma_unmap_single(dev, request->dma_desc,
e938e465
KP		 371 sizeof(struct talitos_desc),
372 DMA_BIDIRECTIONAL);
9c4a7965
KP		 373
374 /* copy entries so we can call callback outside lock */
375 saved_req.desc = request->desc;
376 saved_req.callback = request->callback;
377 saved_req.context = request->context;
378
379 /* release request entry in fifo */
380 smp_wmb();
381 request->desc = NULL;
382
383 /* increment fifo tail */
4b992628 384 priv->chan[ch].tail = (tail + 1) & (priv->fifo_len - 1);
9c4a7965 385
4b992628 386 spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
ec6644d6 387
4b992628 388 atomic_dec(&priv->chan[ch].submit_count);
ec6644d6 389
9c4a7965
KP		 390 saved_req.callback(dev, saved_req.desc, saved_req.context,
391 status);
392 /* channel may resume processing in single desc error case */
393 if (error && !reset_ch && status == error)
394 return;
4b992628
KP		 395 spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
396 tail = priv->chan[ch].tail;
9c4a7965
KP		 397 }
398
4b992628 399 spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
9c4a7965
KP		 400}
401
402/*
403 * process completed requests for channels that have done status
404 */
405static void talitos_done(unsigned long data)
406{
407 struct device *dev = (struct device *)data;
408 struct talitos_private *priv = dev_get_drvdata(dev);
409 int ch;
410
411 for (ch = 0; ch < priv->num_channels; ch++)
412 flush_channel(dev, ch, 0, 0);
1c2e8811
LN		 413
414 /* At this point, all completed channels have been processed.
415 * Unmask done interrupts for channels completed later on.
416 */
fe5720e2
KP		 417 setbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_INIT);
418 setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT);
9c4a7965
KP		 419}
420
421/*
422 * locate current (offending) descriptor
423 */
424static struct talitos_desc *current_desc(struct device *dev, int ch)
425{
426 struct talitos_private *priv = dev_get_drvdata(dev);
4b992628 427 int tail = priv->chan[ch].tail;
9c4a7965
KP		 428 dma_addr_t cur_desc;
429
430 cur_desc = in_be32(priv->reg + TALITOS_CDPR_LO(ch));
431
4b992628 432 while (priv->chan[ch].fifo[tail].dma_desc != cur_desc) {
9c4a7965 433 tail = (tail + 1) & (priv->fifo_len - 1);
4b992628 434 if (tail == priv->chan[ch].tail) {
9c4a7965
KP		 435 dev_err(dev, "couldn't locate current descriptor\n");
436 return NULL;
437 }
438 }
439
4b992628 440 return priv->chan[ch].fifo[tail].desc;
9c4a7965
KP		 441}
442
443/*
444 * user diagnostics; report root cause of error based on execution unit status
445 */
e938e465
KP		 446static void report_eu_error(struct device *dev, int ch,
447 struct talitos_desc *desc)
9c4a7965
KP		 448{
449 struct talitos_private *priv = dev_get_drvdata(dev);
450 int i;
451
452 switch (desc->hdr & DESC_HDR_SEL0_MASK) {
453 case DESC_HDR_SEL0_AFEU:
454 dev_err(dev, "AFEUISR 0x%08x_%08x\n",
455 in_be32(priv->reg + TALITOS_AFEUISR),
456 in_be32(priv->reg + TALITOS_AFEUISR_LO));
457 break;
458 case DESC_HDR_SEL0_DEU:
459 dev_err(dev, "DEUISR 0x%08x_%08x\n",
460 in_be32(priv->reg + TALITOS_DEUISR),
461 in_be32(priv->reg + TALITOS_DEUISR_LO));
462 break;
463 case DESC_HDR_SEL0_MDEUA:
464 case DESC_HDR_SEL0_MDEUB:
465 dev_err(dev, "MDEUISR 0x%08x_%08x\n",
466 in_be32(priv->reg + TALITOS_MDEUISR),
467 in_be32(priv->reg + TALITOS_MDEUISR_LO));
468 break;
469 case DESC_HDR_SEL0_RNG:
470 dev_err(dev, "RNGUISR 0x%08x_%08x\n",
471 in_be32(priv->reg + TALITOS_RNGUISR),
472 in_be32(priv->reg + TALITOS_RNGUISR_LO));
473 break;
474 case DESC_HDR_SEL0_PKEU:
475 dev_err(dev, "PKEUISR 0x%08x_%08x\n",
476 in_be32(priv->reg + TALITOS_PKEUISR),
477 in_be32(priv->reg + TALITOS_PKEUISR_LO));
478 break;
479 case DESC_HDR_SEL0_AESU:
480 dev_err(dev, "AESUISR 0x%08x_%08x\n",
481 in_be32(priv->reg + TALITOS_AESUISR),
482 in_be32(priv->reg + TALITOS_AESUISR_LO));
483 break;
484 case DESC_HDR_SEL0_CRCU:
485 dev_err(dev, "CRCUISR 0x%08x_%08x\n",
486 in_be32(priv->reg + TALITOS_CRCUISR),
487 in_be32(priv->reg + TALITOS_CRCUISR_LO));
488 break;
489 case DESC_HDR_SEL0_KEU:
490 dev_err(dev, "KEUISR 0x%08x_%08x\n",
491 in_be32(priv->reg + TALITOS_KEUISR),
492 in_be32(priv->reg + TALITOS_KEUISR_LO));
493 break;
494 }
495
496 switch (desc->hdr & DESC_HDR_SEL1_MASK) {
497 case DESC_HDR_SEL1_MDEUA:
498 case DESC_HDR_SEL1_MDEUB:
499 dev_err(dev, "MDEUISR 0x%08x_%08x\n",
500 in_be32(priv->reg + TALITOS_MDEUISR),
501 in_be32(priv->reg + TALITOS_MDEUISR_LO));
502 break;
503 case DESC_HDR_SEL1_CRCU:
504 dev_err(dev, "CRCUISR 0x%08x_%08x\n",
505 in_be32(priv->reg + TALITOS_CRCUISR),
506 in_be32(priv->reg + TALITOS_CRCUISR_LO));
507 break;
508 }
509
510 for (i = 0; i < 8; i++)
511 dev_err(dev, "DESCBUF 0x%08x_%08x\n",
512 in_be32(priv->reg + TALITOS_DESCBUF(ch) + 8*i),
513 in_be32(priv->reg + TALITOS_DESCBUF_LO(ch) + 8*i));
514}
515
516/*
517 * recover from error interrupts
518 */
40405f10 519static void talitos_error(unsigned long data, u32 isr, u32 isr_lo)
9c4a7965
KP		 520{
521 struct device *dev = (struct device *)data;
522 struct talitos_private *priv = dev_get_drvdata(dev);
523 unsigned int timeout = TALITOS_TIMEOUT;
524 int ch, error, reset_dev = 0, reset_ch = 0;
40405f10 525 u32 v, v_lo;
9c4a7965
KP		 526
527 for (ch = 0; ch < priv->num_channels; ch++) {
528 /* skip channels without errors */
529 if (!(isr & (1 << (ch * 2 + 1))))
530 continue;
531
532 error = -EINVAL;
533
534 v = in_be32(priv->reg + TALITOS_CCPSR(ch));
535 v_lo = in_be32(priv->reg + TALITOS_CCPSR_LO(ch));
536
537 if (v_lo & TALITOS_CCPSR_LO_DOF) {
538 dev_err(dev, "double fetch fifo overflow error\n");
539 error = -EAGAIN;
540 reset_ch = 1;
541 }
542 if (v_lo & TALITOS_CCPSR_LO_SOF) {
543 /* h/w dropped descriptor */
544 dev_err(dev, "single fetch fifo overflow error\n");
545 error = -EAGAIN;
546 }
547 if (v_lo & TALITOS_CCPSR_LO_MDTE)
548 dev_err(dev, "master data transfer error\n");
549 if (v_lo & TALITOS_CCPSR_LO_SGDLZ)
550 dev_err(dev, "s/g data length zero error\n");
551 if (v_lo & TALITOS_CCPSR_LO_FPZ)
552 dev_err(dev, "fetch pointer zero error\n");
553 if (v_lo & TALITOS_CCPSR_LO_IDH)
554 dev_err(dev, "illegal descriptor header error\n");
555 if (v_lo & TALITOS_CCPSR_LO_IEU)
556 dev_err(dev, "invalid execution unit error\n");
557 if (v_lo & TALITOS_CCPSR_LO_EU)
558 report_eu_error(dev, ch, current_desc(dev, ch));
559 if (v_lo & TALITOS_CCPSR_LO_GB)
560 dev_err(dev, "gather boundary error\n");
561 if (v_lo & TALITOS_CCPSR_LO_GRL)
562 dev_err(dev, "gather return/length error\n");
563 if (v_lo & TALITOS_CCPSR_LO_SB)
564 dev_err(dev, "scatter boundary error\n");
565 if (v_lo & TALITOS_CCPSR_LO_SRL)
566 dev_err(dev, "scatter return/length error\n");
567
568 flush_channel(dev, ch, error, reset_ch);
569
570 if (reset_ch) {
571 reset_channel(dev, ch);
572 } else {
573 setbits32(priv->reg + TALITOS_CCCR(ch),
574 TALITOS_CCCR_CONT);
575 setbits32(priv->reg + TALITOS_CCCR_LO(ch), 0);
576 while ((in_be32(priv->reg + TALITOS_CCCR(ch)) &
577 TALITOS_CCCR_CONT) && --timeout)
578 cpu_relax();
579 if (timeout == 0) {
580 dev_err(dev, "failed to restart channel %d\n",
581 ch);
582 reset_dev = 1;
583 }
584 }
585 }
586 if (reset_dev || isr & ~TALITOS_ISR_CHERR || isr_lo) {
587 dev_err(dev, "done overflow, internal time out, or rngu error: "
588 "ISR 0x%08x_%08x\n", isr, isr_lo);
589
590 /* purge request queues */
591 for (ch = 0; ch < priv->num_channels; ch++)
592 flush_channel(dev, ch, -EIO, 1);
593
594 /* reset and reinitialize the device */
595 init_device(dev);
596 }
597}
598
599static irqreturn_t talitos_interrupt(int irq, void *data)
600{
601 struct device *dev = data;
602 struct talitos_private *priv = dev_get_drvdata(dev);
603 u32 isr, isr_lo;
604
605 isr = in_be32(priv->reg + TALITOS_ISR);
606 isr_lo = in_be32(priv->reg + TALITOS_ISR_LO);
ca38a814
LN		 607 /* Acknowledge interrupt */
608 out_be32(priv->reg + TALITOS_ICR, isr);
609 out_be32(priv->reg + TALITOS_ICR_LO, isr_lo);
9c4a7965 610
ca38a814 611 if (unlikely((isr & ~TALITOS_ISR_CHDONE) || isr_lo))
40405f10 612 talitos_error((unsigned long)data, isr, isr_lo);
ca38a814 613 else
1c2e8811
LN		 614 if (likely(isr & TALITOS_ISR_CHDONE)) {
615 /* mask further done interrupts. */
616 clrbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_DONE);
617 /* done_task will unmask done interrupts at exit */
9c4a7965 618 tasklet_schedule(&priv->done_task);
1c2e8811 619 }
9c4a7965
KP		 620
621 return (isr || isr_lo) ? IRQ_HANDLED : IRQ_NONE;
622}
623
624/*
625 * hwrng
626 */
627static int talitos_rng_data_present(struct hwrng *rng, int wait)
628{
629 struct device *dev = (struct device *)rng->priv;
630 struct talitos_private *priv = dev_get_drvdata(dev);
631 u32 ofl;
632 int i;
633
634 for (i = 0; i < 20; i++) {
635 ofl = in_be32(priv->reg + TALITOS_RNGUSR_LO) &
636 TALITOS_RNGUSR_LO_OFL;
637 if (ofl || !wait)
638 break;
639 udelay(10);
640 }
641
642 return !!ofl;
643}
644
645static int talitos_rng_data_read(struct hwrng *rng, u32 *data)
646{
647 struct device *dev = (struct device *)rng->priv;
648 struct talitos_private *priv = dev_get_drvdata(dev);
649
650 /* rng fifo requires 64-bit accesses */
651 *data = in_be32(priv->reg + TALITOS_RNGU_FIFO);
652 *data = in_be32(priv->reg + TALITOS_RNGU_FIFO_LO);
653
654 return sizeof(u32);
655}
656
657static int talitos_rng_init(struct hwrng *rng)
658{
659 struct device *dev = (struct device *)rng->priv;
660 struct talitos_private *priv = dev_get_drvdata(dev);
661 unsigned int timeout = TALITOS_TIMEOUT;
662
663 setbits32(priv->reg + TALITOS_RNGURCR_LO, TALITOS_RNGURCR_LO_SR);
664 while (!(in_be32(priv->reg + TALITOS_RNGUSR_LO) & TALITOS_RNGUSR_LO_RD)
665 && --timeout)
666 cpu_relax();
667 if (timeout == 0) {
668 dev_err(dev, "failed to reset rng hw\n");
669 return -ENODEV;
670 }
671
672 /* start generating */
673 setbits32(priv->reg + TALITOS_RNGUDSR_LO, 0);
674
675 return 0;
676}
677
678static int talitos_register_rng(struct device *dev)
679{
680 struct talitos_private *priv = dev_get_drvdata(dev);
681
682 priv->rng.name = dev_driver_string(dev),
683 priv->rng.init = talitos_rng_init,
684 priv->rng.data_present = talitos_rng_data_present,
685 priv->rng.data_read = talitos_rng_data_read,
686 priv->rng.priv = (unsigned long)dev;
687
688 return hwrng_register(&priv->rng);
689}
690
691static void talitos_unregister_rng(struct device *dev)
692{
693 struct talitos_private *priv = dev_get_drvdata(dev);
694
695 hwrng_unregister(&priv->rng);
696}
697
698/*
699 * crypto alg
700 */
701#define TALITOS_CRA_PRIORITY 3000
702#define TALITOS_MAX_KEY_SIZE 64
3952f17e 703#define TALITOS_MAX_IV_LENGTH 16 /* max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */
70bcaca7 704
497f2e6b 705#define MD5_BLOCK_SIZE 64
9c4a7965
KP		 706
707struct talitos_ctx {
708 struct device *dev;
709 __be32 desc_hdr_template;
710 u8 key[TALITOS_MAX_KEY_SIZE];
70bcaca7 711 u8 iv[TALITOS_MAX_IV_LENGTH];
9c4a7965
KP		 712 unsigned int keylen;
713 unsigned int enckeylen;
714 unsigned int authkeylen;
715 unsigned int authsize;
716};
717
497f2e6b
LN		 718#define HASH_MAX_BLOCK_SIZE SHA512_BLOCK_SIZE
719#define TALITOS_MDEU_MAX_CONTEXT_SIZE TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512
720
721struct talitos_ahash_req_ctx {
722 u64 count;
723 u8 hw_context[TALITOS_MDEU_MAX_CONTEXT_SIZE];
724 unsigned int hw_context_size;
725 u8 buf[HASH_MAX_BLOCK_SIZE];
726 u8 bufnext[HASH_MAX_BLOCK_SIZE];
727 unsigned int first;
728 unsigned int last;
729 unsigned int to_hash_later;
730 struct scatterlist bufsl[2];
731 struct scatterlist *psrc;
732};
733
56af8cd4
LN		 734static int aead_setauthsize(struct crypto_aead *authenc,
735 unsigned int authsize)
9c4a7965
KP		 736{
737 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
738
739 ctx->authsize = authsize;
740
741 return 0;
742}
743
56af8cd4
LN		 744static int aead_setkey(struct crypto_aead *authenc,
745 const u8 *key, unsigned int keylen)
9c4a7965
KP		 746{
747 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
748 struct rtattr *rta = (void *)key;
749 struct crypto_authenc_key_param *param;
750 unsigned int authkeylen;
751 unsigned int enckeylen;
752
753 if (!RTA_OK(rta, keylen))
754 goto badkey;
755
756 if (rta->rta_type != CRYPTO_AUTHENC_KEYA_PARAM)
757 goto badkey;
758
759 if (RTA_PAYLOAD(rta) < sizeof(*param))
760 goto badkey;
761
762 param = RTA_DATA(rta);
763 enckeylen = be32_to_cpu(param->enckeylen);
764
765 key += RTA_ALIGN(rta->rta_len);
766 keylen -= RTA_ALIGN(rta->rta_len);
767
768 if (keylen < enckeylen)
769 goto badkey;
770
771 authkeylen = keylen - enckeylen;
772
773 if (keylen > TALITOS_MAX_KEY_SIZE)
774 goto badkey;
775
776 memcpy(&ctx->key, key, keylen);
777
778 ctx->keylen = keylen;
779 ctx->enckeylen = enckeylen;
780 ctx->authkeylen = authkeylen;
781
782 return 0;
783
784badkey:
785 crypto_aead_set_flags(authenc, CRYPTO_TFM_RES_BAD_KEY_LEN);
786 return -EINVAL;
787}
788
789/*
56af8cd4 790 * talitos_edesc - s/w-extended descriptor
9c4a7965
KP		 791 * @src_nents: number of segments in input scatterlist
792 * @dst_nents: number of segments in output scatterlist
793 * @dma_len: length of dma mapped link_tbl space
794 * @dma_link_tbl: bus physical address of link_tbl
795 * @desc: h/w descriptor
796 * @link_tbl: input and output h/w link tables (if {src,dst}_nents > 1)
797 *
798 * if decrypting (with authcheck), or either one of src_nents or dst_nents
799 * is greater than 1, an integrity check value is concatenated to the end
800 * of link_tbl data
801 */
56af8cd4 802struct talitos_edesc {
9c4a7965
KP		 803 int src_nents;
804 int dst_nents;
4de9d0b5
LN		 805 int src_is_chained;
806 int dst_is_chained;
9c4a7965
KP		 807 int dma_len;
808 dma_addr_t dma_link_tbl;
809 struct talitos_desc desc;
810 struct talitos_ptr link_tbl[0];
811};
812
4de9d0b5
LN		 813static int talitos_map_sg(struct device *dev, struct scatterlist *sg,
814 unsigned int nents, enum dma_data_direction dir,
815 int chained)
816{
817 if (unlikely(chained))
818 while (sg) {
819 dma_map_sg(dev, sg, 1, dir);
820 sg = scatterwalk_sg_next(sg);
821 }
822 else
823 dma_map_sg(dev, sg, nents, dir);
824 return nents;
825}
826
827static void talitos_unmap_sg_chain(struct device *dev, struct scatterlist *sg,
828 enum dma_data_direction dir)
829{
830 while (sg) {
831 dma_unmap_sg(dev, sg, 1, dir);
832 sg = scatterwalk_sg_next(sg);
833 }
834}
835
836static void talitos_sg_unmap(struct device *dev,
837 struct talitos_edesc *edesc,
838 struct scatterlist *src,
839 struct scatterlist *dst)
840{
841 unsigned int src_nents = edesc->src_nents ? : 1;
842 unsigned int dst_nents = edesc->dst_nents ? : 1;
843
844 if (src != dst) {
845 if (edesc->src_is_chained)
846 talitos_unmap_sg_chain(dev, src, DMA_TO_DEVICE);
847 else
848 dma_unmap_sg(dev, src, src_nents, DMA_TO_DEVICE);
849
497f2e6b
LN		 850 if (dst) {
851 if (edesc->dst_is_chained)
852 talitos_unmap_sg_chain(dev, dst,
853 DMA_FROM_DEVICE);
854 else
855 dma_unmap_sg(dev, dst, dst_nents,
856 DMA_FROM_DEVICE);
857 }
4de9d0b5
LN		 858 } else
859 if (edesc->src_is_chained)
860 talitos_unmap_sg_chain(dev, src, DMA_BIDIRECTIONAL);
861 else
862 dma_unmap_sg(dev, src, src_nents, DMA_BIDIRECTIONAL);
863}
864
9c4a7965 865static void ipsec_esp_unmap(struct device *dev,
56af8cd4 866 struct talitos_edesc *edesc,
9c4a7965
KP		 867 struct aead_request *areq)
868{
869 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[6], DMA_FROM_DEVICE);
870 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[3], DMA_TO_DEVICE);
871 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
872 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[0], DMA_TO_DEVICE);
873
874 dma_unmap_sg(dev, areq->assoc, 1, DMA_TO_DEVICE);
875
4de9d0b5 876 talitos_sg_unmap(dev, edesc, areq->src, areq->dst);
9c4a7965
KP		 877
878 if (edesc->dma_len)
879 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
880 DMA_BIDIRECTIONAL);
881}
882
883/*
884 * ipsec_esp descriptor callbacks
885 */
886static void ipsec_esp_encrypt_done(struct device *dev,
887 struct talitos_desc *desc, void *context,
888 int err)
889{
890 struct aead_request *areq = context;
9c4a7965
KP		 891 struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
892 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
19bbbc63 893 struct talitos_edesc *edesc;
9c4a7965
KP		 894 struct scatterlist *sg;
895 void *icvdata;
896
19bbbc63
KP		 897 edesc = container_of(desc, struct talitos_edesc, desc);
898
9c4a7965
KP		 899 ipsec_esp_unmap(dev, edesc, areq);
900
901 /* copy the generated ICV to dst */
902 if (edesc->dma_len) {
903 icvdata = &edesc->link_tbl[edesc->src_nents +
f3c85bc1 904 edesc->dst_nents + 2];
9c4a7965
KP		 905 sg = sg_last(areq->dst, edesc->dst_nents);
906 memcpy((char *)sg_virt(sg) + sg->length - ctx->authsize,
907 icvdata, ctx->authsize);
908 }
909
910 kfree(edesc);
911
912 aead_request_complete(areq, err);
913}
914
fe5720e2 915static void ipsec_esp_decrypt_swauth_done(struct device *dev,
e938e465
KP		 916 struct talitos_desc *desc,
917 void *context, int err)
9c4a7965
KP		 918{
919 struct aead_request *req = context;
9c4a7965
KP		 920 struct crypto_aead *authenc = crypto_aead_reqtfm(req);
921 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
19bbbc63 922 struct talitos_edesc *edesc;
9c4a7965
KP		 923 struct scatterlist *sg;
924 void *icvdata;
925
19bbbc63
KP		 926 edesc = container_of(desc, struct talitos_edesc, desc);
927
9c4a7965
KP		 928 ipsec_esp_unmap(dev, edesc, req);
929
930 if (!err) {
931 /* auth check */
932 if (edesc->dma_len)
933 icvdata = &edesc->link_tbl[edesc->src_nents +
f3c85bc1 934 edesc->dst_nents + 2];
9c4a7965
KP		 935 else
936 icvdata = &edesc->link_tbl[0];
937
938 sg = sg_last(req->dst, edesc->dst_nents ? : 1);
939 err = memcmp(icvdata, (char *)sg_virt(sg) + sg->length -
940 ctx->authsize, ctx->authsize) ? -EBADMSG : 0;
941 }
942
943 kfree(edesc);
944
945 aead_request_complete(req, err);
946}
947
fe5720e2 948static void ipsec_esp_decrypt_hwauth_done(struct device *dev,
e938e465
KP		 949 struct talitos_desc *desc,
950 void *context, int err)
fe5720e2
KP		 951{
952 struct aead_request *req = context;
19bbbc63
KP		 953 struct talitos_edesc *edesc;
954
955 edesc = container_of(desc, struct talitos_edesc, desc);
fe5720e2
KP		 956
957 ipsec_esp_unmap(dev, edesc, req);
958
959 /* check ICV auth status */
e938e465
KP		 960 if (!err && ((desc->hdr_lo & DESC_HDR_LO_ICCR1_MASK) !=
961 DESC_HDR_LO_ICCR1_PASS))
962 err = -EBADMSG;
fe5720e2
KP		 963
964 kfree(edesc);
965
966 aead_request_complete(req, err);
967}
968
9c4a7965
KP		 969/*
970 * convert scatterlist to SEC h/w link table format
971 * stop at cryptlen bytes
972 */
70bcaca7 973static int sg_to_link_tbl(struct scatterlist *sg, int sg_count,
9c4a7965
KP		 974 int cryptlen, struct talitos_ptr *link_tbl_ptr)
975{
70bcaca7
LN		 976 int n_sg = sg_count;
977
978 while (n_sg--) {
81eb024c 979 to_talitos_ptr(link_tbl_ptr, sg_dma_address(sg));
9c4a7965
KP		 980 link_tbl_ptr->len = cpu_to_be16(sg_dma_len(sg));
981 link_tbl_ptr->j_extent = 0;
982 link_tbl_ptr++;
983 cryptlen -= sg_dma_len(sg);
4de9d0b5 984 sg = scatterwalk_sg_next(sg);
9c4a7965
KP		 985 }
986
70bcaca7 987 /* adjust (decrease) last one (or two) entry's len to cryptlen */
9c4a7965 988 link_tbl_ptr--;
c0e741d4 989 while (be16_to_cpu(link_tbl_ptr->len) <= (-cryptlen)) {
70bcaca7
LN		 990 /* Empty this entry, and move to previous one */
991 cryptlen += be16_to_cpu(link_tbl_ptr->len);
992 link_tbl_ptr->len = 0;
993 sg_count--;
994 link_tbl_ptr--;
995 }
9c4a7965
KP		 996 link_tbl_ptr->len = cpu_to_be16(be16_to_cpu(link_tbl_ptr->len)
997 + cryptlen);
998
999 /* tag end of link table */
1000 link_tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
70bcaca7
LN		 1001
1002 return sg_count;
9c4a7965
KP		 1003}
1004
1005/*
1006 * fill in and submit ipsec_esp descriptor
1007 */
56af8cd4 1008static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
9c4a7965
KP		 1009 u8 *giv, u64 seq,
1010 void (*callback) (struct device *dev,
1011 struct talitos_desc *desc,
1012 void *context, int error))
1013{
1014 struct crypto_aead *aead = crypto_aead_reqtfm(areq);
1015 struct talitos_ctx *ctx = crypto_aead_ctx(aead);
1016 struct device *dev = ctx->dev;
1017 struct talitos_desc *desc = &edesc->desc;
1018 unsigned int cryptlen = areq->cryptlen;
1019 unsigned int authsize = ctx->authsize;
e41256f1 1020 unsigned int ivsize = crypto_aead_ivsize(aead);
fa86a267 1021 int sg_count, ret;
fe5720e2 1022 int sg_link_tbl_len;
9c4a7965
KP		 1023
1024 /* hmac key */
1025 map_single_talitos_ptr(dev, &desc->ptr[0], ctx->authkeylen, &ctx->key,
1026 0, DMA_TO_DEVICE);
1027 /* hmac data */
e41256f1
KP		 1028 map_single_talitos_ptr(dev, &desc->ptr[1], areq->assoclen + ivsize,
1029 sg_virt(areq->assoc), 0, DMA_TO_DEVICE);
9c4a7965 1030 /* cipher iv */
9c4a7965
KP		 1031 map_single_talitos_ptr(dev, &desc->ptr[2], ivsize, giv ?: areq->iv, 0,
1032 DMA_TO_DEVICE);
1033
1034 /* cipher key */
1035 map_single_talitos_ptr(dev, &desc->ptr[3], ctx->enckeylen,
1036 (char *)&ctx->key + ctx->authkeylen, 0,
1037 DMA_TO_DEVICE);
1038
1039 /*
1040 * cipher in
1041 * map and adjust cipher len to aead request cryptlen.
1042 * extent is bytes of HMAC postpended to ciphertext,
1043 * typically 12 for ipsec
1044 */
1045 desc->ptr[4].len = cpu_to_be16(cryptlen);
1046 desc->ptr[4].j_extent = authsize;
1047
e938e465
KP		 1048 sg_count = talitos_map_sg(dev, areq->src, edesc->src_nents ? : 1,
1049 (areq->src == areq->dst) ? DMA_BIDIRECTIONAL
1050 : DMA_TO_DEVICE,
4de9d0b5 1051 edesc->src_is_chained);
9c4a7965
KP		 1052
1053 if (sg_count == 1) {
81eb024c 1054 to_talitos_ptr(&desc->ptr[4], sg_dma_address(areq->src));
9c4a7965 1055 } else {
fe5720e2
KP		 1056 sg_link_tbl_len = cryptlen;
1057
962a9c99 1058 if (edesc->desc.hdr & DESC_HDR_MODE1_MDEU_CICV)
fe5720e2 1059 sg_link_tbl_len = cryptlen + authsize;
e938e465 1060
fe5720e2 1061 sg_count = sg_to_link_tbl(areq->src, sg_count, sg_link_tbl_len,
70bcaca7
LN		 1062 &edesc->link_tbl[0]);
1063 if (sg_count > 1) {
1064 desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
81eb024c 1065 to_talitos_ptr(&desc->ptr[4], edesc->dma_link_tbl);
e938e465
KP		 1066 dma_sync_single_for_device(dev, edesc->dma_link_tbl,
1067 edesc->dma_len,
1068 DMA_BIDIRECTIONAL);
70bcaca7
LN		 1069 } else {
1070 /* Only one segment now, so no link tbl needed */
81eb024c
KP		 1071 to_talitos_ptr(&desc->ptr[4],
1072 sg_dma_address(areq->src));
70bcaca7 1073 }
9c4a7965
KP		 1074 }
1075
1076 /* cipher out */
1077 desc->ptr[5].len = cpu_to_be16(cryptlen);
1078 desc->ptr[5].j_extent = authsize;
1079
e938e465 1080 if (areq->src != areq->dst)
4de9d0b5
LN		 1081 sg_count = talitos_map_sg(dev, areq->dst,
1082 edesc->dst_nents ? : 1,
1083 DMA_FROM_DEVICE,
1084 edesc->dst_is_chained);
9c4a7965
KP		 1085
1086 if (sg_count == 1) {
81eb024c 1087 to_talitos_ptr(&desc->ptr[5], sg_dma_address(areq->dst));
9c4a7965
KP		 1088 } else {
1089 struct talitos_ptr *link_tbl_ptr =
f3c85bc1 1090 &edesc->link_tbl[edesc->src_nents + 1];
9c4a7965 1091
81eb024c
KP		 1092 to_talitos_ptr(&desc->ptr[5], edesc->dma_link_tbl +
1093 (edesc->src_nents + 1) *
1094 sizeof(struct talitos_ptr));
fe5720e2
KP		 1095 sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
1096 link_tbl_ptr);
1097
f3c85bc1 1098 /* Add an entry to the link table for ICV data */
9c4a7965 1099 link_tbl_ptr += sg_count - 1;
9c4a7965 1100 link_tbl_ptr->j_extent = 0;
f3c85bc1 1101 sg_count++;
9c4a7965
KP		 1102 link_tbl_ptr++;
1103 link_tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
1104 link_tbl_ptr->len = cpu_to_be16(authsize);
1105
1106 /* icv data follows link tables */
81eb024c
KP		 1107 to_talitos_ptr(link_tbl_ptr, edesc->dma_link_tbl +
1108 (edesc->src_nents + edesc->dst_nents + 2) *
1109 sizeof(struct talitos_ptr));
9c4a7965
KP		 1110 desc->ptr[5].j_extent |= DESC_PTR_LNKTBL_JUMP;
1111 dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
1112 edesc->dma_len, DMA_BIDIRECTIONAL);
1113 }
1114
1115 /* iv out */
1116 map_single_talitos_ptr(dev, &desc->ptr[6], ivsize, ctx->iv, 0,
1117 DMA_FROM_DEVICE);
1118
fa86a267
KP		 1119 ret = talitos_submit(dev, desc, callback, areq);
1120 if (ret != -EINPROGRESS) {
1121 ipsec_esp_unmap(dev, edesc, areq);
1122 kfree(edesc);
1123 }
1124 return ret;
9c4a7965
KP		 1125}
1126
9c4a7965
KP		 1127/*
1128 * derive number of elements in scatterlist
1129 */
4de9d0b5 1130static int sg_count(struct scatterlist *sg_list, int nbytes, int *chained)
9c4a7965
KP		 1131{
1132 struct scatterlist *sg = sg_list;
1133 int sg_nents = 0;
1134
4de9d0b5
LN		 1135 *chained = 0;
1136 while (nbytes > 0) {
9c4a7965
KP		 1137 sg_nents++;
1138 nbytes -= sg->length;
4de9d0b5
LN		 1139 if (!sg_is_last(sg) && (sg + 1)->length == 0)
1140 *chained = 1;
1141 sg = scatterwalk_sg_next(sg);
9c4a7965
KP		 1142 }
1143
1144 return sg_nents;
1145}
1146
497f2e6b
LN		 1147/**
1148 * sg_copy_end_to_buffer - Copy end data from SG list to a linear buffer
1149 * @sgl: The SG list
1150 * @nents: Number of SG entries
1151 * @buf: Where to copy to
1152 * @buflen: The number of bytes to copy
1153 * @skip: The number of bytes to skip before copying.
1154 * Note: skip + buflen should equal SG total size.
1155 *
1156 * Returns the number of copied bytes.
1157 *
1158 **/
1159static size_t sg_copy_end_to_buffer(struct scatterlist *sgl, unsigned int nents,
1160 void *buf, size_t buflen, unsigned int skip)
1161{
1162 unsigned int offset = 0;
1163 unsigned int boffset = 0;
1164 struct sg_mapping_iter miter;
1165 unsigned long flags;
1166 unsigned int sg_flags = SG_MITER_ATOMIC;
1167 size_t total_buffer = buflen + skip;
1168
1169 sg_flags |= SG_MITER_FROM_SG;
1170
1171 sg_miter_start(&miter, sgl, nents, sg_flags);
1172
1173 local_irq_save(flags);
1174
1175 while (sg_miter_next(&miter) && offset < total_buffer) {
1176 unsigned int len;
1177 unsigned int ignore;
1178
1179 if ((offset + miter.length) > skip) {
1180 if (offset < skip) {
1181 /* Copy part of this segment */
1182 ignore = skip - offset;
1183 len = miter.length - ignore;
1184 memcpy(buf + boffset, miter.addr + ignore, len);
1185 } else {
1186 /* Copy all of this segment */
1187 len = miter.length;
1188 memcpy(buf + boffset, miter.addr, len);
1189 }
1190 boffset += len;
1191 }
1192 offset += miter.length;
1193 }
1194
1195 sg_miter_stop(&miter);
1196
1197 local_irq_restore(flags);
1198 return boffset;
1199}
1200
9c4a7965 1201/*
56af8cd4 1202 * allocate and map the extended descriptor
9c4a7965 1203 */
4de9d0b5
LN		 1204static struct talitos_edesc *talitos_edesc_alloc(struct device *dev,
1205 struct scatterlist *src,
1206 struct scatterlist *dst,
497f2e6b 1207 int hash_result,
4de9d0b5
LN		 1208 unsigned int cryptlen,
1209 unsigned int authsize,
1210 int icv_stashing,
1211 u32 cryptoflags)
9c4a7965 1212{
56af8cd4 1213 struct talitos_edesc *edesc;
9c4a7965 1214 int src_nents, dst_nents, alloc_len, dma_len;
4de9d0b5
LN		 1215 int src_chained, dst_chained = 0;
1216 gfp_t flags = cryptoflags & CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL :
586725f8 1217 GFP_ATOMIC;
9c4a7965 1218
4de9d0b5
LN		 1219 if (cryptlen + authsize > TALITOS_MAX_DATA_LEN) {
1220 dev_err(dev, "length exceeds h/w max limit\n");
9c4a7965
KP		 1221 return ERR_PTR(-EINVAL);
1222 }
1223
4de9d0b5 1224 src_nents = sg_count(src, cryptlen + authsize, &src_chained);
9c4a7965
KP		 1225 src_nents = (src_nents == 1) ? 0 : src_nents;
1226
497f2e6b
LN		 1227 if (hash_result) {
1228 dst_nents = 0;
9c4a7965 1229 } else {
497f2e6b
LN		 1230 if (dst == src) {
1231 dst_nents = src_nents;
1232 } else {
1233 dst_nents = sg_count(dst, cryptlen + authsize,
1234 &dst_chained);
1235 dst_nents = (dst_nents == 1) ? 0 : dst_nents;
1236 }
9c4a7965
KP		 1237 }
1238
1239 /*
1240 * allocate space for base edesc plus the link tables,
f3c85bc1 1241 * allowing for two separate entries for ICV and generated ICV (+ 2),
9c4a7965
KP		 1242 * and the ICV data itself
1243 */
56af8cd4 1244 alloc_len = sizeof(struct talitos_edesc);
9c4a7965 1245 if (src_nents || dst_nents) {
f3c85bc1 1246 dma_len = (src_nents + dst_nents + 2) *
4de9d0b5 1247 sizeof(struct talitos_ptr) + authsize;
9c4a7965
KP		 1248 alloc_len += dma_len;
1249 } else {
1250 dma_len = 0;
4de9d0b5 1251 alloc_len += icv_stashing ? authsize : 0;
9c4a7965
KP		 1252 }
1253
586725f8 1254 edesc = kmalloc(alloc_len, GFP_DMA | flags);
9c4a7965 1255 if (!edesc) {
4de9d0b5 1256 dev_err(dev, "could not allocate edescriptor\n");
9c4a7965
KP		 1257 return ERR_PTR(-ENOMEM);
1258 }
1259
1260 edesc->src_nents = src_nents;
1261 edesc->dst_nents = dst_nents;
4de9d0b5
LN		 1262 edesc->src_is_chained = src_chained;
1263 edesc->dst_is_chained = dst_chained;
9c4a7965 1264 edesc->dma_len = dma_len;
497f2e6b
LN		 1265 if (dma_len)
1266 edesc->dma_link_tbl = dma_map_single(dev, &edesc->link_tbl[0],
1267 edesc->dma_len,
1268 DMA_BIDIRECTIONAL);
9c4a7965
KP		 1269
1270 return edesc;
1271}
1272
4de9d0b5
LN		 1273static struct talitos_edesc *aead_edesc_alloc(struct aead_request *areq,
1274 int icv_stashing)
1275{
1276 struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
1277 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1278
497f2e6b 1279 return talitos_edesc_alloc(ctx->dev, areq->src, areq->dst, 0,
4de9d0b5
LN		 1280 areq->cryptlen, ctx->authsize, icv_stashing,
1281 areq->base.flags);
1282}
1283
56af8cd4 1284static int aead_encrypt(struct aead_request *req)
9c4a7965
KP		 1285{
1286 struct crypto_aead *authenc = crypto_aead_reqtfm(req);
1287 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
56af8cd4 1288 struct talitos_edesc *edesc;
9c4a7965
KP		 1289
1290 /* allocate extended descriptor */
4de9d0b5 1291 edesc = aead_edesc_alloc(req, 0);
9c4a7965
KP		 1292 if (IS_ERR(edesc))
1293 return PTR_ERR(edesc);
1294
1295 /* set encrypt */
70bcaca7 1296 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
9c4a7965
KP		 1297
1298 return ipsec_esp(edesc, req, NULL, 0, ipsec_esp_encrypt_done);
1299}
1300
56af8cd4 1301static int aead_decrypt(struct aead_request *req)
9c4a7965
KP		 1302{
1303 struct crypto_aead *authenc = crypto_aead_reqtfm(req);
1304 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1305 unsigned int authsize = ctx->authsize;
fe5720e2 1306 struct talitos_private *priv = dev_get_drvdata(ctx->dev);
56af8cd4 1307 struct talitos_edesc *edesc;
9c4a7965
KP		 1308 struct scatterlist *sg;
1309 void *icvdata;
1310
1311 req->cryptlen -= authsize;
1312
1313 /* allocate extended descriptor */
4de9d0b5 1314 edesc = aead_edesc_alloc(req, 1);
9c4a7965
KP		 1315 if (IS_ERR(edesc))
1316 return PTR_ERR(edesc);
1317
fe5720e2 1318 if ((priv->features & TALITOS_FTR_HW_AUTH_CHECK) &&
e938e465
KP		 1319 ((!edesc->src_nents && !edesc->dst_nents) ||
1320 priv->features & TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT)) {
9c4a7965 1321
fe5720e2 1322 /* decrypt and check the ICV */
e938e465
KP		 1323 edesc->desc.hdr = ctx->desc_hdr_template |
1324 DESC_HDR_DIR_INBOUND |
fe5720e2 1325 DESC_HDR_MODE1_MDEU_CICV;
9c4a7965 1326
fe5720e2
KP		 1327 /* reset integrity check result bits */
1328 edesc->desc.hdr_lo = 0;
9c4a7965 1329
e938e465
KP		 1330 return ipsec_esp(edesc, req, NULL, 0,
1331 ipsec_esp_decrypt_hwauth_done);
fe5720e2 1332
e938e465 1333 }
fe5720e2 1334
e938e465
KP		 1335 /* Have to check the ICV with software */
1336 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
fe5720e2 1337
e938e465
KP		 1338 /* stash incoming ICV for later cmp with ICV generated by the h/w */
1339 if (edesc->dma_len)
1340 icvdata = &edesc->link_tbl[edesc->src_nents +
1341 edesc->dst_nents + 2];
1342 else
1343 icvdata = &edesc->link_tbl[0];
fe5720e2 1344
e938e465 1345 sg = sg_last(req->src, edesc->src_nents ? : 1);
fe5720e2 1346
e938e465
KP		 1347 memcpy(icvdata, (char *)sg_virt(sg) + sg->length - ctx->authsize,
1348 ctx->authsize);
fe5720e2 1349
e938e465 1350 return ipsec_esp(edesc, req, NULL, 0, ipsec_esp_decrypt_swauth_done);
9c4a7965
KP		 1351}
1352
56af8cd4 1353static int aead_givencrypt(struct aead_givcrypt_request *req)
9c4a7965
KP		 1354{
1355 struct aead_request *areq = &req->areq;
1356 struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
1357 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
56af8cd4 1358 struct talitos_edesc *edesc;
9c4a7965
KP		 1359
1360 /* allocate extended descriptor */
4de9d0b5 1361 edesc = aead_edesc_alloc(areq, 0);
9c4a7965
KP		 1362 if (IS_ERR(edesc))
1363 return PTR_ERR(edesc);
1364
1365 /* set encrypt */
70bcaca7 1366 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
9c4a7965
KP		 1367
1368 memcpy(req->giv, ctx->iv, crypto_aead_ivsize(authenc));
ba95487d
KP		 1369 /* avoid consecutive packets going out with same IV */
1370 *(__be64 *)req->giv ^= cpu_to_be64(req->seq);
9c4a7965
KP		 1371
1372 return ipsec_esp(edesc, areq, req->giv, req->seq,
1373 ipsec_esp_encrypt_done);
1374}
1375
4de9d0b5
LN		 1376static int ablkcipher_setkey(struct crypto_ablkcipher *cipher,
1377 const u8 *key, unsigned int keylen)
1378{
1379 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1380 struct ablkcipher_alg *alg = crypto_ablkcipher_alg(cipher);
1381
1382 if (keylen > TALITOS_MAX_KEY_SIZE)
1383 goto badkey;
1384
1385 if (keylen < alg->min_keysize || keylen > alg->max_keysize)
1386 goto badkey;
1387
1388 memcpy(&ctx->key, key, keylen);
1389 ctx->keylen = keylen;
1390
1391 return 0;
1392
1393badkey:
1394 crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
1395 return -EINVAL;
1396}
1397
1398static void common_nonsnoop_unmap(struct device *dev,
1399 struct talitos_edesc *edesc,
1400 struct ablkcipher_request *areq)
1401{
1402 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
1403 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
1404 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1], DMA_TO_DEVICE);
1405
1406 talitos_sg_unmap(dev, edesc, areq->src, areq->dst);
1407
1408 if (edesc->dma_len)
1409 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
1410 DMA_BIDIRECTIONAL);
1411}
1412
1413static void ablkcipher_done(struct device *dev,
1414 struct talitos_desc *desc, void *context,
1415 int err)
1416{
1417 struct ablkcipher_request *areq = context;
19bbbc63
KP		 1418 struct talitos_edesc *edesc;
1419
1420 edesc = container_of(desc, struct talitos_edesc, desc);
4de9d0b5
LN		 1421
1422 common_nonsnoop_unmap(dev, edesc, areq);
1423
1424 kfree(edesc);
1425
1426 areq->base.complete(&areq->base, err);
1427}
1428
1429static int common_nonsnoop(struct talitos_edesc *edesc,
1430 struct ablkcipher_request *areq,
1431 u8 *giv,
1432 void (*callback) (struct device *dev,
1433 struct talitos_desc *desc,
1434 void *context, int error))
1435{
1436 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1437 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1438 struct device *dev = ctx->dev;
1439 struct talitos_desc *desc = &edesc->desc;
1440 unsigned int cryptlen = areq->nbytes;
1441 unsigned int ivsize;
1442 int sg_count, ret;
1443
1444 /* first DWORD empty */
1445 desc->ptr[0].len = 0;
81eb024c 1446 to_talitos_ptr(&desc->ptr[0], 0);
4de9d0b5
LN		 1447 desc->ptr[0].j_extent = 0;
1448
1449 /* cipher iv */
1450 ivsize = crypto_ablkcipher_ivsize(cipher);
1451 map_single_talitos_ptr(dev, &desc->ptr[1], ivsize, giv ?: areq->info, 0,
1452 DMA_TO_DEVICE);
1453
1454 /* cipher key */
1455 map_single_talitos_ptr(dev, &desc->ptr[2], ctx->keylen,
1456 (char *)&ctx->key, 0, DMA_TO_DEVICE);
1457
1458 /*
1459 * cipher in
1460 */
1461 desc->ptr[3].len = cpu_to_be16(cryptlen);
1462 desc->ptr[3].j_extent = 0;
1463
1464 sg_count = talitos_map_sg(dev, areq->src, edesc->src_nents ? : 1,
1465 (areq->src == areq->dst) ? DMA_BIDIRECTIONAL
1466 : DMA_TO_DEVICE,
1467 edesc->src_is_chained);
1468
1469 if (sg_count == 1) {
81eb024c 1470 to_talitos_ptr(&desc->ptr[3], sg_dma_address(areq->src));
4de9d0b5
LN		 1471 } else {
1472 sg_count = sg_to_link_tbl(areq->src, sg_count, cryptlen,
1473 &edesc->link_tbl[0]);
1474 if (sg_count > 1) {
81eb024c 1475 to_talitos_ptr(&desc->ptr[3], edesc->dma_link_tbl);
4de9d0b5 1476 desc->ptr[3].j_extent |= DESC_PTR_LNKTBL_JUMP;
e938e465
KP		 1477 dma_sync_single_for_device(dev, edesc->dma_link_tbl,
1478 edesc->dma_len,
1479 DMA_BIDIRECTIONAL);
4de9d0b5
LN		 1480 } else {
1481 /* Only one segment now, so no link tbl needed */
81eb024c
KP		 1482 to_talitos_ptr(&desc->ptr[3],
1483 sg_dma_address(areq->src));
4de9d0b5
LN		 1484 }
1485 }
1486
1487 /* cipher out */
1488 desc->ptr[4].len = cpu_to_be16(cryptlen);
1489 desc->ptr[4].j_extent = 0;
1490
1491 if (areq->src != areq->dst)
1492 sg_count = talitos_map_sg(dev, areq->dst,
1493 edesc->dst_nents ? : 1,
1494 DMA_FROM_DEVICE,
1495 edesc->dst_is_chained);
1496
1497 if (sg_count == 1) {
81eb024c 1498 to_talitos_ptr(&desc->ptr[4], sg_dma_address(areq->dst));
4de9d0b5
LN		 1499 } else {
1500 struct talitos_ptr *link_tbl_ptr =
1501 &edesc->link_tbl[edesc->src_nents + 1];
1502
81eb024c
KP		 1503 to_talitos_ptr(&desc->ptr[4], edesc->dma_link_tbl +
1504 (edesc->src_nents + 1) *
1505 sizeof(struct talitos_ptr));
4de9d0b5 1506 desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
4de9d0b5
LN		 1507 sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
1508 link_tbl_ptr);
1509 dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
1510 edesc->dma_len, DMA_BIDIRECTIONAL);
1511 }
1512
1513 /* iv out */
1514 map_single_talitos_ptr(dev, &desc->ptr[5], ivsize, ctx->iv, 0,
1515 DMA_FROM_DEVICE);
1516
1517 /* last DWORD empty */
1518 desc->ptr[6].len = 0;
81eb024c 1519 to_talitos_ptr(&desc->ptr[6], 0);
4de9d0b5
LN		 1520 desc->ptr[6].j_extent = 0;
1521
1522 ret = talitos_submit(dev, desc, callback, areq);
1523 if (ret != -EINPROGRESS) {
1524 common_nonsnoop_unmap(dev, edesc, areq);
1525 kfree(edesc);
1526 }
1527 return ret;
1528}
1529
e938e465
KP		 1530static struct talitos_edesc *ablkcipher_edesc_alloc(struct ablkcipher_request *
1531 areq)
4de9d0b5
LN		 1532{
1533 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1534 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1535
497f2e6b
LN		 1536 return talitos_edesc_alloc(ctx->dev, areq->src, areq->dst, 0,
1537 areq->nbytes, 0, 0, areq->base.flags);
4de9d0b5
LN		 1538}
1539
1540static int ablkcipher_encrypt(struct ablkcipher_request *areq)
1541{
1542 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1543 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1544 struct talitos_edesc *edesc;
1545
1546 /* allocate extended descriptor */
1547 edesc = ablkcipher_edesc_alloc(areq);
1548 if (IS_ERR(edesc))
1549 return PTR_ERR(edesc);
1550
1551 /* set encrypt */
1552 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
1553
1554 return common_nonsnoop(edesc, areq, NULL, ablkcipher_done);
1555}
1556
1557static int ablkcipher_decrypt(struct ablkcipher_request *areq)
1558{
1559 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1560 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1561 struct talitos_edesc *edesc;
1562
1563 /* allocate extended descriptor */
1564 edesc = ablkcipher_edesc_alloc(areq);
1565 if (IS_ERR(edesc))
1566 return PTR_ERR(edesc);
1567
1568 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
1569
1570 return common_nonsnoop(edesc, areq, NULL, ablkcipher_done);
1571}
1572
497f2e6b
LN		 1573static void common_nonsnoop_hash_unmap(struct device *dev,
1574 struct talitos_edesc *edesc,
1575 struct ahash_request *areq)
1576{
1577 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1578
1579 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
1580
1581 /* When using hashctx-in, must unmap it. */
1582 if (edesc->desc.ptr[1].len)
1583 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1],
1584 DMA_TO_DEVICE);
1585
1586 if (edesc->desc.ptr[2].len)
1587 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2],
1588 DMA_TO_DEVICE);
1589
1590 talitos_sg_unmap(dev, edesc, req_ctx->psrc, NULL);
1591
1592 if (edesc->dma_len)
1593 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
1594 DMA_BIDIRECTIONAL);
1595
1596}
1597
1598static void ahash_done(struct device *dev,
1599 struct talitos_desc *desc, void *context,
1600 int err)
1601{
1602 struct ahash_request *areq = context;
1603 struct talitos_edesc *edesc =
1604 container_of(desc, struct talitos_edesc, desc);
1605 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1606
1607 if (!req_ctx->last && req_ctx->to_hash_later) {
1608 /* Position any partial block for next update/final/finup */
1609 memcpy(req_ctx->buf, req_ctx->bufnext, req_ctx->to_hash_later);
1610 }
1611 common_nonsnoop_hash_unmap(dev, edesc, areq);
1612
1613 kfree(edesc);
1614
1615 areq->base.complete(&areq->base, err);
1616}
1617
1618static int common_nonsnoop_hash(struct talitos_edesc *edesc,
1619 struct ahash_request *areq, unsigned int length,
1620 void (*callback) (struct device *dev,
1621 struct talitos_desc *desc,
1622 void *context, int error))
1623{
1624 struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1625 struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1626 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1627 struct device *dev = ctx->dev;
1628 struct talitos_desc *desc = &edesc->desc;
1629 int sg_count, ret;
1630
1631 /* first DWORD empty */
1632 desc->ptr[0] = zero_entry;
1633
1634 /* hash context in (if not first) */
1635 if (!req_ctx->first) {
1636 map_single_talitos_ptr(dev, &desc->ptr[1],
1637 req_ctx->hw_context_size,
1638 (char *)req_ctx->hw_context, 0,
1639 DMA_TO_DEVICE);
1640 } else {
1641 desc->ptr[1] = zero_entry;
1642 /* Indicate next op is not the first. */
1643 req_ctx->first = 0;
1644 }
1645
1646 /* HMAC key */
1647 if (ctx->keylen)
1648 map_single_talitos_ptr(dev, &desc->ptr[2], ctx->keylen,
1649 (char *)&ctx->key, 0, DMA_TO_DEVICE);
1650 else
1651 desc->ptr[2] = zero_entry;
1652
1653 /*
1654 * data in
1655 */
1656 desc->ptr[3].len = cpu_to_be16(length);
1657 desc->ptr[3].j_extent = 0;
1658
1659 sg_count = talitos_map_sg(dev, req_ctx->psrc,
1660 edesc->src_nents ? : 1,
1661 DMA_TO_DEVICE,
1662 edesc->src_is_chained);
1663
1664 if (sg_count == 1) {
1665 to_talitos_ptr(&desc->ptr[3], sg_dma_address(req_ctx->psrc));
1666 } else {
1667 sg_count = sg_to_link_tbl(req_ctx->psrc, sg_count, length,
1668 &edesc->link_tbl[0]);
1669 if (sg_count > 1) {
1670 desc->ptr[3].j_extent |= DESC_PTR_LNKTBL_JUMP;
1671 to_talitos_ptr(&desc->ptr[3], edesc->dma_link_tbl);
1672 dma_sync_single_for_device(ctx->dev,
1673 edesc->dma_link_tbl,
1674 edesc->dma_len,
1675 DMA_BIDIRECTIONAL);
1676 } else {
1677 /* Only one segment now, so no link tbl needed */
1678 to_talitos_ptr(&desc->ptr[3],
1679 sg_dma_address(req_ctx->psrc));
1680 }
1681 }
1682
1683 /* fifth DWORD empty */
1684 desc->ptr[4] = zero_entry;
1685
1686 /* hash/HMAC out -or- hash context out */
1687 if (req_ctx->last)
1688 map_single_talitos_ptr(dev, &desc->ptr[5],
1689 crypto_ahash_digestsize(tfm),
1690 areq->result, 0, DMA_FROM_DEVICE);
1691 else
1692 map_single_talitos_ptr(dev, &desc->ptr[5],
1693 req_ctx->hw_context_size,
1694 req_ctx->hw_context, 0, DMA_FROM_DEVICE);
1695
1696 /* last DWORD empty */
1697 desc->ptr[6] = zero_entry;
1698
1699 ret = talitos_submit(dev, desc, callback, areq);
1700 if (ret != -EINPROGRESS) {
1701 common_nonsnoop_hash_unmap(dev, edesc, areq);
1702 kfree(edesc);
1703 }
1704 return ret;
1705}
1706
1707static struct talitos_edesc *ahash_edesc_alloc(struct ahash_request *areq,
1708 unsigned int nbytes)
1709{
1710 struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1711 struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1712 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1713
1714 return talitos_edesc_alloc(ctx->dev, req_ctx->psrc, NULL, 1,
1715 nbytes, 0, 0, areq->base.flags);
1716}
1717
1718static int ahash_init(struct ahash_request *areq)
1719{
1720 struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1721 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1722
1723 /* Initialize the context */
1724 req_ctx->count = 0;
1725 req_ctx->first = 1; /* first indicates h/w must init it's context */
1726 req_ctx->hw_context_size =
1727 (crypto_ahash_digestsize(tfm) <= SHA256_DIGEST_SIZE)
1728 ? TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256
1729 : TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512;
1730
1731 return 0;
1732}
1733
1734static int ahash_process_req(struct ahash_request *areq, unsigned int nbytes)
1735{
1736 struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1737 struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1738 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1739 struct talitos_edesc *edesc;
1740 unsigned int blocksize =
1741 crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
1742 unsigned int nbytes_to_hash;
1743 unsigned int to_hash_later;
1744 unsigned int index;
1745 int chained;
1746
1747 index = req_ctx->count & (blocksize - 1);
1748 req_ctx->count += nbytes;
1749
1750 if (!req_ctx->last && (index + nbytes) < blocksize) {
1751 /* Buffer the partial block */
1752 sg_copy_to_buffer(areq->src,
1753 sg_count(areq->src, nbytes, &chained),
1754 req_ctx->buf + index, nbytes);
1755 return 0;
1756 }
1757
1758 if (index) {
1759 /* partial block from previous update; chain it in. */
1760 sg_init_table(req_ctx->bufsl, (nbytes) ? 2 : 1);
1761 sg_set_buf(req_ctx->bufsl, req_ctx->buf, index);
1762 if (nbytes)
1763 scatterwalk_sg_chain(req_ctx->bufsl, 2,
1764 areq->src);
1765 req_ctx->psrc = req_ctx->bufsl;
1766 } else {
1767 req_ctx->psrc = areq->src;
1768 }
1769 nbytes_to_hash = index + nbytes;
1770 if (!req_ctx->last) {
1771 to_hash_later = (nbytes_to_hash & (blocksize - 1));
1772 if (to_hash_later) {
1773 int nents;
1774 /* Must copy to_hash_later bytes from the end
1775 * to bufnext (a partial block) for later.
1776 */
1777 nents = sg_count(areq->src, nbytes, &chained);
1778 sg_copy_end_to_buffer(areq->src, nents,
1779 req_ctx->bufnext,
1780 to_hash_later,
1781 nbytes - to_hash_later);
1782
1783 /* Adjust count for what will be hashed now */
1784 nbytes_to_hash -= to_hash_later;
1785 }
1786 req_ctx->to_hash_later = to_hash_later;
1787 }
1788
1789 /* allocate extended descriptor */
1790 edesc = ahash_edesc_alloc(areq, nbytes_to_hash);
1791 if (IS_ERR(edesc))
1792 return PTR_ERR(edesc);
1793
1794 edesc->desc.hdr = ctx->desc_hdr_template;
1795
1796 /* On last one, request SEC to pad; otherwise continue */
1797 if (req_ctx->last)
1798 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_PAD;
1799 else
1800 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_CONT;
1801
1802 /* On first one, request SEC to INIT hash. */
1803 if (req_ctx->first)
1804 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_INIT;
1805
1806 /* When the tfm context has a keylen, it's an HMAC.
1807 * A first or last (ie. not middle) descriptor must request HMAC.
1808 */
1809 if (ctx->keylen && (req_ctx->first || req_ctx->last))
1810 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_HMAC;
1811
1812 return common_nonsnoop_hash(edesc, areq, nbytes_to_hash,
1813 ahash_done);
1814}
1815
1816static int ahash_update(struct ahash_request *areq)
1817{
1818 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1819
1820 req_ctx->last = 0;
1821
1822 return ahash_process_req(areq, areq->nbytes);
1823}
1824
1825static int ahash_final(struct ahash_request *areq)
1826{
1827 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1828
1829 req_ctx->last = 1;
1830
1831 return ahash_process_req(areq, 0);
1832}
1833
1834static int ahash_finup(struct ahash_request *areq)
1835{
1836 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1837
1838 req_ctx->last = 1;
1839
1840 return ahash_process_req(areq, areq->nbytes);
1841}
1842
1843static int ahash_digest(struct ahash_request *areq)
1844{
1845 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1846
1847 ahash_init(areq);
1848 req_ctx->last = 1;
1849
1850 return ahash_process_req(areq, areq->nbytes);
1851}
1852
9c4a7965 1853struct talitos_alg_template {
d5e4aaef
LN		 1854 u32 type;
1855 union {
1856 struct crypto_alg crypto;
acbf7c62 1857 struct ahash_alg hash;
d5e4aaef 1858 } alg;
9c4a7965
KP		 1859 __be32 desc_hdr_template;
1860};
1861
1862static struct talitos_alg_template driver_algs[] = {
56af8cd4 1863 /* AEAD algorithms. These use a single-pass ipsec_esp descriptor */
d5e4aaef
LN		 1864 { .type = CRYPTO_ALG_TYPE_AEAD,
1865 .alg.crypto = {
56af8cd4
LN		 1866 .cra_name = "authenc(hmac(sha1),cbc(aes))",
1867 .cra_driver_name = "authenc-hmac-sha1-cbc-aes-talitos",
1868 .cra_blocksize = AES_BLOCK_SIZE,
1869 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1870 .cra_type = &crypto_aead_type,
1871 .cra_aead = {
1872 .setkey = aead_setkey,
1873 .setauthsize = aead_setauthsize,
1874 .encrypt = aead_encrypt,
1875 .decrypt = aead_decrypt,
1876 .givencrypt = aead_givencrypt,
1877 .geniv = "<built-in>",
1878 .ivsize = AES_BLOCK_SIZE,
1879 .maxauthsize = SHA1_DIGEST_SIZE,
1880 }
1881 },
9c4a7965
KP		 1882 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1883 DESC_HDR_SEL0_AESU |
1884 DESC_HDR_MODE0_AESU_CBC |
1885 DESC_HDR_SEL1_MDEUA |
1886 DESC_HDR_MODE1_MDEU_INIT |
1887 DESC_HDR_MODE1_MDEU_PAD |
1888 DESC_HDR_MODE1_MDEU_SHA1_HMAC,
70bcaca7 1889 },
d5e4aaef
LN		 1890 { .type = CRYPTO_ALG_TYPE_AEAD,
1891 .alg.crypto = {
56af8cd4
LN		 1892 .cra_name = "authenc(hmac(sha1),cbc(des3_ede))",
1893 .cra_driver_name = "authenc-hmac-sha1-cbc-3des-talitos",
1894 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1895 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1896 .cra_type = &crypto_aead_type,
1897 .cra_aead = {
1898 .setkey = aead_setkey,
1899 .setauthsize = aead_setauthsize,
1900 .encrypt = aead_encrypt,
1901 .decrypt = aead_decrypt,
1902 .givencrypt = aead_givencrypt,
1903 .geniv = "<built-in>",
1904 .ivsize = DES3_EDE_BLOCK_SIZE,
1905 .maxauthsize = SHA1_DIGEST_SIZE,
1906 }
1907 },
70bcaca7
LN		 1908 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1909 DESC_HDR_SEL0_DEU |
1910 DESC_HDR_MODE0_DEU_CBC |
1911 DESC_HDR_MODE0_DEU_3DES |
1912 DESC_HDR_SEL1_MDEUA |
1913 DESC_HDR_MODE1_MDEU_INIT |
1914 DESC_HDR_MODE1_MDEU_PAD |
1915 DESC_HDR_MODE1_MDEU_SHA1_HMAC,
3952f17e 1916 },
d5e4aaef
LN		 1917 { .type = CRYPTO_ALG_TYPE_AEAD,
1918 .alg.crypto = {
56af8cd4
LN		 1919 .cra_name = "authenc(hmac(sha256),cbc(aes))",
1920 .cra_driver_name = "authenc-hmac-sha256-cbc-aes-talitos",
1921 .cra_blocksize = AES_BLOCK_SIZE,
1922 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1923 .cra_type = &crypto_aead_type,
1924 .cra_aead = {
1925 .setkey = aead_setkey,
1926 .setauthsize = aead_setauthsize,
1927 .encrypt = aead_encrypt,
1928 .decrypt = aead_decrypt,
1929 .givencrypt = aead_givencrypt,
1930 .geniv = "<built-in>",
1931 .ivsize = AES_BLOCK_SIZE,
1932 .maxauthsize = SHA256_DIGEST_SIZE,
1933 }
1934 },
3952f17e
LN		 1935 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1936 DESC_HDR_SEL0_AESU |
1937 DESC_HDR_MODE0_AESU_CBC |
1938 DESC_HDR_SEL1_MDEUA |
1939 DESC_HDR_MODE1_MDEU_INIT |
1940 DESC_HDR_MODE1_MDEU_PAD |
1941 DESC_HDR_MODE1_MDEU_SHA256_HMAC,
1942 },
d5e4aaef
LN		 1943 { .type = CRYPTO_ALG_TYPE_AEAD,
1944 .alg.crypto = {
56af8cd4
LN		 1945 .cra_name = "authenc(hmac(sha256),cbc(des3_ede))",
1946 .cra_driver_name = "authenc-hmac-sha256-cbc-3des-talitos",
1947 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1948 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1949 .cra_type = &crypto_aead_type,
1950 .cra_aead = {
1951 .setkey = aead_setkey,
1952 .setauthsize = aead_setauthsize,
1953 .encrypt = aead_encrypt,
1954 .decrypt = aead_decrypt,
1955 .givencrypt = aead_givencrypt,
1956 .geniv = "<built-in>",
1957 .ivsize = DES3_EDE_BLOCK_SIZE,
1958 .maxauthsize = SHA256_DIGEST_SIZE,
1959 }
1960 },
3952f17e
LN		 1961 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1962 DESC_HDR_SEL0_DEU |
1963 DESC_HDR_MODE0_DEU_CBC |
1964 DESC_HDR_MODE0_DEU_3DES |
1965 DESC_HDR_SEL1_MDEUA |
1966 DESC_HDR_MODE1_MDEU_INIT |
1967 DESC_HDR_MODE1_MDEU_PAD |
1968 DESC_HDR_MODE1_MDEU_SHA256_HMAC,
1969 },
d5e4aaef
LN		 1970 { .type = CRYPTO_ALG_TYPE_AEAD,
1971 .alg.crypto = {
56af8cd4
LN		 1972 .cra_name = "authenc(hmac(md5),cbc(aes))",
1973 .cra_driver_name = "authenc-hmac-md5-cbc-aes-talitos",
1974 .cra_blocksize = AES_BLOCK_SIZE,
1975 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1976 .cra_type = &crypto_aead_type,
1977 .cra_aead = {
1978 .setkey = aead_setkey,
1979 .setauthsize = aead_setauthsize,
1980 .encrypt = aead_encrypt,
1981 .decrypt = aead_decrypt,
1982 .givencrypt = aead_givencrypt,
1983 .geniv = "<built-in>",
1984 .ivsize = AES_BLOCK_SIZE,
1985 .maxauthsize = MD5_DIGEST_SIZE,
1986 }
1987 },
3952f17e
LN		 1988 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1989 DESC_HDR_SEL0_AESU |
1990 DESC_HDR_MODE0_AESU_CBC |
1991 DESC_HDR_SEL1_MDEUA |
1992 DESC_HDR_MODE1_MDEU_INIT |
1993 DESC_HDR_MODE1_MDEU_PAD |
1994 DESC_HDR_MODE1_MDEU_MD5_HMAC,
1995 },
d5e4aaef
LN		 1996 { .type = CRYPTO_ALG_TYPE_AEAD,
1997 .alg.crypto = {
56af8cd4
LN		 1998 .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
1999 .cra_driver_name = "authenc-hmac-md5-cbc-3des-talitos",
2000 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2001 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2002 .cra_type = &crypto_aead_type,
2003 .cra_aead = {
2004 .setkey = aead_setkey,
2005 .setauthsize = aead_setauthsize,
2006 .encrypt = aead_encrypt,
2007 .decrypt = aead_decrypt,
2008 .givencrypt = aead_givencrypt,
2009 .geniv = "<built-in>",
2010 .ivsize = DES3_EDE_BLOCK_SIZE,
2011 .maxauthsize = MD5_DIGEST_SIZE,
2012 }
2013 },
3952f17e
LN		 2014 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2015 DESC_HDR_SEL0_DEU |
2016 DESC_HDR_MODE0_DEU_CBC |
2017 DESC_HDR_MODE0_DEU_3DES |
2018 DESC_HDR_SEL1_MDEUA |
2019 DESC_HDR_MODE1_MDEU_INIT |
2020 DESC_HDR_MODE1_MDEU_PAD |
2021 DESC_HDR_MODE1_MDEU_MD5_HMAC,
4de9d0b5
LN		 2022 },
2023 /* ABLKCIPHER algorithms. */
d5e4aaef
LN		 2024 { .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
2025 .alg.crypto = {
4de9d0b5
LN		 2026 .cra_name = "cbc(aes)",
2027 .cra_driver_name = "cbc-aes-talitos",
2028 .cra_blocksize = AES_BLOCK_SIZE,
2029 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
2030 CRYPTO_ALG_ASYNC,
2031 .cra_type = &crypto_ablkcipher_type,
2032 .cra_ablkcipher = {
2033 .setkey = ablkcipher_setkey,
2034 .encrypt = ablkcipher_encrypt,
2035 .decrypt = ablkcipher_decrypt,
2036 .geniv = "eseqiv",
2037 .min_keysize = AES_MIN_KEY_SIZE,
2038 .max_keysize = AES_MAX_KEY_SIZE,
2039 .ivsize = AES_BLOCK_SIZE,
2040 }
2041 },
2042 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2043 DESC_HDR_SEL0_AESU |
2044 DESC_HDR_MODE0_AESU_CBC,
2045 },
d5e4aaef
LN		 2046 { .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
2047 .alg.crypto = {
4de9d0b5
LN		 2048 .cra_name = "cbc(des3_ede)",
2049 .cra_driver_name = "cbc-3des-talitos",
2050 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2051 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
2052 CRYPTO_ALG_ASYNC,
2053 .cra_type = &crypto_ablkcipher_type,
2054 .cra_ablkcipher = {
2055 .setkey = ablkcipher_setkey,
2056 .encrypt = ablkcipher_encrypt,
2057 .decrypt = ablkcipher_decrypt,
2058 .geniv = "eseqiv",
2059 .min_keysize = DES3_EDE_KEY_SIZE,
2060 .max_keysize = DES3_EDE_KEY_SIZE,
2061 .ivsize = DES3_EDE_BLOCK_SIZE,
2062 }
2063 },
2064 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2065 DESC_HDR_SEL0_DEU |
2066 DESC_HDR_MODE0_DEU_CBC |
2067 DESC_HDR_MODE0_DEU_3DES,
497f2e6b
LN		 2068 },
2069 /* AHASH algorithms. */
2070 { .type = CRYPTO_ALG_TYPE_AHASH,
2071 .alg.hash = {
2072 .init = ahash_init,
2073 .update = ahash_update,
2074 .final = ahash_final,
2075 .finup = ahash_finup,
2076 .digest = ahash_digest,
2077 .halg.digestsize = MD5_DIGEST_SIZE,
2078 .halg.base = {
2079 .cra_name = "md5",
2080 .cra_driver_name = "md5-talitos",
2081 .cra_blocksize = MD5_BLOCK_SIZE,
2082 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2083 CRYPTO_ALG_ASYNC,
2084 .cra_type = &crypto_ahash_type
2085 }
2086 },
2087 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2088 DESC_HDR_SEL0_MDEUA |
2089 DESC_HDR_MODE0_MDEU_MD5,
2090 },
2091 { .type = CRYPTO_ALG_TYPE_AHASH,
2092 .alg.hash = {
2093 .init = ahash_init,
2094 .update = ahash_update,
2095 .final = ahash_final,
2096 .finup = ahash_finup,
2097 .digest = ahash_digest,
2098 .halg.digestsize = SHA1_DIGEST_SIZE,
2099 .halg.base = {
2100 .cra_name = "sha1",
2101 .cra_driver_name = "sha1-talitos",
2102 .cra_blocksize = SHA1_BLOCK_SIZE,
2103 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2104 CRYPTO_ALG_ASYNC,
2105 .cra_type = &crypto_ahash_type
2106 }
2107 },
2108 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2109 DESC_HDR_SEL0_MDEUA |
2110 DESC_HDR_MODE0_MDEU_SHA1,
2111 },
2112 { .type = CRYPTO_ALG_TYPE_AHASH,
2113 .alg.hash = {
2114 .init = ahash_init,
2115 .update = ahash_update,
2116 .final = ahash_final,
2117 .finup = ahash_finup,
2118 .digest = ahash_digest,
2119 .halg.digestsize = SHA256_DIGEST_SIZE,
2120 .halg.base = {
2121 .cra_name = "sha256",
2122 .cra_driver_name = "sha256-talitos",
2123 .cra_blocksize = SHA256_BLOCK_SIZE,
2124 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2125 CRYPTO_ALG_ASYNC,
2126 .cra_type = &crypto_ahash_type
2127 }
2128 },
2129 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2130 DESC_HDR_SEL0_MDEUA |
2131 DESC_HDR_MODE0_MDEU_SHA256,
2132 },
2133 { .type = CRYPTO_ALG_TYPE_AHASH,
2134 .alg.hash = {
2135 .init = ahash_init,
2136 .update = ahash_update,
2137 .final = ahash_final,
2138 .finup = ahash_finup,
2139 .digest = ahash_digest,
2140 .halg.digestsize = SHA384_DIGEST_SIZE,
2141 .halg.base = {
2142 .cra_name = "sha384",
2143 .cra_driver_name = "sha384-talitos",
2144 .cra_blocksize = SHA384_BLOCK_SIZE,
2145 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2146 CRYPTO_ALG_ASYNC,
2147 .cra_type = &crypto_ahash_type
2148 }
2149 },
2150 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2151 DESC_HDR_SEL0_MDEUB |
2152 DESC_HDR_MODE0_MDEUB_SHA384,
2153 },
2154 { .type = CRYPTO_ALG_TYPE_AHASH,
2155 .alg.hash = {
2156 .init = ahash_init,
2157 .update = ahash_update,
2158 .final = ahash_final,
2159 .finup = ahash_finup,
2160 .digest = ahash_digest,
2161 .halg.digestsize = SHA512_DIGEST_SIZE,
2162 .halg.base = {
2163 .cra_name = "sha512",
2164 .cra_driver_name = "sha512-talitos",
2165 .cra_blocksize = SHA512_BLOCK_SIZE,
2166 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2167 CRYPTO_ALG_ASYNC,
2168 .cra_type = &crypto_ahash_type
2169 }
2170 },
2171 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2172 DESC_HDR_SEL0_MDEUB |
2173 DESC_HDR_MODE0_MDEUB_SHA512,
2174 },
9c4a7965
KP		 2175};
2176
2177struct talitos_crypto_alg {
2178 struct list_head entry;
2179 struct device *dev;
acbf7c62 2180 struct talitos_alg_template algt;
9c4a7965
KP		 2181};
2182
2183static int talitos_cra_init(struct crypto_tfm *tfm)
2184{
2185 struct crypto_alg *alg = tfm->__crt_alg;
19bbbc63 2186 struct talitos_crypto_alg *talitos_alg;
9c4a7965
KP		 2187 struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
2188
497f2e6b
LN		 2189 if ((alg->cra_flags & CRYPTO_ALG_TYPE_MASK) == CRYPTO_ALG_TYPE_AHASH)
2190 talitos_alg = container_of(__crypto_ahash_alg(alg),
2191 struct talitos_crypto_alg,
2192 algt.alg.hash);
2193 else
2194 talitos_alg = container_of(alg, struct talitos_crypto_alg,
2195 algt.alg.crypto);
19bbbc63 2196
9c4a7965
KP		 2197 /* update context with ptr to dev */
2198 ctx->dev = talitos_alg->dev;
19bbbc63 2199
9c4a7965 2200 /* copy descriptor header template value */
acbf7c62 2201 ctx->desc_hdr_template = talitos_alg->algt.desc_hdr_template;
9c4a7965 2202
497f2e6b
LN		 2203 return 0;
2204}
2205
2206static int talitos_cra_init_aead(struct crypto_tfm *tfm)
2207{
2208 struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
2209
2210 talitos_cra_init(tfm);
2211
9c4a7965 2212 /* random first IV */
70bcaca7 2213 get_random_bytes(ctx->iv, TALITOS_MAX_IV_LENGTH);
9c4a7965
KP		 2214
2215 return 0;
2216}
2217
497f2e6b
LN		 2218static int talitos_cra_init_ahash(struct crypto_tfm *tfm)
2219{
2220 struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
2221
2222 talitos_cra_init(tfm);
2223
2224 ctx->keylen = 0;
2225 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
2226 sizeof(struct talitos_ahash_req_ctx));
2227
2228 return 0;
2229}
2230
9c4a7965
KP		 2231/*
2232 * given the alg's descriptor header template, determine whether descriptor
2233 * type and primary/secondary execution units required match the hw
2234 * capabilities description provided in the device tree node.
2235 */
2236static int hw_supports(struct device *dev, __be32 desc_hdr_template)
2237{
2238 struct talitos_private *priv = dev_get_drvdata(dev);
2239 int ret;
2240
2241 ret = (1 << DESC_TYPE(desc_hdr_template) & priv->desc_types) &&
2242 (1 << PRIMARY_EU(desc_hdr_template) & priv->exec_units);
2243
2244 if (SECONDARY_EU(desc_hdr_template))
2245 ret = ret && (1 << SECONDARY_EU(desc_hdr_template)
2246 & priv->exec_units);
2247
2248 return ret;
2249}
2250
596f1034 2251static int talitos_remove(struct of_device *ofdev)
9c4a7965
KP		 2252{
2253 struct device *dev = &ofdev->dev;
2254 struct talitos_private *priv = dev_get_drvdata(dev);
2255 struct talitos_crypto_alg *t_alg, *n;
2256 int i;
2257
2258 list_for_each_entry_safe(t_alg, n, &priv->alg_list, entry) {
acbf7c62
LN		 2259 switch (t_alg->algt.type) {
2260 case CRYPTO_ALG_TYPE_ABLKCIPHER:
2261 case CRYPTO_ALG_TYPE_AEAD:
2262 crypto_unregister_alg(&t_alg->algt.alg.crypto);
2263 break;
2264 case CRYPTO_ALG_TYPE_AHASH:
2265 crypto_unregister_ahash(&t_alg->algt.alg.hash);
2266 break;
2267 }
9c4a7965
KP		 2268 list_del(&t_alg->entry);
2269 kfree(t_alg);
2270 }
2271
2272 if (hw_supports(dev, DESC_HDR_SEL0_RNG))
2273 talitos_unregister_rng(dev);
2274
4b992628
KP		 2275 for (i = 0; i < priv->num_channels; i++)
2276 if (priv->chan[i].fifo)
2277 kfree(priv->chan[i].fifo);
9c4a7965 2278
4b992628 2279 kfree(priv->chan);
9c4a7965
KP		 2280
2281 if (priv->irq != NO_IRQ) {
2282 free_irq(priv->irq, dev);
2283 irq_dispose_mapping(priv->irq);
2284 }
2285
2286 tasklet_kill(&priv->done_task);
9c4a7965
KP		 2287
2288 iounmap(priv->reg);
2289
2290 dev_set_drvdata(dev, NULL);
2291
2292 kfree(priv);
2293
2294 return 0;
2295}
2296
2297static struct talitos_crypto_alg *talitos_alg_alloc(struct device *dev,
2298 struct talitos_alg_template
2299 *template)
2300{
2301 struct talitos_crypto_alg *t_alg;
2302 struct crypto_alg *alg;
2303
2304 t_alg = kzalloc(sizeof(struct talitos_crypto_alg), GFP_KERNEL);
2305 if (!t_alg)
2306 return ERR_PTR(-ENOMEM);
2307
acbf7c62
LN		 2308 t_alg->algt = *template;
2309
2310 switch (t_alg->algt.type) {
2311 case CRYPTO_ALG_TYPE_ABLKCIPHER:
497f2e6b
LN		 2312 alg = &t_alg->algt.alg.crypto;
2313 alg->cra_init = talitos_cra_init;
2314 break;
acbf7c62
LN		 2315 case CRYPTO_ALG_TYPE_AEAD:
2316 alg = &t_alg->algt.alg.crypto;
497f2e6b 2317 alg->cra_init = talitos_cra_init_aead;
acbf7c62
LN		 2318 break;
2319 case CRYPTO_ALG_TYPE_AHASH:
2320 alg = &t_alg->algt.alg.hash.halg.base;
497f2e6b
LN		 2321 alg->cra_init = talitos_cra_init_ahash;
2322 break;
acbf7c62 2323 }
9c4a7965 2324
9c4a7965 2325 alg->cra_module = THIS_MODULE;
9c4a7965 2326 alg->cra_priority = TALITOS_CRA_PRIORITY;
9c4a7965 2327 alg->cra_alignmask = 0;
9c4a7965 2328 alg->cra_ctxsize = sizeof(struct talitos_ctx);
9c4a7965 2329
9c4a7965
KP		 2330 t_alg->dev = dev;
2331
2332 return t_alg;
2333}
2334
2335static int talitos_probe(struct of_device *ofdev,
2336 const struct of_device_id *match)
2337{
2338 struct device *dev = &ofdev->dev;
2339 struct device_node *np = ofdev->node;
2340 struct talitos_private *priv;
2341 const unsigned int *prop;
2342 int i, err;
2343
2344 priv = kzalloc(sizeof(struct talitos_private), GFP_KERNEL);
2345 if (!priv)
2346 return -ENOMEM;
2347
2348 dev_set_drvdata(dev, priv);
2349
2350 priv->ofdev = ofdev;
2351
2352 tasklet_init(&priv->done_task, talitos_done, (unsigned long)dev);
9c4a7965 2353
fe5720e2
KP		 2354 INIT_LIST_HEAD(&priv->alg_list);
2355
9c4a7965
KP		 2356 priv->irq = irq_of_parse_and_map(np, 0);
2357
2358 if (priv->irq == NO_IRQ) {
2359 dev_err(dev, "failed to map irq\n");
2360 err = -EINVAL;
2361 goto err_out;
2362 }
2363
2364 /* get the irq line */
2365 err = request_irq(priv->irq, talitos_interrupt, 0,
2366 dev_driver_string(dev), dev);
2367 if (err) {
2368 dev_err(dev, "failed to request irq %d\n", priv->irq);
2369 irq_dispose_mapping(priv->irq);
2370 priv->irq = NO_IRQ;
2371 goto err_out;
2372 }
2373
2374 priv->reg = of_iomap(np, 0);
2375 if (!priv->reg) {
2376 dev_err(dev, "failed to of_iomap\n");
2377 err = -ENOMEM;
2378 goto err_out;
2379 }
2380
2381 /* get SEC version capabilities from device tree */
2382 prop = of_get_property(np, "fsl,num-channels", NULL);
2383 if (prop)
2384 priv->num_channels = *prop;
2385
2386 prop = of_get_property(np, "fsl,channel-fifo-len", NULL);
2387 if (prop)
2388 priv->chfifo_len = *prop;
2389
2390 prop = of_get_property(np, "fsl,exec-units-mask", NULL);
2391 if (prop)
2392 priv->exec_units = *prop;
2393
2394 prop = of_get_property(np, "fsl,descriptor-types-mask", NULL);
2395 if (prop)
2396 priv->desc_types = *prop;
2397
2398 if (!is_power_of_2(priv->num_channels) || !priv->chfifo_len ||
2399 !priv->exec_units || !priv->desc_types) {
2400 dev_err(dev, "invalid property data in device tree node\n");
2401 err = -EINVAL;
2402 goto err_out;
2403 }
2404
f3c85bc1
LN		 2405 if (of_device_is_compatible(np, "fsl,sec3.0"))
2406 priv->features |= TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT;
2407
fe5720e2
KP		 2408 if (of_device_is_compatible(np, "fsl,sec2.1"))
2409 priv->features |= TALITOS_FTR_HW_AUTH_CHECK;
2410
4b992628
KP		 2411 priv->chan = kzalloc(sizeof(struct talitos_channel) *
2412 priv->num_channels, GFP_KERNEL);
2413 if (!priv->chan) {
2414 dev_err(dev, "failed to allocate channel management space\n");
9c4a7965
KP		 2415 err = -ENOMEM;
2416 goto err_out;
2417 }
2418
2419 for (i = 0; i < priv->num_channels; i++) {
4b992628
KP		 2420 spin_lock_init(&priv->chan[i].head_lock);
2421 spin_lock_init(&priv->chan[i].tail_lock);
9c4a7965
KP		 2422 }
2423
2424 priv->fifo_len = roundup_pow_of_two(priv->chfifo_len);
2425
2426 for (i = 0; i < priv->num_channels; i++) {
4b992628
KP		 2427 priv->chan[i].fifo = kzalloc(sizeof(struct talitos_request) *
2428 priv->fifo_len, GFP_KERNEL);
2429 if (!priv->chan[i].fifo) {
9c4a7965
KP		 2430 dev_err(dev, "failed to allocate request fifo %d\n", i);
2431 err = -ENOMEM;
2432 goto err_out;
2433 }
2434 }
2435
ec6644d6 2436 for (i = 0; i < priv->num_channels; i++)
4b992628
KP		 2437 atomic_set(&priv->chan[i].submit_count,
2438 -(priv->chfifo_len - 1));
9c4a7965 2439
81eb024c
KP		 2440 dma_set_mask(dev, DMA_BIT_MASK(36));
2441
9c4a7965
KP		 2442 /* reset and initialize the h/w */
2443 err = init_device(dev);
2444 if (err) {
2445 dev_err(dev, "failed to initialize device\n");
2446 goto err_out;
2447 }
2448
2449 /* register the RNG, if available */
2450 if (hw_supports(dev, DESC_HDR_SEL0_RNG)) {
2451 err = talitos_register_rng(dev);
2452 if (err) {
2453 dev_err(dev, "failed to register hwrng: %d\n", err);
2454 goto err_out;
2455 } else
2456 dev_info(dev, "hwrng\n");
2457 }
2458
2459 /* register crypto algorithms the device supports */
9c4a7965
KP		 2460 for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
2461 if (hw_supports(dev, driver_algs[i].desc_hdr_template)) {
2462 struct talitos_crypto_alg *t_alg;
acbf7c62 2463 char *name = NULL;
9c4a7965
KP		 2464
2465 t_alg = talitos_alg_alloc(dev, &driver_algs[i]);
2466 if (IS_ERR(t_alg)) {
2467 err = PTR_ERR(t_alg);
2468 goto err_out;
2469 }
2470
acbf7c62
LN		 2471 switch (t_alg->algt.type) {
2472 case CRYPTO_ALG_TYPE_ABLKCIPHER:
2473 case CRYPTO_ALG_TYPE_AEAD:
2474 err = crypto_register_alg(
2475 &t_alg->algt.alg.crypto);
2476 name = t_alg->algt.alg.crypto.cra_driver_name;
2477 break;
2478 case CRYPTO_ALG_TYPE_AHASH:
2479 err = crypto_register_ahash(
2480 &t_alg->algt.alg.hash);
2481 name =
2482 t_alg->algt.alg.hash.halg.base.cra_driver_name;
2483 break;
2484 }
9c4a7965
KP		 2485 if (err) {
2486 dev_err(dev, "%s alg registration failed\n",
acbf7c62 2487 name);
9c4a7965
KP		 2488 kfree(t_alg);
2489 } else {
2490 list_add_tail(&t_alg->entry, &priv->alg_list);
acbf7c62 2491 dev_info(dev, "%s\n", name);
9c4a7965
KP		 2492 }
2493 }
2494 }
2495
2496 return 0;
2497
2498err_out:
2499 talitos_remove(ofdev);
9c4a7965
KP		 2500
2501 return err;
2502}
2503
6c3f975a 2504static const struct of_device_id talitos_match[] = {
9c4a7965
KP		 2505 {
2506 .compatible = "fsl,sec2.0",
2507 },
2508 {},
2509};
2510MODULE_DEVICE_TABLE(of, talitos_match);
2511
2512static struct of_platform_driver talitos_driver = {
2513 .name = "talitos",
2514 .match_table = talitos_match,
2515 .probe = talitos_probe,
596f1034 2516 .remove = talitos_remove,
9c4a7965
KP		 2517};
2518
2519static int __init talitos_init(void)
2520{
2521 return of_register_platform_driver(&talitos_driver);
2522}
2523module_init(talitos_init);
2524
2525static void __exit talitos_exit(void)
2526{
2527 of_unregister_platform_driver(&talitos_driver);
2528}
2529module_exit(talitos_exit);
2530
2531MODULE_LICENSE("GPL");
2532MODULE_AUTHOR("Kim Phillips <kim.phillips@freescale.com>");
2533MODULE_DESCRIPTION("Freescale integrated security engine (SEC) driver");
Linux kernel - Deliverables
This page took 0.256917 seconds and 5 git commands to generate.