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e8689e63 LW |
1 | /* |
2 | * Copyright (c) 2006 ARM Ltd. | |
3 | * Copyright (c) 2010 ST-Ericsson SA | |
4 | * | |
5 | * Author: Peter Pearse <peter.pearse@arm.com> | |
6 | * Author: Linus Walleij <linus.walleij@stericsson.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the Free | |
10 | * Software Foundation; either version 2 of the License, or (at your option) | |
11 | * any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
16 | * more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License along with | |
19 | * this program; if not, write to the Free Software Foundation, Inc., 59 | |
20 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
21 | * | |
94ae8522 RKAL |
22 | * The full GNU General Public License is in this distribution in the file |
23 | * called COPYING. | |
e8689e63 LW |
24 | * |
25 | * Documentation: ARM DDI 0196G == PL080 | |
94ae8522 | 26 | * Documentation: ARM DDI 0218E == PL081 |
e8689e63 | 27 | * |
94ae8522 RKAL |
28 | * PL080 & PL081 both have 16 sets of DMA signals that can be routed to any |
29 | * channel. | |
e8689e63 LW |
30 | * |
31 | * The PL080 has 8 channels available for simultaneous use, and the PL081 | |
32 | * has only two channels. So on these DMA controllers the number of channels | |
33 | * and the number of incoming DMA signals are two totally different things. | |
34 | * It is usually not possible to theoretically handle all physical signals, | |
35 | * so a multiplexing scheme with possible denial of use is necessary. | |
36 | * | |
37 | * The PL080 has a dual bus master, PL081 has a single master. | |
38 | * | |
39 | * Memory to peripheral transfer may be visualized as | |
40 | * Get data from memory to DMAC | |
41 | * Until no data left | |
42 | * On burst request from peripheral | |
43 | * Destination burst from DMAC to peripheral | |
44 | * Clear burst request | |
45 | * Raise terminal count interrupt | |
46 | * | |
47 | * For peripherals with a FIFO: | |
48 | * Source burst size == half the depth of the peripheral FIFO | |
49 | * Destination burst size == the depth of the peripheral FIFO | |
50 | * | |
51 | * (Bursts are irrelevant for mem to mem transfers - there are no burst | |
52 | * signals, the DMA controller will simply facilitate its AHB master.) | |
53 | * | |
54 | * ASSUMES default (little) endianness for DMA transfers | |
55 | * | |
9dc2c200 RKAL |
56 | * The PL08x has two flow control settings: |
57 | * - DMAC flow control: the transfer size defines the number of transfers | |
58 | * which occur for the current LLI entry, and the DMAC raises TC at the | |
59 | * end of every LLI entry. Observed behaviour shows the DMAC listening | |
60 | * to both the BREQ and SREQ signals (contrary to documented), | |
61 | * transferring data if either is active. The LBREQ and LSREQ signals | |
62 | * are ignored. | |
63 | * | |
64 | * - Peripheral flow control: the transfer size is ignored (and should be | |
65 | * zero). The data is transferred from the current LLI entry, until | |
66 | * after the final transfer signalled by LBREQ or LSREQ. The DMAC | |
67 | * will then move to the next LLI entry. | |
68 | * | |
69 | * Only the former works sanely with scatter lists, so we only implement | |
70 | * the DMAC flow control method. However, peripherals which use the LBREQ | |
71 | * and LSREQ signals (eg, MMCI) are unable to use this mode, which through | |
72 | * these hardware restrictions prevents them from using scatter DMA. | |
e8689e63 LW |
73 | * |
74 | * Global TODO: | |
75 | * - Break out common code from arch/arm/mach-s3c64xx and share | |
76 | */ | |
730404ac | 77 | #include <linux/amba/bus.h> |
e8689e63 LW |
78 | #include <linux/amba/pl08x.h> |
79 | #include <linux/debugfs.h> | |
0c38d701 VK |
80 | #include <linux/delay.h> |
81 | #include <linux/device.h> | |
82 | #include <linux/dmaengine.h> | |
83 | #include <linux/dmapool.h> | |
84 | #include <linux/init.h> | |
85 | #include <linux/interrupt.h> | |
86 | #include <linux/module.h> | |
b7b6018b | 87 | #include <linux/pm_runtime.h> |
e8689e63 | 88 | #include <linux/seq_file.h> |
0c38d701 | 89 | #include <linux/slab.h> |
e8689e63 | 90 | #include <asm/hardware/pl080.h> |
e8689e63 LW |
91 | |
92 | #define DRIVER_NAME "pl08xdmac" | |
93 | ||
94 | /** | |
94ae8522 | 95 | * struct vendor_data - vendor-specific config parameters for PL08x derivatives |
e8689e63 | 96 | * @channels: the number of channels available in this variant |
94ae8522 | 97 | * @dualmaster: whether this version supports dual AHB masters or not. |
e8689e63 LW |
98 | */ |
99 | struct vendor_data { | |
e8689e63 LW |
100 | u8 channels; |
101 | bool dualmaster; | |
102 | }; | |
103 | ||
104 | /* | |
105 | * PL08X private data structures | |
e8b5e11d | 106 | * An LLI struct - see PL08x TRM. Note that next uses bit[0] as a bus bit, |
e25761d7 RKAL |
107 | * start & end do not - their bus bit info is in cctl. Also note that these |
108 | * are fixed 32-bit quantities. | |
e8689e63 | 109 | */ |
7cb72ad9 | 110 | struct pl08x_lli { |
e25761d7 RKAL |
111 | u32 src; |
112 | u32 dst; | |
bfddfb45 | 113 | u32 lli; |
e8689e63 LW |
114 | u32 cctl; |
115 | }; | |
116 | ||
117 | /** | |
118 | * struct pl08x_driver_data - the local state holder for the PL08x | |
119 | * @slave: slave engine for this instance | |
120 | * @memcpy: memcpy engine for this instance | |
121 | * @base: virtual memory base (remapped) for the PL08x | |
122 | * @adev: the corresponding AMBA (PrimeCell) bus entry | |
123 | * @vd: vendor data for this PL08x variant | |
124 | * @pd: platform data passed in from the platform/machine | |
125 | * @phy_chans: array of data for the physical channels | |
126 | * @pool: a pool for the LLI descriptors | |
127 | * @pool_ctr: counter of LLIs in the pool | |
3e27ee84 VK |
128 | * @lli_buses: bitmask to or in to LLI pointer selecting AHB port for LLI |
129 | * fetches | |
30749cb4 | 130 | * @mem_buses: set to indicate memory transfers on AHB2. |
e8689e63 LW |
131 | * @lock: a spinlock for this struct |
132 | */ | |
133 | struct pl08x_driver_data { | |
134 | struct dma_device slave; | |
135 | struct dma_device memcpy; | |
136 | void __iomem *base; | |
137 | struct amba_device *adev; | |
f96ca9ec | 138 | const struct vendor_data *vd; |
e8689e63 LW |
139 | struct pl08x_platform_data *pd; |
140 | struct pl08x_phy_chan *phy_chans; | |
141 | struct dma_pool *pool; | |
142 | int pool_ctr; | |
30749cb4 RKAL |
143 | u8 lli_buses; |
144 | u8 mem_buses; | |
e8689e63 LW |
145 | spinlock_t lock; |
146 | }; | |
147 | ||
148 | /* | |
149 | * PL08X specific defines | |
150 | */ | |
151 | ||
152 | /* | |
153 | * Memory boundaries: the manual for PL08x says that the controller | |
154 | * cannot read past a 1KiB boundary, so these defines are used to | |
155 | * create transfer LLIs that do not cross such boundaries. | |
156 | */ | |
157 | #define PL08X_BOUNDARY_SHIFT (10) /* 1KB 0x400 */ | |
158 | #define PL08X_BOUNDARY_SIZE (1 << PL08X_BOUNDARY_SHIFT) | |
159 | ||
e8689e63 LW |
160 | /* Size (bytes) of each LLI buffer allocated for one transfer */ |
161 | # define PL08X_LLI_TSFR_SIZE 0x2000 | |
162 | ||
e8b5e11d | 163 | /* Maximum times we call dma_pool_alloc on this pool without freeing */ |
7cb72ad9 | 164 | #define MAX_NUM_TSFR_LLIS (PL08X_LLI_TSFR_SIZE/sizeof(struct pl08x_lli)) |
e8689e63 LW |
165 | #define PL08X_ALIGN 8 |
166 | ||
167 | static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan) | |
168 | { | |
169 | return container_of(chan, struct pl08x_dma_chan, chan); | |
170 | } | |
171 | ||
501e67e8 RKAL |
172 | static inline struct pl08x_txd *to_pl08x_txd(struct dma_async_tx_descriptor *tx) |
173 | { | |
174 | return container_of(tx, struct pl08x_txd, tx); | |
175 | } | |
176 | ||
e8689e63 LW |
177 | /* |
178 | * Physical channel handling | |
179 | */ | |
180 | ||
181 | /* Whether a certain channel is busy or not */ | |
182 | static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch) | |
183 | { | |
184 | unsigned int val; | |
185 | ||
186 | val = readl(ch->base + PL080_CH_CONFIG); | |
187 | return val & PL080_CONFIG_ACTIVE; | |
188 | } | |
189 | ||
190 | /* | |
191 | * Set the initial DMA register values i.e. those for the first LLI | |
e8b5e11d | 192 | * The next LLI pointer and the configuration interrupt bit have |
c885bee4 RKAL |
193 | * been set when the LLIs were constructed. Poke them into the hardware |
194 | * and start the transfer. | |
e8689e63 | 195 | */ |
c885bee4 RKAL |
196 | static void pl08x_start_txd(struct pl08x_dma_chan *plchan, |
197 | struct pl08x_txd *txd) | |
e8689e63 | 198 | { |
c885bee4 | 199 | struct pl08x_driver_data *pl08x = plchan->host; |
e8689e63 | 200 | struct pl08x_phy_chan *phychan = plchan->phychan; |
19524d77 | 201 | struct pl08x_lli *lli = &txd->llis_va[0]; |
09b3c323 | 202 | u32 val; |
c885bee4 RKAL |
203 | |
204 | plchan->at = txd; | |
e8689e63 | 205 | |
c885bee4 RKAL |
206 | /* Wait for channel inactive */ |
207 | while (pl08x_phy_channel_busy(phychan)) | |
208 | cpu_relax(); | |
e8689e63 | 209 | |
c885bee4 RKAL |
210 | dev_vdbg(&pl08x->adev->dev, |
211 | "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, " | |
19524d77 RKAL |
212 | "clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n", |
213 | phychan->id, lli->src, lli->dst, lli->lli, lli->cctl, | |
09b3c323 | 214 | txd->ccfg); |
19524d77 RKAL |
215 | |
216 | writel(lli->src, phychan->base + PL080_CH_SRC_ADDR); | |
217 | writel(lli->dst, phychan->base + PL080_CH_DST_ADDR); | |
218 | writel(lli->lli, phychan->base + PL080_CH_LLI); | |
219 | writel(lli->cctl, phychan->base + PL080_CH_CONTROL); | |
09b3c323 | 220 | writel(txd->ccfg, phychan->base + PL080_CH_CONFIG); |
c885bee4 RKAL |
221 | |
222 | /* Enable the DMA channel */ | |
223 | /* Do not access config register until channel shows as disabled */ | |
224 | while (readl(pl08x->base + PL080_EN_CHAN) & (1 << phychan->id)) | |
19386b32 | 225 | cpu_relax(); |
e8689e63 | 226 | |
c885bee4 RKAL |
227 | /* Do not access config register until channel shows as inactive */ |
228 | val = readl(phychan->base + PL080_CH_CONFIG); | |
e8689e63 | 229 | while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE)) |
c885bee4 | 230 | val = readl(phychan->base + PL080_CH_CONFIG); |
e8689e63 | 231 | |
c885bee4 | 232 | writel(val | PL080_CONFIG_ENABLE, phychan->base + PL080_CH_CONFIG); |
e8689e63 LW |
233 | } |
234 | ||
235 | /* | |
81796616 | 236 | * Pause the channel by setting the HALT bit. |
e8689e63 | 237 | * |
81796616 RKAL |
238 | * For M->P transfers, pause the DMAC first and then stop the peripheral - |
239 | * the FIFO can only drain if the peripheral is still requesting data. | |
240 | * (note: this can still timeout if the DMAC FIFO never drains of data.) | |
e8689e63 | 241 | * |
81796616 RKAL |
242 | * For P->M transfers, disable the peripheral first to stop it filling |
243 | * the DMAC FIFO, and then pause the DMAC. | |
e8689e63 LW |
244 | */ |
245 | static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch) | |
246 | { | |
247 | u32 val; | |
81796616 | 248 | int timeout; |
e8689e63 LW |
249 | |
250 | /* Set the HALT bit and wait for the FIFO to drain */ | |
251 | val = readl(ch->base + PL080_CH_CONFIG); | |
252 | val |= PL080_CONFIG_HALT; | |
253 | writel(val, ch->base + PL080_CH_CONFIG); | |
254 | ||
255 | /* Wait for channel inactive */ | |
81796616 RKAL |
256 | for (timeout = 1000; timeout; timeout--) { |
257 | if (!pl08x_phy_channel_busy(ch)) | |
258 | break; | |
259 | udelay(1); | |
260 | } | |
261 | if (pl08x_phy_channel_busy(ch)) | |
262 | pr_err("pl08x: channel%u timeout waiting for pause\n", ch->id); | |
e8689e63 LW |
263 | } |
264 | ||
265 | static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch) | |
266 | { | |
267 | u32 val; | |
268 | ||
269 | /* Clear the HALT bit */ | |
270 | val = readl(ch->base + PL080_CH_CONFIG); | |
271 | val &= ~PL080_CONFIG_HALT; | |
272 | writel(val, ch->base + PL080_CH_CONFIG); | |
273 | } | |
274 | ||
fb526210 RKAL |
275 | /* |
276 | * pl08x_terminate_phy_chan() stops the channel, clears the FIFO and | |
277 | * clears any pending interrupt status. This should not be used for | |
278 | * an on-going transfer, but as a method of shutting down a channel | |
279 | * (eg, when it's no longer used) or terminating a transfer. | |
280 | */ | |
281 | static void pl08x_terminate_phy_chan(struct pl08x_driver_data *pl08x, | |
282 | struct pl08x_phy_chan *ch) | |
e8689e63 | 283 | { |
fb526210 | 284 | u32 val = readl(ch->base + PL080_CH_CONFIG); |
e8689e63 | 285 | |
fb526210 RKAL |
286 | val &= ~(PL080_CONFIG_ENABLE | PL080_CONFIG_ERR_IRQ_MASK | |
287 | PL080_CONFIG_TC_IRQ_MASK); | |
e8689e63 | 288 | |
e8689e63 | 289 | writel(val, ch->base + PL080_CH_CONFIG); |
fb526210 RKAL |
290 | |
291 | writel(1 << ch->id, pl08x->base + PL080_ERR_CLEAR); | |
292 | writel(1 << ch->id, pl08x->base + PL080_TC_CLEAR); | |
e8689e63 LW |
293 | } |
294 | ||
295 | static inline u32 get_bytes_in_cctl(u32 cctl) | |
296 | { | |
297 | /* The source width defines the number of bytes */ | |
298 | u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK; | |
299 | ||
300 | switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) { | |
301 | case PL080_WIDTH_8BIT: | |
302 | break; | |
303 | case PL080_WIDTH_16BIT: | |
304 | bytes *= 2; | |
305 | break; | |
306 | case PL080_WIDTH_32BIT: | |
307 | bytes *= 4; | |
308 | break; | |
309 | } | |
310 | return bytes; | |
311 | } | |
312 | ||
313 | /* The channel should be paused when calling this */ | |
314 | static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan) | |
315 | { | |
316 | struct pl08x_phy_chan *ch; | |
e8689e63 LW |
317 | struct pl08x_txd *txd; |
318 | unsigned long flags; | |
cace6585 | 319 | size_t bytes = 0; |
e8689e63 LW |
320 | |
321 | spin_lock_irqsave(&plchan->lock, flags); | |
e8689e63 LW |
322 | ch = plchan->phychan; |
323 | txd = plchan->at; | |
324 | ||
325 | /* | |
db9f136a RKAL |
326 | * Follow the LLIs to get the number of remaining |
327 | * bytes in the currently active transaction. | |
e8689e63 LW |
328 | */ |
329 | if (ch && txd) { | |
4c0df6a3 | 330 | u32 clli = readl(ch->base + PL080_CH_LLI) & ~PL080_LLI_LM_AHB2; |
e8689e63 | 331 | |
db9f136a | 332 | /* First get the remaining bytes in the active transfer */ |
e8689e63 LW |
333 | bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL)); |
334 | ||
335 | if (clli) { | |
db9f136a RKAL |
336 | struct pl08x_lli *llis_va = txd->llis_va; |
337 | dma_addr_t llis_bus = txd->llis_bus; | |
338 | int index; | |
339 | ||
340 | BUG_ON(clli < llis_bus || clli >= llis_bus + | |
341 | sizeof(struct pl08x_lli) * MAX_NUM_TSFR_LLIS); | |
e8689e63 | 342 | |
db9f136a RKAL |
343 | /* |
344 | * Locate the next LLI - as this is an array, | |
345 | * it's simple maths to find. | |
346 | */ | |
347 | index = (clli - llis_bus) / sizeof(struct pl08x_lli); | |
348 | ||
349 | for (; index < MAX_NUM_TSFR_LLIS; index++) { | |
350 | bytes += get_bytes_in_cctl(llis_va[index].cctl); | |
e8689e63 | 351 | |
e8689e63 | 352 | /* |
e8b5e11d | 353 | * A LLI pointer of 0 terminates the LLI list |
e8689e63 | 354 | */ |
db9f136a RKAL |
355 | if (!llis_va[index].lli) |
356 | break; | |
e8689e63 LW |
357 | } |
358 | } | |
359 | } | |
360 | ||
361 | /* Sum up all queued transactions */ | |
15c17232 | 362 | if (!list_empty(&plchan->pend_list)) { |
db9f136a | 363 | struct pl08x_txd *txdi; |
15c17232 | 364 | list_for_each_entry(txdi, &plchan->pend_list, node) { |
e8689e63 LW |
365 | bytes += txdi->len; |
366 | } | |
e8689e63 LW |
367 | } |
368 | ||
369 | spin_unlock_irqrestore(&plchan->lock, flags); | |
370 | ||
371 | return bytes; | |
372 | } | |
373 | ||
374 | /* | |
375 | * Allocate a physical channel for a virtual channel | |
94ae8522 RKAL |
376 | * |
377 | * Try to locate a physical channel to be used for this transfer. If all | |
378 | * are taken return NULL and the requester will have to cope by using | |
379 | * some fallback PIO mode or retrying later. | |
e8689e63 LW |
380 | */ |
381 | static struct pl08x_phy_chan * | |
382 | pl08x_get_phy_channel(struct pl08x_driver_data *pl08x, | |
383 | struct pl08x_dma_chan *virt_chan) | |
384 | { | |
385 | struct pl08x_phy_chan *ch = NULL; | |
386 | unsigned long flags; | |
387 | int i; | |
388 | ||
e8689e63 LW |
389 | for (i = 0; i < pl08x->vd->channels; i++) { |
390 | ch = &pl08x->phy_chans[i]; | |
391 | ||
392 | spin_lock_irqsave(&ch->lock, flags); | |
393 | ||
394 | if (!ch->serving) { | |
395 | ch->serving = virt_chan; | |
396 | ch->signal = -1; | |
397 | spin_unlock_irqrestore(&ch->lock, flags); | |
398 | break; | |
399 | } | |
400 | ||
401 | spin_unlock_irqrestore(&ch->lock, flags); | |
402 | } | |
403 | ||
404 | if (i == pl08x->vd->channels) { | |
405 | /* No physical channel available, cope with it */ | |
406 | return NULL; | |
407 | } | |
408 | ||
b7b6018b | 409 | pm_runtime_get_sync(&pl08x->adev->dev); |
e8689e63 LW |
410 | return ch; |
411 | } | |
412 | ||
413 | static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x, | |
414 | struct pl08x_phy_chan *ch) | |
415 | { | |
416 | unsigned long flags; | |
417 | ||
fb526210 RKAL |
418 | spin_lock_irqsave(&ch->lock, flags); |
419 | ||
e8689e63 | 420 | /* Stop the channel and clear its interrupts */ |
fb526210 | 421 | pl08x_terminate_phy_chan(pl08x, ch); |
e8689e63 | 422 | |
b7b6018b VK |
423 | pm_runtime_put(&pl08x->adev->dev); |
424 | ||
e8689e63 | 425 | /* Mark it as free */ |
e8689e63 LW |
426 | ch->serving = NULL; |
427 | spin_unlock_irqrestore(&ch->lock, flags); | |
428 | } | |
429 | ||
430 | /* | |
431 | * LLI handling | |
432 | */ | |
433 | ||
434 | static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded) | |
435 | { | |
436 | switch (coded) { | |
437 | case PL080_WIDTH_8BIT: | |
438 | return 1; | |
439 | case PL080_WIDTH_16BIT: | |
440 | return 2; | |
441 | case PL080_WIDTH_32BIT: | |
442 | return 4; | |
443 | default: | |
444 | break; | |
445 | } | |
446 | BUG(); | |
447 | return 0; | |
448 | } | |
449 | ||
450 | static inline u32 pl08x_cctl_bits(u32 cctl, u8 srcwidth, u8 dstwidth, | |
cace6585 | 451 | size_t tsize) |
e8689e63 LW |
452 | { |
453 | u32 retbits = cctl; | |
454 | ||
e8b5e11d | 455 | /* Remove all src, dst and transfer size bits */ |
e8689e63 LW |
456 | retbits &= ~PL080_CONTROL_DWIDTH_MASK; |
457 | retbits &= ~PL080_CONTROL_SWIDTH_MASK; | |
458 | retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK; | |
459 | ||
460 | /* Then set the bits according to the parameters */ | |
461 | switch (srcwidth) { | |
462 | case 1: | |
463 | retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT; | |
464 | break; | |
465 | case 2: | |
466 | retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT; | |
467 | break; | |
468 | case 4: | |
469 | retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT; | |
470 | break; | |
471 | default: | |
472 | BUG(); | |
473 | break; | |
474 | } | |
475 | ||
476 | switch (dstwidth) { | |
477 | case 1: | |
478 | retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT; | |
479 | break; | |
480 | case 2: | |
481 | retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT; | |
482 | break; | |
483 | case 4: | |
484 | retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT; | |
485 | break; | |
486 | default: | |
487 | BUG(); | |
488 | break; | |
489 | } | |
490 | ||
491 | retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT; | |
492 | return retbits; | |
493 | } | |
494 | ||
542361f8 RKAL |
495 | struct pl08x_lli_build_data { |
496 | struct pl08x_txd *txd; | |
542361f8 RKAL |
497 | struct pl08x_bus_data srcbus; |
498 | struct pl08x_bus_data dstbus; | |
499 | size_t remainder; | |
25c94f7f | 500 | u32 lli_bus; |
542361f8 RKAL |
501 | }; |
502 | ||
e8689e63 | 503 | /* |
0532e6fc VK |
504 | * Autoselect a master bus to use for the transfer. Slave will be the chosen as |
505 | * victim in case src & dest are not similarly aligned. i.e. If after aligning | |
506 | * masters address with width requirements of transfer (by sending few byte by | |
507 | * byte data), slave is still not aligned, then its width will be reduced to | |
508 | * BYTE. | |
509 | * - prefers the destination bus if both available | |
510 | * - if fixed address on one bus the other will be chosen | |
e8689e63 | 511 | */ |
542361f8 RKAL |
512 | static void pl08x_choose_master_bus(struct pl08x_lli_build_data *bd, |
513 | struct pl08x_bus_data **mbus, struct pl08x_bus_data **sbus, u32 cctl) | |
e8689e63 LW |
514 | { |
515 | if (!(cctl & PL080_CONTROL_DST_INCR)) { | |
542361f8 RKAL |
516 | *mbus = &bd->srcbus; |
517 | *sbus = &bd->dstbus; | |
e8689e63 | 518 | } else if (!(cctl & PL080_CONTROL_SRC_INCR)) { |
542361f8 RKAL |
519 | *mbus = &bd->dstbus; |
520 | *sbus = &bd->srcbus; | |
e8689e63 | 521 | } else { |
542361f8 RKAL |
522 | if (bd->dstbus.buswidth == 4) { |
523 | *mbus = &bd->dstbus; | |
524 | *sbus = &bd->srcbus; | |
525 | } else if (bd->srcbus.buswidth == 4) { | |
526 | *mbus = &bd->srcbus; | |
527 | *sbus = &bd->dstbus; | |
528 | } else if (bd->dstbus.buswidth == 2) { | |
529 | *mbus = &bd->dstbus; | |
530 | *sbus = &bd->srcbus; | |
531 | } else if (bd->srcbus.buswidth == 2) { | |
532 | *mbus = &bd->srcbus; | |
533 | *sbus = &bd->dstbus; | |
e8689e63 | 534 | } else { |
542361f8 RKAL |
535 | /* bd->srcbus.buswidth == 1 */ |
536 | *mbus = &bd->dstbus; | |
537 | *sbus = &bd->srcbus; | |
e8689e63 LW |
538 | } |
539 | } | |
540 | } | |
541 | ||
542 | /* | |
94ae8522 | 543 | * Fills in one LLI for a certain transfer descriptor and advance the counter |
e8689e63 | 544 | */ |
542361f8 RKAL |
545 | static void pl08x_fill_lli_for_desc(struct pl08x_lli_build_data *bd, |
546 | int num_llis, int len, u32 cctl) | |
e8689e63 | 547 | { |
542361f8 RKAL |
548 | struct pl08x_lli *llis_va = bd->txd->llis_va; |
549 | dma_addr_t llis_bus = bd->txd->llis_bus; | |
e8689e63 LW |
550 | |
551 | BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS); | |
552 | ||
30749cb4 | 553 | llis_va[num_llis].cctl = cctl; |
542361f8 RKAL |
554 | llis_va[num_llis].src = bd->srcbus.addr; |
555 | llis_va[num_llis].dst = bd->dstbus.addr; | |
3e27ee84 VK |
556 | llis_va[num_llis].lli = llis_bus + (num_llis + 1) * |
557 | sizeof(struct pl08x_lli); | |
25c94f7f | 558 | llis_va[num_llis].lli |= bd->lli_bus; |
e8689e63 LW |
559 | |
560 | if (cctl & PL080_CONTROL_SRC_INCR) | |
542361f8 | 561 | bd->srcbus.addr += len; |
e8689e63 | 562 | if (cctl & PL080_CONTROL_DST_INCR) |
542361f8 | 563 | bd->dstbus.addr += len; |
e8689e63 | 564 | |
542361f8 | 565 | BUG_ON(bd->remainder < len); |
cace6585 | 566 | |
542361f8 | 567 | bd->remainder -= len; |
e8689e63 LW |
568 | } |
569 | ||
570 | /* | |
b61be8d7 RKAL |
571 | * Return number of bytes to fill to boundary, or len. |
572 | * This calculation works for any value of addr. | |
e8689e63 | 573 | */ |
cace6585 | 574 | static inline size_t pl08x_pre_boundary(u32 addr, size_t len) |
e8689e63 | 575 | { |
b61be8d7 RKAL |
576 | size_t boundary_len = PL08X_BOUNDARY_SIZE - |
577 | (addr & (PL08X_BOUNDARY_SIZE - 1)); | |
e8689e63 | 578 | |
b61be8d7 | 579 | return min(boundary_len, len); |
e8689e63 LW |
580 | } |
581 | ||
582 | /* | |
583 | * This fills in the table of LLIs for the transfer descriptor | |
584 | * Note that we assume we never have to change the burst sizes | |
585 | * Return 0 for error | |
586 | */ | |
587 | static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x, | |
588 | struct pl08x_txd *txd) | |
589 | { | |
e8689e63 | 590 | struct pl08x_bus_data *mbus, *sbus; |
542361f8 | 591 | struct pl08x_lli_build_data bd; |
e8689e63 LW |
592 | int num_llis = 0; |
593 | u32 cctl; | |
3e27ee84 | 594 | size_t max_bytes_per_lli, total_bytes = 0; |
7cb72ad9 | 595 | struct pl08x_lli *llis_va; |
e8689e63 | 596 | |
3e27ee84 | 597 | txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT, &txd->llis_bus); |
e8689e63 LW |
598 | if (!txd->llis_va) { |
599 | dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__); | |
600 | return 0; | |
601 | } | |
602 | ||
603 | pl08x->pool_ctr++; | |
604 | ||
70b5ed6b RKAL |
605 | /* Get the default CCTL */ |
606 | cctl = txd->cctl; | |
e8689e63 | 607 | |
542361f8 | 608 | bd.txd = txd; |
d7244e9a RKAL |
609 | bd.srcbus.addr = txd->src_addr; |
610 | bd.dstbus.addr = txd->dst_addr; | |
25c94f7f | 611 | bd.lli_bus = (pl08x->lli_buses & PL08X_AHB2) ? PL080_LLI_LM_AHB2 : 0; |
542361f8 | 612 | |
e8689e63 | 613 | /* Find maximum width of the source bus */ |
542361f8 | 614 | bd.srcbus.maxwidth = |
e8689e63 LW |
615 | pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_SWIDTH_MASK) >> |
616 | PL080_CONTROL_SWIDTH_SHIFT); | |
617 | ||
618 | /* Find maximum width of the destination bus */ | |
542361f8 | 619 | bd.dstbus.maxwidth = |
e8689e63 LW |
620 | pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_DWIDTH_MASK) >> |
621 | PL080_CONTROL_DWIDTH_SHIFT); | |
622 | ||
623 | /* Set up the bus widths to the maximum */ | |
542361f8 RKAL |
624 | bd.srcbus.buswidth = bd.srcbus.maxwidth; |
625 | bd.dstbus.buswidth = bd.dstbus.maxwidth; | |
e8689e63 LW |
626 | |
627 | /* | |
628 | * Bytes transferred == tsize * MIN(buswidths), not max(buswidths) | |
629 | */ | |
542361f8 | 630 | max_bytes_per_lli = min(bd.srcbus.buswidth, bd.dstbus.buswidth) * |
e8689e63 | 631 | PL080_CONTROL_TRANSFER_SIZE_MASK; |
e8689e63 LW |
632 | |
633 | /* We need to count this down to zero */ | |
542361f8 | 634 | bd.remainder = txd->len; |
e8689e63 | 635 | |
542361f8 | 636 | pl08x_choose_master_bus(&bd, &mbus, &sbus, cctl); |
e8689e63 | 637 | |
fc74eb79 RKAL |
638 | dev_vdbg(&pl08x->adev->dev, "src=0x%08x%s/%u dst=0x%08x%s/%u len=%zu llimax=%zu\n", |
639 | bd.srcbus.addr, cctl & PL080_CONTROL_SRC_INCR ? "+" : "", | |
640 | bd.srcbus.buswidth, | |
641 | bd.dstbus.addr, cctl & PL080_CONTROL_DST_INCR ? "+" : "", | |
642 | bd.dstbus.buswidth, | |
643 | bd.remainder, max_bytes_per_lli); | |
644 | dev_vdbg(&pl08x->adev->dev, "mbus=%s sbus=%s\n", | |
645 | mbus == &bd.srcbus ? "src" : "dst", | |
646 | sbus == &bd.srcbus ? "src" : "dst"); | |
647 | ||
e8689e63 | 648 | if (txd->len < mbus->buswidth) { |
94ae8522 | 649 | /* Less than a bus width available - send as single bytes */ |
542361f8 | 650 | while (bd.remainder) { |
e8689e63 LW |
651 | dev_vdbg(&pl08x->adev->dev, |
652 | "%s single byte LLIs for a transfer of " | |
9c132992 | 653 | "less than a bus width (remain 0x%08x)\n", |
542361f8 | 654 | __func__, bd.remainder); |
e8689e63 | 655 | cctl = pl08x_cctl_bits(cctl, 1, 1, 1); |
542361f8 | 656 | pl08x_fill_lli_for_desc(&bd, num_llis++, 1, cctl); |
e8689e63 LW |
657 | total_bytes++; |
658 | } | |
659 | } else { | |
94ae8522 | 660 | /* Make one byte LLIs until master bus is aligned */ |
e8689e63 LW |
661 | while ((mbus->addr) % (mbus->buswidth)) { |
662 | dev_vdbg(&pl08x->adev->dev, | |
663 | "%s adjustment lli for less than bus width " | |
9c132992 | 664 | "(remain 0x%08x)\n", |
542361f8 | 665 | __func__, bd.remainder); |
e8689e63 | 666 | cctl = pl08x_cctl_bits(cctl, 1, 1, 1); |
542361f8 | 667 | pl08x_fill_lli_for_desc(&bd, num_llis++, 1, cctl); |
e8689e63 LW |
668 | total_bytes++; |
669 | } | |
670 | ||
671 | /* | |
94ae8522 | 672 | * Master now aligned |
e8689e63 LW |
673 | * - if slave is not then we must set its width down |
674 | */ | |
675 | if (sbus->addr % sbus->buswidth) { | |
676 | dev_dbg(&pl08x->adev->dev, | |
677 | "%s set down bus width to one byte\n", | |
678 | __func__); | |
679 | ||
680 | sbus->buswidth = 1; | |
681 | } | |
682 | ||
683 | /* | |
684 | * Make largest possible LLIs until less than one bus | |
685 | * width left | |
686 | */ | |
542361f8 | 687 | while (bd.remainder > (mbus->buswidth - 1)) { |
cace6585 | 688 | size_t lli_len, target_len, tsize, odd_bytes; |
e8689e63 LW |
689 | |
690 | /* | |
691 | * If enough left try to send max possible, | |
692 | * otherwise try to send the remainder | |
693 | */ | |
542361f8 | 694 | target_len = min(bd.remainder, max_bytes_per_lli); |
e8689e63 LW |
695 | |
696 | /* | |
5f638b4f RKAL |
697 | * Set bus lengths for incrementing buses to the |
698 | * number of bytes which fill to next memory boundary, | |
699 | * limiting on the target length calculated above. | |
e8689e63 LW |
700 | */ |
701 | if (cctl & PL080_CONTROL_SRC_INCR) | |
542361f8 RKAL |
702 | bd.srcbus.fill_bytes = |
703 | pl08x_pre_boundary(bd.srcbus.addr, | |
5f638b4f | 704 | target_len); |
e8689e63 | 705 | else |
542361f8 | 706 | bd.srcbus.fill_bytes = target_len; |
e8689e63 LW |
707 | |
708 | if (cctl & PL080_CONTROL_DST_INCR) | |
542361f8 RKAL |
709 | bd.dstbus.fill_bytes = |
710 | pl08x_pre_boundary(bd.dstbus.addr, | |
5f638b4f | 711 | target_len); |
e8689e63 | 712 | else |
542361f8 | 713 | bd.dstbus.fill_bytes = target_len; |
e8689e63 | 714 | |
5f638b4f | 715 | /* Find the nearest */ |
542361f8 RKAL |
716 | lli_len = min(bd.srcbus.fill_bytes, |
717 | bd.dstbus.fill_bytes); | |
e8689e63 | 718 | |
542361f8 | 719 | BUG_ON(lli_len > bd.remainder); |
e8689e63 LW |
720 | |
721 | if (lli_len <= 0) { | |
722 | dev_err(&pl08x->adev->dev, | |
cace6585 | 723 | "%s lli_len is %zu, <= 0\n", |
e8689e63 LW |
724 | __func__, lli_len); |
725 | return 0; | |
726 | } | |
727 | ||
728 | if (lli_len == target_len) { | |
729 | /* | |
94ae8522 RKAL |
730 | * Can send what we wanted. |
731 | * Maintain alignment | |
e8689e63 LW |
732 | */ |
733 | lli_len = (lli_len/mbus->buswidth) * | |
734 | mbus->buswidth; | |
735 | odd_bytes = 0; | |
736 | } else { | |
737 | /* | |
738 | * So now we know how many bytes to transfer | |
94ae8522 RKAL |
739 | * to get to the nearest boundary. The next |
740 | * LLI will past the boundary. However, we | |
741 | * may be working to a boundary on the slave | |
742 | * bus. We need to ensure the master stays | |
743 | * aligned, and that we are working in | |
744 | * multiples of the bus widths. | |
e8689e63 LW |
745 | */ |
746 | odd_bytes = lli_len % mbus->buswidth; | |
e8689e63 LW |
747 | lli_len -= odd_bytes; |
748 | ||
749 | } | |
750 | ||
751 | if (lli_len) { | |
752 | /* | |
753 | * Check against minimum bus alignment: | |
754 | * Calculate actual transfer size in relation | |
755 | * to bus width an get a maximum remainder of | |
756 | * the smallest bus width - 1 | |
757 | */ | |
758 | /* FIXME: use round_down()? */ | |
759 | tsize = lli_len / min(mbus->buswidth, | |
760 | sbus->buswidth); | |
761 | lli_len = tsize * min(mbus->buswidth, | |
762 | sbus->buswidth); | |
763 | ||
764 | if (target_len != lli_len) { | |
765 | dev_vdbg(&pl08x->adev->dev, | |
cace6585 | 766 | "%s can't send what we want. Desired 0x%08zx, lli of 0x%08zx bytes in txd of 0x%08zx\n", |
e8689e63 LW |
767 | __func__, target_len, lli_len, txd->len); |
768 | } | |
769 | ||
770 | cctl = pl08x_cctl_bits(cctl, | |
542361f8 RKAL |
771 | bd.srcbus.buswidth, |
772 | bd.dstbus.buswidth, | |
e8689e63 LW |
773 | tsize); |
774 | ||
775 | dev_vdbg(&pl08x->adev->dev, | |
cace6585 | 776 | "%s fill lli with single lli chunk of size 0x%08zx (remainder 0x%08zx)\n", |
542361f8 RKAL |
777 | __func__, lli_len, bd.remainder); |
778 | pl08x_fill_lli_for_desc(&bd, num_llis++, | |
779 | lli_len, cctl); | |
e8689e63 LW |
780 | total_bytes += lli_len; |
781 | } | |
782 | ||
e8689e63 LW |
783 | if (odd_bytes) { |
784 | /* | |
94ae8522 RKAL |
785 | * Creep past the boundary, maintaining |
786 | * master alignment | |
e8689e63 LW |
787 | */ |
788 | int j; | |
789 | for (j = 0; (j < mbus->buswidth) | |
542361f8 | 790 | && (bd.remainder); j++) { |
e8689e63 LW |
791 | cctl = pl08x_cctl_bits(cctl, 1, 1, 1); |
792 | dev_vdbg(&pl08x->adev->dev, | |
cace6585 | 793 | "%s align with boundary, single byte (remain 0x%08zx)\n", |
542361f8 RKAL |
794 | __func__, bd.remainder); |
795 | pl08x_fill_lli_for_desc(&bd, | |
796 | num_llis++, 1, cctl); | |
e8689e63 LW |
797 | total_bytes++; |
798 | } | |
799 | } | |
800 | } | |
801 | ||
802 | /* | |
803 | * Send any odd bytes | |
804 | */ | |
542361f8 | 805 | while (bd.remainder) { |
e8689e63 LW |
806 | cctl = pl08x_cctl_bits(cctl, 1, 1, 1); |
807 | dev_vdbg(&pl08x->adev->dev, | |
cace6585 | 808 | "%s align with boundary, single odd byte (remain %zu)\n", |
542361f8 RKAL |
809 | __func__, bd.remainder); |
810 | pl08x_fill_lli_for_desc(&bd, num_llis++, 1, cctl); | |
e8689e63 LW |
811 | total_bytes++; |
812 | } | |
813 | } | |
814 | if (total_bytes != txd->len) { | |
815 | dev_err(&pl08x->adev->dev, | |
cace6585 | 816 | "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n", |
e8689e63 LW |
817 | __func__, total_bytes, txd->len); |
818 | return 0; | |
819 | } | |
820 | ||
821 | if (num_llis >= MAX_NUM_TSFR_LLIS) { | |
822 | dev_err(&pl08x->adev->dev, | |
823 | "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n", | |
824 | __func__, (u32) MAX_NUM_TSFR_LLIS); | |
825 | return 0; | |
826 | } | |
b58b6b5b RKAL |
827 | |
828 | llis_va = txd->llis_va; | |
94ae8522 | 829 | /* The final LLI terminates the LLI. */ |
bfddfb45 | 830 | llis_va[num_llis - 1].lli = 0; |
94ae8522 | 831 | /* The final LLI element shall also fire an interrupt. */ |
b58b6b5b | 832 | llis_va[num_llis - 1].cctl |= PL080_CONTROL_TC_IRQ_EN; |
e8689e63 | 833 | |
e8689e63 LW |
834 | #ifdef VERBOSE_DEBUG |
835 | { | |
836 | int i; | |
837 | ||
fc74eb79 RKAL |
838 | dev_vdbg(&pl08x->adev->dev, |
839 | "%-3s %-9s %-10s %-10s %-10s %s\n", | |
840 | "lli", "", "csrc", "cdst", "clli", "cctl"); | |
e8689e63 LW |
841 | for (i = 0; i < num_llis; i++) { |
842 | dev_vdbg(&pl08x->adev->dev, | |
fc74eb79 RKAL |
843 | "%3d @%p: 0x%08x 0x%08x 0x%08x 0x%08x\n", |
844 | i, &llis_va[i], llis_va[i].src, | |
845 | llis_va[i].dst, llis_va[i].lli, llis_va[i].cctl | |
e8689e63 LW |
846 | ); |
847 | } | |
848 | } | |
849 | #endif | |
850 | ||
851 | return num_llis; | |
852 | } | |
853 | ||
854 | /* You should call this with the struct pl08x lock held */ | |
855 | static void pl08x_free_txd(struct pl08x_driver_data *pl08x, | |
856 | struct pl08x_txd *txd) | |
857 | { | |
e8689e63 | 858 | /* Free the LLI */ |
56b61882 | 859 | dma_pool_free(pl08x->pool, txd->llis_va, txd->llis_bus); |
e8689e63 LW |
860 | |
861 | pl08x->pool_ctr--; | |
862 | ||
863 | kfree(txd); | |
864 | } | |
865 | ||
866 | static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x, | |
867 | struct pl08x_dma_chan *plchan) | |
868 | { | |
869 | struct pl08x_txd *txdi = NULL; | |
870 | struct pl08x_txd *next; | |
871 | ||
15c17232 | 872 | if (!list_empty(&plchan->pend_list)) { |
e8689e63 | 873 | list_for_each_entry_safe(txdi, |
15c17232 | 874 | next, &plchan->pend_list, node) { |
e8689e63 LW |
875 | list_del(&txdi->node); |
876 | pl08x_free_txd(pl08x, txdi); | |
877 | } | |
e8689e63 LW |
878 | } |
879 | } | |
880 | ||
881 | /* | |
882 | * The DMA ENGINE API | |
883 | */ | |
884 | static int pl08x_alloc_chan_resources(struct dma_chan *chan) | |
885 | { | |
886 | return 0; | |
887 | } | |
888 | ||
889 | static void pl08x_free_chan_resources(struct dma_chan *chan) | |
890 | { | |
891 | } | |
892 | ||
893 | /* | |
894 | * This should be called with the channel plchan->lock held | |
895 | */ | |
896 | static int prep_phy_channel(struct pl08x_dma_chan *plchan, | |
897 | struct pl08x_txd *txd) | |
898 | { | |
899 | struct pl08x_driver_data *pl08x = plchan->host; | |
900 | struct pl08x_phy_chan *ch; | |
901 | int ret; | |
902 | ||
903 | /* Check if we already have a channel */ | |
904 | if (plchan->phychan) | |
905 | return 0; | |
906 | ||
907 | ch = pl08x_get_phy_channel(pl08x, plchan); | |
908 | if (!ch) { | |
909 | /* No physical channel available, cope with it */ | |
910 | dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name); | |
911 | return -EBUSY; | |
912 | } | |
913 | ||
914 | /* | |
915 | * OK we have a physical channel: for memcpy() this is all we | |
916 | * need, but for slaves the physical signals may be muxed! | |
917 | * Can the platform allow us to use this channel? | |
918 | */ | |
3e27ee84 | 919 | if (plchan->slave && ch->signal < 0 && pl08x->pd->get_signal) { |
e8689e63 LW |
920 | ret = pl08x->pd->get_signal(plchan); |
921 | if (ret < 0) { | |
922 | dev_dbg(&pl08x->adev->dev, | |
923 | "unable to use physical channel %d for transfer on %s due to platform restrictions\n", | |
924 | ch->id, plchan->name); | |
925 | /* Release physical channel & return */ | |
926 | pl08x_put_phy_channel(pl08x, ch); | |
927 | return -EBUSY; | |
928 | } | |
929 | ch->signal = ret; | |
09b3c323 RKAL |
930 | |
931 | /* Assign the flow control signal to this channel */ | |
932 | if (txd->direction == DMA_TO_DEVICE) | |
933 | txd->ccfg |= ch->signal << PL080_CONFIG_DST_SEL_SHIFT; | |
934 | else if (txd->direction == DMA_FROM_DEVICE) | |
935 | txd->ccfg |= ch->signal << PL080_CONFIG_SRC_SEL_SHIFT; | |
e8689e63 LW |
936 | } |
937 | ||
938 | dev_dbg(&pl08x->adev->dev, "allocated physical channel %d and signal %d for xfer on %s\n", | |
939 | ch->id, | |
940 | ch->signal, | |
941 | plchan->name); | |
942 | ||
8087aacd | 943 | plchan->phychan_hold++; |
e8689e63 LW |
944 | plchan->phychan = ch; |
945 | ||
946 | return 0; | |
947 | } | |
948 | ||
8c8cc2b1 RKAL |
949 | static void release_phy_channel(struct pl08x_dma_chan *plchan) |
950 | { | |
951 | struct pl08x_driver_data *pl08x = plchan->host; | |
952 | ||
953 | if ((plchan->phychan->signal >= 0) && pl08x->pd->put_signal) { | |
954 | pl08x->pd->put_signal(plchan); | |
955 | plchan->phychan->signal = -1; | |
956 | } | |
957 | pl08x_put_phy_channel(pl08x, plchan->phychan); | |
958 | plchan->phychan = NULL; | |
959 | } | |
960 | ||
e8689e63 LW |
961 | static dma_cookie_t pl08x_tx_submit(struct dma_async_tx_descriptor *tx) |
962 | { | |
963 | struct pl08x_dma_chan *plchan = to_pl08x_chan(tx->chan); | |
501e67e8 | 964 | struct pl08x_txd *txd = to_pl08x_txd(tx); |
c370e594 RKAL |
965 | unsigned long flags; |
966 | ||
967 | spin_lock_irqsave(&plchan->lock, flags); | |
e8689e63 | 968 | |
91aa5fad RKAL |
969 | plchan->chan.cookie += 1; |
970 | if (plchan->chan.cookie < 0) | |
971 | plchan->chan.cookie = 1; | |
972 | tx->cookie = plchan->chan.cookie; | |
501e67e8 RKAL |
973 | |
974 | /* Put this onto the pending list */ | |
975 | list_add_tail(&txd->node, &plchan->pend_list); | |
976 | ||
977 | /* | |
978 | * If there was no physical channel available for this memcpy, | |
979 | * stack the request up and indicate that the channel is waiting | |
980 | * for a free physical channel. | |
981 | */ | |
982 | if (!plchan->slave && !plchan->phychan) { | |
983 | /* Do this memcpy whenever there is a channel ready */ | |
984 | plchan->state = PL08X_CHAN_WAITING; | |
985 | plchan->waiting = txd; | |
8087aacd RKAL |
986 | } else { |
987 | plchan->phychan_hold--; | |
501e67e8 RKAL |
988 | } |
989 | ||
c370e594 | 990 | spin_unlock_irqrestore(&plchan->lock, flags); |
e8689e63 LW |
991 | |
992 | return tx->cookie; | |
993 | } | |
994 | ||
995 | static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt( | |
996 | struct dma_chan *chan, unsigned long flags) | |
997 | { | |
998 | struct dma_async_tx_descriptor *retval = NULL; | |
999 | ||
1000 | return retval; | |
1001 | } | |
1002 | ||
1003 | /* | |
94ae8522 RKAL |
1004 | * Code accessing dma_async_is_complete() in a tight loop may give problems. |
1005 | * If slaves are relying on interrupts to signal completion this function | |
1006 | * must not be called with interrupts disabled. | |
e8689e63 | 1007 | */ |
3e27ee84 VK |
1008 | static enum dma_status pl08x_dma_tx_status(struct dma_chan *chan, |
1009 | dma_cookie_t cookie, struct dma_tx_state *txstate) | |
e8689e63 LW |
1010 | { |
1011 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1012 | dma_cookie_t last_used; | |
1013 | dma_cookie_t last_complete; | |
1014 | enum dma_status ret; | |
1015 | u32 bytesleft = 0; | |
1016 | ||
91aa5fad | 1017 | last_used = plchan->chan.cookie; |
e8689e63 LW |
1018 | last_complete = plchan->lc; |
1019 | ||
1020 | ret = dma_async_is_complete(cookie, last_complete, last_used); | |
1021 | if (ret == DMA_SUCCESS) { | |
1022 | dma_set_tx_state(txstate, last_complete, last_used, 0); | |
1023 | return ret; | |
1024 | } | |
1025 | ||
e8689e63 LW |
1026 | /* |
1027 | * This cookie not complete yet | |
1028 | */ | |
91aa5fad | 1029 | last_used = plchan->chan.cookie; |
e8689e63 LW |
1030 | last_complete = plchan->lc; |
1031 | ||
1032 | /* Get number of bytes left in the active transactions and queue */ | |
1033 | bytesleft = pl08x_getbytes_chan(plchan); | |
1034 | ||
1035 | dma_set_tx_state(txstate, last_complete, last_used, | |
1036 | bytesleft); | |
1037 | ||
1038 | if (plchan->state == PL08X_CHAN_PAUSED) | |
1039 | return DMA_PAUSED; | |
1040 | ||
1041 | /* Whether waiting or running, we're in progress */ | |
1042 | return DMA_IN_PROGRESS; | |
1043 | } | |
1044 | ||
1045 | /* PrimeCell DMA extension */ | |
1046 | struct burst_table { | |
760596c6 | 1047 | u32 burstwords; |
e8689e63 LW |
1048 | u32 reg; |
1049 | }; | |
1050 | ||
1051 | static const struct burst_table burst_sizes[] = { | |
1052 | { | |
1053 | .burstwords = 256, | |
760596c6 | 1054 | .reg = PL080_BSIZE_256, |
e8689e63 LW |
1055 | }, |
1056 | { | |
1057 | .burstwords = 128, | |
760596c6 | 1058 | .reg = PL080_BSIZE_128, |
e8689e63 LW |
1059 | }, |
1060 | { | |
1061 | .burstwords = 64, | |
760596c6 | 1062 | .reg = PL080_BSIZE_64, |
e8689e63 LW |
1063 | }, |
1064 | { | |
1065 | .burstwords = 32, | |
760596c6 | 1066 | .reg = PL080_BSIZE_32, |
e8689e63 LW |
1067 | }, |
1068 | { | |
1069 | .burstwords = 16, | |
760596c6 | 1070 | .reg = PL080_BSIZE_16, |
e8689e63 LW |
1071 | }, |
1072 | { | |
1073 | .burstwords = 8, | |
760596c6 | 1074 | .reg = PL080_BSIZE_8, |
e8689e63 LW |
1075 | }, |
1076 | { | |
1077 | .burstwords = 4, | |
760596c6 | 1078 | .reg = PL080_BSIZE_4, |
e8689e63 LW |
1079 | }, |
1080 | { | |
760596c6 RKAL |
1081 | .burstwords = 0, |
1082 | .reg = PL080_BSIZE_1, | |
e8689e63 LW |
1083 | }, |
1084 | }; | |
1085 | ||
121c8476 RKAL |
1086 | /* |
1087 | * Given the source and destination available bus masks, select which | |
1088 | * will be routed to each port. We try to have source and destination | |
1089 | * on separate ports, but always respect the allowable settings. | |
1090 | */ | |
1091 | static u32 pl08x_select_bus(u8 src, u8 dst) | |
1092 | { | |
1093 | u32 cctl = 0; | |
1094 | ||
1095 | if (!(dst & PL08X_AHB1) || ((dst & PL08X_AHB2) && (src & PL08X_AHB1))) | |
1096 | cctl |= PL080_CONTROL_DST_AHB2; | |
1097 | if (!(src & PL08X_AHB1) || ((src & PL08X_AHB2) && !(dst & PL08X_AHB2))) | |
1098 | cctl |= PL080_CONTROL_SRC_AHB2; | |
1099 | ||
1100 | return cctl; | |
1101 | } | |
1102 | ||
f14c426c RKAL |
1103 | static u32 pl08x_cctl(u32 cctl) |
1104 | { | |
1105 | cctl &= ~(PL080_CONTROL_SRC_AHB2 | PL080_CONTROL_DST_AHB2 | | |
1106 | PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR | | |
1107 | PL080_CONTROL_PROT_MASK); | |
1108 | ||
1109 | /* Access the cell in privileged mode, non-bufferable, non-cacheable */ | |
1110 | return cctl | PL080_CONTROL_PROT_SYS; | |
1111 | } | |
1112 | ||
aa88cdaa RKAL |
1113 | static u32 pl08x_width(enum dma_slave_buswidth width) |
1114 | { | |
1115 | switch (width) { | |
1116 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
1117 | return PL080_WIDTH_8BIT; | |
1118 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
1119 | return PL080_WIDTH_16BIT; | |
1120 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
1121 | return PL080_WIDTH_32BIT; | |
f32807f1 VK |
1122 | default: |
1123 | return ~0; | |
aa88cdaa | 1124 | } |
aa88cdaa RKAL |
1125 | } |
1126 | ||
760596c6 RKAL |
1127 | static u32 pl08x_burst(u32 maxburst) |
1128 | { | |
1129 | int i; | |
1130 | ||
1131 | for (i = 0; i < ARRAY_SIZE(burst_sizes); i++) | |
1132 | if (burst_sizes[i].burstwords <= maxburst) | |
1133 | break; | |
1134 | ||
1135 | return burst_sizes[i].reg; | |
1136 | } | |
1137 | ||
f0fd9446 RKAL |
1138 | static int dma_set_runtime_config(struct dma_chan *chan, |
1139 | struct dma_slave_config *config) | |
e8689e63 LW |
1140 | { |
1141 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1142 | struct pl08x_driver_data *pl08x = plchan->host; | |
e8689e63 | 1143 | enum dma_slave_buswidth addr_width; |
760596c6 | 1144 | u32 width, burst, maxburst; |
e8689e63 | 1145 | u32 cctl = 0; |
b7f75865 RKAL |
1146 | |
1147 | if (!plchan->slave) | |
1148 | return -EINVAL; | |
e8689e63 LW |
1149 | |
1150 | /* Transfer direction */ | |
1151 | plchan->runtime_direction = config->direction; | |
1152 | if (config->direction == DMA_TO_DEVICE) { | |
e8689e63 LW |
1153 | addr_width = config->dst_addr_width; |
1154 | maxburst = config->dst_maxburst; | |
1155 | } else if (config->direction == DMA_FROM_DEVICE) { | |
e8689e63 LW |
1156 | addr_width = config->src_addr_width; |
1157 | maxburst = config->src_maxburst; | |
1158 | } else { | |
1159 | dev_err(&pl08x->adev->dev, | |
1160 | "bad runtime_config: alien transfer direction\n"); | |
f0fd9446 | 1161 | return -EINVAL; |
e8689e63 LW |
1162 | } |
1163 | ||
aa88cdaa RKAL |
1164 | width = pl08x_width(addr_width); |
1165 | if (width == ~0) { | |
e8689e63 LW |
1166 | dev_err(&pl08x->adev->dev, |
1167 | "bad runtime_config: alien address width\n"); | |
f0fd9446 | 1168 | return -EINVAL; |
e8689e63 LW |
1169 | } |
1170 | ||
aa88cdaa RKAL |
1171 | cctl |= width << PL080_CONTROL_SWIDTH_SHIFT; |
1172 | cctl |= width << PL080_CONTROL_DWIDTH_SHIFT; | |
1173 | ||
e8689e63 | 1174 | /* |
4440aacf RKAL |
1175 | * If this channel will only request single transfers, set this |
1176 | * down to ONE element. Also select one element if no maxburst | |
1177 | * is specified. | |
e8689e63 | 1178 | */ |
760596c6 RKAL |
1179 | if (plchan->cd->single) |
1180 | maxburst = 1; | |
1181 | ||
1182 | burst = pl08x_burst(maxburst); | |
1183 | cctl |= burst << PL080_CONTROL_SB_SIZE_SHIFT; | |
1184 | cctl |= burst << PL080_CONTROL_DB_SIZE_SHIFT; | |
e8689e63 | 1185 | |
b207b4d0 RKAL |
1186 | if (plchan->runtime_direction == DMA_FROM_DEVICE) { |
1187 | plchan->src_addr = config->src_addr; | |
121c8476 RKAL |
1188 | plchan->src_cctl = pl08x_cctl(cctl) | PL080_CONTROL_DST_INCR | |
1189 | pl08x_select_bus(plchan->cd->periph_buses, | |
1190 | pl08x->mem_buses); | |
b207b4d0 RKAL |
1191 | } else { |
1192 | plchan->dst_addr = config->dst_addr; | |
121c8476 RKAL |
1193 | plchan->dst_cctl = pl08x_cctl(cctl) | PL080_CONTROL_SRC_INCR | |
1194 | pl08x_select_bus(pl08x->mem_buses, | |
1195 | plchan->cd->periph_buses); | |
b207b4d0 | 1196 | } |
f0fd9446 | 1197 | |
e8689e63 LW |
1198 | dev_dbg(&pl08x->adev->dev, |
1199 | "configured channel %s (%s) for %s, data width %d, " | |
4983a04f | 1200 | "maxburst %d words, LE, CCTL=0x%08x\n", |
e8689e63 LW |
1201 | dma_chan_name(chan), plchan->name, |
1202 | (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX", | |
1203 | addr_width, | |
1204 | maxburst, | |
4983a04f | 1205 | cctl); |
f0fd9446 RKAL |
1206 | |
1207 | return 0; | |
e8689e63 LW |
1208 | } |
1209 | ||
1210 | /* | |
1211 | * Slave transactions callback to the slave device to allow | |
1212 | * synchronization of slave DMA signals with the DMAC enable | |
1213 | */ | |
1214 | static void pl08x_issue_pending(struct dma_chan *chan) | |
1215 | { | |
1216 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
e8689e63 LW |
1217 | unsigned long flags; |
1218 | ||
1219 | spin_lock_irqsave(&plchan->lock, flags); | |
9c0bb43b RKAL |
1220 | /* Something is already active, or we're waiting for a channel... */ |
1221 | if (plchan->at || plchan->state == PL08X_CHAN_WAITING) { | |
1222 | spin_unlock_irqrestore(&plchan->lock, flags); | |
e8689e63 | 1223 | return; |
9c0bb43b | 1224 | } |
e8689e63 LW |
1225 | |
1226 | /* Take the first element in the queue and execute it */ | |
15c17232 | 1227 | if (!list_empty(&plchan->pend_list)) { |
e8689e63 LW |
1228 | struct pl08x_txd *next; |
1229 | ||
15c17232 | 1230 | next = list_first_entry(&plchan->pend_list, |
e8689e63 LW |
1231 | struct pl08x_txd, |
1232 | node); | |
1233 | list_del(&next->node); | |
e8689e63 LW |
1234 | plchan->state = PL08X_CHAN_RUNNING; |
1235 | ||
c885bee4 | 1236 | pl08x_start_txd(plchan, next); |
e8689e63 LW |
1237 | } |
1238 | ||
1239 | spin_unlock_irqrestore(&plchan->lock, flags); | |
1240 | } | |
1241 | ||
1242 | static int pl08x_prep_channel_resources(struct pl08x_dma_chan *plchan, | |
1243 | struct pl08x_txd *txd) | |
1244 | { | |
e8689e63 | 1245 | struct pl08x_driver_data *pl08x = plchan->host; |
c370e594 RKAL |
1246 | unsigned long flags; |
1247 | int num_llis, ret; | |
e8689e63 LW |
1248 | |
1249 | num_llis = pl08x_fill_llis_for_desc(pl08x, txd); | |
dafa7317 RKAL |
1250 | if (!num_llis) { |
1251 | kfree(txd); | |
e8689e63 | 1252 | return -EINVAL; |
dafa7317 | 1253 | } |
e8689e63 | 1254 | |
c370e594 | 1255 | spin_lock_irqsave(&plchan->lock, flags); |
e8689e63 | 1256 | |
e8689e63 LW |
1257 | /* |
1258 | * See if we already have a physical channel allocated, | |
1259 | * else this is the time to try to get one. | |
1260 | */ | |
1261 | ret = prep_phy_channel(plchan, txd); | |
1262 | if (ret) { | |
1263 | /* | |
501e67e8 RKAL |
1264 | * No physical channel was available. |
1265 | * | |
1266 | * memcpy transfers can be sorted out at submission time. | |
1267 | * | |
1268 | * Slave transfers may have been denied due to platform | |
1269 | * channel muxing restrictions. Since there is no guarantee | |
1270 | * that this will ever be resolved, and the signal must be | |
1271 | * acquired AFTER acquiring the physical channel, we will let | |
1272 | * them be NACK:ed with -EBUSY here. The drivers can retry | |
1273 | * the prep() call if they are eager on doing this using DMA. | |
e8689e63 LW |
1274 | */ |
1275 | if (plchan->slave) { | |
1276 | pl08x_free_txd_list(pl08x, plchan); | |
501e67e8 | 1277 | pl08x_free_txd(pl08x, txd); |
c370e594 | 1278 | spin_unlock_irqrestore(&plchan->lock, flags); |
e8689e63 LW |
1279 | return -EBUSY; |
1280 | } | |
e8689e63 LW |
1281 | } else |
1282 | /* | |
94ae8522 RKAL |
1283 | * Else we're all set, paused and ready to roll, status |
1284 | * will switch to PL08X_CHAN_RUNNING when we call | |
1285 | * issue_pending(). If there is something running on the | |
1286 | * channel already we don't change its state. | |
e8689e63 LW |
1287 | */ |
1288 | if (plchan->state == PL08X_CHAN_IDLE) | |
1289 | plchan->state = PL08X_CHAN_PAUSED; | |
1290 | ||
c370e594 | 1291 | spin_unlock_irqrestore(&plchan->lock, flags); |
e8689e63 LW |
1292 | |
1293 | return 0; | |
1294 | } | |
1295 | ||
c0428794 RKAL |
1296 | static struct pl08x_txd *pl08x_get_txd(struct pl08x_dma_chan *plchan, |
1297 | unsigned long flags) | |
ac3cd20d | 1298 | { |
b201c111 | 1299 | struct pl08x_txd *txd = kzalloc(sizeof(*txd), GFP_NOWAIT); |
ac3cd20d RKAL |
1300 | |
1301 | if (txd) { | |
1302 | dma_async_tx_descriptor_init(&txd->tx, &plchan->chan); | |
c0428794 | 1303 | txd->tx.flags = flags; |
ac3cd20d RKAL |
1304 | txd->tx.tx_submit = pl08x_tx_submit; |
1305 | INIT_LIST_HEAD(&txd->node); | |
4983a04f RKAL |
1306 | |
1307 | /* Always enable error and terminal interrupts */ | |
1308 | txd->ccfg = PL080_CONFIG_ERR_IRQ_MASK | | |
1309 | PL080_CONFIG_TC_IRQ_MASK; | |
ac3cd20d RKAL |
1310 | } |
1311 | return txd; | |
1312 | } | |
1313 | ||
e8689e63 LW |
1314 | /* |
1315 | * Initialize a descriptor to be used by memcpy submit | |
1316 | */ | |
1317 | static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy( | |
1318 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
1319 | size_t len, unsigned long flags) | |
1320 | { | |
1321 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1322 | struct pl08x_driver_data *pl08x = plchan->host; | |
1323 | struct pl08x_txd *txd; | |
1324 | int ret; | |
1325 | ||
c0428794 | 1326 | txd = pl08x_get_txd(plchan, flags); |
e8689e63 LW |
1327 | if (!txd) { |
1328 | dev_err(&pl08x->adev->dev, | |
1329 | "%s no memory for descriptor\n", __func__); | |
1330 | return NULL; | |
1331 | } | |
1332 | ||
e8689e63 | 1333 | txd->direction = DMA_NONE; |
d7244e9a RKAL |
1334 | txd->src_addr = src; |
1335 | txd->dst_addr = dest; | |
c7da9a56 | 1336 | txd->len = len; |
e8689e63 LW |
1337 | |
1338 | /* Set platform data for m2m */ | |
4983a04f | 1339 | txd->ccfg |= PL080_FLOW_MEM2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT; |
c7da9a56 RKAL |
1340 | txd->cctl = pl08x->pd->memcpy_channel.cctl & |
1341 | ~(PL080_CONTROL_DST_AHB2 | PL080_CONTROL_SRC_AHB2); | |
4983a04f | 1342 | |
e8689e63 | 1343 | /* Both to be incremented or the code will break */ |
70b5ed6b | 1344 | txd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR; |
c7da9a56 | 1345 | |
c7da9a56 | 1346 | if (pl08x->vd->dualmaster) |
121c8476 RKAL |
1347 | txd->cctl |= pl08x_select_bus(pl08x->mem_buses, |
1348 | pl08x->mem_buses); | |
e8689e63 | 1349 | |
e8689e63 LW |
1350 | ret = pl08x_prep_channel_resources(plchan, txd); |
1351 | if (ret) | |
1352 | return NULL; | |
e8689e63 LW |
1353 | |
1354 | return &txd->tx; | |
1355 | } | |
1356 | ||
3e2a037c | 1357 | static struct dma_async_tx_descriptor *pl08x_prep_slave_sg( |
e8689e63 LW |
1358 | struct dma_chan *chan, struct scatterlist *sgl, |
1359 | unsigned int sg_len, enum dma_data_direction direction, | |
1360 | unsigned long flags) | |
1361 | { | |
1362 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1363 | struct pl08x_driver_data *pl08x = plchan->host; | |
1364 | struct pl08x_txd *txd; | |
1365 | int ret; | |
1366 | ||
1367 | /* | |
1368 | * Current implementation ASSUMES only one sg | |
1369 | */ | |
1370 | if (sg_len != 1) { | |
1371 | dev_err(&pl08x->adev->dev, "%s prepared too long sglist\n", | |
1372 | __func__); | |
1373 | BUG(); | |
1374 | } | |
1375 | ||
1376 | dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n", | |
1377 | __func__, sgl->length, plchan->name); | |
1378 | ||
c0428794 | 1379 | txd = pl08x_get_txd(plchan, flags); |
e8689e63 LW |
1380 | if (!txd) { |
1381 | dev_err(&pl08x->adev->dev, "%s no txd\n", __func__); | |
1382 | return NULL; | |
1383 | } | |
1384 | ||
e8689e63 LW |
1385 | if (direction != plchan->runtime_direction) |
1386 | dev_err(&pl08x->adev->dev, "%s DMA setup does not match " | |
1387 | "the direction configured for the PrimeCell\n", | |
1388 | __func__); | |
1389 | ||
1390 | /* | |
1391 | * Set up addresses, the PrimeCell configured address | |
1392 | * will take precedence since this may configure the | |
1393 | * channel target address dynamically at runtime. | |
1394 | */ | |
1395 | txd->direction = direction; | |
c7da9a56 RKAL |
1396 | txd->len = sgl->length; |
1397 | ||
e8689e63 | 1398 | if (direction == DMA_TO_DEVICE) { |
4983a04f | 1399 | txd->ccfg |= PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT; |
121c8476 | 1400 | txd->cctl = plchan->dst_cctl; |
d7244e9a | 1401 | txd->src_addr = sgl->dma_address; |
b207b4d0 | 1402 | txd->dst_addr = plchan->dst_addr; |
e8689e63 | 1403 | } else if (direction == DMA_FROM_DEVICE) { |
4983a04f | 1404 | txd->ccfg |= PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT; |
121c8476 | 1405 | txd->cctl = plchan->src_cctl; |
b207b4d0 | 1406 | txd->src_addr = plchan->src_addr; |
d7244e9a | 1407 | txd->dst_addr = sgl->dma_address; |
e8689e63 LW |
1408 | } else { |
1409 | dev_err(&pl08x->adev->dev, | |
1410 | "%s direction unsupported\n", __func__); | |
1411 | return NULL; | |
1412 | } | |
e8689e63 LW |
1413 | |
1414 | ret = pl08x_prep_channel_resources(plchan, txd); | |
1415 | if (ret) | |
1416 | return NULL; | |
e8689e63 LW |
1417 | |
1418 | return &txd->tx; | |
1419 | } | |
1420 | ||
1421 | static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, | |
1422 | unsigned long arg) | |
1423 | { | |
1424 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1425 | struct pl08x_driver_data *pl08x = plchan->host; | |
1426 | unsigned long flags; | |
1427 | int ret = 0; | |
1428 | ||
1429 | /* Controls applicable to inactive channels */ | |
1430 | if (cmd == DMA_SLAVE_CONFIG) { | |
f0fd9446 RKAL |
1431 | return dma_set_runtime_config(chan, |
1432 | (struct dma_slave_config *)arg); | |
e8689e63 LW |
1433 | } |
1434 | ||
1435 | /* | |
1436 | * Anything succeeds on channels with no physical allocation and | |
1437 | * no queued transfers. | |
1438 | */ | |
1439 | spin_lock_irqsave(&plchan->lock, flags); | |
1440 | if (!plchan->phychan && !plchan->at) { | |
1441 | spin_unlock_irqrestore(&plchan->lock, flags); | |
1442 | return 0; | |
1443 | } | |
1444 | ||
1445 | switch (cmd) { | |
1446 | case DMA_TERMINATE_ALL: | |
1447 | plchan->state = PL08X_CHAN_IDLE; | |
1448 | ||
1449 | if (plchan->phychan) { | |
fb526210 | 1450 | pl08x_terminate_phy_chan(pl08x, plchan->phychan); |
e8689e63 LW |
1451 | |
1452 | /* | |
1453 | * Mark physical channel as free and free any slave | |
1454 | * signal | |
1455 | */ | |
8c8cc2b1 | 1456 | release_phy_channel(plchan); |
e8689e63 | 1457 | } |
e8689e63 LW |
1458 | /* Dequeue jobs and free LLIs */ |
1459 | if (plchan->at) { | |
1460 | pl08x_free_txd(pl08x, plchan->at); | |
1461 | plchan->at = NULL; | |
1462 | } | |
1463 | /* Dequeue jobs not yet fired as well */ | |
1464 | pl08x_free_txd_list(pl08x, plchan); | |
1465 | break; | |
1466 | case DMA_PAUSE: | |
1467 | pl08x_pause_phy_chan(plchan->phychan); | |
1468 | plchan->state = PL08X_CHAN_PAUSED; | |
1469 | break; | |
1470 | case DMA_RESUME: | |
1471 | pl08x_resume_phy_chan(plchan->phychan); | |
1472 | plchan->state = PL08X_CHAN_RUNNING; | |
1473 | break; | |
1474 | default: | |
1475 | /* Unknown command */ | |
1476 | ret = -ENXIO; | |
1477 | break; | |
1478 | } | |
1479 | ||
1480 | spin_unlock_irqrestore(&plchan->lock, flags); | |
1481 | ||
1482 | return ret; | |
1483 | } | |
1484 | ||
1485 | bool pl08x_filter_id(struct dma_chan *chan, void *chan_id) | |
1486 | { | |
1487 | struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); | |
1488 | char *name = chan_id; | |
1489 | ||
1490 | /* Check that the channel is not taken! */ | |
1491 | if (!strcmp(plchan->name, name)) | |
1492 | return true; | |
1493 | ||
1494 | return false; | |
1495 | } | |
1496 | ||
1497 | /* | |
1498 | * Just check that the device is there and active | |
94ae8522 RKAL |
1499 | * TODO: turn this bit on/off depending on the number of physical channels |
1500 | * actually used, if it is zero... well shut it off. That will save some | |
1501 | * power. Cut the clock at the same time. | |
e8689e63 LW |
1502 | */ |
1503 | static void pl08x_ensure_on(struct pl08x_driver_data *pl08x) | |
1504 | { | |
1505 | u32 val; | |
1506 | ||
1507 | val = readl(pl08x->base + PL080_CONFIG); | |
1508 | val &= ~(PL080_CONFIG_M2_BE | PL080_CONFIG_M1_BE | PL080_CONFIG_ENABLE); | |
e8b5e11d | 1509 | /* We implicitly clear bit 1 and that means little-endian mode */ |
e8689e63 LW |
1510 | val |= PL080_CONFIG_ENABLE; |
1511 | writel(val, pl08x->base + PL080_CONFIG); | |
1512 | } | |
1513 | ||
3d992e1a RKAL |
1514 | static void pl08x_unmap_buffers(struct pl08x_txd *txd) |
1515 | { | |
1516 | struct device *dev = txd->tx.chan->device->dev; | |
1517 | ||
1518 | if (!(txd->tx.flags & DMA_COMPL_SKIP_SRC_UNMAP)) { | |
1519 | if (txd->tx.flags & DMA_COMPL_SRC_UNMAP_SINGLE) | |
1520 | dma_unmap_single(dev, txd->src_addr, txd->len, | |
1521 | DMA_TO_DEVICE); | |
1522 | else | |
1523 | dma_unmap_page(dev, txd->src_addr, txd->len, | |
1524 | DMA_TO_DEVICE); | |
1525 | } | |
1526 | if (!(txd->tx.flags & DMA_COMPL_SKIP_DEST_UNMAP)) { | |
1527 | if (txd->tx.flags & DMA_COMPL_DEST_UNMAP_SINGLE) | |
1528 | dma_unmap_single(dev, txd->dst_addr, txd->len, | |
1529 | DMA_FROM_DEVICE); | |
1530 | else | |
1531 | dma_unmap_page(dev, txd->dst_addr, txd->len, | |
1532 | DMA_FROM_DEVICE); | |
1533 | } | |
1534 | } | |
1535 | ||
e8689e63 LW |
1536 | static void pl08x_tasklet(unsigned long data) |
1537 | { | |
1538 | struct pl08x_dma_chan *plchan = (struct pl08x_dma_chan *) data; | |
e8689e63 | 1539 | struct pl08x_driver_data *pl08x = plchan->host; |
858c21c0 | 1540 | struct pl08x_txd *txd; |
bf072af4 | 1541 | unsigned long flags; |
e8689e63 | 1542 | |
bf072af4 | 1543 | spin_lock_irqsave(&plchan->lock, flags); |
e8689e63 | 1544 | |
858c21c0 RKAL |
1545 | txd = plchan->at; |
1546 | plchan->at = NULL; | |
e8689e63 | 1547 | |
858c21c0 | 1548 | if (txd) { |
94ae8522 | 1549 | /* Update last completed */ |
858c21c0 | 1550 | plchan->lc = txd->tx.cookie; |
e8689e63 | 1551 | } |
8087aacd | 1552 | |
94ae8522 | 1553 | /* If a new descriptor is queued, set it up plchan->at is NULL here */ |
15c17232 | 1554 | if (!list_empty(&plchan->pend_list)) { |
e8689e63 LW |
1555 | struct pl08x_txd *next; |
1556 | ||
15c17232 | 1557 | next = list_first_entry(&plchan->pend_list, |
e8689e63 LW |
1558 | struct pl08x_txd, |
1559 | node); | |
1560 | list_del(&next->node); | |
c885bee4 RKAL |
1561 | |
1562 | pl08x_start_txd(plchan, next); | |
8087aacd RKAL |
1563 | } else if (plchan->phychan_hold) { |
1564 | /* | |
1565 | * This channel is still in use - we have a new txd being | |
1566 | * prepared and will soon be queued. Don't give up the | |
1567 | * physical channel. | |
1568 | */ | |
e8689e63 LW |
1569 | } else { |
1570 | struct pl08x_dma_chan *waiting = NULL; | |
1571 | ||
1572 | /* | |
1573 | * No more jobs, so free up the physical channel | |
1574 | * Free any allocated signal on slave transfers too | |
1575 | */ | |
8c8cc2b1 | 1576 | release_phy_channel(plchan); |
e8689e63 LW |
1577 | plchan->state = PL08X_CHAN_IDLE; |
1578 | ||
1579 | /* | |
94ae8522 RKAL |
1580 | * And NOW before anyone else can grab that free:d up |
1581 | * physical channel, see if there is some memcpy pending | |
1582 | * that seriously needs to start because of being stacked | |
1583 | * up while we were choking the physical channels with data. | |
e8689e63 LW |
1584 | */ |
1585 | list_for_each_entry(waiting, &pl08x->memcpy.channels, | |
1586 | chan.device_node) { | |
3e27ee84 VK |
1587 | if (waiting->state == PL08X_CHAN_WAITING && |
1588 | waiting->waiting != NULL) { | |
e8689e63 LW |
1589 | int ret; |
1590 | ||
1591 | /* This should REALLY not fail now */ | |
1592 | ret = prep_phy_channel(waiting, | |
1593 | waiting->waiting); | |
1594 | BUG_ON(ret); | |
8087aacd | 1595 | waiting->phychan_hold--; |
e8689e63 LW |
1596 | waiting->state = PL08X_CHAN_RUNNING; |
1597 | waiting->waiting = NULL; | |
1598 | pl08x_issue_pending(&waiting->chan); | |
1599 | break; | |
1600 | } | |
1601 | } | |
1602 | } | |
1603 | ||
bf072af4 | 1604 | spin_unlock_irqrestore(&plchan->lock, flags); |
858c21c0 | 1605 | |
3d992e1a RKAL |
1606 | if (txd) { |
1607 | dma_async_tx_callback callback = txd->tx.callback; | |
1608 | void *callback_param = txd->tx.callback_param; | |
1609 | ||
1610 | /* Don't try to unmap buffers on slave channels */ | |
1611 | if (!plchan->slave) | |
1612 | pl08x_unmap_buffers(txd); | |
1613 | ||
1614 | /* Free the descriptor */ | |
1615 | spin_lock_irqsave(&plchan->lock, flags); | |
1616 | pl08x_free_txd(pl08x, txd); | |
1617 | spin_unlock_irqrestore(&plchan->lock, flags); | |
1618 | ||
1619 | /* Callback to signal completion */ | |
1620 | if (callback) | |
1621 | callback(callback_param); | |
1622 | } | |
e8689e63 LW |
1623 | } |
1624 | ||
1625 | static irqreturn_t pl08x_irq(int irq, void *dev) | |
1626 | { | |
1627 | struct pl08x_driver_data *pl08x = dev; | |
1628 | u32 mask = 0; | |
1629 | u32 val; | |
1630 | int i; | |
1631 | ||
1632 | val = readl(pl08x->base + PL080_ERR_STATUS); | |
1633 | if (val) { | |
94ae8522 | 1634 | /* An error interrupt (on one or more channels) */ |
e8689e63 LW |
1635 | dev_err(&pl08x->adev->dev, |
1636 | "%s error interrupt, register value 0x%08x\n", | |
1637 | __func__, val); | |
1638 | /* | |
1639 | * Simply clear ALL PL08X error interrupts, | |
1640 | * regardless of channel and cause | |
1641 | * FIXME: should be 0x00000003 on PL081 really. | |
1642 | */ | |
1643 | writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR); | |
1644 | } | |
1645 | val = readl(pl08x->base + PL080_INT_STATUS); | |
1646 | for (i = 0; i < pl08x->vd->channels; i++) { | |
1647 | if ((1 << i) & val) { | |
1648 | /* Locate physical channel */ | |
1649 | struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i]; | |
1650 | struct pl08x_dma_chan *plchan = phychan->serving; | |
1651 | ||
1652 | /* Schedule tasklet on this channel */ | |
1653 | tasklet_schedule(&plchan->tasklet); | |
1654 | ||
1655 | mask |= (1 << i); | |
1656 | } | |
1657 | } | |
94ae8522 | 1658 | /* Clear only the terminal interrupts on channels we processed */ |
e8689e63 LW |
1659 | writel(mask, pl08x->base + PL080_TC_CLEAR); |
1660 | ||
1661 | return mask ? IRQ_HANDLED : IRQ_NONE; | |
1662 | } | |
1663 | ||
121c8476 RKAL |
1664 | static void pl08x_dma_slave_init(struct pl08x_dma_chan *chan) |
1665 | { | |
1666 | u32 cctl = pl08x_cctl(chan->cd->cctl); | |
1667 | ||
1668 | chan->slave = true; | |
1669 | chan->name = chan->cd->bus_id; | |
1670 | chan->src_addr = chan->cd->addr; | |
1671 | chan->dst_addr = chan->cd->addr; | |
1672 | chan->src_cctl = cctl | PL080_CONTROL_DST_INCR | | |
1673 | pl08x_select_bus(chan->cd->periph_buses, chan->host->mem_buses); | |
1674 | chan->dst_cctl = cctl | PL080_CONTROL_SRC_INCR | | |
1675 | pl08x_select_bus(chan->host->mem_buses, chan->cd->periph_buses); | |
1676 | } | |
1677 | ||
e8689e63 LW |
1678 | /* |
1679 | * Initialise the DMAC memcpy/slave channels. | |
1680 | * Make a local wrapper to hold required data | |
1681 | */ | |
1682 | static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x, | |
3e27ee84 | 1683 | struct dma_device *dmadev, unsigned int channels, bool slave) |
e8689e63 LW |
1684 | { |
1685 | struct pl08x_dma_chan *chan; | |
1686 | int i; | |
1687 | ||
1688 | INIT_LIST_HEAD(&dmadev->channels); | |
94ae8522 | 1689 | |
e8689e63 LW |
1690 | /* |
1691 | * Register as many many memcpy as we have physical channels, | |
1692 | * we won't always be able to use all but the code will have | |
1693 | * to cope with that situation. | |
1694 | */ | |
1695 | for (i = 0; i < channels; i++) { | |
b201c111 | 1696 | chan = kzalloc(sizeof(*chan), GFP_KERNEL); |
e8689e63 LW |
1697 | if (!chan) { |
1698 | dev_err(&pl08x->adev->dev, | |
1699 | "%s no memory for channel\n", __func__); | |
1700 | return -ENOMEM; | |
1701 | } | |
1702 | ||
1703 | chan->host = pl08x; | |
1704 | chan->state = PL08X_CHAN_IDLE; | |
1705 | ||
1706 | if (slave) { | |
e8689e63 | 1707 | chan->cd = &pl08x->pd->slave_channels[i]; |
121c8476 | 1708 | pl08x_dma_slave_init(chan); |
e8689e63 LW |
1709 | } else { |
1710 | chan->cd = &pl08x->pd->memcpy_channel; | |
1711 | chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i); | |
1712 | if (!chan->name) { | |
1713 | kfree(chan); | |
1714 | return -ENOMEM; | |
1715 | } | |
1716 | } | |
b58b6b5b RKAL |
1717 | if (chan->cd->circular_buffer) { |
1718 | dev_err(&pl08x->adev->dev, | |
1719 | "channel %s: circular buffers not supported\n", | |
1720 | chan->name); | |
1721 | kfree(chan); | |
1722 | continue; | |
1723 | } | |
175a5e61 | 1724 | dev_dbg(&pl08x->adev->dev, |
e8689e63 LW |
1725 | "initialize virtual channel \"%s\"\n", |
1726 | chan->name); | |
1727 | ||
1728 | chan->chan.device = dmadev; | |
91aa5fad RKAL |
1729 | chan->chan.cookie = 0; |
1730 | chan->lc = 0; | |
e8689e63 LW |
1731 | |
1732 | spin_lock_init(&chan->lock); | |
15c17232 | 1733 | INIT_LIST_HEAD(&chan->pend_list); |
e8689e63 LW |
1734 | tasklet_init(&chan->tasklet, pl08x_tasklet, |
1735 | (unsigned long) chan); | |
1736 | ||
1737 | list_add_tail(&chan->chan.device_node, &dmadev->channels); | |
1738 | } | |
1739 | dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n", | |
1740 | i, slave ? "slave" : "memcpy"); | |
1741 | return i; | |
1742 | } | |
1743 | ||
1744 | static void pl08x_free_virtual_channels(struct dma_device *dmadev) | |
1745 | { | |
1746 | struct pl08x_dma_chan *chan = NULL; | |
1747 | struct pl08x_dma_chan *next; | |
1748 | ||
1749 | list_for_each_entry_safe(chan, | |
1750 | next, &dmadev->channels, chan.device_node) { | |
1751 | list_del(&chan->chan.device_node); | |
1752 | kfree(chan); | |
1753 | } | |
1754 | } | |
1755 | ||
1756 | #ifdef CONFIG_DEBUG_FS | |
1757 | static const char *pl08x_state_str(enum pl08x_dma_chan_state state) | |
1758 | { | |
1759 | switch (state) { | |
1760 | case PL08X_CHAN_IDLE: | |
1761 | return "idle"; | |
1762 | case PL08X_CHAN_RUNNING: | |
1763 | return "running"; | |
1764 | case PL08X_CHAN_PAUSED: | |
1765 | return "paused"; | |
1766 | case PL08X_CHAN_WAITING: | |
1767 | return "waiting"; | |
1768 | default: | |
1769 | break; | |
1770 | } | |
1771 | return "UNKNOWN STATE"; | |
1772 | } | |
1773 | ||
1774 | static int pl08x_debugfs_show(struct seq_file *s, void *data) | |
1775 | { | |
1776 | struct pl08x_driver_data *pl08x = s->private; | |
1777 | struct pl08x_dma_chan *chan; | |
1778 | struct pl08x_phy_chan *ch; | |
1779 | unsigned long flags; | |
1780 | int i; | |
1781 | ||
1782 | seq_printf(s, "PL08x physical channels:\n"); | |
1783 | seq_printf(s, "CHANNEL:\tUSER:\n"); | |
1784 | seq_printf(s, "--------\t-----\n"); | |
1785 | for (i = 0; i < pl08x->vd->channels; i++) { | |
1786 | struct pl08x_dma_chan *virt_chan; | |
1787 | ||
1788 | ch = &pl08x->phy_chans[i]; | |
1789 | ||
1790 | spin_lock_irqsave(&ch->lock, flags); | |
1791 | virt_chan = ch->serving; | |
1792 | ||
1793 | seq_printf(s, "%d\t\t%s\n", | |
1794 | ch->id, virt_chan ? virt_chan->name : "(none)"); | |
1795 | ||
1796 | spin_unlock_irqrestore(&ch->lock, flags); | |
1797 | } | |
1798 | ||
1799 | seq_printf(s, "\nPL08x virtual memcpy channels:\n"); | |
1800 | seq_printf(s, "CHANNEL:\tSTATE:\n"); | |
1801 | seq_printf(s, "--------\t------\n"); | |
1802 | list_for_each_entry(chan, &pl08x->memcpy.channels, chan.device_node) { | |
3e2a037c | 1803 | seq_printf(s, "%s\t\t%s\n", chan->name, |
e8689e63 LW |
1804 | pl08x_state_str(chan->state)); |
1805 | } | |
1806 | ||
1807 | seq_printf(s, "\nPL08x virtual slave channels:\n"); | |
1808 | seq_printf(s, "CHANNEL:\tSTATE:\n"); | |
1809 | seq_printf(s, "--------\t------\n"); | |
1810 | list_for_each_entry(chan, &pl08x->slave.channels, chan.device_node) { | |
3e2a037c | 1811 | seq_printf(s, "%s\t\t%s\n", chan->name, |
e8689e63 LW |
1812 | pl08x_state_str(chan->state)); |
1813 | } | |
1814 | ||
1815 | return 0; | |
1816 | } | |
1817 | ||
1818 | static int pl08x_debugfs_open(struct inode *inode, struct file *file) | |
1819 | { | |
1820 | return single_open(file, pl08x_debugfs_show, inode->i_private); | |
1821 | } | |
1822 | ||
1823 | static const struct file_operations pl08x_debugfs_operations = { | |
1824 | .open = pl08x_debugfs_open, | |
1825 | .read = seq_read, | |
1826 | .llseek = seq_lseek, | |
1827 | .release = single_release, | |
1828 | }; | |
1829 | ||
1830 | static void init_pl08x_debugfs(struct pl08x_driver_data *pl08x) | |
1831 | { | |
1832 | /* Expose a simple debugfs interface to view all clocks */ | |
3e27ee84 VK |
1833 | (void) debugfs_create_file(dev_name(&pl08x->adev->dev), |
1834 | S_IFREG | S_IRUGO, NULL, pl08x, | |
1835 | &pl08x_debugfs_operations); | |
e8689e63 LW |
1836 | } |
1837 | ||
1838 | #else | |
1839 | static inline void init_pl08x_debugfs(struct pl08x_driver_data *pl08x) | |
1840 | { | |
1841 | } | |
1842 | #endif | |
1843 | ||
aa25afad | 1844 | static int pl08x_probe(struct amba_device *adev, const struct amba_id *id) |
e8689e63 LW |
1845 | { |
1846 | struct pl08x_driver_data *pl08x; | |
f96ca9ec | 1847 | const struct vendor_data *vd = id->data; |
e8689e63 LW |
1848 | int ret = 0; |
1849 | int i; | |
1850 | ||
1851 | ret = amba_request_regions(adev, NULL); | |
1852 | if (ret) | |
1853 | return ret; | |
1854 | ||
1855 | /* Create the driver state holder */ | |
b201c111 | 1856 | pl08x = kzalloc(sizeof(*pl08x), GFP_KERNEL); |
e8689e63 LW |
1857 | if (!pl08x) { |
1858 | ret = -ENOMEM; | |
1859 | goto out_no_pl08x; | |
1860 | } | |
1861 | ||
b7b6018b VK |
1862 | pm_runtime_set_active(&adev->dev); |
1863 | pm_runtime_enable(&adev->dev); | |
1864 | ||
e8689e63 LW |
1865 | /* Initialize memcpy engine */ |
1866 | dma_cap_set(DMA_MEMCPY, pl08x->memcpy.cap_mask); | |
1867 | pl08x->memcpy.dev = &adev->dev; | |
1868 | pl08x->memcpy.device_alloc_chan_resources = pl08x_alloc_chan_resources; | |
1869 | pl08x->memcpy.device_free_chan_resources = pl08x_free_chan_resources; | |
1870 | pl08x->memcpy.device_prep_dma_memcpy = pl08x_prep_dma_memcpy; | |
1871 | pl08x->memcpy.device_prep_dma_interrupt = pl08x_prep_dma_interrupt; | |
1872 | pl08x->memcpy.device_tx_status = pl08x_dma_tx_status; | |
1873 | pl08x->memcpy.device_issue_pending = pl08x_issue_pending; | |
1874 | pl08x->memcpy.device_control = pl08x_control; | |
1875 | ||
1876 | /* Initialize slave engine */ | |
1877 | dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask); | |
1878 | pl08x->slave.dev = &adev->dev; | |
1879 | pl08x->slave.device_alloc_chan_resources = pl08x_alloc_chan_resources; | |
1880 | pl08x->slave.device_free_chan_resources = pl08x_free_chan_resources; | |
1881 | pl08x->slave.device_prep_dma_interrupt = pl08x_prep_dma_interrupt; | |
1882 | pl08x->slave.device_tx_status = pl08x_dma_tx_status; | |
1883 | pl08x->slave.device_issue_pending = pl08x_issue_pending; | |
1884 | pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg; | |
1885 | pl08x->slave.device_control = pl08x_control; | |
1886 | ||
1887 | /* Get the platform data */ | |
1888 | pl08x->pd = dev_get_platdata(&adev->dev); | |
1889 | if (!pl08x->pd) { | |
1890 | dev_err(&adev->dev, "no platform data supplied\n"); | |
1891 | goto out_no_platdata; | |
1892 | } | |
1893 | ||
1894 | /* Assign useful pointers to the driver state */ | |
1895 | pl08x->adev = adev; | |
1896 | pl08x->vd = vd; | |
1897 | ||
30749cb4 RKAL |
1898 | /* By default, AHB1 only. If dualmaster, from platform */ |
1899 | pl08x->lli_buses = PL08X_AHB1; | |
1900 | pl08x->mem_buses = PL08X_AHB1; | |
1901 | if (pl08x->vd->dualmaster) { | |
1902 | pl08x->lli_buses = pl08x->pd->lli_buses; | |
1903 | pl08x->mem_buses = pl08x->pd->mem_buses; | |
1904 | } | |
1905 | ||
e8689e63 LW |
1906 | /* A DMA memory pool for LLIs, align on 1-byte boundary */ |
1907 | pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev, | |
1908 | PL08X_LLI_TSFR_SIZE, PL08X_ALIGN, 0); | |
1909 | if (!pl08x->pool) { | |
1910 | ret = -ENOMEM; | |
1911 | goto out_no_lli_pool; | |
1912 | } | |
1913 | ||
1914 | spin_lock_init(&pl08x->lock); | |
1915 | ||
1916 | pl08x->base = ioremap(adev->res.start, resource_size(&adev->res)); | |
1917 | if (!pl08x->base) { | |
1918 | ret = -ENOMEM; | |
1919 | goto out_no_ioremap; | |
1920 | } | |
1921 | ||
1922 | /* Turn on the PL08x */ | |
1923 | pl08x_ensure_on(pl08x); | |
1924 | ||
94ae8522 | 1925 | /* Attach the interrupt handler */ |
e8689e63 LW |
1926 | writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR); |
1927 | writel(0x000000FF, pl08x->base + PL080_TC_CLEAR); | |
1928 | ||
1929 | ret = request_irq(adev->irq[0], pl08x_irq, IRQF_DISABLED, | |
b05cd8f4 | 1930 | DRIVER_NAME, pl08x); |
e8689e63 LW |
1931 | if (ret) { |
1932 | dev_err(&adev->dev, "%s failed to request interrupt %d\n", | |
1933 | __func__, adev->irq[0]); | |
1934 | goto out_no_irq; | |
1935 | } | |
1936 | ||
1937 | /* Initialize physical channels */ | |
b201c111 | 1938 | pl08x->phy_chans = kmalloc((vd->channels * sizeof(*pl08x->phy_chans)), |
e8689e63 LW |
1939 | GFP_KERNEL); |
1940 | if (!pl08x->phy_chans) { | |
1941 | dev_err(&adev->dev, "%s failed to allocate " | |
1942 | "physical channel holders\n", | |
1943 | __func__); | |
1944 | goto out_no_phychans; | |
1945 | } | |
1946 | ||
1947 | for (i = 0; i < vd->channels; i++) { | |
1948 | struct pl08x_phy_chan *ch = &pl08x->phy_chans[i]; | |
1949 | ||
1950 | ch->id = i; | |
1951 | ch->base = pl08x->base + PL080_Cx_BASE(i); | |
1952 | spin_lock_init(&ch->lock); | |
1953 | ch->serving = NULL; | |
1954 | ch->signal = -1; | |
175a5e61 VK |
1955 | dev_dbg(&adev->dev, "physical channel %d is %s\n", |
1956 | i, pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE"); | |
e8689e63 LW |
1957 | } |
1958 | ||
1959 | /* Register as many memcpy channels as there are physical channels */ | |
1960 | ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->memcpy, | |
1961 | pl08x->vd->channels, false); | |
1962 | if (ret <= 0) { | |
1963 | dev_warn(&pl08x->adev->dev, | |
1964 | "%s failed to enumerate memcpy channels - %d\n", | |
1965 | __func__, ret); | |
1966 | goto out_no_memcpy; | |
1967 | } | |
1968 | pl08x->memcpy.chancnt = ret; | |
1969 | ||
1970 | /* Register slave channels */ | |
1971 | ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->slave, | |
3e27ee84 | 1972 | pl08x->pd->num_slave_channels, true); |
e8689e63 LW |
1973 | if (ret <= 0) { |
1974 | dev_warn(&pl08x->adev->dev, | |
1975 | "%s failed to enumerate slave channels - %d\n", | |
1976 | __func__, ret); | |
1977 | goto out_no_slave; | |
1978 | } | |
1979 | pl08x->slave.chancnt = ret; | |
1980 | ||
1981 | ret = dma_async_device_register(&pl08x->memcpy); | |
1982 | if (ret) { | |
1983 | dev_warn(&pl08x->adev->dev, | |
1984 | "%s failed to register memcpy as an async device - %d\n", | |
1985 | __func__, ret); | |
1986 | goto out_no_memcpy_reg; | |
1987 | } | |
1988 | ||
1989 | ret = dma_async_device_register(&pl08x->slave); | |
1990 | if (ret) { | |
1991 | dev_warn(&pl08x->adev->dev, | |
1992 | "%s failed to register slave as an async device - %d\n", | |
1993 | __func__, ret); | |
1994 | goto out_no_slave_reg; | |
1995 | } | |
1996 | ||
1997 | amba_set_drvdata(adev, pl08x); | |
1998 | init_pl08x_debugfs(pl08x); | |
b05cd8f4 RKAL |
1999 | dev_info(&pl08x->adev->dev, "DMA: PL%03x rev%u at 0x%08llx irq %d\n", |
2000 | amba_part(adev), amba_rev(adev), | |
2001 | (unsigned long long)adev->res.start, adev->irq[0]); | |
b7b6018b VK |
2002 | |
2003 | pm_runtime_put(&adev->dev); | |
e8689e63 LW |
2004 | return 0; |
2005 | ||
2006 | out_no_slave_reg: | |
2007 | dma_async_device_unregister(&pl08x->memcpy); | |
2008 | out_no_memcpy_reg: | |
2009 | pl08x_free_virtual_channels(&pl08x->slave); | |
2010 | out_no_slave: | |
2011 | pl08x_free_virtual_channels(&pl08x->memcpy); | |
2012 | out_no_memcpy: | |
2013 | kfree(pl08x->phy_chans); | |
2014 | out_no_phychans: | |
2015 | free_irq(adev->irq[0], pl08x); | |
2016 | out_no_irq: | |
2017 | iounmap(pl08x->base); | |
2018 | out_no_ioremap: | |
2019 | dma_pool_destroy(pl08x->pool); | |
2020 | out_no_lli_pool: | |
2021 | out_no_platdata: | |
b7b6018b VK |
2022 | pm_runtime_put(&adev->dev); |
2023 | pm_runtime_disable(&adev->dev); | |
2024 | ||
e8689e63 LW |
2025 | kfree(pl08x); |
2026 | out_no_pl08x: | |
2027 | amba_release_regions(adev); | |
2028 | return ret; | |
2029 | } | |
2030 | ||
2031 | /* PL080 has 8 channels and the PL080 have just 2 */ | |
2032 | static struct vendor_data vendor_pl080 = { | |
e8689e63 LW |
2033 | .channels = 8, |
2034 | .dualmaster = true, | |
2035 | }; | |
2036 | ||
2037 | static struct vendor_data vendor_pl081 = { | |
e8689e63 LW |
2038 | .channels = 2, |
2039 | .dualmaster = false, | |
2040 | }; | |
2041 | ||
2042 | static struct amba_id pl08x_ids[] = { | |
2043 | /* PL080 */ | |
2044 | { | |
2045 | .id = 0x00041080, | |
2046 | .mask = 0x000fffff, | |
2047 | .data = &vendor_pl080, | |
2048 | }, | |
2049 | /* PL081 */ | |
2050 | { | |
2051 | .id = 0x00041081, | |
2052 | .mask = 0x000fffff, | |
2053 | .data = &vendor_pl081, | |
2054 | }, | |
2055 | /* Nomadik 8815 PL080 variant */ | |
2056 | { | |
2057 | .id = 0x00280880, | |
2058 | .mask = 0x00ffffff, | |
2059 | .data = &vendor_pl080, | |
2060 | }, | |
2061 | { 0, 0 }, | |
2062 | }; | |
2063 | ||
2064 | static struct amba_driver pl08x_amba_driver = { | |
2065 | .drv.name = DRIVER_NAME, | |
2066 | .id_table = pl08x_ids, | |
2067 | .probe = pl08x_probe, | |
2068 | }; | |
2069 | ||
2070 | static int __init pl08x_init(void) | |
2071 | { | |
2072 | int retval; | |
2073 | retval = amba_driver_register(&pl08x_amba_driver); | |
2074 | if (retval) | |
2075 | printk(KERN_WARNING DRIVER_NAME | |
e8b5e11d | 2076 | "failed to register as an AMBA device (%d)\n", |
e8689e63 LW |
2077 | retval); |
2078 | return retval; | |
2079 | } | |
2080 | subsys_initcall(pl08x_init); |