Commit | Line | Data |
---|---|---|
dc78baa2 NF |
1 | /* |
2 | * Driver for the Atmel AHB DMA Controller (aka HDMA or DMAC on AT91 systems) | |
3 | * | |
4 | * Copyright (C) 2008 Atmel Corporation | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * | |
12 | * This supports the Atmel AHB DMA Controller, | |
13 | * | |
14 | * The driver has currently been tested with the Atmel AT91SAM9RL | |
15 | * and AT91SAM9G45 series. | |
16 | */ | |
17 | ||
18 | #include <linux/clk.h> | |
19 | #include <linux/dmaengine.h> | |
20 | #include <linux/dma-mapping.h> | |
21 | #include <linux/dmapool.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/platform_device.h> | |
25 | ||
26 | #include "at_hdmac_regs.h" | |
27 | ||
28 | /* | |
29 | * Glossary | |
30 | * -------- | |
31 | * | |
32 | * at_hdmac : Name of the ATmel AHB DMA Controller | |
33 | * at_dma_ / atdma : ATmel DMA controller entity related | |
34 | * atc_ / atchan : ATmel DMA Channel entity related | |
35 | */ | |
36 | ||
37 | #define ATC_DEFAULT_CFG (ATC_FIFOCFG_HALFFIFO) | |
38 | #define ATC_DEFAULT_CTRLA (0) | |
39 | #define ATC_DEFAULT_CTRLB (ATC_SIF(0) \ | |
40 | |ATC_DIF(1)) | |
41 | ||
42 | /* | |
43 | * Initial number of descriptors to allocate for each channel. This could | |
44 | * be increased during dma usage. | |
45 | */ | |
46 | static unsigned int init_nr_desc_per_channel = 64; | |
47 | module_param(init_nr_desc_per_channel, uint, 0644); | |
48 | MODULE_PARM_DESC(init_nr_desc_per_channel, | |
49 | "initial descriptors per channel (default: 64)"); | |
50 | ||
51 | ||
52 | /* prototypes */ | |
53 | static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx); | |
54 | ||
55 | ||
56 | /*----------------------------------------------------------------------*/ | |
57 | ||
58 | static struct at_desc *atc_first_active(struct at_dma_chan *atchan) | |
59 | { | |
60 | return list_first_entry(&atchan->active_list, | |
61 | struct at_desc, desc_node); | |
62 | } | |
63 | ||
64 | static struct at_desc *atc_first_queued(struct at_dma_chan *atchan) | |
65 | { | |
66 | return list_first_entry(&atchan->queue, | |
67 | struct at_desc, desc_node); | |
68 | } | |
69 | ||
70 | /** | |
71 | * atc_alloc_descriptor - allocate and return an initilized descriptor | |
72 | * @chan: the channel to allocate descriptors for | |
73 | * @gfp_flags: GFP allocation flags | |
74 | * | |
75 | * Note: The ack-bit is positioned in the descriptor flag at creation time | |
76 | * to make initial allocation more convenient. This bit will be cleared | |
77 | * and control will be given to client at usage time (during | |
78 | * preparation functions). | |
79 | */ | |
80 | static struct at_desc *atc_alloc_descriptor(struct dma_chan *chan, | |
81 | gfp_t gfp_flags) | |
82 | { | |
83 | struct at_desc *desc = NULL; | |
84 | struct at_dma *atdma = to_at_dma(chan->device); | |
85 | dma_addr_t phys; | |
86 | ||
87 | desc = dma_pool_alloc(atdma->dma_desc_pool, gfp_flags, &phys); | |
88 | if (desc) { | |
89 | memset(desc, 0, sizeof(struct at_desc)); | |
285a3c71 | 90 | INIT_LIST_HEAD(&desc->tx_list); |
dc78baa2 NF |
91 | dma_async_tx_descriptor_init(&desc->txd, chan); |
92 | /* txd.flags will be overwritten in prep functions */ | |
93 | desc->txd.flags = DMA_CTRL_ACK; | |
94 | desc->txd.tx_submit = atc_tx_submit; | |
95 | desc->txd.phys = phys; | |
96 | } | |
97 | ||
98 | return desc; | |
99 | } | |
100 | ||
101 | /** | |
af901ca1 | 102 | * atc_desc_get - get an unused descriptor from free_list |
dc78baa2 NF |
103 | * @atchan: channel we want a new descriptor for |
104 | */ | |
105 | static struct at_desc *atc_desc_get(struct at_dma_chan *atchan) | |
106 | { | |
107 | struct at_desc *desc, *_desc; | |
108 | struct at_desc *ret = NULL; | |
109 | unsigned int i = 0; | |
110 | LIST_HEAD(tmp_list); | |
111 | ||
112 | spin_lock_bh(&atchan->lock); | |
113 | list_for_each_entry_safe(desc, _desc, &atchan->free_list, desc_node) { | |
114 | i++; | |
115 | if (async_tx_test_ack(&desc->txd)) { | |
116 | list_del(&desc->desc_node); | |
117 | ret = desc; | |
118 | break; | |
119 | } | |
120 | dev_dbg(chan2dev(&atchan->chan_common), | |
121 | "desc %p not ACKed\n", desc); | |
122 | } | |
123 | spin_unlock_bh(&atchan->lock); | |
124 | dev_vdbg(chan2dev(&atchan->chan_common), | |
125 | "scanned %u descriptors on freelist\n", i); | |
126 | ||
127 | /* no more descriptor available in initial pool: create one more */ | |
128 | if (!ret) { | |
129 | ret = atc_alloc_descriptor(&atchan->chan_common, GFP_ATOMIC); | |
130 | if (ret) { | |
131 | spin_lock_bh(&atchan->lock); | |
132 | atchan->descs_allocated++; | |
133 | spin_unlock_bh(&atchan->lock); | |
134 | } else { | |
135 | dev_err(chan2dev(&atchan->chan_common), | |
136 | "not enough descriptors available\n"); | |
137 | } | |
138 | } | |
139 | ||
140 | return ret; | |
141 | } | |
142 | ||
143 | /** | |
144 | * atc_desc_put - move a descriptor, including any children, to the free list | |
145 | * @atchan: channel we work on | |
146 | * @desc: descriptor, at the head of a chain, to move to free list | |
147 | */ | |
148 | static void atc_desc_put(struct at_dma_chan *atchan, struct at_desc *desc) | |
149 | { | |
150 | if (desc) { | |
151 | struct at_desc *child; | |
152 | ||
153 | spin_lock_bh(&atchan->lock); | |
285a3c71 | 154 | list_for_each_entry(child, &desc->tx_list, desc_node) |
dc78baa2 NF |
155 | dev_vdbg(chan2dev(&atchan->chan_common), |
156 | "moving child desc %p to freelist\n", | |
157 | child); | |
285a3c71 | 158 | list_splice_init(&desc->tx_list, &atchan->free_list); |
dc78baa2 NF |
159 | dev_vdbg(chan2dev(&atchan->chan_common), |
160 | "moving desc %p to freelist\n", desc); | |
161 | list_add(&desc->desc_node, &atchan->free_list); | |
162 | spin_unlock_bh(&atchan->lock); | |
163 | } | |
164 | } | |
165 | ||
166 | /** | |
167 | * atc_assign_cookie - compute and assign new cookie | |
168 | * @atchan: channel we work on | |
169 | * @desc: descriptor to asign cookie for | |
170 | * | |
171 | * Called with atchan->lock held and bh disabled | |
172 | */ | |
173 | static dma_cookie_t | |
174 | atc_assign_cookie(struct at_dma_chan *atchan, struct at_desc *desc) | |
175 | { | |
176 | dma_cookie_t cookie = atchan->chan_common.cookie; | |
177 | ||
178 | if (++cookie < 0) | |
179 | cookie = 1; | |
180 | ||
181 | atchan->chan_common.cookie = cookie; | |
182 | desc->txd.cookie = cookie; | |
183 | ||
184 | return cookie; | |
185 | } | |
186 | ||
187 | /** | |
188 | * atc_dostart - starts the DMA engine for real | |
189 | * @atchan: the channel we want to start | |
190 | * @first: first descriptor in the list we want to begin with | |
191 | * | |
192 | * Called with atchan->lock held and bh disabled | |
193 | */ | |
194 | static void atc_dostart(struct at_dma_chan *atchan, struct at_desc *first) | |
195 | { | |
196 | struct at_dma *atdma = to_at_dma(atchan->chan_common.device); | |
197 | ||
198 | /* ASSERT: channel is idle */ | |
199 | if (atc_chan_is_enabled(atchan)) { | |
200 | dev_err(chan2dev(&atchan->chan_common), | |
201 | "BUG: Attempted to start non-idle channel\n"); | |
202 | dev_err(chan2dev(&atchan->chan_common), | |
203 | " channel: s0x%x d0x%x ctrl0x%x:0x%x l0x%x\n", | |
204 | channel_readl(atchan, SADDR), | |
205 | channel_readl(atchan, DADDR), | |
206 | channel_readl(atchan, CTRLA), | |
207 | channel_readl(atchan, CTRLB), | |
208 | channel_readl(atchan, DSCR)); | |
209 | ||
210 | /* The tasklet will hopefully advance the queue... */ | |
211 | return; | |
212 | } | |
213 | ||
214 | vdbg_dump_regs(atchan); | |
215 | ||
216 | /* clear any pending interrupt */ | |
217 | while (dma_readl(atdma, EBCISR)) | |
218 | cpu_relax(); | |
219 | ||
220 | channel_writel(atchan, SADDR, 0); | |
221 | channel_writel(atchan, DADDR, 0); | |
222 | channel_writel(atchan, CTRLA, 0); | |
223 | channel_writel(atchan, CTRLB, 0); | |
224 | channel_writel(atchan, DSCR, first->txd.phys); | |
225 | dma_writel(atdma, CHER, atchan->mask); | |
226 | ||
227 | vdbg_dump_regs(atchan); | |
228 | } | |
229 | ||
230 | /** | |
231 | * atc_chain_complete - finish work for one transaction chain | |
232 | * @atchan: channel we work on | |
233 | * @desc: descriptor at the head of the chain we want do complete | |
234 | * | |
235 | * Called with atchan->lock held and bh disabled */ | |
236 | static void | |
237 | atc_chain_complete(struct at_dma_chan *atchan, struct at_desc *desc) | |
238 | { | |
239 | dma_async_tx_callback callback; | |
240 | void *param; | |
241 | struct dma_async_tx_descriptor *txd = &desc->txd; | |
242 | ||
243 | dev_vdbg(chan2dev(&atchan->chan_common), | |
244 | "descriptor %u complete\n", txd->cookie); | |
245 | ||
246 | atchan->completed_cookie = txd->cookie; | |
247 | callback = txd->callback; | |
248 | param = txd->callback_param; | |
249 | ||
250 | /* move children to free_list */ | |
285a3c71 | 251 | list_splice_init(&desc->tx_list, &atchan->free_list); |
dc78baa2 NF |
252 | /* move myself to free_list */ |
253 | list_move(&desc->desc_node, &atchan->free_list); | |
254 | ||
255 | /* unmap dma addresses */ | |
657a77fa AN |
256 | if (!atchan->chan_common.private) { |
257 | struct device *parent = chan2parent(&atchan->chan_common); | |
258 | if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) { | |
259 | if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE) | |
260 | dma_unmap_single(parent, | |
261 | desc->lli.daddr, | |
262 | desc->len, DMA_FROM_DEVICE); | |
263 | else | |
264 | dma_unmap_page(parent, | |
265 | desc->lli.daddr, | |
266 | desc->len, DMA_FROM_DEVICE); | |
267 | } | |
268 | if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) { | |
269 | if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE) | |
270 | dma_unmap_single(parent, | |
271 | desc->lli.saddr, | |
272 | desc->len, DMA_TO_DEVICE); | |
273 | else | |
274 | dma_unmap_page(parent, | |
275 | desc->lli.saddr, | |
276 | desc->len, DMA_TO_DEVICE); | |
277 | } | |
dc78baa2 NF |
278 | } |
279 | ||
280 | /* | |
281 | * The API requires that no submissions are done from a | |
282 | * callback, so we don't need to drop the lock here | |
283 | */ | |
284 | if (callback) | |
285 | callback(param); | |
286 | ||
287 | dma_run_dependencies(txd); | |
288 | } | |
289 | ||
290 | /** | |
291 | * atc_complete_all - finish work for all transactions | |
292 | * @atchan: channel to complete transactions for | |
293 | * | |
294 | * Eventually submit queued descriptors if any | |
295 | * | |
296 | * Assume channel is idle while calling this function | |
297 | * Called with atchan->lock held and bh disabled | |
298 | */ | |
299 | static void atc_complete_all(struct at_dma_chan *atchan) | |
300 | { | |
301 | struct at_desc *desc, *_desc; | |
302 | LIST_HEAD(list); | |
303 | ||
304 | dev_vdbg(chan2dev(&atchan->chan_common), "complete all\n"); | |
305 | ||
306 | BUG_ON(atc_chan_is_enabled(atchan)); | |
307 | ||
308 | /* | |
309 | * Submit queued descriptors ASAP, i.e. before we go through | |
310 | * the completed ones. | |
311 | */ | |
312 | if (!list_empty(&atchan->queue)) | |
313 | atc_dostart(atchan, atc_first_queued(atchan)); | |
314 | /* empty active_list now it is completed */ | |
315 | list_splice_init(&atchan->active_list, &list); | |
316 | /* empty queue list by moving descriptors (if any) to active_list */ | |
317 | list_splice_init(&atchan->queue, &atchan->active_list); | |
318 | ||
319 | list_for_each_entry_safe(desc, _desc, &list, desc_node) | |
320 | atc_chain_complete(atchan, desc); | |
321 | } | |
322 | ||
323 | /** | |
324 | * atc_cleanup_descriptors - cleanup up finished descriptors in active_list | |
325 | * @atchan: channel to be cleaned up | |
326 | * | |
327 | * Called with atchan->lock held and bh disabled | |
328 | */ | |
329 | static void atc_cleanup_descriptors(struct at_dma_chan *atchan) | |
330 | { | |
331 | struct at_desc *desc, *_desc; | |
332 | struct at_desc *child; | |
333 | ||
334 | dev_vdbg(chan2dev(&atchan->chan_common), "cleanup descriptors\n"); | |
335 | ||
336 | list_for_each_entry_safe(desc, _desc, &atchan->active_list, desc_node) { | |
337 | if (!(desc->lli.ctrla & ATC_DONE)) | |
338 | /* This one is currently in progress */ | |
339 | return; | |
340 | ||
285a3c71 | 341 | list_for_each_entry(child, &desc->tx_list, desc_node) |
dc78baa2 NF |
342 | if (!(child->lli.ctrla & ATC_DONE)) |
343 | /* Currently in progress */ | |
344 | return; | |
345 | ||
346 | /* | |
347 | * No descriptors so far seem to be in progress, i.e. | |
348 | * this chain must be done. | |
349 | */ | |
350 | atc_chain_complete(atchan, desc); | |
351 | } | |
352 | } | |
353 | ||
354 | /** | |
355 | * atc_advance_work - at the end of a transaction, move forward | |
356 | * @atchan: channel where the transaction ended | |
357 | * | |
358 | * Called with atchan->lock held and bh disabled | |
359 | */ | |
360 | static void atc_advance_work(struct at_dma_chan *atchan) | |
361 | { | |
362 | dev_vdbg(chan2dev(&atchan->chan_common), "advance_work\n"); | |
363 | ||
364 | if (list_empty(&atchan->active_list) || | |
365 | list_is_singular(&atchan->active_list)) { | |
366 | atc_complete_all(atchan); | |
367 | } else { | |
368 | atc_chain_complete(atchan, atc_first_active(atchan)); | |
369 | /* advance work */ | |
370 | atc_dostart(atchan, atc_first_active(atchan)); | |
371 | } | |
372 | } | |
373 | ||
374 | ||
375 | /** | |
376 | * atc_handle_error - handle errors reported by DMA controller | |
377 | * @atchan: channel where error occurs | |
378 | * | |
379 | * Called with atchan->lock held and bh disabled | |
380 | */ | |
381 | static void atc_handle_error(struct at_dma_chan *atchan) | |
382 | { | |
383 | struct at_desc *bad_desc; | |
384 | struct at_desc *child; | |
385 | ||
386 | /* | |
387 | * The descriptor currently at the head of the active list is | |
388 | * broked. Since we don't have any way to report errors, we'll | |
389 | * just have to scream loudly and try to carry on. | |
390 | */ | |
391 | bad_desc = atc_first_active(atchan); | |
392 | list_del_init(&bad_desc->desc_node); | |
393 | ||
394 | /* As we are stopped, take advantage to push queued descriptors | |
395 | * in active_list */ | |
396 | list_splice_init(&atchan->queue, atchan->active_list.prev); | |
397 | ||
398 | /* Try to restart the controller */ | |
399 | if (!list_empty(&atchan->active_list)) | |
400 | atc_dostart(atchan, atc_first_active(atchan)); | |
401 | ||
402 | /* | |
403 | * KERN_CRITICAL may seem harsh, but since this only happens | |
404 | * when someone submits a bad physical address in a | |
405 | * descriptor, we should consider ourselves lucky that the | |
406 | * controller flagged an error instead of scribbling over | |
407 | * random memory locations. | |
408 | */ | |
409 | dev_crit(chan2dev(&atchan->chan_common), | |
410 | "Bad descriptor submitted for DMA!\n"); | |
411 | dev_crit(chan2dev(&atchan->chan_common), | |
412 | " cookie: %d\n", bad_desc->txd.cookie); | |
413 | atc_dump_lli(atchan, &bad_desc->lli); | |
285a3c71 | 414 | list_for_each_entry(child, &bad_desc->tx_list, desc_node) |
dc78baa2 NF |
415 | atc_dump_lli(atchan, &child->lli); |
416 | ||
417 | /* Pretend the descriptor completed successfully */ | |
418 | atc_chain_complete(atchan, bad_desc); | |
419 | } | |
420 | ||
421 | ||
422 | /*-- IRQ & Tasklet ---------------------------------------------------*/ | |
423 | ||
424 | static void atc_tasklet(unsigned long data) | |
425 | { | |
426 | struct at_dma_chan *atchan = (struct at_dma_chan *)data; | |
427 | ||
428 | /* Channel cannot be enabled here */ | |
429 | if (atc_chan_is_enabled(atchan)) { | |
430 | dev_err(chan2dev(&atchan->chan_common), | |
431 | "BUG: channel enabled in tasklet\n"); | |
432 | return; | |
433 | } | |
434 | ||
435 | spin_lock(&atchan->lock); | |
436 | if (test_and_clear_bit(0, &atchan->error_status)) | |
437 | atc_handle_error(atchan); | |
438 | else | |
439 | atc_advance_work(atchan); | |
440 | ||
441 | spin_unlock(&atchan->lock); | |
442 | } | |
443 | ||
444 | static irqreturn_t at_dma_interrupt(int irq, void *dev_id) | |
445 | { | |
446 | struct at_dma *atdma = (struct at_dma *)dev_id; | |
447 | struct at_dma_chan *atchan; | |
448 | int i; | |
449 | u32 status, pending, imr; | |
450 | int ret = IRQ_NONE; | |
451 | ||
452 | do { | |
453 | imr = dma_readl(atdma, EBCIMR); | |
454 | status = dma_readl(atdma, EBCISR); | |
455 | pending = status & imr; | |
456 | ||
457 | if (!pending) | |
458 | break; | |
459 | ||
460 | dev_vdbg(atdma->dma_common.dev, | |
461 | "interrupt: status = 0x%08x, 0x%08x, 0x%08x\n", | |
462 | status, imr, pending); | |
463 | ||
464 | for (i = 0; i < atdma->dma_common.chancnt; i++) { | |
465 | atchan = &atdma->chan[i]; | |
466 | if (pending & (AT_DMA_CBTC(i) | AT_DMA_ERR(i))) { | |
467 | if (pending & AT_DMA_ERR(i)) { | |
468 | /* Disable channel on AHB error */ | |
469 | dma_writel(atdma, CHDR, atchan->mask); | |
470 | /* Give information to tasklet */ | |
471 | set_bit(0, &atchan->error_status); | |
472 | } | |
473 | tasklet_schedule(&atchan->tasklet); | |
474 | ret = IRQ_HANDLED; | |
475 | } | |
476 | } | |
477 | ||
478 | } while (pending); | |
479 | ||
480 | return ret; | |
481 | } | |
482 | ||
483 | ||
484 | /*-- DMA Engine API --------------------------------------------------*/ | |
485 | ||
486 | /** | |
487 | * atc_tx_submit - set the prepared descriptor(s) to be executed by the engine | |
488 | * @desc: descriptor at the head of the transaction chain | |
489 | * | |
490 | * Queue chain if DMA engine is working already | |
491 | * | |
492 | * Cookie increment and adding to active_list or queue must be atomic | |
493 | */ | |
494 | static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx) | |
495 | { | |
496 | struct at_desc *desc = txd_to_at_desc(tx); | |
497 | struct at_dma_chan *atchan = to_at_dma_chan(tx->chan); | |
498 | dma_cookie_t cookie; | |
499 | ||
500 | spin_lock_bh(&atchan->lock); | |
501 | cookie = atc_assign_cookie(atchan, desc); | |
502 | ||
503 | if (list_empty(&atchan->active_list)) { | |
504 | dev_vdbg(chan2dev(tx->chan), "tx_submit: started %u\n", | |
505 | desc->txd.cookie); | |
506 | atc_dostart(atchan, desc); | |
507 | list_add_tail(&desc->desc_node, &atchan->active_list); | |
508 | } else { | |
509 | dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u\n", | |
510 | desc->txd.cookie); | |
511 | list_add_tail(&desc->desc_node, &atchan->queue); | |
512 | } | |
513 | ||
514 | spin_unlock_bh(&atchan->lock); | |
515 | ||
516 | return cookie; | |
517 | } | |
518 | ||
519 | /** | |
520 | * atc_prep_dma_memcpy - prepare a memcpy operation | |
521 | * @chan: the channel to prepare operation on | |
522 | * @dest: operation virtual destination address | |
523 | * @src: operation virtual source address | |
524 | * @len: operation length | |
525 | * @flags: tx descriptor status flags | |
526 | */ | |
527 | static struct dma_async_tx_descriptor * | |
528 | atc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
529 | size_t len, unsigned long flags) | |
530 | { | |
531 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
532 | struct at_desc *desc = NULL; | |
533 | struct at_desc *first = NULL; | |
534 | struct at_desc *prev = NULL; | |
535 | size_t xfer_count; | |
536 | size_t offset; | |
537 | unsigned int src_width; | |
538 | unsigned int dst_width; | |
539 | u32 ctrla; | |
540 | u32 ctrlb; | |
541 | ||
542 | dev_vdbg(chan2dev(chan), "prep_dma_memcpy: d0x%x s0x%x l0x%zx f0x%lx\n", | |
543 | dest, src, len, flags); | |
544 | ||
545 | if (unlikely(!len)) { | |
546 | dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n"); | |
547 | return NULL; | |
548 | } | |
549 | ||
550 | ctrla = ATC_DEFAULT_CTRLA; | |
551 | ctrlb = ATC_DEFAULT_CTRLB | |
552 | | ATC_SRC_ADDR_MODE_INCR | |
553 | | ATC_DST_ADDR_MODE_INCR | |
554 | | ATC_FC_MEM2MEM; | |
555 | ||
556 | /* | |
557 | * We can be a lot more clever here, but this should take care | |
558 | * of the most common optimization. | |
559 | */ | |
560 | if (!((src | dest | len) & 3)) { | |
561 | ctrla |= ATC_SRC_WIDTH_WORD | ATC_DST_WIDTH_WORD; | |
562 | src_width = dst_width = 2; | |
563 | } else if (!((src | dest | len) & 1)) { | |
564 | ctrla |= ATC_SRC_WIDTH_HALFWORD | ATC_DST_WIDTH_HALFWORD; | |
565 | src_width = dst_width = 1; | |
566 | } else { | |
567 | ctrla |= ATC_SRC_WIDTH_BYTE | ATC_DST_WIDTH_BYTE; | |
568 | src_width = dst_width = 0; | |
569 | } | |
570 | ||
571 | for (offset = 0; offset < len; offset += xfer_count << src_width) { | |
572 | xfer_count = min_t(size_t, (len - offset) >> src_width, | |
573 | ATC_BTSIZE_MAX); | |
574 | ||
575 | desc = atc_desc_get(atchan); | |
576 | if (!desc) | |
577 | goto err_desc_get; | |
578 | ||
579 | desc->lli.saddr = src + offset; | |
580 | desc->lli.daddr = dest + offset; | |
581 | desc->lli.ctrla = ctrla | xfer_count; | |
582 | desc->lli.ctrlb = ctrlb; | |
583 | ||
584 | desc->txd.cookie = 0; | |
585 | async_tx_ack(&desc->txd); | |
586 | ||
587 | if (!first) { | |
588 | first = desc; | |
589 | } else { | |
590 | /* inform the HW lli about chaining */ | |
591 | prev->lli.dscr = desc->txd.phys; | |
592 | /* insert the link descriptor to the LD ring */ | |
593 | list_add_tail(&desc->desc_node, | |
285a3c71 | 594 | &first->tx_list); |
dc78baa2 NF |
595 | } |
596 | prev = desc; | |
597 | } | |
598 | ||
599 | /* First descriptor of the chain embedds additional information */ | |
600 | first->txd.cookie = -EBUSY; | |
601 | first->len = len; | |
602 | ||
603 | /* set end-of-link to the last link descriptor of list*/ | |
604 | set_desc_eol(desc); | |
605 | ||
606 | desc->txd.flags = flags; /* client is in control of this ack */ | |
607 | ||
608 | return &first->txd; | |
609 | ||
610 | err_desc_get: | |
611 | atc_desc_put(atchan, first); | |
612 | return NULL; | |
613 | } | |
614 | ||
808347f6 NF |
615 | |
616 | /** | |
617 | * atc_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction | |
618 | * @chan: DMA channel | |
619 | * @sgl: scatterlist to transfer to/from | |
620 | * @sg_len: number of entries in @scatterlist | |
621 | * @direction: DMA direction | |
622 | * @flags: tx descriptor status flags | |
623 | */ | |
624 | static struct dma_async_tx_descriptor * | |
625 | atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
626 | unsigned int sg_len, enum dma_data_direction direction, | |
627 | unsigned long flags) | |
628 | { | |
629 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
630 | struct at_dma_slave *atslave = chan->private; | |
631 | struct at_desc *first = NULL; | |
632 | struct at_desc *prev = NULL; | |
633 | u32 ctrla; | |
634 | u32 ctrlb; | |
635 | dma_addr_t reg; | |
636 | unsigned int reg_width; | |
637 | unsigned int mem_width; | |
638 | unsigned int i; | |
639 | struct scatterlist *sg; | |
640 | size_t total_len = 0; | |
641 | ||
642 | dev_vdbg(chan2dev(chan), "prep_slave_sg: %s f0x%lx\n", | |
643 | direction == DMA_TO_DEVICE ? "TO DEVICE" : "FROM DEVICE", | |
644 | flags); | |
645 | ||
646 | if (unlikely(!atslave || !sg_len)) { | |
647 | dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n"); | |
648 | return NULL; | |
649 | } | |
650 | ||
651 | reg_width = atslave->reg_width; | |
652 | ||
808347f6 NF |
653 | ctrla = ATC_DEFAULT_CTRLA | atslave->ctrla; |
654 | ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN; | |
655 | ||
656 | switch (direction) { | |
657 | case DMA_TO_DEVICE: | |
658 | ctrla |= ATC_DST_WIDTH(reg_width); | |
659 | ctrlb |= ATC_DST_ADDR_MODE_FIXED | |
660 | | ATC_SRC_ADDR_MODE_INCR | |
661 | | ATC_FC_MEM2PER; | |
662 | reg = atslave->tx_reg; | |
663 | for_each_sg(sgl, sg, sg_len, i) { | |
664 | struct at_desc *desc; | |
665 | u32 len; | |
666 | u32 mem; | |
667 | ||
668 | desc = atc_desc_get(atchan); | |
669 | if (!desc) | |
670 | goto err_desc_get; | |
671 | ||
672 | mem = sg_phys(sg); | |
673 | len = sg_dma_len(sg); | |
674 | mem_width = 2; | |
675 | if (unlikely(mem & 3 || len & 3)) | |
676 | mem_width = 0; | |
677 | ||
678 | desc->lli.saddr = mem; | |
679 | desc->lli.daddr = reg; | |
680 | desc->lli.ctrla = ctrla | |
681 | | ATC_SRC_WIDTH(mem_width) | |
682 | | len >> mem_width; | |
683 | desc->lli.ctrlb = ctrlb; | |
684 | ||
685 | if (!first) { | |
686 | first = desc; | |
687 | } else { | |
688 | /* inform the HW lli about chaining */ | |
689 | prev->lli.dscr = desc->txd.phys; | |
690 | /* insert the link descriptor to the LD ring */ | |
691 | list_add_tail(&desc->desc_node, | |
285a3c71 | 692 | &first->tx_list); |
808347f6 NF |
693 | } |
694 | prev = desc; | |
695 | total_len += len; | |
696 | } | |
697 | break; | |
698 | case DMA_FROM_DEVICE: | |
699 | ctrla |= ATC_SRC_WIDTH(reg_width); | |
700 | ctrlb |= ATC_DST_ADDR_MODE_INCR | |
701 | | ATC_SRC_ADDR_MODE_FIXED | |
702 | | ATC_FC_PER2MEM; | |
703 | ||
704 | reg = atslave->rx_reg; | |
705 | for_each_sg(sgl, sg, sg_len, i) { | |
706 | struct at_desc *desc; | |
707 | u32 len; | |
708 | u32 mem; | |
709 | ||
710 | desc = atc_desc_get(atchan); | |
711 | if (!desc) | |
712 | goto err_desc_get; | |
713 | ||
714 | mem = sg_phys(sg); | |
715 | len = sg_dma_len(sg); | |
716 | mem_width = 2; | |
717 | if (unlikely(mem & 3 || len & 3)) | |
718 | mem_width = 0; | |
719 | ||
720 | desc->lli.saddr = reg; | |
721 | desc->lli.daddr = mem; | |
722 | desc->lli.ctrla = ctrla | |
723 | | ATC_DST_WIDTH(mem_width) | |
724 | | len >> mem_width; | |
725 | desc->lli.ctrlb = ctrlb; | |
726 | ||
727 | if (!first) { | |
728 | first = desc; | |
729 | } else { | |
730 | /* inform the HW lli about chaining */ | |
731 | prev->lli.dscr = desc->txd.phys; | |
732 | /* insert the link descriptor to the LD ring */ | |
733 | list_add_tail(&desc->desc_node, | |
285a3c71 | 734 | &first->tx_list); |
808347f6 NF |
735 | } |
736 | prev = desc; | |
737 | total_len += len; | |
738 | } | |
739 | break; | |
740 | default: | |
741 | return NULL; | |
742 | } | |
743 | ||
744 | /* set end-of-link to the last link descriptor of list*/ | |
745 | set_desc_eol(prev); | |
746 | ||
747 | /* First descriptor of the chain embedds additional information */ | |
748 | first->txd.cookie = -EBUSY; | |
749 | first->len = total_len; | |
750 | ||
751 | /* last link descriptor of list is responsible of flags */ | |
752 | prev->txd.flags = flags; /* client is in control of this ack */ | |
753 | ||
754 | return &first->txd; | |
755 | ||
756 | err_desc_get: | |
757 | dev_err(chan2dev(chan), "not enough descriptors available\n"); | |
758 | atc_desc_put(atchan, first); | |
759 | return NULL; | |
760 | } | |
761 | ||
c3635c78 | 762 | static int atc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd) |
808347f6 NF |
763 | { |
764 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
765 | struct at_dma *atdma = to_at_dma(chan->device); | |
766 | struct at_desc *desc, *_desc; | |
767 | LIST_HEAD(list); | |
768 | ||
c3635c78 LW |
769 | /* Only supports DMA_TERMINATE_ALL */ |
770 | if (cmd != DMA_TERMINATE_ALL) | |
771 | return -ENXIO; | |
772 | ||
808347f6 NF |
773 | /* |
774 | * This is only called when something went wrong elsewhere, so | |
775 | * we don't really care about the data. Just disable the | |
776 | * channel. We still have to poll the channel enable bit due | |
777 | * to AHB/HSB limitations. | |
778 | */ | |
779 | spin_lock_bh(&atchan->lock); | |
780 | ||
781 | dma_writel(atdma, CHDR, atchan->mask); | |
782 | ||
783 | /* confirm that this channel is disabled */ | |
784 | while (dma_readl(atdma, CHSR) & atchan->mask) | |
785 | cpu_relax(); | |
786 | ||
787 | /* active_list entries will end up before queued entries */ | |
788 | list_splice_init(&atchan->queue, &list); | |
789 | list_splice_init(&atchan->active_list, &list); | |
790 | ||
791 | spin_unlock_bh(&atchan->lock); | |
792 | ||
793 | /* Flush all pending and queued descriptors */ | |
794 | list_for_each_entry_safe(desc, _desc, &list, desc_node) | |
795 | atc_chain_complete(atchan, desc); | |
c3635c78 LW |
796 | |
797 | return 0; | |
808347f6 NF |
798 | } |
799 | ||
dc78baa2 | 800 | /** |
07934481 | 801 | * atc_tx_status - poll for transaction completion |
dc78baa2 NF |
802 | * @chan: DMA channel |
803 | * @cookie: transaction identifier to check status of | |
07934481 | 804 | * @txstate: if not %NULL updated with transaction state |
dc78baa2 | 805 | * |
07934481 | 806 | * If @txstate is passed in, upon return it reflect the driver |
dc78baa2 NF |
807 | * internal state and can be used with dma_async_is_complete() to check |
808 | * the status of multiple cookies without re-checking hardware state. | |
809 | */ | |
810 | static enum dma_status | |
07934481 | 811 | atc_tx_status(struct dma_chan *chan, |
dc78baa2 | 812 | dma_cookie_t cookie, |
07934481 | 813 | struct dma_tx_state *txstate) |
dc78baa2 NF |
814 | { |
815 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
816 | dma_cookie_t last_used; | |
817 | dma_cookie_t last_complete; | |
818 | enum dma_status ret; | |
819 | ||
4297a462 | 820 | spin_lock_bh(&atchan->lock); |
dc78baa2 NF |
821 | |
822 | last_complete = atchan->completed_cookie; | |
823 | last_used = chan->cookie; | |
824 | ||
825 | ret = dma_async_is_complete(cookie, last_complete, last_used); | |
826 | if (ret != DMA_SUCCESS) { | |
827 | atc_cleanup_descriptors(atchan); | |
828 | ||
829 | last_complete = atchan->completed_cookie; | |
830 | last_used = chan->cookie; | |
831 | ||
832 | ret = dma_async_is_complete(cookie, last_complete, last_used); | |
833 | } | |
834 | ||
4297a462 | 835 | spin_unlock_bh(&atchan->lock); |
dc78baa2 | 836 | |
bca34692 | 837 | dma_set_tx_state(txstate, last_complete, last_used, 0); |
07934481 LW |
838 | dev_vdbg(chan2dev(chan), "tx_status: %d (d%d, u%d)\n", |
839 | cookie, last_complete ? last_complete : 0, | |
840 | last_used ? last_used : 0); | |
dc78baa2 NF |
841 | |
842 | return ret; | |
843 | } | |
844 | ||
845 | /** | |
846 | * atc_issue_pending - try to finish work | |
847 | * @chan: target DMA channel | |
848 | */ | |
849 | static void atc_issue_pending(struct dma_chan *chan) | |
850 | { | |
851 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
852 | ||
853 | dev_vdbg(chan2dev(chan), "issue_pending\n"); | |
854 | ||
855 | if (!atc_chan_is_enabled(atchan)) { | |
856 | spin_lock_bh(&atchan->lock); | |
857 | atc_advance_work(atchan); | |
858 | spin_unlock_bh(&atchan->lock); | |
859 | } | |
860 | } | |
861 | ||
862 | /** | |
863 | * atc_alloc_chan_resources - allocate resources for DMA channel | |
864 | * @chan: allocate descriptor resources for this channel | |
865 | * @client: current client requesting the channel be ready for requests | |
866 | * | |
867 | * return - the number of allocated descriptors | |
868 | */ | |
869 | static int atc_alloc_chan_resources(struct dma_chan *chan) | |
870 | { | |
871 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
872 | struct at_dma *atdma = to_at_dma(chan->device); | |
873 | struct at_desc *desc; | |
808347f6 | 874 | struct at_dma_slave *atslave; |
dc78baa2 | 875 | int i; |
808347f6 | 876 | u32 cfg; |
dc78baa2 NF |
877 | LIST_HEAD(tmp_list); |
878 | ||
879 | dev_vdbg(chan2dev(chan), "alloc_chan_resources\n"); | |
880 | ||
881 | /* ASSERT: channel is idle */ | |
882 | if (atc_chan_is_enabled(atchan)) { | |
883 | dev_dbg(chan2dev(chan), "DMA channel not idle ?\n"); | |
884 | return -EIO; | |
885 | } | |
886 | ||
808347f6 NF |
887 | cfg = ATC_DEFAULT_CFG; |
888 | ||
889 | atslave = chan->private; | |
890 | if (atslave) { | |
891 | /* | |
892 | * We need controller-specific data to set up slave | |
893 | * transfers. | |
894 | */ | |
895 | BUG_ON(!atslave->dma_dev || atslave->dma_dev != atdma->dma_common.dev); | |
896 | ||
897 | /* if cfg configuration specified take it instad of default */ | |
898 | if (atslave->cfg) | |
899 | cfg = atslave->cfg; | |
900 | } | |
901 | ||
902 | /* have we already been set up? | |
903 | * reconfigure channel but no need to reallocate descriptors */ | |
dc78baa2 NF |
904 | if (!list_empty(&atchan->free_list)) |
905 | return atchan->descs_allocated; | |
906 | ||
907 | /* Allocate initial pool of descriptors */ | |
908 | for (i = 0; i < init_nr_desc_per_channel; i++) { | |
909 | desc = atc_alloc_descriptor(chan, GFP_KERNEL); | |
910 | if (!desc) { | |
911 | dev_err(atdma->dma_common.dev, | |
912 | "Only %d initial descriptors\n", i); | |
913 | break; | |
914 | } | |
915 | list_add_tail(&desc->desc_node, &tmp_list); | |
916 | } | |
917 | ||
918 | spin_lock_bh(&atchan->lock); | |
919 | atchan->descs_allocated = i; | |
920 | list_splice(&tmp_list, &atchan->free_list); | |
921 | atchan->completed_cookie = chan->cookie = 1; | |
922 | spin_unlock_bh(&atchan->lock); | |
923 | ||
924 | /* channel parameters */ | |
808347f6 | 925 | channel_writel(atchan, CFG, cfg); |
dc78baa2 NF |
926 | |
927 | dev_dbg(chan2dev(chan), | |
928 | "alloc_chan_resources: allocated %d descriptors\n", | |
929 | atchan->descs_allocated); | |
930 | ||
931 | return atchan->descs_allocated; | |
932 | } | |
933 | ||
934 | /** | |
935 | * atc_free_chan_resources - free all channel resources | |
936 | * @chan: DMA channel | |
937 | */ | |
938 | static void atc_free_chan_resources(struct dma_chan *chan) | |
939 | { | |
940 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
941 | struct at_dma *atdma = to_at_dma(chan->device); | |
942 | struct at_desc *desc, *_desc; | |
943 | LIST_HEAD(list); | |
944 | ||
945 | dev_dbg(chan2dev(chan), "free_chan_resources: (descs allocated=%u)\n", | |
946 | atchan->descs_allocated); | |
947 | ||
948 | /* ASSERT: channel is idle */ | |
949 | BUG_ON(!list_empty(&atchan->active_list)); | |
950 | BUG_ON(!list_empty(&atchan->queue)); | |
951 | BUG_ON(atc_chan_is_enabled(atchan)); | |
952 | ||
953 | list_for_each_entry_safe(desc, _desc, &atchan->free_list, desc_node) { | |
954 | dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc); | |
955 | list_del(&desc->desc_node); | |
956 | /* free link descriptor */ | |
957 | dma_pool_free(atdma->dma_desc_pool, desc, desc->txd.phys); | |
958 | } | |
959 | list_splice_init(&atchan->free_list, &list); | |
960 | atchan->descs_allocated = 0; | |
961 | ||
962 | dev_vdbg(chan2dev(chan), "free_chan_resources: done\n"); | |
963 | } | |
964 | ||
965 | ||
966 | /*-- Module Management -----------------------------------------------*/ | |
967 | ||
968 | /** | |
969 | * at_dma_off - disable DMA controller | |
970 | * @atdma: the Atmel HDAMC device | |
971 | */ | |
972 | static void at_dma_off(struct at_dma *atdma) | |
973 | { | |
974 | dma_writel(atdma, EN, 0); | |
975 | ||
976 | /* disable all interrupts */ | |
977 | dma_writel(atdma, EBCIDR, -1L); | |
978 | ||
979 | /* confirm that all channels are disabled */ | |
980 | while (dma_readl(atdma, CHSR) & atdma->all_chan_mask) | |
981 | cpu_relax(); | |
982 | } | |
983 | ||
984 | static int __init at_dma_probe(struct platform_device *pdev) | |
985 | { | |
986 | struct at_dma_platform_data *pdata; | |
987 | struct resource *io; | |
988 | struct at_dma *atdma; | |
989 | size_t size; | |
990 | int irq; | |
991 | int err; | |
992 | int i; | |
993 | ||
994 | /* get DMA Controller parameters from platform */ | |
995 | pdata = pdev->dev.platform_data; | |
996 | if (!pdata || pdata->nr_channels > AT_DMA_MAX_NR_CHANNELS) | |
997 | return -EINVAL; | |
998 | ||
999 | io = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1000 | if (!io) | |
1001 | return -EINVAL; | |
1002 | ||
1003 | irq = platform_get_irq(pdev, 0); | |
1004 | if (irq < 0) | |
1005 | return irq; | |
1006 | ||
1007 | size = sizeof(struct at_dma); | |
1008 | size += pdata->nr_channels * sizeof(struct at_dma_chan); | |
1009 | atdma = kzalloc(size, GFP_KERNEL); | |
1010 | if (!atdma) | |
1011 | return -ENOMEM; | |
1012 | ||
1013 | /* discover transaction capabilites from the platform data */ | |
1014 | atdma->dma_common.cap_mask = pdata->cap_mask; | |
1015 | atdma->all_chan_mask = (1 << pdata->nr_channels) - 1; | |
1016 | ||
1017 | size = io->end - io->start + 1; | |
1018 | if (!request_mem_region(io->start, size, pdev->dev.driver->name)) { | |
1019 | err = -EBUSY; | |
1020 | goto err_kfree; | |
1021 | } | |
1022 | ||
1023 | atdma->regs = ioremap(io->start, size); | |
1024 | if (!atdma->regs) { | |
1025 | err = -ENOMEM; | |
1026 | goto err_release_r; | |
1027 | } | |
1028 | ||
1029 | atdma->clk = clk_get(&pdev->dev, "dma_clk"); | |
1030 | if (IS_ERR(atdma->clk)) { | |
1031 | err = PTR_ERR(atdma->clk); | |
1032 | goto err_clk; | |
1033 | } | |
1034 | clk_enable(atdma->clk); | |
1035 | ||
1036 | /* force dma off, just in case */ | |
1037 | at_dma_off(atdma); | |
1038 | ||
1039 | err = request_irq(irq, at_dma_interrupt, 0, "at_hdmac", atdma); | |
1040 | if (err) | |
1041 | goto err_irq; | |
1042 | ||
1043 | platform_set_drvdata(pdev, atdma); | |
1044 | ||
1045 | /* create a pool of consistent memory blocks for hardware descriptors */ | |
1046 | atdma->dma_desc_pool = dma_pool_create("at_hdmac_desc_pool", | |
1047 | &pdev->dev, sizeof(struct at_desc), | |
1048 | 4 /* word alignment */, 0); | |
1049 | if (!atdma->dma_desc_pool) { | |
1050 | dev_err(&pdev->dev, "No memory for descriptors dma pool\n"); | |
1051 | err = -ENOMEM; | |
1052 | goto err_pool_create; | |
1053 | } | |
1054 | ||
1055 | /* clear any pending interrupt */ | |
1056 | while (dma_readl(atdma, EBCISR)) | |
1057 | cpu_relax(); | |
1058 | ||
1059 | /* initialize channels related values */ | |
1060 | INIT_LIST_HEAD(&atdma->dma_common.channels); | |
1061 | for (i = 0; i < pdata->nr_channels; i++, atdma->dma_common.chancnt++) { | |
1062 | struct at_dma_chan *atchan = &atdma->chan[i]; | |
1063 | ||
1064 | atchan->chan_common.device = &atdma->dma_common; | |
1065 | atchan->chan_common.cookie = atchan->completed_cookie = 1; | |
1066 | atchan->chan_common.chan_id = i; | |
1067 | list_add_tail(&atchan->chan_common.device_node, | |
1068 | &atdma->dma_common.channels); | |
1069 | ||
1070 | atchan->ch_regs = atdma->regs + ch_regs(i); | |
1071 | spin_lock_init(&atchan->lock); | |
1072 | atchan->mask = 1 << i; | |
1073 | ||
1074 | INIT_LIST_HEAD(&atchan->active_list); | |
1075 | INIT_LIST_HEAD(&atchan->queue); | |
1076 | INIT_LIST_HEAD(&atchan->free_list); | |
1077 | ||
1078 | tasklet_init(&atchan->tasklet, atc_tasklet, | |
1079 | (unsigned long)atchan); | |
1080 | atc_enable_irq(atchan); | |
1081 | } | |
1082 | ||
1083 | /* set base routines */ | |
1084 | atdma->dma_common.device_alloc_chan_resources = atc_alloc_chan_resources; | |
1085 | atdma->dma_common.device_free_chan_resources = atc_free_chan_resources; | |
07934481 | 1086 | atdma->dma_common.device_tx_status = atc_tx_status; |
dc78baa2 NF |
1087 | atdma->dma_common.device_issue_pending = atc_issue_pending; |
1088 | atdma->dma_common.dev = &pdev->dev; | |
1089 | ||
1090 | /* set prep routines based on capability */ | |
1091 | if (dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask)) | |
1092 | atdma->dma_common.device_prep_dma_memcpy = atc_prep_dma_memcpy; | |
1093 | ||
808347f6 NF |
1094 | if (dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask)) { |
1095 | atdma->dma_common.device_prep_slave_sg = atc_prep_slave_sg; | |
c3635c78 | 1096 | atdma->dma_common.device_control = atc_control; |
808347f6 NF |
1097 | } |
1098 | ||
dc78baa2 NF |
1099 | dma_writel(atdma, EN, AT_DMA_ENABLE); |
1100 | ||
1101 | dev_info(&pdev->dev, "Atmel AHB DMA Controller ( %s%s), %d channels\n", | |
1102 | dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask) ? "cpy " : "", | |
1103 | dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask) ? "slave " : "", | |
1104 | atdma->dma_common.chancnt); | |
1105 | ||
1106 | dma_async_device_register(&atdma->dma_common); | |
1107 | ||
1108 | return 0; | |
1109 | ||
1110 | err_pool_create: | |
1111 | platform_set_drvdata(pdev, NULL); | |
1112 | free_irq(platform_get_irq(pdev, 0), atdma); | |
1113 | err_irq: | |
1114 | clk_disable(atdma->clk); | |
1115 | clk_put(atdma->clk); | |
1116 | err_clk: | |
1117 | iounmap(atdma->regs); | |
1118 | atdma->regs = NULL; | |
1119 | err_release_r: | |
1120 | release_mem_region(io->start, size); | |
1121 | err_kfree: | |
1122 | kfree(atdma); | |
1123 | return err; | |
1124 | } | |
1125 | ||
1126 | static int __exit at_dma_remove(struct platform_device *pdev) | |
1127 | { | |
1128 | struct at_dma *atdma = platform_get_drvdata(pdev); | |
1129 | struct dma_chan *chan, *_chan; | |
1130 | struct resource *io; | |
1131 | ||
1132 | at_dma_off(atdma); | |
1133 | dma_async_device_unregister(&atdma->dma_common); | |
1134 | ||
1135 | dma_pool_destroy(atdma->dma_desc_pool); | |
1136 | platform_set_drvdata(pdev, NULL); | |
1137 | free_irq(platform_get_irq(pdev, 0), atdma); | |
1138 | ||
1139 | list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels, | |
1140 | device_node) { | |
1141 | struct at_dma_chan *atchan = to_at_dma_chan(chan); | |
1142 | ||
1143 | /* Disable interrupts */ | |
1144 | atc_disable_irq(atchan); | |
1145 | tasklet_disable(&atchan->tasklet); | |
1146 | ||
1147 | tasklet_kill(&atchan->tasklet); | |
1148 | list_del(&chan->device_node); | |
1149 | } | |
1150 | ||
1151 | clk_disable(atdma->clk); | |
1152 | clk_put(atdma->clk); | |
1153 | ||
1154 | iounmap(atdma->regs); | |
1155 | atdma->regs = NULL; | |
1156 | ||
1157 | io = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1158 | release_mem_region(io->start, io->end - io->start + 1); | |
1159 | ||
1160 | kfree(atdma); | |
1161 | ||
1162 | return 0; | |
1163 | } | |
1164 | ||
1165 | static void at_dma_shutdown(struct platform_device *pdev) | |
1166 | { | |
1167 | struct at_dma *atdma = platform_get_drvdata(pdev); | |
1168 | ||
1169 | at_dma_off(platform_get_drvdata(pdev)); | |
1170 | clk_disable(atdma->clk); | |
1171 | } | |
1172 | ||
33f82d14 | 1173 | static int at_dma_suspend_noirq(struct device *dev) |
dc78baa2 | 1174 | { |
33f82d14 DW |
1175 | struct platform_device *pdev = to_platform_device(dev); |
1176 | struct at_dma *atdma = platform_get_drvdata(pdev); | |
dc78baa2 NF |
1177 | |
1178 | at_dma_off(platform_get_drvdata(pdev)); | |
1179 | clk_disable(atdma->clk); | |
1180 | return 0; | |
1181 | } | |
1182 | ||
33f82d14 | 1183 | static int at_dma_resume_noirq(struct device *dev) |
dc78baa2 | 1184 | { |
33f82d14 DW |
1185 | struct platform_device *pdev = to_platform_device(dev); |
1186 | struct at_dma *atdma = platform_get_drvdata(pdev); | |
dc78baa2 NF |
1187 | |
1188 | clk_enable(atdma->clk); | |
1189 | dma_writel(atdma, EN, AT_DMA_ENABLE); | |
1190 | return 0; | |
dc78baa2 NF |
1191 | } |
1192 | ||
47145210 | 1193 | static const struct dev_pm_ops at_dma_dev_pm_ops = { |
33f82d14 DW |
1194 | .suspend_noirq = at_dma_suspend_noirq, |
1195 | .resume_noirq = at_dma_resume_noirq, | |
1196 | }; | |
1197 | ||
dc78baa2 NF |
1198 | static struct platform_driver at_dma_driver = { |
1199 | .remove = __exit_p(at_dma_remove), | |
1200 | .shutdown = at_dma_shutdown, | |
dc78baa2 NF |
1201 | .driver = { |
1202 | .name = "at_hdmac", | |
33f82d14 | 1203 | .pm = &at_dma_dev_pm_ops, |
dc78baa2 NF |
1204 | }, |
1205 | }; | |
1206 | ||
1207 | static int __init at_dma_init(void) | |
1208 | { | |
1209 | return platform_driver_probe(&at_dma_driver, at_dma_probe); | |
1210 | } | |
1211 | module_init(at_dma_init); | |
1212 | ||
1213 | static void __exit at_dma_exit(void) | |
1214 | { | |
1215 | platform_driver_unregister(&at_dma_driver); | |
1216 | } | |
1217 | module_exit(at_dma_exit); | |
1218 | ||
1219 | MODULE_DESCRIPTION("Atmel AHB DMA Controller driver"); | |
1220 | MODULE_AUTHOR("Nicolas Ferre <nicolas.ferre@atmel.com>"); | |
1221 | MODULE_LICENSE("GPL"); | |
1222 | MODULE_ALIAS("platform:at_hdmac"); |