Commit | Line | Data |
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e1f7c9ee LD |
1 | /* |
2 | * Driver for the Atmel Extensible DMA Controller (aka XDMAC on AT91 systems) | |
3 | * | |
4 | * Copyright (C) 2014 Atmel Corporation | |
5 | * | |
6 | * Author: Ludovic Desroches <ludovic.desroches@atmel.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License version 2 as published by | |
10 | * the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
21 | #include <asm/barrier.h> | |
22 | #include <dt-bindings/dma/at91.h> | |
23 | #include <linux/clk.h> | |
24 | #include <linux/dmaengine.h> | |
25 | #include <linux/dmapool.h> | |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/irq.h> | |
6d3a7d9e | 28 | #include <linux/kernel.h> |
e1f7c9ee LD |
29 | #include <linux/list.h> |
30 | #include <linux/module.h> | |
31 | #include <linux/of_dma.h> | |
32 | #include <linux/of_platform.h> | |
33 | #include <linux/platform_device.h> | |
34 | #include <linux/pm.h> | |
35 | ||
36 | #include "dmaengine.h" | |
37 | ||
38 | /* Global registers */ | |
39 | #define AT_XDMAC_GTYPE 0x00 /* Global Type Register */ | |
40 | #define AT_XDMAC_NB_CH(i) (((i) & 0x1F) + 1) /* Number of Channels Minus One */ | |
41 | #define AT_XDMAC_FIFO_SZ(i) (((i) >> 5) & 0x7FF) /* Number of Bytes */ | |
42 | #define AT_XDMAC_NB_REQ(i) ((((i) >> 16) & 0x3F) + 1) /* Number of Peripheral Requests Minus One */ | |
43 | #define AT_XDMAC_GCFG 0x04 /* Global Configuration Register */ | |
44 | #define AT_XDMAC_GWAC 0x08 /* Global Weighted Arbiter Configuration Register */ | |
45 | #define AT_XDMAC_GIE 0x0C /* Global Interrupt Enable Register */ | |
46 | #define AT_XDMAC_GID 0x10 /* Global Interrupt Disable Register */ | |
47 | #define AT_XDMAC_GIM 0x14 /* Global Interrupt Mask Register */ | |
48 | #define AT_XDMAC_GIS 0x18 /* Global Interrupt Status Register */ | |
49 | #define AT_XDMAC_GE 0x1C /* Global Channel Enable Register */ | |
50 | #define AT_XDMAC_GD 0x20 /* Global Channel Disable Register */ | |
51 | #define AT_XDMAC_GS 0x24 /* Global Channel Status Register */ | |
52 | #define AT_XDMAC_GRS 0x28 /* Global Channel Read Suspend Register */ | |
53 | #define AT_XDMAC_GWS 0x2C /* Global Write Suspend Register */ | |
54 | #define AT_XDMAC_GRWS 0x30 /* Global Channel Read Write Suspend Register */ | |
55 | #define AT_XDMAC_GRWR 0x34 /* Global Channel Read Write Resume Register */ | |
56 | #define AT_XDMAC_GSWR 0x38 /* Global Channel Software Request Register */ | |
57 | #define AT_XDMAC_GSWS 0x3C /* Global channel Software Request Status Register */ | |
58 | #define AT_XDMAC_GSWF 0x40 /* Global Channel Software Flush Request Register */ | |
59 | #define AT_XDMAC_VERSION 0xFFC /* XDMAC Version Register */ | |
60 | ||
61 | /* Channel relative registers offsets */ | |
62 | #define AT_XDMAC_CIE 0x00 /* Channel Interrupt Enable Register */ | |
63 | #define AT_XDMAC_CIE_BIE BIT(0) /* End of Block Interrupt Enable Bit */ | |
64 | #define AT_XDMAC_CIE_LIE BIT(1) /* End of Linked List Interrupt Enable Bit */ | |
65 | #define AT_XDMAC_CIE_DIE BIT(2) /* End of Disable Interrupt Enable Bit */ | |
66 | #define AT_XDMAC_CIE_FIE BIT(3) /* End of Flush Interrupt Enable Bit */ | |
67 | #define AT_XDMAC_CIE_RBEIE BIT(4) /* Read Bus Error Interrupt Enable Bit */ | |
68 | #define AT_XDMAC_CIE_WBEIE BIT(5) /* Write Bus Error Interrupt Enable Bit */ | |
69 | #define AT_XDMAC_CIE_ROIE BIT(6) /* Request Overflow Interrupt Enable Bit */ | |
70 | #define AT_XDMAC_CID 0x04 /* Channel Interrupt Disable Register */ | |
71 | #define AT_XDMAC_CID_BID BIT(0) /* End of Block Interrupt Disable Bit */ | |
72 | #define AT_XDMAC_CID_LID BIT(1) /* End of Linked List Interrupt Disable Bit */ | |
73 | #define AT_XDMAC_CID_DID BIT(2) /* End of Disable Interrupt Disable Bit */ | |
74 | #define AT_XDMAC_CID_FID BIT(3) /* End of Flush Interrupt Disable Bit */ | |
75 | #define AT_XDMAC_CID_RBEID BIT(4) /* Read Bus Error Interrupt Disable Bit */ | |
76 | #define AT_XDMAC_CID_WBEID BIT(5) /* Write Bus Error Interrupt Disable Bit */ | |
77 | #define AT_XDMAC_CID_ROID BIT(6) /* Request Overflow Interrupt Disable Bit */ | |
78 | #define AT_XDMAC_CIM 0x08 /* Channel Interrupt Mask Register */ | |
79 | #define AT_XDMAC_CIM_BIM BIT(0) /* End of Block Interrupt Mask Bit */ | |
80 | #define AT_XDMAC_CIM_LIM BIT(1) /* End of Linked List Interrupt Mask Bit */ | |
81 | #define AT_XDMAC_CIM_DIM BIT(2) /* End of Disable Interrupt Mask Bit */ | |
82 | #define AT_XDMAC_CIM_FIM BIT(3) /* End of Flush Interrupt Mask Bit */ | |
83 | #define AT_XDMAC_CIM_RBEIM BIT(4) /* Read Bus Error Interrupt Mask Bit */ | |
84 | #define AT_XDMAC_CIM_WBEIM BIT(5) /* Write Bus Error Interrupt Mask Bit */ | |
85 | #define AT_XDMAC_CIM_ROIM BIT(6) /* Request Overflow Interrupt Mask Bit */ | |
86 | #define AT_XDMAC_CIS 0x0C /* Channel Interrupt Status Register */ | |
87 | #define AT_XDMAC_CIS_BIS BIT(0) /* End of Block Interrupt Status Bit */ | |
88 | #define AT_XDMAC_CIS_LIS BIT(1) /* End of Linked List Interrupt Status Bit */ | |
89 | #define AT_XDMAC_CIS_DIS BIT(2) /* End of Disable Interrupt Status Bit */ | |
90 | #define AT_XDMAC_CIS_FIS BIT(3) /* End of Flush Interrupt Status Bit */ | |
91 | #define AT_XDMAC_CIS_RBEIS BIT(4) /* Read Bus Error Interrupt Status Bit */ | |
92 | #define AT_XDMAC_CIS_WBEIS BIT(5) /* Write Bus Error Interrupt Status Bit */ | |
93 | #define AT_XDMAC_CIS_ROIS BIT(6) /* Request Overflow Interrupt Status Bit */ | |
94 | #define AT_XDMAC_CSA 0x10 /* Channel Source Address Register */ | |
95 | #define AT_XDMAC_CDA 0x14 /* Channel Destination Address Register */ | |
96 | #define AT_XDMAC_CNDA 0x18 /* Channel Next Descriptor Address Register */ | |
97 | #define AT_XDMAC_CNDA_NDAIF(i) ((i) & 0x1) /* Channel x Next Descriptor Interface */ | |
98 | #define AT_XDMAC_CNDA_NDA(i) ((i) & 0xfffffffc) /* Channel x Next Descriptor Address */ | |
99 | #define AT_XDMAC_CNDC 0x1C /* Channel Next Descriptor Control Register */ | |
100 | #define AT_XDMAC_CNDC_NDE (0x1 << 0) /* Channel x Next Descriptor Enable */ | |
101 | #define AT_XDMAC_CNDC_NDSUP (0x1 << 1) /* Channel x Next Descriptor Source Update */ | |
102 | #define AT_XDMAC_CNDC_NDDUP (0x1 << 2) /* Channel x Next Descriptor Destination Update */ | |
103 | #define AT_XDMAC_CNDC_NDVIEW_NDV0 (0x0 << 3) /* Channel x Next Descriptor View 0 */ | |
104 | #define AT_XDMAC_CNDC_NDVIEW_NDV1 (0x1 << 3) /* Channel x Next Descriptor View 1 */ | |
105 | #define AT_XDMAC_CNDC_NDVIEW_NDV2 (0x2 << 3) /* Channel x Next Descriptor View 2 */ | |
106 | #define AT_XDMAC_CNDC_NDVIEW_NDV3 (0x3 << 3) /* Channel x Next Descriptor View 3 */ | |
107 | #define AT_XDMAC_CUBC 0x20 /* Channel Microblock Control Register */ | |
108 | #define AT_XDMAC_CBC 0x24 /* Channel Block Control Register */ | |
109 | #define AT_XDMAC_CC 0x28 /* Channel Configuration Register */ | |
110 | #define AT_XDMAC_CC_TYPE (0x1 << 0) /* Channel Transfer Type */ | |
111 | #define AT_XDMAC_CC_TYPE_MEM_TRAN (0x0 << 0) /* Memory to Memory Transfer */ | |
112 | #define AT_XDMAC_CC_TYPE_PER_TRAN (0x1 << 0) /* Peripheral to Memory or Memory to Peripheral Transfer */ | |
113 | #define AT_XDMAC_CC_MBSIZE_MASK (0x3 << 1) | |
114 | #define AT_XDMAC_CC_MBSIZE_SINGLE (0x0 << 1) | |
115 | #define AT_XDMAC_CC_MBSIZE_FOUR (0x1 << 1) | |
116 | #define AT_XDMAC_CC_MBSIZE_EIGHT (0x2 << 1) | |
117 | #define AT_XDMAC_CC_MBSIZE_SIXTEEN (0x3 << 1) | |
118 | #define AT_XDMAC_CC_DSYNC (0x1 << 4) /* Channel Synchronization */ | |
119 | #define AT_XDMAC_CC_DSYNC_PER2MEM (0x0 << 4) | |
120 | #define AT_XDMAC_CC_DSYNC_MEM2PER (0x1 << 4) | |
121 | #define AT_XDMAC_CC_PROT (0x1 << 5) /* Channel Protection */ | |
122 | #define AT_XDMAC_CC_PROT_SEC (0x0 << 5) | |
123 | #define AT_XDMAC_CC_PROT_UNSEC (0x1 << 5) | |
124 | #define AT_XDMAC_CC_SWREQ (0x1 << 6) /* Channel Software Request Trigger */ | |
125 | #define AT_XDMAC_CC_SWREQ_HWR_CONNECTED (0x0 << 6) | |
126 | #define AT_XDMAC_CC_SWREQ_SWR_CONNECTED (0x1 << 6) | |
127 | #define AT_XDMAC_CC_MEMSET (0x1 << 7) /* Channel Fill Block of memory */ | |
128 | #define AT_XDMAC_CC_MEMSET_NORMAL_MODE (0x0 << 7) | |
129 | #define AT_XDMAC_CC_MEMSET_HW_MODE (0x1 << 7) | |
130 | #define AT_XDMAC_CC_CSIZE(i) ((0x7 & (i)) << 8) /* Channel Chunk Size */ | |
131 | #define AT_XDMAC_CC_DWIDTH_OFFSET 11 | |
132 | #define AT_XDMAC_CC_DWIDTH_MASK (0x3 << AT_XDMAC_CC_DWIDTH_OFFSET) | |
133 | #define AT_XDMAC_CC_DWIDTH(i) ((0x3 & (i)) << AT_XDMAC_CC_DWIDTH_OFFSET) /* Channel Data Width */ | |
134 | #define AT_XDMAC_CC_DWIDTH_BYTE 0x0 | |
135 | #define AT_XDMAC_CC_DWIDTH_HALFWORD 0x1 | |
136 | #define AT_XDMAC_CC_DWIDTH_WORD 0x2 | |
137 | #define AT_XDMAC_CC_DWIDTH_DWORD 0x3 | |
138 | #define AT_XDMAC_CC_SIF(i) ((0x1 & (i)) << 13) /* Channel Source Interface Identifier */ | |
139 | #define AT_XDMAC_CC_DIF(i) ((0x1 & (i)) << 14) /* Channel Destination Interface Identifier */ | |
140 | #define AT_XDMAC_CC_SAM_MASK (0x3 << 16) /* Channel Source Addressing Mode */ | |
141 | #define AT_XDMAC_CC_SAM_FIXED_AM (0x0 << 16) | |
142 | #define AT_XDMAC_CC_SAM_INCREMENTED_AM (0x1 << 16) | |
143 | #define AT_XDMAC_CC_SAM_UBS_AM (0x2 << 16) | |
144 | #define AT_XDMAC_CC_SAM_UBS_DS_AM (0x3 << 16) | |
145 | #define AT_XDMAC_CC_DAM_MASK (0x3 << 18) /* Channel Source Addressing Mode */ | |
146 | #define AT_XDMAC_CC_DAM_FIXED_AM (0x0 << 18) | |
147 | #define AT_XDMAC_CC_DAM_INCREMENTED_AM (0x1 << 18) | |
148 | #define AT_XDMAC_CC_DAM_UBS_AM (0x2 << 18) | |
149 | #define AT_XDMAC_CC_DAM_UBS_DS_AM (0x3 << 18) | |
150 | #define AT_XDMAC_CC_INITD (0x1 << 21) /* Channel Initialization Terminated (read only) */ | |
151 | #define AT_XDMAC_CC_INITD_TERMINATED (0x0 << 21) | |
152 | #define AT_XDMAC_CC_INITD_IN_PROGRESS (0x1 << 21) | |
153 | #define AT_XDMAC_CC_RDIP (0x1 << 22) /* Read in Progress (read only) */ | |
154 | #define AT_XDMAC_CC_RDIP_DONE (0x0 << 22) | |
155 | #define AT_XDMAC_CC_RDIP_IN_PROGRESS (0x1 << 22) | |
156 | #define AT_XDMAC_CC_WRIP (0x1 << 23) /* Write in Progress (read only) */ | |
157 | #define AT_XDMAC_CC_WRIP_DONE (0x0 << 23) | |
158 | #define AT_XDMAC_CC_WRIP_IN_PROGRESS (0x1 << 23) | |
159 | #define AT_XDMAC_CC_PERID(i) (0x7f & (h) << 24) /* Channel Peripheral Identifier */ | |
160 | #define AT_XDMAC_CDS_MSP 0x2C /* Channel Data Stride Memory Set Pattern */ | |
161 | #define AT_XDMAC_CSUS 0x30 /* Channel Source Microblock Stride */ | |
162 | #define AT_XDMAC_CDUS 0x34 /* Channel Destination Microblock Stride */ | |
163 | ||
164 | #define AT_XDMAC_CHAN_REG_BASE 0x50 /* Channel registers base address */ | |
165 | ||
166 | /* Microblock control members */ | |
167 | #define AT_XDMAC_MBR_UBC_UBLEN_MAX 0xFFFFFFUL /* Maximum Microblock Length */ | |
168 | #define AT_XDMAC_MBR_UBC_NDE (0x1 << 24) /* Next Descriptor Enable */ | |
169 | #define AT_XDMAC_MBR_UBC_NSEN (0x1 << 25) /* Next Descriptor Source Update */ | |
170 | #define AT_XDMAC_MBR_UBC_NDEN (0x1 << 26) /* Next Descriptor Destination Update */ | |
171 | #define AT_XDMAC_MBR_UBC_NDV0 (0x0 << 27) /* Next Descriptor View 0 */ | |
172 | #define AT_XDMAC_MBR_UBC_NDV1 (0x1 << 27) /* Next Descriptor View 1 */ | |
173 | #define AT_XDMAC_MBR_UBC_NDV2 (0x2 << 27) /* Next Descriptor View 2 */ | |
174 | #define AT_XDMAC_MBR_UBC_NDV3 (0x3 << 27) /* Next Descriptor View 3 */ | |
175 | ||
176 | #define AT_XDMAC_MAX_CHAN 0x20 | |
765c37d8 LD |
177 | #define AT_XDMAC_MAX_CSIZE 16 /* 16 data */ |
178 | #define AT_XDMAC_MAX_DWIDTH 8 /* 64 bits */ | |
e1f7c9ee | 179 | |
8ac82f88 LD |
180 | #define AT_XDMAC_DMA_BUSWIDTHS\ |
181 | (BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) |\ | |
182 | BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |\ | |
183 | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |\ | |
184 | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |\ | |
185 | BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)) | |
186 | ||
e1f7c9ee LD |
187 | enum atc_status { |
188 | AT_XDMAC_CHAN_IS_CYCLIC = 0, | |
189 | AT_XDMAC_CHAN_IS_PAUSED, | |
190 | }; | |
191 | ||
192 | /* ----- Channels ----- */ | |
193 | struct at_xdmac_chan { | |
194 | struct dma_chan chan; | |
195 | void __iomem *ch_regs; | |
196 | u32 mask; /* Channel Mask */ | |
765c37d8 | 197 | u32 cfg; /* Channel Configuration Register */ |
e1f7c9ee LD |
198 | u8 perid; /* Peripheral ID */ |
199 | u8 perif; /* Peripheral Interface */ | |
200 | u8 memif; /* Memory Interface */ | |
734bb9a7 | 201 | u32 save_cc; |
e1f7c9ee LD |
202 | u32 save_cim; |
203 | u32 save_cnda; | |
204 | u32 save_cndc; | |
205 | unsigned long status; | |
206 | struct tasklet_struct tasklet; | |
765c37d8 | 207 | struct dma_slave_config sconfig; |
e1f7c9ee LD |
208 | |
209 | spinlock_t lock; | |
210 | ||
211 | struct list_head xfers_list; | |
212 | struct list_head free_descs_list; | |
213 | }; | |
214 | ||
215 | ||
216 | /* ----- Controller ----- */ | |
217 | struct at_xdmac { | |
218 | struct dma_device dma; | |
219 | void __iomem *regs; | |
220 | int irq; | |
221 | struct clk *clk; | |
222 | u32 save_gim; | |
223 | u32 save_gs; | |
224 | struct dma_pool *at_xdmac_desc_pool; | |
225 | struct at_xdmac_chan chan[0]; | |
226 | }; | |
227 | ||
228 | ||
229 | /* ----- Descriptors ----- */ | |
230 | ||
231 | /* Linked List Descriptor */ | |
232 | struct at_xdmac_lld { | |
233 | dma_addr_t mbr_nda; /* Next Descriptor Member */ | |
234 | u32 mbr_ubc; /* Microblock Control Member */ | |
235 | dma_addr_t mbr_sa; /* Source Address Member */ | |
236 | dma_addr_t mbr_da; /* Destination Address Member */ | |
237 | u32 mbr_cfg; /* Configuration Register */ | |
ee0fe35c MR |
238 | u32 mbr_bc; /* Block Control Register */ |
239 | u32 mbr_ds; /* Data Stride Register */ | |
240 | u32 mbr_sus; /* Source Microblock Stride Register */ | |
241 | u32 mbr_dus; /* Destination Microblock Stride Register */ | |
e1f7c9ee LD |
242 | }; |
243 | ||
244 | ||
245 | struct at_xdmac_desc { | |
246 | struct at_xdmac_lld lld; | |
247 | enum dma_transfer_direction direction; | |
248 | struct dma_async_tx_descriptor tx_dma_desc; | |
249 | struct list_head desc_node; | |
250 | /* Following members are only used by the first descriptor */ | |
251 | bool active_xfer; | |
252 | unsigned int xfer_size; | |
253 | struct list_head descs_list; | |
254 | struct list_head xfer_node; | |
255 | }; | |
256 | ||
257 | static inline void __iomem *at_xdmac_chan_reg_base(struct at_xdmac *atxdmac, unsigned int chan_nb) | |
258 | { | |
259 | return atxdmac->regs + (AT_XDMAC_CHAN_REG_BASE + chan_nb * 0x40); | |
260 | } | |
261 | ||
6e5ae29b | 262 | #define at_xdmac_read(atxdmac, reg) readl_relaxed((atxdmac)->regs + (reg)) |
e1f7c9ee | 263 | #define at_xdmac_write(atxdmac, reg, value) \ |
6e5ae29b | 264 | writel_relaxed((value), (atxdmac)->regs + (reg)) |
e1f7c9ee | 265 | |
6e5ae29b LD |
266 | #define at_xdmac_chan_read(atchan, reg) readl_relaxed((atchan)->ch_regs + (reg)) |
267 | #define at_xdmac_chan_write(atchan, reg, value) writel_relaxed((value), (atchan)->ch_regs + (reg)) | |
e1f7c9ee LD |
268 | |
269 | static inline struct at_xdmac_chan *to_at_xdmac_chan(struct dma_chan *dchan) | |
270 | { | |
271 | return container_of(dchan, struct at_xdmac_chan, chan); | |
272 | } | |
273 | ||
274 | static struct device *chan2dev(struct dma_chan *chan) | |
275 | { | |
276 | return &chan->dev->device; | |
277 | } | |
278 | ||
279 | static inline struct at_xdmac *to_at_xdmac(struct dma_device *ddev) | |
280 | { | |
281 | return container_of(ddev, struct at_xdmac, dma); | |
282 | } | |
283 | ||
284 | static inline struct at_xdmac_desc *txd_to_at_desc(struct dma_async_tx_descriptor *txd) | |
285 | { | |
286 | return container_of(txd, struct at_xdmac_desc, tx_dma_desc); | |
287 | } | |
288 | ||
289 | static inline int at_xdmac_chan_is_cyclic(struct at_xdmac_chan *atchan) | |
290 | { | |
291 | return test_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status); | |
292 | } | |
293 | ||
294 | static inline int at_xdmac_chan_is_paused(struct at_xdmac_chan *atchan) | |
295 | { | |
296 | return test_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status); | |
297 | } | |
298 | ||
299 | static inline int at_xdmac_csize(u32 maxburst) | |
300 | { | |
301 | int csize; | |
302 | ||
303 | csize = ffs(maxburst) - 1; | |
304 | if (csize > 4) | |
305 | csize = -EINVAL; | |
306 | ||
307 | return csize; | |
308 | }; | |
309 | ||
310 | static inline u8 at_xdmac_get_dwidth(u32 cfg) | |
311 | { | |
312 | return (cfg & AT_XDMAC_CC_DWIDTH_MASK) >> AT_XDMAC_CC_DWIDTH_OFFSET; | |
313 | }; | |
314 | ||
315 | static unsigned int init_nr_desc_per_channel = 64; | |
316 | module_param(init_nr_desc_per_channel, uint, 0644); | |
317 | MODULE_PARM_DESC(init_nr_desc_per_channel, | |
318 | "initial descriptors per channel (default: 64)"); | |
319 | ||
320 | ||
321 | static bool at_xdmac_chan_is_enabled(struct at_xdmac_chan *atchan) | |
322 | { | |
323 | return at_xdmac_chan_read(atchan, AT_XDMAC_GS) & atchan->mask; | |
324 | } | |
325 | ||
326 | static void at_xdmac_off(struct at_xdmac *atxdmac) | |
327 | { | |
328 | at_xdmac_write(atxdmac, AT_XDMAC_GD, -1L); | |
329 | ||
330 | /* Wait that all chans are disabled. */ | |
331 | while (at_xdmac_read(atxdmac, AT_XDMAC_GS)) | |
332 | cpu_relax(); | |
333 | ||
334 | at_xdmac_write(atxdmac, AT_XDMAC_GID, -1L); | |
335 | } | |
336 | ||
337 | /* Call with lock hold. */ | |
338 | static void at_xdmac_start_xfer(struct at_xdmac_chan *atchan, | |
339 | struct at_xdmac_desc *first) | |
340 | { | |
341 | struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device); | |
342 | u32 reg; | |
343 | ||
344 | dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, first); | |
345 | ||
346 | if (at_xdmac_chan_is_enabled(atchan)) | |
347 | return; | |
348 | ||
349 | /* Set transfer as active to not try to start it again. */ | |
350 | first->active_xfer = true; | |
351 | ||
352 | /* Tell xdmac where to get the first descriptor. */ | |
353 | reg = AT_XDMAC_CNDA_NDA(first->tx_dma_desc.phys) | |
354 | | AT_XDMAC_CNDA_NDAIF(atchan->memif); | |
355 | at_xdmac_chan_write(atchan, AT_XDMAC_CNDA, reg); | |
356 | ||
357 | /* | |
6d3a7d9e | 358 | * When doing non cyclic transfer we need to use the next |
e1f7c9ee LD |
359 | * descriptor view 2 since some fields of the configuration register |
360 | * depend on transfer size and src/dest addresses. | |
361 | */ | |
20cadcb4 | 362 | if (at_xdmac_chan_is_cyclic(atchan)) |
e1f7c9ee | 363 | reg = AT_XDMAC_CNDC_NDVIEW_NDV1; |
20cadcb4 | 364 | else if (first->lld.mbr_ubc & AT_XDMAC_MBR_UBC_NDV3) |
ee0fe35c | 365 | reg = AT_XDMAC_CNDC_NDVIEW_NDV3; |
20cadcb4 | 366 | else |
e1f7c9ee | 367 | reg = AT_XDMAC_CNDC_NDVIEW_NDV2; |
20cadcb4 LD |
368 | /* |
369 | * Even if the register will be updated from the configuration in the | |
370 | * descriptor when using view 2 or higher, the PROT bit won't be set | |
371 | * properly. This bit can be modified only by using the channel | |
372 | * configuration register. | |
373 | */ | |
374 | at_xdmac_chan_write(atchan, AT_XDMAC_CC, first->lld.mbr_cfg); | |
e1f7c9ee LD |
375 | |
376 | reg |= AT_XDMAC_CNDC_NDDUP | |
377 | | AT_XDMAC_CNDC_NDSUP | |
378 | | AT_XDMAC_CNDC_NDE; | |
379 | at_xdmac_chan_write(atchan, AT_XDMAC_CNDC, reg); | |
380 | ||
381 | dev_vdbg(chan2dev(&atchan->chan), | |
382 | "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n", | |
383 | __func__, at_xdmac_chan_read(atchan, AT_XDMAC_CC), | |
384 | at_xdmac_chan_read(atchan, AT_XDMAC_CNDA), | |
385 | at_xdmac_chan_read(atchan, AT_XDMAC_CNDC), | |
386 | at_xdmac_chan_read(atchan, AT_XDMAC_CSA), | |
387 | at_xdmac_chan_read(atchan, AT_XDMAC_CDA), | |
388 | at_xdmac_chan_read(atchan, AT_XDMAC_CUBC)); | |
389 | ||
390 | at_xdmac_chan_write(atchan, AT_XDMAC_CID, 0xffffffff); | |
391 | reg = AT_XDMAC_CIE_RBEIE | AT_XDMAC_CIE_WBEIE | AT_XDMAC_CIE_ROIE; | |
392 | /* | |
393 | * There is no end of list when doing cyclic dma, we need to get | |
394 | * an interrupt after each periods. | |
395 | */ | |
396 | if (at_xdmac_chan_is_cyclic(atchan)) | |
397 | at_xdmac_chan_write(atchan, AT_XDMAC_CIE, | |
398 | reg | AT_XDMAC_CIE_BIE); | |
399 | else | |
400 | at_xdmac_chan_write(atchan, AT_XDMAC_CIE, | |
401 | reg | AT_XDMAC_CIE_LIE); | |
402 | at_xdmac_write(atxdmac, AT_XDMAC_GIE, atchan->mask); | |
403 | dev_vdbg(chan2dev(&atchan->chan), | |
404 | "%s: enable channel (0x%08x)\n", __func__, atchan->mask); | |
405 | wmb(); | |
406 | at_xdmac_write(atxdmac, AT_XDMAC_GE, atchan->mask); | |
407 | ||
408 | dev_vdbg(chan2dev(&atchan->chan), | |
409 | "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n", | |
410 | __func__, at_xdmac_chan_read(atchan, AT_XDMAC_CC), | |
411 | at_xdmac_chan_read(atchan, AT_XDMAC_CNDA), | |
412 | at_xdmac_chan_read(atchan, AT_XDMAC_CNDC), | |
413 | at_xdmac_chan_read(atchan, AT_XDMAC_CSA), | |
414 | at_xdmac_chan_read(atchan, AT_XDMAC_CDA), | |
415 | at_xdmac_chan_read(atchan, AT_XDMAC_CUBC)); | |
416 | ||
417 | } | |
418 | ||
419 | static dma_cookie_t at_xdmac_tx_submit(struct dma_async_tx_descriptor *tx) | |
420 | { | |
421 | struct at_xdmac_desc *desc = txd_to_at_desc(tx); | |
422 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(tx->chan); | |
423 | dma_cookie_t cookie; | |
4c374fc7 | 424 | unsigned long irqflags; |
e1f7c9ee | 425 | |
4c374fc7 | 426 | spin_lock_irqsave(&atchan->lock, irqflags); |
e1f7c9ee LD |
427 | cookie = dma_cookie_assign(tx); |
428 | ||
429 | dev_vdbg(chan2dev(tx->chan), "%s: atchan 0x%p, add desc 0x%p to xfers_list\n", | |
430 | __func__, atchan, desc); | |
431 | list_add_tail(&desc->xfer_node, &atchan->xfers_list); | |
432 | if (list_is_singular(&atchan->xfers_list)) | |
433 | at_xdmac_start_xfer(atchan, desc); | |
434 | ||
4c374fc7 | 435 | spin_unlock_irqrestore(&atchan->lock, irqflags); |
e1f7c9ee LD |
436 | return cookie; |
437 | } | |
438 | ||
439 | static struct at_xdmac_desc *at_xdmac_alloc_desc(struct dma_chan *chan, | |
440 | gfp_t gfp_flags) | |
441 | { | |
442 | struct at_xdmac_desc *desc; | |
443 | struct at_xdmac *atxdmac = to_at_xdmac(chan->device); | |
444 | dma_addr_t phys; | |
445 | ||
446 | desc = dma_pool_alloc(atxdmac->at_xdmac_desc_pool, gfp_flags, &phys); | |
447 | if (desc) { | |
448 | memset(desc, 0, sizeof(*desc)); | |
449 | INIT_LIST_HEAD(&desc->descs_list); | |
450 | dma_async_tx_descriptor_init(&desc->tx_dma_desc, chan); | |
451 | desc->tx_dma_desc.tx_submit = at_xdmac_tx_submit; | |
452 | desc->tx_dma_desc.phys = phys; | |
453 | } | |
454 | ||
455 | return desc; | |
456 | } | |
457 | ||
458 | /* Call must be protected by lock. */ | |
459 | static struct at_xdmac_desc *at_xdmac_get_desc(struct at_xdmac_chan *atchan) | |
460 | { | |
461 | struct at_xdmac_desc *desc; | |
462 | ||
463 | if (list_empty(&atchan->free_descs_list)) { | |
464 | desc = at_xdmac_alloc_desc(&atchan->chan, GFP_NOWAIT); | |
465 | } else { | |
466 | desc = list_first_entry(&atchan->free_descs_list, | |
467 | struct at_xdmac_desc, desc_node); | |
468 | list_del(&desc->desc_node); | |
469 | desc->active_xfer = false; | |
470 | } | |
471 | ||
472 | return desc; | |
473 | } | |
474 | ||
0d0ee751 MR |
475 | static void at_xdmac_queue_desc(struct dma_chan *chan, |
476 | struct at_xdmac_desc *prev, | |
477 | struct at_xdmac_desc *desc) | |
478 | { | |
479 | if (!prev || !desc) | |
480 | return; | |
481 | ||
482 | prev->lld.mbr_nda = desc->tx_dma_desc.phys; | |
483 | prev->lld.mbr_ubc |= AT_XDMAC_MBR_UBC_NDE; | |
484 | ||
485 | dev_dbg(chan2dev(chan), "%s: chain lld: prev=0x%p, mbr_nda=%pad\n", | |
486 | __func__, prev, &prev->lld.mbr_nda); | |
487 | } | |
488 | ||
6007ccb5 MR |
489 | static inline void at_xdmac_increment_block_count(struct dma_chan *chan, |
490 | struct at_xdmac_desc *desc) | |
491 | { | |
492 | if (!desc) | |
493 | return; | |
494 | ||
495 | desc->lld.mbr_bc++; | |
496 | ||
497 | dev_dbg(chan2dev(chan), | |
498 | "%s: incrementing the block count of the desc 0x%p\n", | |
499 | __func__, desc); | |
500 | } | |
501 | ||
e1f7c9ee LD |
502 | static struct dma_chan *at_xdmac_xlate(struct of_phandle_args *dma_spec, |
503 | struct of_dma *of_dma) | |
504 | { | |
505 | struct at_xdmac *atxdmac = of_dma->of_dma_data; | |
506 | struct at_xdmac_chan *atchan; | |
507 | struct dma_chan *chan; | |
508 | struct device *dev = atxdmac->dma.dev; | |
509 | ||
510 | if (dma_spec->args_count != 1) { | |
511 | dev_err(dev, "dma phandler args: bad number of args\n"); | |
512 | return NULL; | |
513 | } | |
514 | ||
515 | chan = dma_get_any_slave_channel(&atxdmac->dma); | |
516 | if (!chan) { | |
517 | dev_err(dev, "can't get a dma channel\n"); | |
518 | return NULL; | |
519 | } | |
520 | ||
521 | atchan = to_at_xdmac_chan(chan); | |
522 | atchan->memif = AT91_XDMAC_DT_GET_MEM_IF(dma_spec->args[0]); | |
523 | atchan->perif = AT91_XDMAC_DT_GET_PER_IF(dma_spec->args[0]); | |
524 | atchan->perid = AT91_XDMAC_DT_GET_PERID(dma_spec->args[0]); | |
525 | dev_dbg(dev, "chan dt cfg: memif=%u perif=%u perid=%u\n", | |
526 | atchan->memif, atchan->perif, atchan->perid); | |
527 | ||
528 | return chan; | |
529 | } | |
530 | ||
765c37d8 LD |
531 | static int at_xdmac_compute_chan_conf(struct dma_chan *chan, |
532 | enum dma_transfer_direction direction) | |
533 | { | |
534 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); | |
535 | int csize, dwidth; | |
536 | ||
537 | if (direction == DMA_DEV_TO_MEM) { | |
538 | atchan->cfg = | |
539 | AT91_XDMAC_DT_PERID(atchan->perid) | |
540 | | AT_XDMAC_CC_DAM_INCREMENTED_AM | |
541 | | AT_XDMAC_CC_SAM_FIXED_AM | |
542 | | AT_XDMAC_CC_DIF(atchan->memif) | |
543 | | AT_XDMAC_CC_SIF(atchan->perif) | |
544 | | AT_XDMAC_CC_SWREQ_HWR_CONNECTED | |
545 | | AT_XDMAC_CC_DSYNC_PER2MEM | |
546 | | AT_XDMAC_CC_MBSIZE_SIXTEEN | |
547 | | AT_XDMAC_CC_TYPE_PER_TRAN; | |
548 | csize = ffs(atchan->sconfig.src_maxburst) - 1; | |
549 | if (csize < 0) { | |
550 | dev_err(chan2dev(chan), "invalid src maxburst value\n"); | |
551 | return -EINVAL; | |
552 | } | |
553 | atchan->cfg |= AT_XDMAC_CC_CSIZE(csize); | |
554 | dwidth = ffs(atchan->sconfig.src_addr_width) - 1; | |
555 | if (dwidth < 0) { | |
556 | dev_err(chan2dev(chan), "invalid src addr width value\n"); | |
557 | return -EINVAL; | |
558 | } | |
559 | atchan->cfg |= AT_XDMAC_CC_DWIDTH(dwidth); | |
560 | } else if (direction == DMA_MEM_TO_DEV) { | |
561 | atchan->cfg = | |
562 | AT91_XDMAC_DT_PERID(atchan->perid) | |
563 | | AT_XDMAC_CC_DAM_FIXED_AM | |
564 | | AT_XDMAC_CC_SAM_INCREMENTED_AM | |
565 | | AT_XDMAC_CC_DIF(atchan->perif) | |
566 | | AT_XDMAC_CC_SIF(atchan->memif) | |
567 | | AT_XDMAC_CC_SWREQ_HWR_CONNECTED | |
568 | | AT_XDMAC_CC_DSYNC_MEM2PER | |
569 | | AT_XDMAC_CC_MBSIZE_SIXTEEN | |
570 | | AT_XDMAC_CC_TYPE_PER_TRAN; | |
571 | csize = ffs(atchan->sconfig.dst_maxburst) - 1; | |
572 | if (csize < 0) { | |
573 | dev_err(chan2dev(chan), "invalid src maxburst value\n"); | |
574 | return -EINVAL; | |
575 | } | |
576 | atchan->cfg |= AT_XDMAC_CC_CSIZE(csize); | |
577 | dwidth = ffs(atchan->sconfig.dst_addr_width) - 1; | |
578 | if (dwidth < 0) { | |
579 | dev_err(chan2dev(chan), "invalid dst addr width value\n"); | |
580 | return -EINVAL; | |
581 | } | |
582 | atchan->cfg |= AT_XDMAC_CC_DWIDTH(dwidth); | |
583 | } | |
584 | ||
585 | dev_dbg(chan2dev(chan), "%s: cfg=0x%08x\n", __func__, atchan->cfg); | |
586 | ||
587 | return 0; | |
588 | } | |
589 | ||
590 | /* | |
591 | * Only check that maxburst and addr width values are supported by the | |
592 | * the controller but not that the configuration is good to perform the | |
593 | * transfer since we don't know the direction at this stage. | |
594 | */ | |
595 | static int at_xdmac_check_slave_config(struct dma_slave_config *sconfig) | |
596 | { | |
597 | if ((sconfig->src_maxburst > AT_XDMAC_MAX_CSIZE) | |
598 | || (sconfig->dst_maxburst > AT_XDMAC_MAX_CSIZE)) | |
599 | return -EINVAL; | |
600 | ||
601 | if ((sconfig->src_addr_width > AT_XDMAC_MAX_DWIDTH) | |
602 | || (sconfig->dst_addr_width > AT_XDMAC_MAX_DWIDTH)) | |
603 | return -EINVAL; | |
604 | ||
605 | return 0; | |
606 | } | |
607 | ||
e1f7c9ee LD |
608 | static int at_xdmac_set_slave_config(struct dma_chan *chan, |
609 | struct dma_slave_config *sconfig) | |
610 | { | |
611 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); | |
e1f7c9ee | 612 | |
765c37d8 LD |
613 | if (at_xdmac_check_slave_config(sconfig)) { |
614 | dev_err(chan2dev(chan), "invalid slave configuration\n"); | |
e1f7c9ee LD |
615 | return -EINVAL; |
616 | } | |
e1f7c9ee | 617 | |
765c37d8 | 618 | memcpy(&atchan->sconfig, sconfig, sizeof(atchan->sconfig)); |
e1f7c9ee LD |
619 | |
620 | return 0; | |
621 | } | |
622 | ||
623 | static struct dma_async_tx_descriptor * | |
624 | at_xdmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
625 | unsigned int sg_len, enum dma_transfer_direction direction, | |
626 | unsigned long flags, void *context) | |
627 | { | |
35ca0ee4 LD |
628 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); |
629 | struct at_xdmac_desc *first = NULL, *prev = NULL; | |
630 | struct scatterlist *sg; | |
631 | int i; | |
632 | unsigned int xfer_size = 0; | |
633 | unsigned long irqflags; | |
4c374fc7 | 634 | struct dma_async_tx_descriptor *ret = NULL; |
e1f7c9ee LD |
635 | |
636 | if (!sgl) | |
637 | return NULL; | |
638 | ||
639 | if (!is_slave_direction(direction)) { | |
640 | dev_err(chan2dev(chan), "invalid DMA direction\n"); | |
641 | return NULL; | |
642 | } | |
643 | ||
644 | dev_dbg(chan2dev(chan), "%s: sg_len=%d, dir=%s, flags=0x%lx\n", | |
645 | __func__, sg_len, | |
646 | direction == DMA_MEM_TO_DEV ? "to device" : "from device", | |
647 | flags); | |
648 | ||
649 | /* Protect dma_sconfig field that can be modified by set_slave_conf. */ | |
4c374fc7 | 650 | spin_lock_irqsave(&atchan->lock, irqflags); |
e1f7c9ee | 651 | |
765c37d8 LD |
652 | if (at_xdmac_compute_chan_conf(chan, direction)) |
653 | goto spin_unlock; | |
654 | ||
e1f7c9ee LD |
655 | /* Prepare descriptors. */ |
656 | for_each_sg(sgl, sg, sg_len, i) { | |
657 | struct at_xdmac_desc *desc = NULL; | |
6d3a7d9e | 658 | u32 len, mem, dwidth, fixed_dwidth; |
e1f7c9ee LD |
659 | |
660 | len = sg_dma_len(sg); | |
661 | mem = sg_dma_address(sg); | |
662 | if (unlikely(!len)) { | |
663 | dev_err(chan2dev(chan), "sg data length is zero\n"); | |
4c374fc7 | 664 | goto spin_unlock; |
e1f7c9ee LD |
665 | } |
666 | dev_dbg(chan2dev(chan), "%s: * sg%d len=%u, mem=0x%08x\n", | |
667 | __func__, i, len, mem); | |
668 | ||
669 | desc = at_xdmac_get_desc(atchan); | |
670 | if (!desc) { | |
671 | dev_err(chan2dev(chan), "can't get descriptor\n"); | |
672 | if (first) | |
673 | list_splice_init(&first->descs_list, &atchan->free_descs_list); | |
4c374fc7 | 674 | goto spin_unlock; |
e1f7c9ee LD |
675 | } |
676 | ||
677 | /* Linked list descriptor setup. */ | |
678 | if (direction == DMA_DEV_TO_MEM) { | |
765c37d8 | 679 | desc->lld.mbr_sa = atchan->sconfig.src_addr; |
e1f7c9ee | 680 | desc->lld.mbr_da = mem; |
e1f7c9ee LD |
681 | } else { |
682 | desc->lld.mbr_sa = mem; | |
765c37d8 | 683 | desc->lld.mbr_da = atchan->sconfig.dst_addr; |
e1f7c9ee | 684 | } |
1c8a38b1 | 685 | dwidth = at_xdmac_get_dwidth(atchan->cfg); |
6d3a7d9e | 686 | fixed_dwidth = IS_ALIGNED(len, 1 << dwidth) |
1c8a38b1 | 687 | ? dwidth |
6d3a7d9e LD |
688 | : AT_XDMAC_CC_DWIDTH_BYTE; |
689 | desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV2 /* next descriptor view */ | |
be835074 LD |
690 | | AT_XDMAC_MBR_UBC_NDEN /* next descriptor dst parameter update */ |
691 | | AT_XDMAC_MBR_UBC_NSEN /* next descriptor src parameter update */ | |
6d3a7d9e | 692 | | (len >> fixed_dwidth); /* microblock length */ |
1c8a38b1 CP |
693 | desc->lld.mbr_cfg = (atchan->cfg & ~AT_XDMAC_CC_DWIDTH_MASK) | |
694 | AT_XDMAC_CC_DWIDTH(fixed_dwidth); | |
e1f7c9ee | 695 | dev_dbg(chan2dev(chan), |
82e24246 VK |
696 | "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n", |
697 | __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc); | |
e1f7c9ee LD |
698 | |
699 | /* Chain lld. */ | |
0d0ee751 MR |
700 | if (prev) |
701 | at_xdmac_queue_desc(chan, prev, desc); | |
e1f7c9ee LD |
702 | |
703 | prev = desc; | |
704 | if (!first) | |
705 | first = desc; | |
706 | ||
707 | dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n", | |
708 | __func__, desc, first); | |
709 | list_add_tail(&desc->desc_node, &first->descs_list); | |
57819276 | 710 | xfer_size += len; |
e1f7c9ee LD |
711 | } |
712 | ||
e1f7c9ee LD |
713 | |
714 | first->tx_dma_desc.flags = flags; | |
57819276 | 715 | first->xfer_size = xfer_size; |
e1f7c9ee | 716 | first->direction = direction; |
4c374fc7 | 717 | ret = &first->tx_dma_desc; |
e1f7c9ee | 718 | |
4c374fc7 LD |
719 | spin_unlock: |
720 | spin_unlock_irqrestore(&atchan->lock, irqflags); | |
721 | return ret; | |
e1f7c9ee LD |
722 | } |
723 | ||
724 | static struct dma_async_tx_descriptor * | |
725 | at_xdmac_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, | |
726 | size_t buf_len, size_t period_len, | |
727 | enum dma_transfer_direction direction, | |
728 | unsigned long flags) | |
729 | { | |
730 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); | |
731 | struct at_xdmac_desc *first = NULL, *prev = NULL; | |
732 | unsigned int periods = buf_len / period_len; | |
733 | int i; | |
4c374fc7 | 734 | unsigned long irqflags; |
e1f7c9ee | 735 | |
82e24246 VK |
736 | dev_dbg(chan2dev(chan), "%s: buf_addr=%pad, buf_len=%zd, period_len=%zd, dir=%s, flags=0x%lx\n", |
737 | __func__, &buf_addr, buf_len, period_len, | |
e1f7c9ee LD |
738 | direction == DMA_MEM_TO_DEV ? "mem2per" : "per2mem", flags); |
739 | ||
740 | if (!is_slave_direction(direction)) { | |
741 | dev_err(chan2dev(chan), "invalid DMA direction\n"); | |
742 | return NULL; | |
743 | } | |
744 | ||
745 | if (test_and_set_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status)) { | |
746 | dev_err(chan2dev(chan), "channel currently used\n"); | |
747 | return NULL; | |
748 | } | |
749 | ||
765c37d8 LD |
750 | if (at_xdmac_compute_chan_conf(chan, direction)) |
751 | return NULL; | |
752 | ||
e1f7c9ee LD |
753 | for (i = 0; i < periods; i++) { |
754 | struct at_xdmac_desc *desc = NULL; | |
755 | ||
4c374fc7 | 756 | spin_lock_irqsave(&atchan->lock, irqflags); |
e1f7c9ee LD |
757 | desc = at_xdmac_get_desc(atchan); |
758 | if (!desc) { | |
759 | dev_err(chan2dev(chan), "can't get descriptor\n"); | |
760 | if (first) | |
761 | list_splice_init(&first->descs_list, &atchan->free_descs_list); | |
4c374fc7 | 762 | spin_unlock_irqrestore(&atchan->lock, irqflags); |
e1f7c9ee LD |
763 | return NULL; |
764 | } | |
4c374fc7 | 765 | spin_unlock_irqrestore(&atchan->lock, irqflags); |
e1f7c9ee | 766 | dev_dbg(chan2dev(chan), |
82e24246 VK |
767 | "%s: desc=0x%p, tx_dma_desc.phys=%pad\n", |
768 | __func__, desc, &desc->tx_dma_desc.phys); | |
e1f7c9ee LD |
769 | |
770 | if (direction == DMA_DEV_TO_MEM) { | |
765c37d8 | 771 | desc->lld.mbr_sa = atchan->sconfig.src_addr; |
e1f7c9ee | 772 | desc->lld.mbr_da = buf_addr + i * period_len; |
e1f7c9ee LD |
773 | } else { |
774 | desc->lld.mbr_sa = buf_addr + i * period_len; | |
765c37d8 | 775 | desc->lld.mbr_da = atchan->sconfig.dst_addr; |
5ac7d582 | 776 | } |
765c37d8 | 777 | desc->lld.mbr_cfg = atchan->cfg; |
e1f7c9ee LD |
778 | desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV1 |
779 | | AT_XDMAC_MBR_UBC_NDEN | |
780 | | AT_XDMAC_MBR_UBC_NSEN | |
6eb9d3c1 | 781 | | period_len >> at_xdmac_get_dwidth(desc->lld.mbr_cfg); |
e1f7c9ee LD |
782 | |
783 | dev_dbg(chan2dev(chan), | |
82e24246 VK |
784 | "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n", |
785 | __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc); | |
e1f7c9ee LD |
786 | |
787 | /* Chain lld. */ | |
0d0ee751 MR |
788 | if (prev) |
789 | at_xdmac_queue_desc(chan, prev, desc); | |
e1f7c9ee LD |
790 | |
791 | prev = desc; | |
792 | if (!first) | |
793 | first = desc; | |
794 | ||
795 | dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n", | |
796 | __func__, desc, first); | |
797 | list_add_tail(&desc->desc_node, &first->descs_list); | |
798 | } | |
799 | ||
e900c30d | 800 | at_xdmac_queue_desc(chan, prev, first); |
e1f7c9ee LD |
801 | first->tx_dma_desc.flags = flags; |
802 | first->xfer_size = buf_len; | |
803 | first->direction = direction; | |
804 | ||
805 | return &first->tx_dma_desc; | |
806 | } | |
807 | ||
f0816a36 MR |
808 | static inline u32 at_xdmac_align_width(struct dma_chan *chan, dma_addr_t addr) |
809 | { | |
810 | u32 width; | |
811 | ||
812 | /* | |
813 | * Check address alignment to select the greater data width we | |
814 | * can use. | |
815 | * | |
816 | * Some XDMAC implementations don't provide dword transfer, in | |
817 | * this case selecting dword has the same behavior as | |
818 | * selecting word transfers. | |
819 | */ | |
820 | if (!(addr & 7)) { | |
821 | width = AT_XDMAC_CC_DWIDTH_DWORD; | |
822 | dev_dbg(chan2dev(chan), "%s: dwidth: double word\n", __func__); | |
823 | } else if (!(addr & 3)) { | |
824 | width = AT_XDMAC_CC_DWIDTH_WORD; | |
825 | dev_dbg(chan2dev(chan), "%s: dwidth: word\n", __func__); | |
826 | } else if (!(addr & 1)) { | |
827 | width = AT_XDMAC_CC_DWIDTH_HALFWORD; | |
828 | dev_dbg(chan2dev(chan), "%s: dwidth: half word\n", __func__); | |
829 | } else { | |
830 | width = AT_XDMAC_CC_DWIDTH_BYTE; | |
831 | dev_dbg(chan2dev(chan), "%s: dwidth: byte\n", __func__); | |
832 | } | |
833 | ||
834 | return width; | |
835 | } | |
836 | ||
6007ccb5 MR |
837 | static struct at_xdmac_desc * |
838 | at_xdmac_interleaved_queue_desc(struct dma_chan *chan, | |
839 | struct at_xdmac_chan *atchan, | |
840 | struct at_xdmac_desc *prev, | |
841 | dma_addr_t src, dma_addr_t dst, | |
842 | struct dma_interleaved_template *xt, | |
843 | struct data_chunk *chunk) | |
844 | { | |
845 | struct at_xdmac_desc *desc; | |
846 | u32 dwidth; | |
847 | unsigned long flags; | |
848 | size_t ublen; | |
849 | /* | |
850 | * WARNING: The channel configuration is set here since there is no | |
851 | * dmaengine_slave_config call in this case. Moreover we don't know the | |
852 | * direction, it involves we can't dynamically set the source and dest | |
853 | * interface so we have to use the same one. Only interface 0 allows EBI | |
854 | * access. Hopefully we can access DDR through both ports (at least on | |
855 | * SAMA5D4x), so we can use the same interface for source and dest, | |
856 | * that solves the fact we don't know the direction. | |
857 | */ | |
858 | u32 chan_cc = AT_XDMAC_CC_DIF(0) | |
859 | | AT_XDMAC_CC_SIF(0) | |
860 | | AT_XDMAC_CC_MBSIZE_SIXTEEN | |
861 | | AT_XDMAC_CC_TYPE_MEM_TRAN; | |
862 | ||
863 | dwidth = at_xdmac_align_width(chan, src | dst | chunk->size); | |
864 | if (chunk->size >= (AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth)) { | |
865 | dev_dbg(chan2dev(chan), | |
866 | "%s: chunk too big (%d, max size %lu)...\n", | |
867 | __func__, chunk->size, | |
868 | AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth); | |
869 | return NULL; | |
870 | } | |
871 | ||
872 | if (prev) | |
873 | dev_dbg(chan2dev(chan), | |
874 | "Adding items at the end of desc 0x%p\n", prev); | |
875 | ||
876 | if (xt->src_inc) { | |
877 | if (xt->src_sgl) | |
878 | chan_cc |= AT_XDMAC_CC_SAM_UBS_DS_AM; | |
879 | else | |
880 | chan_cc |= AT_XDMAC_CC_SAM_INCREMENTED_AM; | |
881 | } | |
882 | ||
883 | if (xt->dst_inc) { | |
884 | if (xt->dst_sgl) | |
885 | chan_cc |= AT_XDMAC_CC_DAM_UBS_DS_AM; | |
886 | else | |
887 | chan_cc |= AT_XDMAC_CC_DAM_INCREMENTED_AM; | |
888 | } | |
889 | ||
890 | spin_lock_irqsave(&atchan->lock, flags); | |
891 | desc = at_xdmac_get_desc(atchan); | |
892 | spin_unlock_irqrestore(&atchan->lock, flags); | |
893 | if (!desc) { | |
894 | dev_err(chan2dev(chan), "can't get descriptor\n"); | |
895 | return NULL; | |
896 | } | |
897 | ||
898 | chan_cc |= AT_XDMAC_CC_DWIDTH(dwidth); | |
899 | ||
900 | ublen = chunk->size >> dwidth; | |
901 | ||
902 | desc->lld.mbr_sa = src; | |
903 | desc->lld.mbr_da = dst; | |
87d001ef MR |
904 | desc->lld.mbr_sus = dmaengine_get_src_icg(xt, chunk); |
905 | desc->lld.mbr_dus = dmaengine_get_dst_icg(xt, chunk); | |
6007ccb5 MR |
906 | |
907 | desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV3 | |
908 | | AT_XDMAC_MBR_UBC_NDEN | |
909 | | AT_XDMAC_MBR_UBC_NSEN | |
910 | | ublen; | |
911 | desc->lld.mbr_cfg = chan_cc; | |
912 | ||
913 | dev_dbg(chan2dev(chan), | |
914 | "%s: lld: mbr_sa=0x%08x, mbr_da=0x%08x, mbr_ubc=0x%08x, mbr_cfg=0x%08x\n", | |
915 | __func__, desc->lld.mbr_sa, desc->lld.mbr_da, | |
916 | desc->lld.mbr_ubc, desc->lld.mbr_cfg); | |
917 | ||
918 | /* Chain lld. */ | |
919 | if (prev) | |
920 | at_xdmac_queue_desc(chan, prev, desc); | |
921 | ||
922 | return desc; | |
923 | } | |
924 | ||
6007ccb5 MR |
925 | static struct dma_async_tx_descriptor * |
926 | at_xdmac_prep_interleaved(struct dma_chan *chan, | |
927 | struct dma_interleaved_template *xt, | |
928 | unsigned long flags) | |
929 | { | |
930 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); | |
931 | struct at_xdmac_desc *prev = NULL, *first = NULL; | |
932 | struct data_chunk *chunk, *prev_chunk = NULL; | |
933 | dma_addr_t dst_addr, src_addr; | |
934 | size_t dst_skip, src_skip, len = 0; | |
935 | size_t prev_dst_icg = 0, prev_src_icg = 0; | |
936 | int i; | |
937 | ||
938 | if (!xt || (xt->numf != 1) || (xt->dir != DMA_MEM_TO_MEM)) | |
939 | return NULL; | |
940 | ||
941 | dev_dbg(chan2dev(chan), "%s: src=0x%08x, dest=0x%08x, numf=%d, frame_size=%d, flags=0x%lx\n", | |
942 | __func__, xt->src_start, xt->dst_start, xt->numf, | |
943 | xt->frame_size, flags); | |
944 | ||
945 | src_addr = xt->src_start; | |
946 | dst_addr = xt->dst_start; | |
947 | ||
948 | for (i = 0; i < xt->frame_size; i++) { | |
949 | struct at_xdmac_desc *desc; | |
950 | size_t src_icg, dst_icg; | |
951 | ||
952 | chunk = xt->sgl + i; | |
953 | ||
87d001ef MR |
954 | dst_icg = dmaengine_get_dst_icg(xt, chunk); |
955 | src_icg = dmaengine_get_src_icg(xt, chunk); | |
6007ccb5 MR |
956 | |
957 | src_skip = chunk->size + src_icg; | |
958 | dst_skip = chunk->size + dst_icg; | |
959 | ||
960 | dev_dbg(chan2dev(chan), | |
961 | "%s: chunk size=%d, src icg=%d, dst icg=%d\n", | |
962 | __func__, chunk->size, src_icg, dst_icg); | |
963 | ||
964 | /* | |
965 | * Handle the case where we just have the same | |
966 | * transfer to setup, we can just increase the | |
967 | * block number and reuse the same descriptor. | |
968 | */ | |
969 | if (prev_chunk && prev && | |
970 | (prev_chunk->size == chunk->size) && | |
971 | (prev_src_icg == src_icg) && | |
972 | (prev_dst_icg == dst_icg)) { | |
973 | dev_dbg(chan2dev(chan), | |
974 | "%s: same configuration that the previous chunk, merging the descriptors...\n", | |
975 | __func__); | |
976 | at_xdmac_increment_block_count(chan, prev); | |
977 | continue; | |
978 | } | |
979 | ||
980 | desc = at_xdmac_interleaved_queue_desc(chan, atchan, | |
981 | prev, | |
982 | src_addr, dst_addr, | |
983 | xt, chunk); | |
984 | if (!desc) { | |
985 | list_splice_init(&first->descs_list, | |
986 | &atchan->free_descs_list); | |
987 | return NULL; | |
988 | } | |
989 | ||
990 | if (!first) | |
991 | first = desc; | |
992 | ||
993 | dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n", | |
994 | __func__, desc, first); | |
995 | list_add_tail(&desc->desc_node, &first->descs_list); | |
996 | ||
997 | if (xt->src_sgl) | |
998 | src_addr += src_skip; | |
999 | ||
1000 | if (xt->dst_sgl) | |
1001 | dst_addr += dst_skip; | |
1002 | ||
1003 | len += chunk->size; | |
1004 | prev_chunk = chunk; | |
1005 | prev_dst_icg = dst_icg; | |
1006 | prev_src_icg = src_icg; | |
1007 | prev = desc; | |
1008 | } | |
1009 | ||
1010 | first->tx_dma_desc.cookie = -EBUSY; | |
1011 | first->tx_dma_desc.flags = flags; | |
1012 | first->xfer_size = len; | |
1013 | ||
1014 | return &first->tx_dma_desc; | |
1015 | } | |
1016 | ||
e1f7c9ee LD |
1017 | static struct dma_async_tx_descriptor * |
1018 | at_xdmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
1019 | size_t len, unsigned long flags) | |
1020 | { | |
1021 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); | |
1022 | struct at_xdmac_desc *first = NULL, *prev = NULL; | |
1023 | size_t remaining_size = len, xfer_size = 0, ublen; | |
1024 | dma_addr_t src_addr = src, dst_addr = dest; | |
1025 | u32 dwidth; | |
1026 | /* | |
1027 | * WARNING: We don't know the direction, it involves we can't | |
1028 | * dynamically set the source and dest interface so we have to use the | |
1029 | * same one. Only interface 0 allows EBI access. Hopefully we can | |
1030 | * access DDR through both ports (at least on SAMA5D4x), so we can use | |
1031 | * the same interface for source and dest, that solves the fact we | |
1032 | * don't know the direction. | |
1033 | */ | |
1034 | u32 chan_cc = AT_XDMAC_CC_DAM_INCREMENTED_AM | |
1035 | | AT_XDMAC_CC_SAM_INCREMENTED_AM | |
1036 | | AT_XDMAC_CC_DIF(0) | |
1037 | | AT_XDMAC_CC_SIF(0) | |
1038 | | AT_XDMAC_CC_MBSIZE_SIXTEEN | |
1039 | | AT_XDMAC_CC_TYPE_MEM_TRAN; | |
4c374fc7 | 1040 | unsigned long irqflags; |
e1f7c9ee | 1041 | |
82e24246 VK |
1042 | dev_dbg(chan2dev(chan), "%s: src=%pad, dest=%pad, len=%zd, flags=0x%lx\n", |
1043 | __func__, &src, &dest, len, flags); | |
e1f7c9ee LD |
1044 | |
1045 | if (unlikely(!len)) | |
1046 | return NULL; | |
1047 | ||
f0816a36 | 1048 | dwidth = at_xdmac_align_width(chan, src_addr | dst_addr); |
e1f7c9ee LD |
1049 | |
1050 | /* Prepare descriptors. */ | |
1051 | while (remaining_size) { | |
1052 | struct at_xdmac_desc *desc = NULL; | |
1053 | ||
c66ec04e | 1054 | dev_dbg(chan2dev(chan), "%s: remaining_size=%zu\n", __func__, remaining_size); |
e1f7c9ee | 1055 | |
4c374fc7 | 1056 | spin_lock_irqsave(&atchan->lock, irqflags); |
e1f7c9ee | 1057 | desc = at_xdmac_get_desc(atchan); |
4c374fc7 | 1058 | spin_unlock_irqrestore(&atchan->lock, irqflags); |
e1f7c9ee LD |
1059 | if (!desc) { |
1060 | dev_err(chan2dev(chan), "can't get descriptor\n"); | |
1061 | if (first) | |
1062 | list_splice_init(&first->descs_list, &atchan->free_descs_list); | |
1063 | return NULL; | |
1064 | } | |
1065 | ||
1066 | /* Update src and dest addresses. */ | |
1067 | src_addr += xfer_size; | |
1068 | dst_addr += xfer_size; | |
1069 | ||
1070 | if (remaining_size >= AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth) | |
1071 | xfer_size = AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth; | |
1072 | else | |
1073 | xfer_size = remaining_size; | |
1074 | ||
c66ec04e | 1075 | dev_dbg(chan2dev(chan), "%s: xfer_size=%zu\n", __func__, xfer_size); |
e1f7c9ee LD |
1076 | |
1077 | /* Check remaining length and change data width if needed. */ | |
f0816a36 MR |
1078 | dwidth = at_xdmac_align_width(chan, |
1079 | src_addr | dst_addr | xfer_size); | |
e1f7c9ee LD |
1080 | chan_cc |= AT_XDMAC_CC_DWIDTH(dwidth); |
1081 | ||
1082 | ublen = xfer_size >> dwidth; | |
1083 | remaining_size -= xfer_size; | |
1084 | ||
1085 | desc->lld.mbr_sa = src_addr; | |
1086 | desc->lld.mbr_da = dst_addr; | |
1087 | desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV2 | |
1088 | | AT_XDMAC_MBR_UBC_NDEN | |
1089 | | AT_XDMAC_MBR_UBC_NSEN | |
e1f7c9ee LD |
1090 | | ublen; |
1091 | desc->lld.mbr_cfg = chan_cc; | |
1092 | ||
1093 | dev_dbg(chan2dev(chan), | |
82e24246 VK |
1094 | "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x, mbr_cfg=0x%08x\n", |
1095 | __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc, desc->lld.mbr_cfg); | |
e1f7c9ee LD |
1096 | |
1097 | /* Chain lld. */ | |
0d0ee751 MR |
1098 | if (prev) |
1099 | at_xdmac_queue_desc(chan, prev, desc); | |
e1f7c9ee LD |
1100 | |
1101 | prev = desc; | |
1102 | if (!first) | |
1103 | first = desc; | |
1104 | ||
1105 | dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n", | |
1106 | __func__, desc, first); | |
1107 | list_add_tail(&desc->desc_node, &first->descs_list); | |
1108 | } | |
1109 | ||
1110 | first->tx_dma_desc.flags = flags; | |
1111 | first->xfer_size = len; | |
1112 | ||
1113 | return &first->tx_dma_desc; | |
1114 | } | |
1115 | ||
b206d9a2 MR |
1116 | static struct at_xdmac_desc *at_xdmac_memset_create_desc(struct dma_chan *chan, |
1117 | struct at_xdmac_chan *atchan, | |
1118 | dma_addr_t dst_addr, | |
1119 | size_t len, | |
1120 | int value) | |
1121 | { | |
1122 | struct at_xdmac_desc *desc; | |
1123 | unsigned long flags; | |
1124 | size_t ublen; | |
1125 | u32 dwidth; | |
1126 | /* | |
1127 | * WARNING: The channel configuration is set here since there is no | |
1128 | * dmaengine_slave_config call in this case. Moreover we don't know the | |
1129 | * direction, it involves we can't dynamically set the source and dest | |
1130 | * interface so we have to use the same one. Only interface 0 allows EBI | |
1131 | * access. Hopefully we can access DDR through both ports (at least on | |
1132 | * SAMA5D4x), so we can use the same interface for source and dest, | |
1133 | * that solves the fact we don't know the direction. | |
1134 | */ | |
67a6eedc | 1135 | u32 chan_cc = AT_XDMAC_CC_DAM_UBS_AM |
b206d9a2 MR |
1136 | | AT_XDMAC_CC_SAM_INCREMENTED_AM |
1137 | | AT_XDMAC_CC_DIF(0) | |
1138 | | AT_XDMAC_CC_SIF(0) | |
1139 | | AT_XDMAC_CC_MBSIZE_SIXTEEN | |
1140 | | AT_XDMAC_CC_MEMSET_HW_MODE | |
1141 | | AT_XDMAC_CC_TYPE_MEM_TRAN; | |
1142 | ||
1143 | dwidth = at_xdmac_align_width(chan, dst_addr); | |
1144 | ||
1145 | if (len >= (AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth)) { | |
1146 | dev_err(chan2dev(chan), | |
1147 | "%s: Transfer too large, aborting...\n", | |
1148 | __func__); | |
1149 | return NULL; | |
1150 | } | |
1151 | ||
1152 | spin_lock_irqsave(&atchan->lock, flags); | |
1153 | desc = at_xdmac_get_desc(atchan); | |
1154 | spin_unlock_irqrestore(&atchan->lock, flags); | |
1155 | if (!desc) { | |
1156 | dev_err(chan2dev(chan), "can't get descriptor\n"); | |
1157 | return NULL; | |
1158 | } | |
1159 | ||
1160 | chan_cc |= AT_XDMAC_CC_DWIDTH(dwidth); | |
1161 | ||
1162 | ublen = len >> dwidth; | |
1163 | ||
1164 | desc->lld.mbr_da = dst_addr; | |
1165 | desc->lld.mbr_ds = value; | |
1166 | desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV3 | |
1167 | | AT_XDMAC_MBR_UBC_NDEN | |
1168 | | AT_XDMAC_MBR_UBC_NSEN | |
1169 | | ublen; | |
1170 | desc->lld.mbr_cfg = chan_cc; | |
1171 | ||
1172 | dev_dbg(chan2dev(chan), | |
1173 | "%s: lld: mbr_da=0x%08x, mbr_ds=0x%08x, mbr_ubc=0x%08x, mbr_cfg=0x%08x\n", | |
1174 | __func__, desc->lld.mbr_da, desc->lld.mbr_ds, desc->lld.mbr_ubc, | |
1175 | desc->lld.mbr_cfg); | |
1176 | ||
1177 | return desc; | |
1178 | } | |
1179 | ||
1180 | struct dma_async_tx_descriptor * | |
1181 | at_xdmac_prep_dma_memset(struct dma_chan *chan, dma_addr_t dest, int value, | |
1182 | size_t len, unsigned long flags) | |
1183 | { | |
1184 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); | |
1185 | struct at_xdmac_desc *desc; | |
1186 | ||
1187 | dev_dbg(chan2dev(chan), "%s: dest=0x%08x, len=%d, pattern=0x%x, flags=0x%lx\n", | |
1188 | __func__, dest, len, value, flags); | |
1189 | ||
1190 | if (unlikely(!len)) | |
1191 | return NULL; | |
1192 | ||
1193 | desc = at_xdmac_memset_create_desc(chan, atchan, dest, len, value); | |
1194 | list_add_tail(&desc->desc_node, &desc->descs_list); | |
1195 | ||
1196 | desc->tx_dma_desc.cookie = -EBUSY; | |
1197 | desc->tx_dma_desc.flags = flags; | |
1198 | desc->xfer_size = len; | |
1199 | ||
1200 | return &desc->tx_dma_desc; | |
1201 | } | |
1202 | ||
67a6eedc MR |
1203 | static struct dma_async_tx_descriptor * |
1204 | at_xdmac_prep_dma_memset_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
1205 | unsigned int sg_len, int value, | |
1206 | unsigned long flags) | |
1207 | { | |
1208 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); | |
1209 | struct at_xdmac_desc *desc, *pdesc = NULL, | |
1210 | *ppdesc = NULL, *first = NULL; | |
1211 | struct scatterlist *sg, *psg = NULL, *ppsg = NULL; | |
1212 | size_t stride = 0, pstride = 0, len = 0; | |
1213 | int i; | |
1214 | ||
1215 | if (!sgl) | |
1216 | return NULL; | |
1217 | ||
1218 | dev_dbg(chan2dev(chan), "%s: sg_len=%d, value=0x%x, flags=0x%lx\n", | |
1219 | __func__, sg_len, value, flags); | |
1220 | ||
1221 | /* Prepare descriptors. */ | |
1222 | for_each_sg(sgl, sg, sg_len, i) { | |
1223 | dev_dbg(chan2dev(chan), "%s: dest=0x%08x, len=%d, pattern=0x%x, flags=0x%lx\n", | |
1224 | __func__, sg_dma_address(sg), sg_dma_len(sg), | |
1225 | value, flags); | |
1226 | desc = at_xdmac_memset_create_desc(chan, atchan, | |
1227 | sg_dma_address(sg), | |
1228 | sg_dma_len(sg), | |
1229 | value); | |
1230 | if (!desc && first) | |
1231 | list_splice_init(&first->descs_list, | |
1232 | &atchan->free_descs_list); | |
1233 | ||
1234 | if (!first) | |
1235 | first = desc; | |
1236 | ||
1237 | /* Update our strides */ | |
1238 | pstride = stride; | |
1239 | if (psg) | |
1240 | stride = sg_dma_address(sg) - | |
1241 | (sg_dma_address(psg) + sg_dma_len(psg)); | |
1242 | ||
1243 | /* | |
1244 | * The scatterlist API gives us only the address and | |
1245 | * length of each elements. | |
1246 | * | |
1247 | * Unfortunately, we don't have the stride, which we | |
1248 | * will need to compute. | |
1249 | * | |
1250 | * That make us end up in a situation like this one: | |
1251 | * len stride len stride len | |
1252 | * +-------+ +-------+ +-------+ | |
1253 | * | N-2 | | N-1 | | N | | |
1254 | * +-------+ +-------+ +-------+ | |
1255 | * | |
1256 | * We need all these three elements (N-2, N-1 and N) | |
1257 | * to actually take the decision on whether we need to | |
1258 | * queue N-1 or reuse N-2. | |
1259 | * | |
1260 | * We will only consider N if it is the last element. | |
1261 | */ | |
1262 | if (ppdesc && pdesc) { | |
1263 | if ((stride == pstride) && | |
1264 | (sg_dma_len(ppsg) == sg_dma_len(psg))) { | |
1265 | dev_dbg(chan2dev(chan), | |
1266 | "%s: desc 0x%p can be merged with desc 0x%p\n", | |
1267 | __func__, pdesc, ppdesc); | |
1268 | ||
1269 | /* | |
1270 | * Increment the block count of the | |
1271 | * N-2 descriptor | |
1272 | */ | |
1273 | at_xdmac_increment_block_count(chan, ppdesc); | |
1274 | ppdesc->lld.mbr_dus = stride; | |
1275 | ||
1276 | /* | |
1277 | * Put back the N-1 descriptor in the | |
1278 | * free descriptor list | |
1279 | */ | |
1280 | list_add_tail(&pdesc->desc_node, | |
1281 | &atchan->free_descs_list); | |
1282 | ||
1283 | /* | |
1284 | * Make our N-1 descriptor pointer | |
1285 | * point to the N-2 since they were | |
1286 | * actually merged. | |
1287 | */ | |
1288 | pdesc = ppdesc; | |
1289 | ||
1290 | /* | |
1291 | * Rule out the case where we don't have | |
1292 | * pstride computed yet (our second sg | |
1293 | * element) | |
1294 | * | |
1295 | * We also want to catch the case where there | |
1296 | * would be a negative stride, | |
1297 | */ | |
1298 | } else if (pstride || | |
1299 | sg_dma_address(sg) < sg_dma_address(psg)) { | |
1300 | /* | |
1301 | * Queue the N-1 descriptor after the | |
1302 | * N-2 | |
1303 | */ | |
1304 | at_xdmac_queue_desc(chan, ppdesc, pdesc); | |
1305 | ||
1306 | /* | |
1307 | * Add the N-1 descriptor to the list | |
1308 | * of the descriptors used for this | |
1309 | * transfer | |
1310 | */ | |
1311 | list_add_tail(&desc->desc_node, | |
1312 | &first->descs_list); | |
1313 | dev_dbg(chan2dev(chan), | |
1314 | "%s: add desc 0x%p to descs_list 0x%p\n", | |
1315 | __func__, desc, first); | |
1316 | } | |
1317 | } | |
1318 | ||
1319 | /* | |
1320 | * If we are the last element, just see if we have the | |
1321 | * same size than the previous element. | |
1322 | * | |
1323 | * If so, we can merge it with the previous descriptor | |
1324 | * since we don't care about the stride anymore. | |
1325 | */ | |
1326 | if ((i == (sg_len - 1)) && | |
1327 | sg_dma_len(ppsg) == sg_dma_len(psg)) { | |
1328 | dev_dbg(chan2dev(chan), | |
1329 | "%s: desc 0x%p can be merged with desc 0x%p\n", | |
1330 | __func__, desc, pdesc); | |
1331 | ||
1332 | /* | |
1333 | * Increment the block count of the N-1 | |
1334 | * descriptor | |
1335 | */ | |
1336 | at_xdmac_increment_block_count(chan, pdesc); | |
1337 | pdesc->lld.mbr_dus = stride; | |
1338 | ||
1339 | /* | |
1340 | * Put back the N descriptor in the free | |
1341 | * descriptor list | |
1342 | */ | |
1343 | list_add_tail(&desc->desc_node, | |
1344 | &atchan->free_descs_list); | |
1345 | } | |
1346 | ||
1347 | /* Update our descriptors */ | |
1348 | ppdesc = pdesc; | |
1349 | pdesc = desc; | |
1350 | ||
1351 | /* Update our scatter pointers */ | |
1352 | ppsg = psg; | |
1353 | psg = sg; | |
1354 | ||
1355 | len += sg_dma_len(sg); | |
1356 | } | |
1357 | ||
1358 | first->tx_dma_desc.cookie = -EBUSY; | |
1359 | first->tx_dma_desc.flags = flags; | |
1360 | first->xfer_size = len; | |
1361 | ||
1362 | return &first->tx_dma_desc; | |
1363 | } | |
1364 | ||
e1f7c9ee LD |
1365 | static enum dma_status |
1366 | at_xdmac_tx_status(struct dma_chan *chan, dma_cookie_t cookie, | |
1367 | struct dma_tx_state *txstate) | |
1368 | { | |
1369 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); | |
1370 | struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device); | |
1371 | struct at_xdmac_desc *desc, *_desc; | |
1372 | struct list_head *descs_list; | |
1373 | enum dma_status ret; | |
1374 | int residue; | |
4e097820 | 1375 | u32 cur_nda, mask, value; |
be835074 | 1376 | u8 dwidth = 0; |
4c374fc7 | 1377 | unsigned long flags; |
e1f7c9ee LD |
1378 | |
1379 | ret = dma_cookie_status(chan, cookie, txstate); | |
1380 | if (ret == DMA_COMPLETE) | |
1381 | return ret; | |
1382 | ||
1383 | if (!txstate) | |
1384 | return ret; | |
1385 | ||
4c374fc7 | 1386 | spin_lock_irqsave(&atchan->lock, flags); |
e1f7c9ee LD |
1387 | |
1388 | desc = list_first_entry(&atchan->xfers_list, struct at_xdmac_desc, xfer_node); | |
1389 | ||
1390 | /* | |
1391 | * If the transfer has not been started yet, don't need to compute the | |
1392 | * residue, it's the transfer length. | |
1393 | */ | |
1394 | if (!desc->active_xfer) { | |
1395 | dma_set_residue(txstate, desc->xfer_size); | |
4c374fc7 | 1396 | goto spin_unlock; |
e1f7c9ee LD |
1397 | } |
1398 | ||
1399 | residue = desc->xfer_size; | |
4e097820 CP |
1400 | /* |
1401 | * Flush FIFO: only relevant when the transfer is source peripheral | |
1402 | * synchronized. | |
1403 | */ | |
1404 | mask = AT_XDMAC_CC_TYPE | AT_XDMAC_CC_DSYNC; | |
1405 | value = AT_XDMAC_CC_TYPE_PER_TRAN | AT_XDMAC_CC_DSYNC_PER2MEM; | |
be835074 | 1406 | if ((desc->lld.mbr_cfg & mask) == value) { |
4e097820 CP |
1407 | at_xdmac_write(atxdmac, AT_XDMAC_GSWF, atchan->mask); |
1408 | while (!(at_xdmac_chan_read(atchan, AT_XDMAC_CIS) & AT_XDMAC_CIS_FIS)) | |
1409 | cpu_relax(); | |
1410 | } | |
e1f7c9ee LD |
1411 | |
1412 | cur_nda = at_xdmac_chan_read(atchan, AT_XDMAC_CNDA) & 0xfffffffc; | |
1413 | /* | |
1414 | * Remove size of all microblocks already transferred and the current | |
1415 | * one. Then add the remaining size to transfer of the current | |
1416 | * microblock. | |
1417 | */ | |
1418 | descs_list = &desc->descs_list; | |
1419 | list_for_each_entry_safe(desc, _desc, descs_list, desc_node) { | |
be835074 | 1420 | dwidth = at_xdmac_get_dwidth(desc->lld.mbr_cfg); |
e1f7c9ee LD |
1421 | residue -= (desc->lld.mbr_ubc & 0xffffff) << dwidth; |
1422 | if ((desc->lld.mbr_nda & 0xfffffffc) == cur_nda) | |
1423 | break; | |
1424 | } | |
1425 | residue += at_xdmac_chan_read(atchan, AT_XDMAC_CUBC) << dwidth; | |
1426 | ||
e1f7c9ee LD |
1427 | dma_set_residue(txstate, residue); |
1428 | ||
1429 | dev_dbg(chan2dev(chan), | |
82e24246 VK |
1430 | "%s: desc=0x%p, tx_dma_desc.phys=%pad, tx_status=%d, cookie=%d, residue=%d\n", |
1431 | __func__, desc, &desc->tx_dma_desc.phys, ret, cookie, residue); | |
e1f7c9ee | 1432 | |
4c374fc7 LD |
1433 | spin_unlock: |
1434 | spin_unlock_irqrestore(&atchan->lock, flags); | |
e1f7c9ee LD |
1435 | return ret; |
1436 | } | |
1437 | ||
1438 | /* Call must be protected by lock. */ | |
1439 | static void at_xdmac_remove_xfer(struct at_xdmac_chan *atchan, | |
1440 | struct at_xdmac_desc *desc) | |
1441 | { | |
1442 | dev_dbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc); | |
1443 | ||
1444 | /* | |
1445 | * Remove the transfer from the transfer list then move the transfer | |
1446 | * descriptors into the free descriptors list. | |
1447 | */ | |
1448 | list_del(&desc->xfer_node); | |
1449 | list_splice_init(&desc->descs_list, &atchan->free_descs_list); | |
1450 | } | |
1451 | ||
1452 | static void at_xdmac_advance_work(struct at_xdmac_chan *atchan) | |
1453 | { | |
1454 | struct at_xdmac_desc *desc; | |
4c374fc7 | 1455 | unsigned long flags; |
e1f7c9ee | 1456 | |
4c374fc7 | 1457 | spin_lock_irqsave(&atchan->lock, flags); |
e1f7c9ee LD |
1458 | |
1459 | /* | |
1460 | * If channel is enabled, do nothing, advance_work will be triggered | |
1461 | * after the interruption. | |
1462 | */ | |
1463 | if (!at_xdmac_chan_is_enabled(atchan) && !list_empty(&atchan->xfers_list)) { | |
1464 | desc = list_first_entry(&atchan->xfers_list, | |
1465 | struct at_xdmac_desc, | |
1466 | xfer_node); | |
1467 | dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc); | |
1468 | if (!desc->active_xfer) | |
1469 | at_xdmac_start_xfer(atchan, desc); | |
1470 | } | |
1471 | ||
4c374fc7 | 1472 | spin_unlock_irqrestore(&atchan->lock, flags); |
e1f7c9ee LD |
1473 | } |
1474 | ||
1475 | static void at_xdmac_handle_cyclic(struct at_xdmac_chan *atchan) | |
1476 | { | |
1477 | struct at_xdmac_desc *desc; | |
1478 | struct dma_async_tx_descriptor *txd; | |
1479 | ||
1480 | desc = list_first_entry(&atchan->xfers_list, struct at_xdmac_desc, xfer_node); | |
1481 | txd = &desc->tx_dma_desc; | |
1482 | ||
1483 | if (txd->callback && (txd->flags & DMA_PREP_INTERRUPT)) | |
1484 | txd->callback(txd->callback_param); | |
1485 | } | |
1486 | ||
1487 | static void at_xdmac_tasklet(unsigned long data) | |
1488 | { | |
1489 | struct at_xdmac_chan *atchan = (struct at_xdmac_chan *)data; | |
1490 | struct at_xdmac_desc *desc; | |
1491 | u32 error_mask; | |
1492 | ||
1493 | dev_dbg(chan2dev(&atchan->chan), "%s: status=0x%08lx\n", | |
1494 | __func__, atchan->status); | |
1495 | ||
1496 | error_mask = AT_XDMAC_CIS_RBEIS | |
1497 | | AT_XDMAC_CIS_WBEIS | |
1498 | | AT_XDMAC_CIS_ROIS; | |
1499 | ||
1500 | if (at_xdmac_chan_is_cyclic(atchan)) { | |
1501 | at_xdmac_handle_cyclic(atchan); | |
1502 | } else if ((atchan->status & AT_XDMAC_CIS_LIS) | |
1503 | || (atchan->status & error_mask)) { | |
1504 | struct dma_async_tx_descriptor *txd; | |
1505 | ||
1506 | if (atchan->status & AT_XDMAC_CIS_RBEIS) | |
1507 | dev_err(chan2dev(&atchan->chan), "read bus error!!!"); | |
1508 | if (atchan->status & AT_XDMAC_CIS_WBEIS) | |
1509 | dev_err(chan2dev(&atchan->chan), "write bus error!!!"); | |
1510 | if (atchan->status & AT_XDMAC_CIS_ROIS) | |
1511 | dev_err(chan2dev(&atchan->chan), "request overflow error!!!"); | |
1512 | ||
1513 | spin_lock_bh(&atchan->lock); | |
1514 | desc = list_first_entry(&atchan->xfers_list, | |
1515 | struct at_xdmac_desc, | |
1516 | xfer_node); | |
1517 | dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc); | |
1518 | BUG_ON(!desc->active_xfer); | |
1519 | ||
1520 | txd = &desc->tx_dma_desc; | |
1521 | ||
1522 | at_xdmac_remove_xfer(atchan, desc); | |
1523 | spin_unlock_bh(&atchan->lock); | |
1524 | ||
1525 | if (!at_xdmac_chan_is_cyclic(atchan)) { | |
1526 | dma_cookie_complete(txd); | |
1527 | if (txd->callback && (txd->flags & DMA_PREP_INTERRUPT)) | |
1528 | txd->callback(txd->callback_param); | |
1529 | } | |
1530 | ||
1531 | dma_run_dependencies(txd); | |
1532 | ||
1533 | at_xdmac_advance_work(atchan); | |
1534 | } | |
1535 | } | |
1536 | ||
1537 | static irqreturn_t at_xdmac_interrupt(int irq, void *dev_id) | |
1538 | { | |
1539 | struct at_xdmac *atxdmac = (struct at_xdmac *)dev_id; | |
1540 | struct at_xdmac_chan *atchan; | |
1541 | u32 imr, status, pending; | |
1542 | u32 chan_imr, chan_status; | |
1543 | int i, ret = IRQ_NONE; | |
1544 | ||
1545 | do { | |
1546 | imr = at_xdmac_read(atxdmac, AT_XDMAC_GIM); | |
1547 | status = at_xdmac_read(atxdmac, AT_XDMAC_GIS); | |
1548 | pending = status & imr; | |
1549 | ||
1550 | dev_vdbg(atxdmac->dma.dev, | |
1551 | "%s: status=0x%08x, imr=0x%08x, pending=0x%08x\n", | |
1552 | __func__, status, imr, pending); | |
1553 | ||
1554 | if (!pending) | |
1555 | break; | |
1556 | ||
1557 | /* We have to find which channel has generated the interrupt. */ | |
1558 | for (i = 0; i < atxdmac->dma.chancnt; i++) { | |
1559 | if (!((1 << i) & pending)) | |
1560 | continue; | |
1561 | ||
1562 | atchan = &atxdmac->chan[i]; | |
1563 | chan_imr = at_xdmac_chan_read(atchan, AT_XDMAC_CIM); | |
1564 | chan_status = at_xdmac_chan_read(atchan, AT_XDMAC_CIS); | |
1565 | atchan->status = chan_status & chan_imr; | |
1566 | dev_vdbg(atxdmac->dma.dev, | |
1567 | "%s: chan%d: imr=0x%x, status=0x%x\n", | |
1568 | __func__, i, chan_imr, chan_status); | |
1569 | dev_vdbg(chan2dev(&atchan->chan), | |
1570 | "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n", | |
1571 | __func__, | |
1572 | at_xdmac_chan_read(atchan, AT_XDMAC_CC), | |
1573 | at_xdmac_chan_read(atchan, AT_XDMAC_CNDA), | |
1574 | at_xdmac_chan_read(atchan, AT_XDMAC_CNDC), | |
1575 | at_xdmac_chan_read(atchan, AT_XDMAC_CSA), | |
1576 | at_xdmac_chan_read(atchan, AT_XDMAC_CDA), | |
1577 | at_xdmac_chan_read(atchan, AT_XDMAC_CUBC)); | |
1578 | ||
1579 | if (atchan->status & (AT_XDMAC_CIS_RBEIS | AT_XDMAC_CIS_WBEIS)) | |
1580 | at_xdmac_write(atxdmac, AT_XDMAC_GD, atchan->mask); | |
1581 | ||
1582 | tasklet_schedule(&atchan->tasklet); | |
1583 | ret = IRQ_HANDLED; | |
1584 | } | |
1585 | ||
1586 | } while (pending); | |
1587 | ||
1588 | return ret; | |
1589 | } | |
1590 | ||
1591 | static void at_xdmac_issue_pending(struct dma_chan *chan) | |
1592 | { | |
1593 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); | |
1594 | ||
1595 | dev_dbg(chan2dev(&atchan->chan), "%s\n", __func__); | |
1596 | ||
1597 | if (!at_xdmac_chan_is_cyclic(atchan)) | |
1598 | at_xdmac_advance_work(atchan); | |
1599 | ||
1600 | return; | |
1601 | } | |
1602 | ||
3d138877 LD |
1603 | static int at_xdmac_device_config(struct dma_chan *chan, |
1604 | struct dma_slave_config *config) | |
1605 | { | |
1606 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); | |
1607 | int ret; | |
4c374fc7 | 1608 | unsigned long flags; |
3d138877 LD |
1609 | |
1610 | dev_dbg(chan2dev(chan), "%s\n", __func__); | |
1611 | ||
4c374fc7 | 1612 | spin_lock_irqsave(&atchan->lock, flags); |
3d138877 | 1613 | ret = at_xdmac_set_slave_config(chan, config); |
4c374fc7 | 1614 | spin_unlock_irqrestore(&atchan->lock, flags); |
3d138877 LD |
1615 | |
1616 | return ret; | |
1617 | } | |
1618 | ||
1619 | static int at_xdmac_device_pause(struct dma_chan *chan) | |
e1f7c9ee | 1620 | { |
e1f7c9ee LD |
1621 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); |
1622 | struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device); | |
4c374fc7 | 1623 | unsigned long flags; |
e1f7c9ee | 1624 | |
3d138877 | 1625 | dev_dbg(chan2dev(chan), "%s\n", __func__); |
e1f7c9ee | 1626 | |
cbb85e67 CP |
1627 | if (test_and_set_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status)) |
1628 | return 0; | |
1629 | ||
4c374fc7 | 1630 | spin_lock_irqsave(&atchan->lock, flags); |
3d138877 | 1631 | at_xdmac_write(atxdmac, AT_XDMAC_GRWS, atchan->mask); |
cbb85e67 CP |
1632 | while (at_xdmac_chan_read(atchan, AT_XDMAC_CC) |
1633 | & (AT_XDMAC_CC_WRIP | AT_XDMAC_CC_RDIP)) | |
1634 | cpu_relax(); | |
4c374fc7 | 1635 | spin_unlock_irqrestore(&atchan->lock, flags); |
e1f7c9ee | 1636 | |
3d138877 LD |
1637 | return 0; |
1638 | } | |
e1f7c9ee | 1639 | |
3d138877 LD |
1640 | static int at_xdmac_device_resume(struct dma_chan *chan) |
1641 | { | |
1642 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); | |
1643 | struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device); | |
4c374fc7 | 1644 | unsigned long flags; |
e1f7c9ee | 1645 | |
3d138877 | 1646 | dev_dbg(chan2dev(chan), "%s\n", __func__); |
e1f7c9ee | 1647 | |
4c374fc7 | 1648 | spin_lock_irqsave(&atchan->lock, flags); |
0434a231 | 1649 | if (!at_xdmac_chan_is_paused(atchan)) { |
4c374fc7 | 1650 | spin_unlock_irqrestore(&atchan->lock, flags); |
3d138877 | 1651 | return 0; |
0434a231 | 1652 | } |
e1f7c9ee | 1653 | |
3d138877 LD |
1654 | at_xdmac_write(atxdmac, AT_XDMAC_GRWR, atchan->mask); |
1655 | clear_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status); | |
4c374fc7 | 1656 | spin_unlock_irqrestore(&atchan->lock, flags); |
3d138877 LD |
1657 | |
1658 | return 0; | |
1659 | } | |
e1f7c9ee | 1660 | |
3d138877 LD |
1661 | static int at_xdmac_device_terminate_all(struct dma_chan *chan) |
1662 | { | |
1663 | struct at_xdmac_desc *desc, *_desc; | |
1664 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); | |
1665 | struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device); | |
4c374fc7 | 1666 | unsigned long flags; |
e1f7c9ee | 1667 | |
3d138877 | 1668 | dev_dbg(chan2dev(chan), "%s\n", __func__); |
e1f7c9ee | 1669 | |
4c374fc7 | 1670 | spin_lock_irqsave(&atchan->lock, flags); |
3d138877 LD |
1671 | at_xdmac_write(atxdmac, AT_XDMAC_GD, atchan->mask); |
1672 | while (at_xdmac_read(atxdmac, AT_XDMAC_GS) & atchan->mask) | |
1673 | cpu_relax(); | |
e1f7c9ee | 1674 | |
3d138877 LD |
1675 | /* Cancel all pending transfers. */ |
1676 | list_for_each_entry_safe(desc, _desc, &atchan->xfers_list, xfer_node) | |
1677 | at_xdmac_remove_xfer(atchan, desc); | |
e1f7c9ee | 1678 | |
3d138877 | 1679 | clear_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status); |
4c374fc7 | 1680 | spin_unlock_irqrestore(&atchan->lock, flags); |
e1f7c9ee | 1681 | |
3d138877 | 1682 | return 0; |
e1f7c9ee LD |
1683 | } |
1684 | ||
1685 | static int at_xdmac_alloc_chan_resources(struct dma_chan *chan) | |
1686 | { | |
1687 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); | |
1688 | struct at_xdmac_desc *desc; | |
1689 | int i; | |
4c374fc7 | 1690 | unsigned long flags; |
e1f7c9ee | 1691 | |
4c374fc7 | 1692 | spin_lock_irqsave(&atchan->lock, flags); |
e1f7c9ee LD |
1693 | |
1694 | if (at_xdmac_chan_is_enabled(atchan)) { | |
1695 | dev_err(chan2dev(chan), | |
1696 | "can't allocate channel resources (channel enabled)\n"); | |
1697 | i = -EIO; | |
1698 | goto spin_unlock; | |
1699 | } | |
1700 | ||
1701 | if (!list_empty(&atchan->free_descs_list)) { | |
1702 | dev_err(chan2dev(chan), | |
1703 | "can't allocate channel resources (channel not free from a previous use)\n"); | |
1704 | i = -EIO; | |
1705 | goto spin_unlock; | |
1706 | } | |
1707 | ||
1708 | for (i = 0; i < init_nr_desc_per_channel; i++) { | |
1709 | desc = at_xdmac_alloc_desc(chan, GFP_ATOMIC); | |
1710 | if (!desc) { | |
1711 | dev_warn(chan2dev(chan), | |
1712 | "only %d descriptors have been allocated\n", i); | |
1713 | break; | |
1714 | } | |
1715 | list_add_tail(&desc->desc_node, &atchan->free_descs_list); | |
1716 | } | |
1717 | ||
1718 | dma_cookie_init(chan); | |
1719 | ||
1720 | dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i); | |
1721 | ||
1722 | spin_unlock: | |
4c374fc7 | 1723 | spin_unlock_irqrestore(&atchan->lock, flags); |
e1f7c9ee LD |
1724 | return i; |
1725 | } | |
1726 | ||
1727 | static void at_xdmac_free_chan_resources(struct dma_chan *chan) | |
1728 | { | |
1729 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); | |
1730 | struct at_xdmac *atxdmac = to_at_xdmac(chan->device); | |
1731 | struct at_xdmac_desc *desc, *_desc; | |
1732 | ||
1733 | list_for_each_entry_safe(desc, _desc, &atchan->free_descs_list, desc_node) { | |
1734 | dev_dbg(chan2dev(chan), "%s: freeing descriptor %p\n", __func__, desc); | |
1735 | list_del(&desc->desc_node); | |
1736 | dma_pool_free(atxdmac->at_xdmac_desc_pool, desc, desc->tx_dma_desc.phys); | |
1737 | } | |
1738 | ||
1739 | return; | |
1740 | } | |
1741 | ||
e1f7c9ee LD |
1742 | #ifdef CONFIG_PM |
1743 | static int atmel_xdmac_prepare(struct device *dev) | |
1744 | { | |
1745 | struct platform_device *pdev = to_platform_device(dev); | |
1746 | struct at_xdmac *atxdmac = platform_get_drvdata(pdev); | |
1747 | struct dma_chan *chan, *_chan; | |
1748 | ||
1749 | list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) { | |
1750 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); | |
1751 | ||
1752 | /* Wait for transfer completion, except in cyclic case. */ | |
1753 | if (at_xdmac_chan_is_enabled(atchan) && !at_xdmac_chan_is_cyclic(atchan)) | |
1754 | return -EAGAIN; | |
1755 | } | |
1756 | return 0; | |
1757 | } | |
1758 | #else | |
1759 | # define atmel_xdmac_prepare NULL | |
1760 | #endif | |
1761 | ||
1762 | #ifdef CONFIG_PM_SLEEP | |
1763 | static int atmel_xdmac_suspend(struct device *dev) | |
1764 | { | |
1765 | struct platform_device *pdev = to_platform_device(dev); | |
1766 | struct at_xdmac *atxdmac = platform_get_drvdata(pdev); | |
1767 | struct dma_chan *chan, *_chan; | |
1768 | ||
1769 | list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) { | |
1770 | struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan); | |
1771 | ||
734bb9a7 | 1772 | atchan->save_cc = at_xdmac_chan_read(atchan, AT_XDMAC_CC); |
e1f7c9ee LD |
1773 | if (at_xdmac_chan_is_cyclic(atchan)) { |
1774 | if (!at_xdmac_chan_is_paused(atchan)) | |
3d138877 | 1775 | at_xdmac_device_pause(chan); |
e1f7c9ee LD |
1776 | atchan->save_cim = at_xdmac_chan_read(atchan, AT_XDMAC_CIM); |
1777 | atchan->save_cnda = at_xdmac_chan_read(atchan, AT_XDMAC_CNDA); | |
1778 | atchan->save_cndc = at_xdmac_chan_read(atchan, AT_XDMAC_CNDC); | |
1779 | } | |
1780 | } | |
1781 | atxdmac->save_gim = at_xdmac_read(atxdmac, AT_XDMAC_GIM); | |
1782 | ||
1783 | at_xdmac_off(atxdmac); | |
1784 | clk_disable_unprepare(atxdmac->clk); | |
1785 | return 0; | |
1786 | } | |
1787 | ||
1788 | static int atmel_xdmac_resume(struct device *dev) | |
1789 | { | |
1790 | struct platform_device *pdev = to_platform_device(dev); | |
1791 | struct at_xdmac *atxdmac = platform_get_drvdata(pdev); | |
1792 | struct at_xdmac_chan *atchan; | |
1793 | struct dma_chan *chan, *_chan; | |
1794 | int i; | |
e1f7c9ee LD |
1795 | |
1796 | clk_prepare_enable(atxdmac->clk); | |
1797 | ||
1798 | /* Clear pending interrupts. */ | |
1799 | for (i = 0; i < atxdmac->dma.chancnt; i++) { | |
1800 | atchan = &atxdmac->chan[i]; | |
1801 | while (at_xdmac_chan_read(atchan, AT_XDMAC_CIS)) | |
1802 | cpu_relax(); | |
1803 | } | |
1804 | ||
1805 | at_xdmac_write(atxdmac, AT_XDMAC_GIE, atxdmac->save_gim); | |
1806 | at_xdmac_write(atxdmac, AT_XDMAC_GE, atxdmac->save_gs); | |
1807 | list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) { | |
1808 | atchan = to_at_xdmac_chan(chan); | |
734bb9a7 | 1809 | at_xdmac_chan_write(atchan, AT_XDMAC_CC, atchan->save_cc); |
e1f7c9ee LD |
1810 | if (at_xdmac_chan_is_cyclic(atchan)) { |
1811 | at_xdmac_chan_write(atchan, AT_XDMAC_CNDA, atchan->save_cnda); | |
1812 | at_xdmac_chan_write(atchan, AT_XDMAC_CNDC, atchan->save_cndc); | |
1813 | at_xdmac_chan_write(atchan, AT_XDMAC_CIE, atchan->save_cim); | |
1814 | wmb(); | |
1815 | at_xdmac_write(atxdmac, AT_XDMAC_GE, atchan->mask); | |
1816 | } | |
1817 | } | |
1818 | return 0; | |
1819 | } | |
1820 | #endif /* CONFIG_PM_SLEEP */ | |
1821 | ||
1822 | static int at_xdmac_probe(struct platform_device *pdev) | |
1823 | { | |
1824 | struct resource *res; | |
1825 | struct at_xdmac *atxdmac; | |
1826 | int irq, size, nr_channels, i, ret; | |
1827 | void __iomem *base; | |
1828 | u32 reg; | |
1829 | ||
1830 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1831 | if (!res) | |
1832 | return -EINVAL; | |
1833 | ||
1834 | irq = platform_get_irq(pdev, 0); | |
1835 | if (irq < 0) | |
1836 | return irq; | |
1837 | ||
1838 | base = devm_ioremap_resource(&pdev->dev, res); | |
1839 | if (IS_ERR(base)) | |
1840 | return PTR_ERR(base); | |
1841 | ||
1842 | /* | |
1843 | * Read number of xdmac channels, read helper function can't be used | |
1844 | * since atxdmac is not yet allocated and we need to know the number | |
1845 | * of channels to do the allocation. | |
1846 | */ | |
1847 | reg = readl_relaxed(base + AT_XDMAC_GTYPE); | |
1848 | nr_channels = AT_XDMAC_NB_CH(reg); | |
1849 | if (nr_channels > AT_XDMAC_MAX_CHAN) { | |
1850 | dev_err(&pdev->dev, "invalid number of channels (%u)\n", | |
1851 | nr_channels); | |
1852 | return -EINVAL; | |
1853 | } | |
1854 | ||
1855 | size = sizeof(*atxdmac); | |
1856 | size += nr_channels * sizeof(struct at_xdmac_chan); | |
1857 | atxdmac = devm_kzalloc(&pdev->dev, size, GFP_KERNEL); | |
1858 | if (!atxdmac) { | |
1859 | dev_err(&pdev->dev, "can't allocate at_xdmac structure\n"); | |
1860 | return -ENOMEM; | |
1861 | } | |
1862 | ||
1863 | atxdmac->regs = base; | |
1864 | atxdmac->irq = irq; | |
1865 | ||
1866 | atxdmac->clk = devm_clk_get(&pdev->dev, "dma_clk"); | |
1867 | if (IS_ERR(atxdmac->clk)) { | |
1868 | dev_err(&pdev->dev, "can't get dma_clk\n"); | |
1869 | return PTR_ERR(atxdmac->clk); | |
1870 | } | |
1871 | ||
1872 | /* Do not use dev res to prevent races with tasklet */ | |
1873 | ret = request_irq(atxdmac->irq, at_xdmac_interrupt, 0, "at_xdmac", atxdmac); | |
1874 | if (ret) { | |
1875 | dev_err(&pdev->dev, "can't request irq\n"); | |
1876 | return ret; | |
1877 | } | |
1878 | ||
1879 | ret = clk_prepare_enable(atxdmac->clk); | |
1880 | if (ret) { | |
1881 | dev_err(&pdev->dev, "can't prepare or enable clock\n"); | |
1882 | goto err_free_irq; | |
1883 | } | |
1884 | ||
1885 | atxdmac->at_xdmac_desc_pool = | |
1886 | dmam_pool_create(dev_name(&pdev->dev), &pdev->dev, | |
1887 | sizeof(struct at_xdmac_desc), 4, 0); | |
1888 | if (!atxdmac->at_xdmac_desc_pool) { | |
1889 | dev_err(&pdev->dev, "no memory for descriptors dma pool\n"); | |
1890 | ret = -ENOMEM; | |
1891 | goto err_clk_disable; | |
1892 | } | |
1893 | ||
1894 | dma_cap_set(DMA_CYCLIC, atxdmac->dma.cap_mask); | |
6007ccb5 | 1895 | dma_cap_set(DMA_INTERLEAVE, atxdmac->dma.cap_mask); |
e1f7c9ee | 1896 | dma_cap_set(DMA_MEMCPY, atxdmac->dma.cap_mask); |
b206d9a2 | 1897 | dma_cap_set(DMA_MEMSET, atxdmac->dma.cap_mask); |
67a6eedc | 1898 | dma_cap_set(DMA_MEMSET_SG, atxdmac->dma.cap_mask); |
e1f7c9ee | 1899 | dma_cap_set(DMA_SLAVE, atxdmac->dma.cap_mask); |
fef4cbf2 LD |
1900 | /* |
1901 | * Without DMA_PRIVATE the driver is not able to allocate more than | |
1902 | * one channel, second allocation fails in private_candidate. | |
1903 | */ | |
1904 | dma_cap_set(DMA_PRIVATE, atxdmac->dma.cap_mask); | |
e1f7c9ee LD |
1905 | atxdmac->dma.dev = &pdev->dev; |
1906 | atxdmac->dma.device_alloc_chan_resources = at_xdmac_alloc_chan_resources; | |
1907 | atxdmac->dma.device_free_chan_resources = at_xdmac_free_chan_resources; | |
1908 | atxdmac->dma.device_tx_status = at_xdmac_tx_status; | |
1909 | atxdmac->dma.device_issue_pending = at_xdmac_issue_pending; | |
1910 | atxdmac->dma.device_prep_dma_cyclic = at_xdmac_prep_dma_cyclic; | |
6007ccb5 | 1911 | atxdmac->dma.device_prep_interleaved_dma = at_xdmac_prep_interleaved; |
e1f7c9ee | 1912 | atxdmac->dma.device_prep_dma_memcpy = at_xdmac_prep_dma_memcpy; |
b206d9a2 | 1913 | atxdmac->dma.device_prep_dma_memset = at_xdmac_prep_dma_memset; |
67a6eedc | 1914 | atxdmac->dma.device_prep_dma_memset_sg = at_xdmac_prep_dma_memset_sg; |
e1f7c9ee | 1915 | atxdmac->dma.device_prep_slave_sg = at_xdmac_prep_slave_sg; |
3d138877 LD |
1916 | atxdmac->dma.device_config = at_xdmac_device_config; |
1917 | atxdmac->dma.device_pause = at_xdmac_device_pause; | |
1918 | atxdmac->dma.device_resume = at_xdmac_device_resume; | |
1919 | atxdmac->dma.device_terminate_all = at_xdmac_device_terminate_all; | |
8ac82f88 LD |
1920 | atxdmac->dma.src_addr_widths = AT_XDMAC_DMA_BUSWIDTHS; |
1921 | atxdmac->dma.dst_addr_widths = AT_XDMAC_DMA_BUSWIDTHS; | |
1922 | atxdmac->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); | |
1923 | atxdmac->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; | |
e1f7c9ee LD |
1924 | |
1925 | /* Disable all chans and interrupts. */ | |
1926 | at_xdmac_off(atxdmac); | |
1927 | ||
1928 | /* Init channels. */ | |
1929 | INIT_LIST_HEAD(&atxdmac->dma.channels); | |
1930 | for (i = 0; i < nr_channels; i++) { | |
1931 | struct at_xdmac_chan *atchan = &atxdmac->chan[i]; | |
1932 | ||
1933 | atchan->chan.device = &atxdmac->dma; | |
1934 | list_add_tail(&atchan->chan.device_node, | |
1935 | &atxdmac->dma.channels); | |
1936 | ||
1937 | atchan->ch_regs = at_xdmac_chan_reg_base(atxdmac, i); | |
1938 | atchan->mask = 1 << i; | |
1939 | ||
1940 | spin_lock_init(&atchan->lock); | |
1941 | INIT_LIST_HEAD(&atchan->xfers_list); | |
1942 | INIT_LIST_HEAD(&atchan->free_descs_list); | |
1943 | tasklet_init(&atchan->tasklet, at_xdmac_tasklet, | |
1944 | (unsigned long)atchan); | |
1945 | ||
1946 | /* Clear pending interrupts. */ | |
1947 | while (at_xdmac_chan_read(atchan, AT_XDMAC_CIS)) | |
1948 | cpu_relax(); | |
1949 | } | |
1950 | platform_set_drvdata(pdev, atxdmac); | |
1951 | ||
1952 | ret = dma_async_device_register(&atxdmac->dma); | |
1953 | if (ret) { | |
1954 | dev_err(&pdev->dev, "fail to register DMA engine device\n"); | |
1955 | goto err_clk_disable; | |
1956 | } | |
1957 | ||
1958 | ret = of_dma_controller_register(pdev->dev.of_node, | |
1959 | at_xdmac_xlate, atxdmac); | |
1960 | if (ret) { | |
1961 | dev_err(&pdev->dev, "could not register of dma controller\n"); | |
1962 | goto err_dma_unregister; | |
1963 | } | |
1964 | ||
1965 | dev_info(&pdev->dev, "%d channels, mapped at 0x%p\n", | |
1966 | nr_channels, atxdmac->regs); | |
1967 | ||
1968 | return 0; | |
1969 | ||
1970 | err_dma_unregister: | |
1971 | dma_async_device_unregister(&atxdmac->dma); | |
1972 | err_clk_disable: | |
1973 | clk_disable_unprepare(atxdmac->clk); | |
1974 | err_free_irq: | |
1975 | free_irq(atxdmac->irq, atxdmac->dma.dev); | |
1976 | return ret; | |
1977 | } | |
1978 | ||
1979 | static int at_xdmac_remove(struct platform_device *pdev) | |
1980 | { | |
1981 | struct at_xdmac *atxdmac = (struct at_xdmac *)platform_get_drvdata(pdev); | |
1982 | int i; | |
1983 | ||
1984 | at_xdmac_off(atxdmac); | |
1985 | of_dma_controller_free(pdev->dev.of_node); | |
1986 | dma_async_device_unregister(&atxdmac->dma); | |
1987 | clk_disable_unprepare(atxdmac->clk); | |
1988 | ||
1989 | synchronize_irq(atxdmac->irq); | |
1990 | ||
1991 | free_irq(atxdmac->irq, atxdmac->dma.dev); | |
1992 | ||
1993 | for (i = 0; i < atxdmac->dma.chancnt; i++) { | |
1994 | struct at_xdmac_chan *atchan = &atxdmac->chan[i]; | |
1995 | ||
1996 | tasklet_kill(&atchan->tasklet); | |
1997 | at_xdmac_free_chan_resources(&atchan->chan); | |
1998 | } | |
1999 | ||
2000 | return 0; | |
2001 | } | |
2002 | ||
2003 | static const struct dev_pm_ops atmel_xdmac_dev_pm_ops = { | |
2004 | .prepare = atmel_xdmac_prepare, | |
2005 | SET_LATE_SYSTEM_SLEEP_PM_OPS(atmel_xdmac_suspend, atmel_xdmac_resume) | |
2006 | }; | |
2007 | ||
2008 | static const struct of_device_id atmel_xdmac_dt_ids[] = { | |
2009 | { | |
2010 | .compatible = "atmel,sama5d4-dma", | |
2011 | }, { | |
2012 | /* sentinel */ | |
2013 | } | |
2014 | }; | |
2015 | MODULE_DEVICE_TABLE(of, atmel_xdmac_dt_ids); | |
2016 | ||
2017 | static struct platform_driver at_xdmac_driver = { | |
2018 | .probe = at_xdmac_probe, | |
2019 | .remove = at_xdmac_remove, | |
2020 | .driver = { | |
2021 | .name = "at_xdmac", | |
e1f7c9ee LD |
2022 | .of_match_table = of_match_ptr(atmel_xdmac_dt_ids), |
2023 | .pm = &atmel_xdmac_dev_pm_ops, | |
2024 | } | |
2025 | }; | |
2026 | ||
2027 | static int __init at_xdmac_init(void) | |
2028 | { | |
2029 | return platform_driver_probe(&at_xdmac_driver, at_xdmac_probe); | |
2030 | } | |
2031 | subsys_initcall(at_xdmac_init); | |
2032 | ||
2033 | MODULE_DESCRIPTION("Atmel Extended DMA Controller driver"); | |
2034 | MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>"); | |
2035 | MODULE_LICENSE("GPL"); |