Commit | Line | Data |
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4a776f0a HS |
1 | /* |
2 | * DMA Engine test module | |
3 | * | |
4 | * Copyright (C) 2007 Atmel Corporation | |
851b7e16 | 5 | * Copyright (C) 2013 Intel Corporation |
4a776f0a HS |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
872f05c6 DW |
11 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
12 | ||
4a776f0a | 13 | #include <linux/delay.h> |
b7f080cf | 14 | #include <linux/dma-mapping.h> |
4a776f0a | 15 | #include <linux/dmaengine.h> |
981ed70d | 16 | #include <linux/freezer.h> |
4a776f0a HS |
17 | #include <linux/init.h> |
18 | #include <linux/kthread.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/moduleparam.h> | |
21 | #include <linux/random.h> | |
5a0e3ad6 | 22 | #include <linux/slab.h> |
4a776f0a HS |
23 | #include <linux/wait.h> |
24 | ||
25 | static unsigned int test_buf_size = 16384; | |
a6c268d0 | 26 | module_param(test_buf_size, uint, S_IRUGO | S_IWUSR); |
4a776f0a HS |
27 | MODULE_PARM_DESC(test_buf_size, "Size of the memcpy test buffer"); |
28 | ||
06190d84 | 29 | static char test_channel[20]; |
a6c268d0 AS |
30 | module_param_string(channel, test_channel, sizeof(test_channel), |
31 | S_IRUGO | S_IWUSR); | |
4a776f0a HS |
32 | MODULE_PARM_DESC(channel, "Bus ID of the channel to test (default: any)"); |
33 | ||
a85159fe | 34 | static char test_device[32]; |
a6c268d0 AS |
35 | module_param_string(device, test_device, sizeof(test_device), |
36 | S_IRUGO | S_IWUSR); | |
4a776f0a HS |
37 | MODULE_PARM_DESC(device, "Bus ID of the DMA Engine to test (default: any)"); |
38 | ||
39 | static unsigned int threads_per_chan = 1; | |
a6c268d0 | 40 | module_param(threads_per_chan, uint, S_IRUGO | S_IWUSR); |
4a776f0a HS |
41 | MODULE_PARM_DESC(threads_per_chan, |
42 | "Number of threads to start per channel (default: 1)"); | |
43 | ||
44 | static unsigned int max_channels; | |
a6c268d0 | 45 | module_param(max_channels, uint, S_IRUGO | S_IWUSR); |
33df8ca0 | 46 | MODULE_PARM_DESC(max_channels, |
4a776f0a HS |
47 | "Maximum number of channels to use (default: all)"); |
48 | ||
0a2ff57d | 49 | static unsigned int iterations; |
a6c268d0 | 50 | module_param(iterations, uint, S_IRUGO | S_IWUSR); |
0a2ff57d NF |
51 | MODULE_PARM_DESC(iterations, |
52 | "Iterations before stopping test (default: infinite)"); | |
53 | ||
a0d4cb44 KA |
54 | static unsigned int sg_buffers = 1; |
55 | module_param(sg_buffers, uint, S_IRUGO | S_IWUSR); | |
56 | MODULE_PARM_DESC(sg_buffers, | |
57 | "Number of scatter gather buffers (default: 1)"); | |
58 | ||
59 | static unsigned int dmatest = 1; | |
60 | module_param(dmatest, uint, S_IRUGO | S_IWUSR); | |
61 | MODULE_PARM_DESC(dmatest, | |
62 | "dmatest 0-memcpy 1-slave_sg (default: 1)"); | |
63 | ||
b54d5cb9 | 64 | static unsigned int xor_sources = 3; |
a6c268d0 | 65 | module_param(xor_sources, uint, S_IRUGO | S_IWUSR); |
b54d5cb9 DW |
66 | MODULE_PARM_DESC(xor_sources, |
67 | "Number of xor source buffers (default: 3)"); | |
68 | ||
58691d64 | 69 | static unsigned int pq_sources = 3; |
a6c268d0 | 70 | module_param(pq_sources, uint, S_IRUGO | S_IWUSR); |
58691d64 DW |
71 | MODULE_PARM_DESC(pq_sources, |
72 | "Number of p+q source buffers (default: 3)"); | |
73 | ||
d42efe6b | 74 | static int timeout = 3000; |
a6c268d0 | 75 | module_param(timeout, uint, S_IRUGO | S_IWUSR); |
85ee7a1d JP |
76 | MODULE_PARM_DESC(timeout, "Transfer Timeout in msec (default: 3000), " |
77 | "Pass -1 for infinite timeout"); | |
d42efe6b | 78 | |
e3b9c347 DW |
79 | static bool noverify; |
80 | module_param(noverify, bool, S_IRUGO | S_IWUSR); | |
81 | MODULE_PARM_DESC(noverify, "Disable random data setup and verification"); | |
4a776f0a | 82 | |
50137a7d DW |
83 | static bool verbose; |
84 | module_param(verbose, bool, S_IRUGO | S_IWUSR); | |
85 | MODULE_PARM_DESC(verbose, "Enable \"success\" result messages (default: off)"); | |
4a776f0a | 86 | |
e03e93a9 | 87 | /** |
15b8a8ea | 88 | * struct dmatest_params - test parameters. |
e03e93a9 AS |
89 | * @buf_size: size of the memcpy test buffer |
90 | * @channel: bus ID of the channel to test | |
91 | * @device: bus ID of the DMA Engine to test | |
92 | * @threads_per_chan: number of threads to start per channel | |
93 | * @max_channels: maximum number of channels to use | |
94 | * @iterations: iterations before stopping test | |
95 | * @xor_sources: number of xor source buffers | |
96 | * @pq_sources: number of p+q source buffers | |
97 | * @timeout: transfer timeout in msec, -1 for infinite timeout | |
98 | */ | |
15b8a8ea | 99 | struct dmatest_params { |
e03e93a9 AS |
100 | unsigned int buf_size; |
101 | char channel[20]; | |
a85159fe | 102 | char device[32]; |
e03e93a9 AS |
103 | unsigned int threads_per_chan; |
104 | unsigned int max_channels; | |
105 | unsigned int iterations; | |
106 | unsigned int xor_sources; | |
107 | unsigned int pq_sources; | |
108 | int timeout; | |
e3b9c347 | 109 | bool noverify; |
15b8a8ea AS |
110 | }; |
111 | ||
112 | /** | |
113 | * struct dmatest_info - test information. | |
114 | * @params: test parameters | |
851b7e16 | 115 | * @lock: access protection to the fields of this structure |
15b8a8ea | 116 | */ |
a310d037 | 117 | static struct dmatest_info { |
15b8a8ea AS |
118 | /* Test parameters */ |
119 | struct dmatest_params params; | |
838cc704 AS |
120 | |
121 | /* Internal state */ | |
122 | struct list_head channels; | |
123 | unsigned int nr_channels; | |
851b7e16 | 124 | struct mutex lock; |
a310d037 DW |
125 | bool did_init; |
126 | } test_info = { | |
127 | .channels = LIST_HEAD_INIT(test_info.channels), | |
128 | .lock = __MUTEX_INITIALIZER(test_info.lock), | |
129 | }; | |
851b7e16 | 130 | |
a310d037 DW |
131 | static int dmatest_run_set(const char *val, const struct kernel_param *kp); |
132 | static int dmatest_run_get(char *val, const struct kernel_param *kp); | |
9c27847d | 133 | static const struct kernel_param_ops run_ops = { |
a310d037 DW |
134 | .set = dmatest_run_set, |
135 | .get = dmatest_run_get, | |
e03e93a9 | 136 | }; |
a310d037 DW |
137 | static bool dmatest_run; |
138 | module_param_cb(run, &run_ops, &dmatest_run, S_IRUGO | S_IWUSR); | |
139 | MODULE_PARM_DESC(run, "Run the test (default: false)"); | |
e03e93a9 | 140 | |
a310d037 DW |
141 | /* Maximum amount of mismatched bytes in buffer to print */ |
142 | #define MAX_ERROR_COUNT 32 | |
143 | ||
144 | /* | |
145 | * Initialization patterns. All bytes in the source buffer has bit 7 | |
146 | * set, all bytes in the destination buffer has bit 7 cleared. | |
147 | * | |
148 | * Bit 6 is set for all bytes which are to be copied by the DMA | |
149 | * engine. Bit 5 is set for all bytes which are to be overwritten by | |
150 | * the DMA engine. | |
151 | * | |
152 | * The remaining bits are the inverse of a counter which increments by | |
153 | * one for each byte address. | |
154 | */ | |
155 | #define PATTERN_SRC 0x80 | |
156 | #define PATTERN_DST 0x00 | |
157 | #define PATTERN_COPY 0x40 | |
158 | #define PATTERN_OVERWRITE 0x20 | |
159 | #define PATTERN_COUNT_MASK 0x1f | |
851b7e16 | 160 | |
a310d037 DW |
161 | struct dmatest_thread { |
162 | struct list_head node; | |
163 | struct dmatest_info *info; | |
164 | struct task_struct *task; | |
165 | struct dma_chan *chan; | |
166 | u8 **srcs; | |
167 | u8 **dsts; | |
168 | enum dma_transaction_type type; | |
169 | bool done; | |
170 | }; | |
95019c8c | 171 | |
a310d037 DW |
172 | struct dmatest_chan { |
173 | struct list_head node; | |
174 | struct dma_chan *chan; | |
175 | struct list_head threads; | |
e03e93a9 AS |
176 | }; |
177 | ||
2d88ce76 DW |
178 | static DECLARE_WAIT_QUEUE_HEAD(thread_wait); |
179 | static bool wait; | |
180 | ||
181 | static bool is_threaded_test_run(struct dmatest_info *info) | |
182 | { | |
183 | struct dmatest_chan *dtc; | |
184 | ||
185 | list_for_each_entry(dtc, &info->channels, node) { | |
186 | struct dmatest_thread *thread; | |
187 | ||
188 | list_for_each_entry(thread, &dtc->threads, node) { | |
189 | if (!thread->done) | |
190 | return true; | |
191 | } | |
192 | } | |
193 | ||
194 | return false; | |
195 | } | |
196 | ||
197 | static int dmatest_wait_get(char *val, const struct kernel_param *kp) | |
198 | { | |
199 | struct dmatest_info *info = &test_info; | |
200 | struct dmatest_params *params = &info->params; | |
201 | ||
202 | if (params->iterations) | |
203 | wait_event(thread_wait, !is_threaded_test_run(info)); | |
204 | wait = true; | |
205 | return param_get_bool(val, kp); | |
206 | } | |
207 | ||
9c27847d | 208 | static const struct kernel_param_ops wait_ops = { |
2d88ce76 DW |
209 | .get = dmatest_wait_get, |
210 | .set = param_set_bool, | |
211 | }; | |
212 | module_param_cb(wait, &wait_ops, &wait, S_IRUGO); | |
213 | MODULE_PARM_DESC(wait, "Wait for tests to complete (default: false)"); | |
e03e93a9 | 214 | |
15b8a8ea | 215 | static bool dmatest_match_channel(struct dmatest_params *params, |
e03e93a9 | 216 | struct dma_chan *chan) |
4a776f0a | 217 | { |
15b8a8ea | 218 | if (params->channel[0] == '\0') |
4a776f0a | 219 | return true; |
15b8a8ea | 220 | return strcmp(dma_chan_name(chan), params->channel) == 0; |
4a776f0a HS |
221 | } |
222 | ||
15b8a8ea | 223 | static bool dmatest_match_device(struct dmatest_params *params, |
e03e93a9 | 224 | struct dma_device *device) |
4a776f0a | 225 | { |
15b8a8ea | 226 | if (params->device[0] == '\0') |
4a776f0a | 227 | return true; |
15b8a8ea | 228 | return strcmp(dev_name(device->dev), params->device) == 0; |
4a776f0a HS |
229 | } |
230 | ||
231 | static unsigned long dmatest_random(void) | |
232 | { | |
233 | unsigned long buf; | |
234 | ||
be9fa5a4 | 235 | prandom_bytes(&buf, sizeof(buf)); |
4a776f0a HS |
236 | return buf; |
237 | } | |
238 | ||
e03e93a9 AS |
239 | static void dmatest_init_srcs(u8 **bufs, unsigned int start, unsigned int len, |
240 | unsigned int buf_size) | |
4a776f0a HS |
241 | { |
242 | unsigned int i; | |
b54d5cb9 DW |
243 | u8 *buf; |
244 | ||
245 | for (; (buf = *bufs); bufs++) { | |
246 | for (i = 0; i < start; i++) | |
247 | buf[i] = PATTERN_SRC | (~i & PATTERN_COUNT_MASK); | |
248 | for ( ; i < start + len; i++) | |
249 | buf[i] = PATTERN_SRC | PATTERN_COPY | |
c019894e | 250 | | (~i & PATTERN_COUNT_MASK); |
e03e93a9 | 251 | for ( ; i < buf_size; i++) |
b54d5cb9 DW |
252 | buf[i] = PATTERN_SRC | (~i & PATTERN_COUNT_MASK); |
253 | buf++; | |
254 | } | |
4a776f0a HS |
255 | } |
256 | ||
e03e93a9 AS |
257 | static void dmatest_init_dsts(u8 **bufs, unsigned int start, unsigned int len, |
258 | unsigned int buf_size) | |
4a776f0a HS |
259 | { |
260 | unsigned int i; | |
b54d5cb9 DW |
261 | u8 *buf; |
262 | ||
263 | for (; (buf = *bufs); bufs++) { | |
264 | for (i = 0; i < start; i++) | |
265 | buf[i] = PATTERN_DST | (~i & PATTERN_COUNT_MASK); | |
266 | for ( ; i < start + len; i++) | |
267 | buf[i] = PATTERN_DST | PATTERN_OVERWRITE | |
268 | | (~i & PATTERN_COUNT_MASK); | |
e03e93a9 | 269 | for ( ; i < buf_size; i++) |
b54d5cb9 DW |
270 | buf[i] = PATTERN_DST | (~i & PATTERN_COUNT_MASK); |
271 | } | |
4a776f0a HS |
272 | } |
273 | ||
7b610178 DW |
274 | static void dmatest_mismatch(u8 actual, u8 pattern, unsigned int index, |
275 | unsigned int counter, bool is_srcbuf) | |
276 | { | |
277 | u8 diff = actual ^ pattern; | |
278 | u8 expected = pattern | (~counter & PATTERN_COUNT_MASK); | |
279 | const char *thread_name = current->comm; | |
280 | ||
281 | if (is_srcbuf) | |
282 | pr_warn("%s: srcbuf[0x%x] overwritten! Expected %02x, got %02x\n", | |
283 | thread_name, index, expected, actual); | |
284 | else if ((pattern & PATTERN_COPY) | |
285 | && (diff & (PATTERN_COPY | PATTERN_OVERWRITE))) | |
286 | pr_warn("%s: dstbuf[0x%x] not copied! Expected %02x, got %02x\n", | |
287 | thread_name, index, expected, actual); | |
288 | else if (diff & PATTERN_SRC) | |
289 | pr_warn("%s: dstbuf[0x%x] was copied! Expected %02x, got %02x\n", | |
290 | thread_name, index, expected, actual); | |
291 | else | |
292 | pr_warn("%s: dstbuf[0x%x] mismatch! Expected %02x, got %02x\n", | |
293 | thread_name, index, expected, actual); | |
294 | } | |
295 | ||
296 | static unsigned int dmatest_verify(u8 **bufs, unsigned int start, | |
297 | unsigned int end, unsigned int counter, u8 pattern, | |
298 | bool is_srcbuf) | |
4a776f0a HS |
299 | { |
300 | unsigned int i; | |
301 | unsigned int error_count = 0; | |
302 | u8 actual; | |
b54d5cb9 DW |
303 | u8 expected; |
304 | u8 *buf; | |
305 | unsigned int counter_orig = counter; | |
306 | ||
307 | for (; (buf = *bufs); bufs++) { | |
308 | counter = counter_orig; | |
309 | for (i = start; i < end; i++) { | |
310 | actual = buf[i]; | |
311 | expected = pattern | (~counter & PATTERN_COUNT_MASK); | |
312 | if (actual != expected) { | |
7b610178 DW |
313 | if (error_count < MAX_ERROR_COUNT) |
314 | dmatest_mismatch(actual, pattern, i, | |
315 | counter, is_srcbuf); | |
b54d5cb9 DW |
316 | error_count++; |
317 | } | |
318 | counter++; | |
4a776f0a | 319 | } |
4a776f0a HS |
320 | } |
321 | ||
74b5c07a | 322 | if (error_count > MAX_ERROR_COUNT) |
7b610178 | 323 | pr_warn("%s: %u errors suppressed\n", |
74b5c07a | 324 | current->comm, error_count - MAX_ERROR_COUNT); |
4a776f0a HS |
325 | |
326 | return error_count; | |
327 | } | |
328 | ||
adfa543e TH |
329 | /* poor man's completion - we want to use wait_event_freezable() on it */ |
330 | struct dmatest_done { | |
331 | bool done; | |
332 | wait_queue_head_t *wait; | |
333 | }; | |
334 | ||
335 | static void dmatest_callback(void *arg) | |
e44e0aa3 | 336 | { |
adfa543e TH |
337 | struct dmatest_done *done = arg; |
338 | ||
339 | done->done = true; | |
340 | wake_up_all(done->wait); | |
e44e0aa3 DW |
341 | } |
342 | ||
8be9e32b AM |
343 | static unsigned int min_odd(unsigned int x, unsigned int y) |
344 | { | |
345 | unsigned int val = min(x, y); | |
346 | ||
347 | return val % 2 ? val : val - 1; | |
348 | } | |
349 | ||
872f05c6 DW |
350 | static void result(const char *err, unsigned int n, unsigned int src_off, |
351 | unsigned int dst_off, unsigned int len, unsigned long data) | |
d86b2f29 | 352 | { |
2acec150 | 353 | pr_info("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%lu)\n", |
872f05c6 | 354 | current->comm, n, err, src_off, dst_off, len, data); |
d86b2f29 AS |
355 | } |
356 | ||
872f05c6 DW |
357 | static void dbg_result(const char *err, unsigned int n, unsigned int src_off, |
358 | unsigned int dst_off, unsigned int len, | |
359 | unsigned long data) | |
95019c8c | 360 | { |
2acec150 | 361 | pr_debug("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%lu)\n", |
a835bb85 | 362 | current->comm, n, err, src_off, dst_off, len, data); |
95019c8c AS |
363 | } |
364 | ||
a835bb85 AS |
365 | #define verbose_result(err, n, src_off, dst_off, len, data) ({ \ |
366 | if (verbose) \ | |
367 | result(err, n, src_off, dst_off, len, data); \ | |
368 | else \ | |
369 | dbg_result(err, n, src_off, dst_off, len, data);\ | |
50137a7d | 370 | }) |
95019c8c | 371 | |
86727443 | 372 | static unsigned long long dmatest_persec(s64 runtime, unsigned int val) |
d86b2f29 | 373 | { |
86727443 | 374 | unsigned long long per_sec = 1000000; |
d86b2f29 | 375 | |
86727443 DW |
376 | if (runtime <= 0) |
377 | return 0; | |
95019c8c | 378 | |
86727443 DW |
379 | /* drop precision until runtime is 32-bits */ |
380 | while (runtime > UINT_MAX) { | |
381 | runtime >>= 1; | |
382 | per_sec <<= 1; | |
95019c8c AS |
383 | } |
384 | ||
86727443 DW |
385 | per_sec *= val; |
386 | do_div(per_sec, runtime); | |
387 | return per_sec; | |
95019c8c AS |
388 | } |
389 | ||
86727443 | 390 | static unsigned long long dmatest_KBs(s64 runtime, unsigned long long len) |
95019c8c | 391 | { |
86727443 | 392 | return dmatest_persec(runtime, len >> 10); |
95019c8c AS |
393 | } |
394 | ||
4a776f0a HS |
395 | /* |
396 | * This function repeatedly tests DMA transfers of various lengths and | |
b54d5cb9 DW |
397 | * offsets for a given operation type until it is told to exit by |
398 | * kthread_stop(). There may be multiple threads running this function | |
399 | * in parallel for a single channel, and there may be multiple channels | |
400 | * being tested in parallel. | |
4a776f0a HS |
401 | * |
402 | * Before each test, the source and destination buffer is initialized | |
403 | * with a known pattern. This pattern is different depending on | |
404 | * whether it's in an area which is supposed to be copied or | |
405 | * overwritten, and different in the source and destination buffers. | |
406 | * So if the DMA engine doesn't copy exactly what we tell it to copy, | |
407 | * we'll notice. | |
408 | */ | |
409 | static int dmatest_func(void *data) | |
410 | { | |
adfa543e | 411 | DECLARE_WAIT_QUEUE_HEAD_ONSTACK(done_wait); |
4a776f0a | 412 | struct dmatest_thread *thread = data; |
adfa543e | 413 | struct dmatest_done done = { .wait = &done_wait }; |
e03e93a9 | 414 | struct dmatest_info *info; |
15b8a8ea | 415 | struct dmatest_params *params; |
4a776f0a | 416 | struct dma_chan *chan; |
8be9e32b | 417 | struct dma_device *dev; |
4a776f0a HS |
418 | unsigned int error_count; |
419 | unsigned int failed_tests = 0; | |
420 | unsigned int total_tests = 0; | |
421 | dma_cookie_t cookie; | |
422 | enum dma_status status; | |
b54d5cb9 | 423 | enum dma_ctrl_flags flags; |
945b5af3 | 424 | u8 *pq_coefs = NULL; |
4a776f0a | 425 | int ret; |
b54d5cb9 DW |
426 | int src_cnt; |
427 | int dst_cnt; | |
428 | int i; | |
86727443 DW |
429 | ktime_t ktime; |
430 | s64 runtime = 0; | |
431 | unsigned long long total_len = 0; | |
4a776f0a | 432 | |
adfa543e | 433 | set_freezable(); |
4a776f0a HS |
434 | |
435 | ret = -ENOMEM; | |
4a776f0a HS |
436 | |
437 | smp_rmb(); | |
e03e93a9 | 438 | info = thread->info; |
15b8a8ea | 439 | params = &info->params; |
4a776f0a | 440 | chan = thread->chan; |
8be9e32b | 441 | dev = chan->device; |
b54d5cb9 DW |
442 | if (thread->type == DMA_MEMCPY) |
443 | src_cnt = dst_cnt = 1; | |
a0d4cb44 KA |
444 | else if (thread->type == DMA_SG) |
445 | src_cnt = dst_cnt = sg_buffers; | |
b54d5cb9 | 446 | else if (thread->type == DMA_XOR) { |
8be9e32b | 447 | /* force odd to ensure dst = src */ |
15b8a8ea | 448 | src_cnt = min_odd(params->xor_sources | 1, dev->max_xor); |
b54d5cb9 | 449 | dst_cnt = 1; |
58691d64 | 450 | } else if (thread->type == DMA_PQ) { |
8be9e32b | 451 | /* force odd to ensure dst = src */ |
15b8a8ea | 452 | src_cnt = min_odd(params->pq_sources | 1, dma_maxpq(dev, 0)); |
58691d64 | 453 | dst_cnt = 2; |
945b5af3 | 454 | |
15b8a8ea | 455 | pq_coefs = kmalloc(params->pq_sources+1, GFP_KERNEL); |
945b5af3 AS |
456 | if (!pq_coefs) |
457 | goto err_thread_type; | |
458 | ||
94de648d | 459 | for (i = 0; i < src_cnt; i++) |
58691d64 | 460 | pq_coefs[i] = 1; |
b54d5cb9 | 461 | } else |
945b5af3 | 462 | goto err_thread_type; |
b54d5cb9 DW |
463 | |
464 | thread->srcs = kcalloc(src_cnt+1, sizeof(u8 *), GFP_KERNEL); | |
465 | if (!thread->srcs) | |
466 | goto err_srcs; | |
467 | for (i = 0; i < src_cnt; i++) { | |
15b8a8ea | 468 | thread->srcs[i] = kmalloc(params->buf_size, GFP_KERNEL); |
b54d5cb9 DW |
469 | if (!thread->srcs[i]) |
470 | goto err_srcbuf; | |
471 | } | |
472 | thread->srcs[i] = NULL; | |
473 | ||
474 | thread->dsts = kcalloc(dst_cnt+1, sizeof(u8 *), GFP_KERNEL); | |
475 | if (!thread->dsts) | |
476 | goto err_dsts; | |
477 | for (i = 0; i < dst_cnt; i++) { | |
15b8a8ea | 478 | thread->dsts[i] = kmalloc(params->buf_size, GFP_KERNEL); |
b54d5cb9 DW |
479 | if (!thread->dsts[i]) |
480 | goto err_dstbuf; | |
481 | } | |
482 | thread->dsts[i] = NULL; | |
483 | ||
e44e0aa3 DW |
484 | set_user_nice(current, 10); |
485 | ||
b203bd3f | 486 | /* |
d1cab34c | 487 | * src and dst buffers are freed by ourselves below |
b203bd3f | 488 | */ |
0776ae7b | 489 | flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; |
4a776f0a | 490 | |
86727443 | 491 | ktime = ktime_get(); |
0a2ff57d | 492 | while (!kthread_should_stop() |
15b8a8ea | 493 | && !(params->iterations && total_tests >= params->iterations)) { |
b54d5cb9 | 494 | struct dma_async_tx_descriptor *tx = NULL; |
4076e755 DW |
495 | struct dmaengine_unmap_data *um; |
496 | dma_addr_t srcs[src_cnt]; | |
497 | dma_addr_t *dsts; | |
ede23a58 | 498 | unsigned int src_off, dst_off, len; |
83544ae9 | 499 | u8 align = 0; |
a0d4cb44 KA |
500 | struct scatterlist tx_sg[src_cnt]; |
501 | struct scatterlist rx_sg[src_cnt]; | |
d86be86e | 502 | |
4a776f0a HS |
503 | total_tests++; |
504 | ||
83544ae9 DW |
505 | /* honor alignment restrictions */ |
506 | if (thread->type == DMA_MEMCPY) | |
507 | align = dev->copy_align; | |
508 | else if (thread->type == DMA_XOR) | |
509 | align = dev->xor_align; | |
510 | else if (thread->type == DMA_PQ) | |
511 | align = dev->pq_align; | |
512 | ||
15b8a8ea | 513 | if (1 << align > params->buf_size) { |
cfe4f275 | 514 | pr_err("%u-byte buffer too small for %d-byte alignment\n", |
15b8a8ea | 515 | params->buf_size, 1 << align); |
cfe4f275 GL |
516 | break; |
517 | } | |
518 | ||
ede23a58 | 519 | if (params->noverify) |
e3b9c347 | 520 | len = params->buf_size; |
ede23a58 AS |
521 | else |
522 | len = dmatest_random() % params->buf_size + 1; | |
523 | ||
524 | len = (len >> align) << align; | |
525 | if (!len) | |
526 | len = 1 << align; | |
527 | ||
528 | total_len += len; | |
529 | ||
530 | if (params->noverify) { | |
e3b9c347 DW |
531 | src_off = 0; |
532 | dst_off = 0; | |
533 | } else { | |
e3b9c347 DW |
534 | src_off = dmatest_random() % (params->buf_size - len + 1); |
535 | dst_off = dmatest_random() % (params->buf_size - len + 1); | |
536 | ||
537 | src_off = (src_off >> align) << align; | |
538 | dst_off = (dst_off >> align) << align; | |
539 | ||
540 | dmatest_init_srcs(thread->srcs, src_off, len, | |
541 | params->buf_size); | |
542 | dmatest_init_dsts(thread->dsts, dst_off, len, | |
543 | params->buf_size); | |
544 | } | |
545 | ||
4076e755 DW |
546 | um = dmaengine_get_unmap_data(dev->dev, src_cnt+dst_cnt, |
547 | GFP_KERNEL); | |
548 | if (!um) { | |
549 | failed_tests++; | |
550 | result("unmap data NULL", total_tests, | |
551 | src_off, dst_off, len, ret); | |
552 | continue; | |
553 | } | |
4a776f0a | 554 | |
4076e755 | 555 | um->len = params->buf_size; |
b54d5cb9 | 556 | for (i = 0; i < src_cnt; i++) { |
745c00da | 557 | void *buf = thread->srcs[i]; |
4076e755 | 558 | struct page *pg = virt_to_page(buf); |
745c00da | 559 | unsigned pg_off = (unsigned long) buf & ~PAGE_MASK; |
4076e755 DW |
560 | |
561 | um->addr[i] = dma_map_page(dev->dev, pg, pg_off, | |
562 | um->len, DMA_TO_DEVICE); | |
563 | srcs[i] = um->addr[i] + src_off; | |
564 | ret = dma_mapping_error(dev->dev, um->addr[i]); | |
afde3be1 | 565 | if (ret) { |
4076e755 | 566 | dmaengine_unmap_put(um); |
872f05c6 DW |
567 | result("src mapping error", total_tests, |
568 | src_off, dst_off, len, ret); | |
afde3be1 AS |
569 | failed_tests++; |
570 | continue; | |
571 | } | |
4076e755 | 572 | um->to_cnt++; |
b54d5cb9 | 573 | } |
d86be86e | 574 | /* map with DMA_BIDIRECTIONAL to force writeback/invalidate */ |
4076e755 | 575 | dsts = &um->addr[src_cnt]; |
b54d5cb9 | 576 | for (i = 0; i < dst_cnt; i++) { |
745c00da | 577 | void *buf = thread->dsts[i]; |
4076e755 | 578 | struct page *pg = virt_to_page(buf); |
745c00da | 579 | unsigned pg_off = (unsigned long) buf & ~PAGE_MASK; |
4076e755 DW |
580 | |
581 | dsts[i] = dma_map_page(dev->dev, pg, pg_off, um->len, | |
582 | DMA_BIDIRECTIONAL); | |
583 | ret = dma_mapping_error(dev->dev, dsts[i]); | |
afde3be1 | 584 | if (ret) { |
4076e755 | 585 | dmaengine_unmap_put(um); |
872f05c6 DW |
586 | result("dst mapping error", total_tests, |
587 | src_off, dst_off, len, ret); | |
afde3be1 AS |
588 | failed_tests++; |
589 | continue; | |
590 | } | |
4076e755 | 591 | um->bidi_cnt++; |
b54d5cb9 DW |
592 | } |
593 | ||
a0d4cb44 KA |
594 | sg_init_table(tx_sg, src_cnt); |
595 | sg_init_table(rx_sg, src_cnt); | |
596 | for (i = 0; i < src_cnt; i++) { | |
597 | sg_dma_address(&rx_sg[i]) = srcs[i]; | |
598 | sg_dma_address(&tx_sg[i]) = dsts[i] + dst_off; | |
599 | sg_dma_len(&tx_sg[i]) = len; | |
600 | sg_dma_len(&rx_sg[i]) = len; | |
601 | } | |
602 | ||
b54d5cb9 DW |
603 | if (thread->type == DMA_MEMCPY) |
604 | tx = dev->device_prep_dma_memcpy(chan, | |
4076e755 DW |
605 | dsts[0] + dst_off, |
606 | srcs[0], len, flags); | |
a0d4cb44 KA |
607 | else if (thread->type == DMA_SG) |
608 | tx = dev->device_prep_dma_sg(chan, tx_sg, src_cnt, | |
609 | rx_sg, src_cnt, flags); | |
b54d5cb9 DW |
610 | else if (thread->type == DMA_XOR) |
611 | tx = dev->device_prep_dma_xor(chan, | |
4076e755 DW |
612 | dsts[0] + dst_off, |
613 | srcs, src_cnt, | |
b54d5cb9 | 614 | len, flags); |
58691d64 DW |
615 | else if (thread->type == DMA_PQ) { |
616 | dma_addr_t dma_pq[dst_cnt]; | |
617 | ||
618 | for (i = 0; i < dst_cnt; i++) | |
4076e755 DW |
619 | dma_pq[i] = dsts[i] + dst_off; |
620 | tx = dev->device_prep_dma_pq(chan, dma_pq, srcs, | |
94de648d | 621 | src_cnt, pq_coefs, |
58691d64 DW |
622 | len, flags); |
623 | } | |
d86be86e | 624 | |
d86be86e | 625 | if (!tx) { |
4076e755 | 626 | dmaengine_unmap_put(um); |
872f05c6 DW |
627 | result("prep error", total_tests, src_off, |
628 | dst_off, len, ret); | |
d86be86e AN |
629 | msleep(100); |
630 | failed_tests++; | |
631 | continue; | |
632 | } | |
e44e0aa3 | 633 | |
adfa543e | 634 | done.done = false; |
e44e0aa3 | 635 | tx->callback = dmatest_callback; |
adfa543e | 636 | tx->callback_param = &done; |
d86be86e AN |
637 | cookie = tx->tx_submit(tx); |
638 | ||
4a776f0a | 639 | if (dma_submit_error(cookie)) { |
4076e755 | 640 | dmaengine_unmap_put(um); |
872f05c6 DW |
641 | result("submit error", total_tests, src_off, |
642 | dst_off, len, ret); | |
4a776f0a HS |
643 | msleep(100); |
644 | failed_tests++; | |
645 | continue; | |
646 | } | |
b54d5cb9 | 647 | dma_async_issue_pending(chan); |
4a776f0a | 648 | |
bcc567e3 | 649 | wait_event_freezable_timeout(done_wait, done.done, |
15b8a8ea | 650 | msecs_to_jiffies(params->timeout)); |
981ed70d | 651 | |
e44e0aa3 | 652 | status = dma_async_is_tx_complete(chan, cookie, NULL, NULL); |
4a776f0a | 653 | |
adfa543e TH |
654 | if (!done.done) { |
655 | /* | |
656 | * We're leaving the timed out dma operation with | |
657 | * dangling pointer to done_wait. To make this | |
658 | * correct, we'll need to allocate wait_done for | |
659 | * each test iteration and perform "who's gonna | |
660 | * free it this time?" dancing. For now, just | |
661 | * leave it dangling. | |
662 | */ | |
4076e755 | 663 | dmaengine_unmap_put(um); |
872f05c6 DW |
664 | result("test timed out", total_tests, src_off, dst_off, |
665 | len, 0); | |
e44e0aa3 DW |
666 | failed_tests++; |
667 | continue; | |
19e9f99f | 668 | } else if (status != DMA_COMPLETE) { |
4076e755 | 669 | dmaengine_unmap_put(um); |
872f05c6 DW |
670 | result(status == DMA_ERROR ? |
671 | "completion error status" : | |
672 | "completion busy status", total_tests, src_off, | |
673 | dst_off, len, ret); | |
4a776f0a HS |
674 | failed_tests++; |
675 | continue; | |
676 | } | |
e44e0aa3 | 677 | |
4076e755 | 678 | dmaengine_unmap_put(um); |
4a776f0a | 679 | |
e3b9c347 | 680 | if (params->noverify) { |
50137a7d DW |
681 | verbose_result("test passed", total_tests, src_off, |
682 | dst_off, len, 0); | |
e3b9c347 DW |
683 | continue; |
684 | } | |
4a776f0a | 685 | |
872f05c6 | 686 | pr_debug("%s: verifying source buffer...\n", current->comm); |
e3b9c347 | 687 | error_count = dmatest_verify(thread->srcs, 0, src_off, |
4a776f0a | 688 | 0, PATTERN_SRC, true); |
7b610178 DW |
689 | error_count += dmatest_verify(thread->srcs, src_off, |
690 | src_off + len, src_off, | |
691 | PATTERN_SRC | PATTERN_COPY, true); | |
692 | error_count += dmatest_verify(thread->srcs, src_off + len, | |
693 | params->buf_size, src_off + len, | |
694 | PATTERN_SRC, true); | |
695 | ||
872f05c6 | 696 | pr_debug("%s: verifying dest buffer...\n", current->comm); |
7b610178 | 697 | error_count += dmatest_verify(thread->dsts, 0, dst_off, |
4a776f0a | 698 | 0, PATTERN_DST, false); |
7b610178 DW |
699 | error_count += dmatest_verify(thread->dsts, dst_off, |
700 | dst_off + len, src_off, | |
701 | PATTERN_SRC | PATTERN_COPY, false); | |
702 | error_count += dmatest_verify(thread->dsts, dst_off + len, | |
703 | params->buf_size, dst_off + len, | |
704 | PATTERN_DST, false); | |
4a776f0a HS |
705 | |
706 | if (error_count) { | |
872f05c6 DW |
707 | result("data error", total_tests, src_off, dst_off, |
708 | len, error_count); | |
4a776f0a HS |
709 | failed_tests++; |
710 | } else { | |
50137a7d DW |
711 | verbose_result("test passed", total_tests, src_off, |
712 | dst_off, len, 0); | |
4a776f0a HS |
713 | } |
714 | } | |
86727443 | 715 | runtime = ktime_us_delta(ktime_get(), ktime); |
4a776f0a HS |
716 | |
717 | ret = 0; | |
8e1f50d7 | 718 | err_dstbuf: |
b54d5cb9 DW |
719 | for (i = 0; thread->dsts[i]; i++) |
720 | kfree(thread->dsts[i]); | |
b54d5cb9 DW |
721 | kfree(thread->dsts); |
722 | err_dsts: | |
8e1f50d7 | 723 | err_srcbuf: |
b54d5cb9 DW |
724 | for (i = 0; thread->srcs[i]; i++) |
725 | kfree(thread->srcs[i]); | |
b54d5cb9 DW |
726 | kfree(thread->srcs); |
727 | err_srcs: | |
945b5af3 AS |
728 | kfree(pq_coefs); |
729 | err_thread_type: | |
86727443 DW |
730 | pr_info("%s: summary %u tests, %u failures %llu iops %llu KB/s (%d)\n", |
731 | current->comm, total_tests, failed_tests, | |
732 | dmatest_persec(runtime, total_tests), | |
733 | dmatest_KBs(runtime, total_len), ret); | |
0a2ff57d | 734 | |
9704efaa | 735 | /* terminate all transfers on specified channels */ |
5e034f7b SH |
736 | if (ret) |
737 | dmaengine_terminate_all(chan); | |
738 | ||
3e5ccd86 | 739 | thread->done = true; |
2d88ce76 | 740 | wake_up(&thread_wait); |
0a2ff57d | 741 | |
4a776f0a HS |
742 | return ret; |
743 | } | |
744 | ||
745 | static void dmatest_cleanup_channel(struct dmatest_chan *dtc) | |
746 | { | |
747 | struct dmatest_thread *thread; | |
748 | struct dmatest_thread *_thread; | |
749 | int ret; | |
750 | ||
751 | list_for_each_entry_safe(thread, _thread, &dtc->threads, node) { | |
752 | ret = kthread_stop(thread->task); | |
0adff800 DW |
753 | pr_debug("thread %s exited with status %d\n", |
754 | thread->task->comm, ret); | |
4a776f0a | 755 | list_del(&thread->node); |
2d88ce76 | 756 | put_task_struct(thread->task); |
4a776f0a HS |
757 | kfree(thread); |
758 | } | |
9704efaa VK |
759 | |
760 | /* terminate all transfers on specified channels */ | |
944ea4dd | 761 | dmaengine_terminate_all(dtc->chan); |
9704efaa | 762 | |
4a776f0a HS |
763 | kfree(dtc); |
764 | } | |
765 | ||
e03e93a9 AS |
766 | static int dmatest_add_threads(struct dmatest_info *info, |
767 | struct dmatest_chan *dtc, enum dma_transaction_type type) | |
4a776f0a | 768 | { |
15b8a8ea | 769 | struct dmatest_params *params = &info->params; |
b54d5cb9 DW |
770 | struct dmatest_thread *thread; |
771 | struct dma_chan *chan = dtc->chan; | |
772 | char *op; | |
773 | unsigned int i; | |
4a776f0a | 774 | |
b54d5cb9 DW |
775 | if (type == DMA_MEMCPY) |
776 | op = "copy"; | |
a0d4cb44 KA |
777 | else if (type == DMA_SG) |
778 | op = "sg"; | |
b54d5cb9 DW |
779 | else if (type == DMA_XOR) |
780 | op = "xor"; | |
58691d64 DW |
781 | else if (type == DMA_PQ) |
782 | op = "pq"; | |
b54d5cb9 DW |
783 | else |
784 | return -EINVAL; | |
4a776f0a | 785 | |
15b8a8ea | 786 | for (i = 0; i < params->threads_per_chan; i++) { |
4a776f0a HS |
787 | thread = kzalloc(sizeof(struct dmatest_thread), GFP_KERNEL); |
788 | if (!thread) { | |
0adff800 DW |
789 | pr_warn("No memory for %s-%s%u\n", |
790 | dma_chan_name(chan), op, i); | |
4a776f0a HS |
791 | break; |
792 | } | |
e03e93a9 | 793 | thread->info = info; |
4a776f0a | 794 | thread->chan = dtc->chan; |
b54d5cb9 | 795 | thread->type = type; |
4a776f0a | 796 | smp_wmb(); |
2d88ce76 | 797 | thread->task = kthread_create(dmatest_func, thread, "%s-%s%u", |
b54d5cb9 | 798 | dma_chan_name(chan), op, i); |
4a776f0a | 799 | if (IS_ERR(thread->task)) { |
2d88ce76 | 800 | pr_warn("Failed to create thread %s-%s%u\n", |
0adff800 | 801 | dma_chan_name(chan), op, i); |
4a776f0a HS |
802 | kfree(thread); |
803 | break; | |
804 | } | |
805 | ||
806 | /* srcbuf and dstbuf are allocated by the thread itself */ | |
2d88ce76 | 807 | get_task_struct(thread->task); |
4a776f0a | 808 | list_add_tail(&thread->node, &dtc->threads); |
2d88ce76 | 809 | wake_up_process(thread->task); |
4a776f0a HS |
810 | } |
811 | ||
b54d5cb9 DW |
812 | return i; |
813 | } | |
814 | ||
e03e93a9 AS |
815 | static int dmatest_add_channel(struct dmatest_info *info, |
816 | struct dma_chan *chan) | |
b54d5cb9 DW |
817 | { |
818 | struct dmatest_chan *dtc; | |
819 | struct dma_device *dma_dev = chan->device; | |
820 | unsigned int thread_count = 0; | |
b9033e68 | 821 | int cnt; |
b54d5cb9 DW |
822 | |
823 | dtc = kmalloc(sizeof(struct dmatest_chan), GFP_KERNEL); | |
824 | if (!dtc) { | |
0adff800 | 825 | pr_warn("No memory for %s\n", dma_chan_name(chan)); |
b54d5cb9 DW |
826 | return -ENOMEM; |
827 | } | |
828 | ||
829 | dtc->chan = chan; | |
830 | INIT_LIST_HEAD(&dtc->threads); | |
831 | ||
832 | if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) { | |
a0d4cb44 KA |
833 | if (dmatest == 0) { |
834 | cnt = dmatest_add_threads(info, dtc, DMA_MEMCPY); | |
835 | thread_count += cnt > 0 ? cnt : 0; | |
836 | } | |
b54d5cb9 | 837 | } |
a0d4cb44 KA |
838 | |
839 | if (dma_has_cap(DMA_SG, dma_dev->cap_mask)) { | |
840 | if (dmatest == 1) { | |
841 | cnt = dmatest_add_threads(info, dtc, DMA_SG); | |
842 | thread_count += cnt > 0 ? cnt : 0; | |
843 | } | |
844 | } | |
845 | ||
b54d5cb9 | 846 | if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) { |
e03e93a9 | 847 | cnt = dmatest_add_threads(info, dtc, DMA_XOR); |
f1aef8b6 | 848 | thread_count += cnt > 0 ? cnt : 0; |
b54d5cb9 | 849 | } |
58691d64 | 850 | if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) { |
e03e93a9 | 851 | cnt = dmatest_add_threads(info, dtc, DMA_PQ); |
d07a74a5 | 852 | thread_count += cnt > 0 ? cnt : 0; |
58691d64 | 853 | } |
b54d5cb9 | 854 | |
0adff800 | 855 | pr_info("Started %u threads using %s\n", |
b54d5cb9 | 856 | thread_count, dma_chan_name(chan)); |
4a776f0a | 857 | |
838cc704 AS |
858 | list_add_tail(&dtc->node, &info->channels); |
859 | info->nr_channels++; | |
4a776f0a | 860 | |
33df8ca0 | 861 | return 0; |
4a776f0a HS |
862 | } |
863 | ||
7dd60251 | 864 | static bool filter(struct dma_chan *chan, void *param) |
4a776f0a | 865 | { |
15b8a8ea | 866 | struct dmatest_params *params = param; |
e03e93a9 | 867 | |
15b8a8ea AS |
868 | if (!dmatest_match_channel(params, chan) || |
869 | !dmatest_match_device(params, chan->device)) | |
7dd60251 | 870 | return false; |
33df8ca0 | 871 | else |
7dd60251 | 872 | return true; |
4a776f0a HS |
873 | } |
874 | ||
a9e55495 DW |
875 | static void request_channels(struct dmatest_info *info, |
876 | enum dma_transaction_type type) | |
4a776f0a | 877 | { |
33df8ca0 | 878 | dma_cap_mask_t mask; |
33df8ca0 DW |
879 | |
880 | dma_cap_zero(mask); | |
a9e55495 | 881 | dma_cap_set(type, mask); |
33df8ca0 | 882 | for (;;) { |
a9e55495 DW |
883 | struct dmatest_params *params = &info->params; |
884 | struct dma_chan *chan; | |
885 | ||
15b8a8ea | 886 | chan = dma_request_channel(mask, filter, params); |
33df8ca0 | 887 | if (chan) { |
a9e55495 | 888 | if (dmatest_add_channel(info, chan)) { |
33df8ca0 DW |
889 | dma_release_channel(chan); |
890 | break; /* add_channel failed, punt */ | |
891 | } | |
892 | } else | |
893 | break; /* no more channels available */ | |
15b8a8ea AS |
894 | if (params->max_channels && |
895 | info->nr_channels >= params->max_channels) | |
33df8ca0 DW |
896 | break; /* we have all we need */ |
897 | } | |
4a776f0a | 898 | } |
4a776f0a | 899 | |
a9e55495 | 900 | static void run_threaded_test(struct dmatest_info *info) |
851b7e16 | 901 | { |
a9e55495 | 902 | struct dmatest_params *params = &info->params; |
851b7e16 | 903 | |
a9e55495 DW |
904 | /* Copy test parameters */ |
905 | params->buf_size = test_buf_size; | |
906 | strlcpy(params->channel, strim(test_channel), sizeof(params->channel)); | |
907 | strlcpy(params->device, strim(test_device), sizeof(params->device)); | |
908 | params->threads_per_chan = threads_per_chan; | |
909 | params->max_channels = max_channels; | |
910 | params->iterations = iterations; | |
911 | params->xor_sources = xor_sources; | |
912 | params->pq_sources = pq_sources; | |
913 | params->timeout = timeout; | |
e3b9c347 | 914 | params->noverify = noverify; |
a9e55495 DW |
915 | |
916 | request_channels(info, DMA_MEMCPY); | |
917 | request_channels(info, DMA_XOR); | |
a0d4cb44 | 918 | request_channels(info, DMA_SG); |
a9e55495 | 919 | request_channels(info, DMA_PQ); |
851b7e16 | 920 | } |
851b7e16 | 921 | |
a310d037 | 922 | static void stop_threaded_test(struct dmatest_info *info) |
4a776f0a | 923 | { |
33df8ca0 | 924 | struct dmatest_chan *dtc, *_dtc; |
7cbd4877 | 925 | struct dma_chan *chan; |
33df8ca0 | 926 | |
838cc704 | 927 | list_for_each_entry_safe(dtc, _dtc, &info->channels, node) { |
33df8ca0 | 928 | list_del(&dtc->node); |
7cbd4877 | 929 | chan = dtc->chan; |
33df8ca0 | 930 | dmatest_cleanup_channel(dtc); |
0adff800 | 931 | pr_debug("dropped channel %s\n", dma_chan_name(chan)); |
7cbd4877 | 932 | dma_release_channel(chan); |
33df8ca0 | 933 | } |
838cc704 AS |
934 | |
935 | info->nr_channels = 0; | |
4a776f0a | 936 | } |
e03e93a9 | 937 | |
a9e55495 | 938 | static void restart_threaded_test(struct dmatest_info *info, bool run) |
851b7e16 | 939 | { |
a310d037 DW |
940 | /* we might be called early to set run=, defer running until all |
941 | * parameters have been evaluated | |
942 | */ | |
943 | if (!info->did_init) | |
a9e55495 | 944 | return; |
851b7e16 AS |
945 | |
946 | /* Stop any running test first */ | |
a310d037 | 947 | stop_threaded_test(info); |
851b7e16 AS |
948 | |
949 | /* Run test with new parameters */ | |
a9e55495 | 950 | run_threaded_test(info); |
851b7e16 AS |
951 | } |
952 | ||
a310d037 | 953 | static int dmatest_run_get(char *val, const struct kernel_param *kp) |
851b7e16 | 954 | { |
a310d037 | 955 | struct dmatest_info *info = &test_info; |
851b7e16 AS |
956 | |
957 | mutex_lock(&info->lock); | |
a310d037 DW |
958 | if (is_threaded_test_run(info)) { |
959 | dmatest_run = true; | |
3e5ccd86 | 960 | } else { |
a310d037 DW |
961 | stop_threaded_test(info); |
962 | dmatest_run = false; | |
3e5ccd86 | 963 | } |
851b7e16 | 964 | mutex_unlock(&info->lock); |
851b7e16 | 965 | |
a310d037 | 966 | return param_get_bool(val, kp); |
851b7e16 AS |
967 | } |
968 | ||
a310d037 | 969 | static int dmatest_run_set(const char *val, const struct kernel_param *kp) |
95019c8c | 970 | { |
a310d037 DW |
971 | struct dmatest_info *info = &test_info; |
972 | int ret; | |
95019c8c | 973 | |
a310d037 DW |
974 | mutex_lock(&info->lock); |
975 | ret = param_set_bool(val, kp); | |
976 | if (ret) { | |
851b7e16 | 977 | mutex_unlock(&info->lock); |
a310d037 | 978 | return ret; |
95019c8c AS |
979 | } |
980 | ||
a310d037 DW |
981 | if (is_threaded_test_run(info)) |
982 | ret = -EBUSY; | |
983 | else if (dmatest_run) | |
a9e55495 | 984 | restart_threaded_test(info, dmatest_run); |
851b7e16 | 985 | |
a310d037 | 986 | mutex_unlock(&info->lock); |
851b7e16 | 987 | |
a310d037 | 988 | return ret; |
851b7e16 AS |
989 | } |
990 | ||
e03e93a9 AS |
991 | static int __init dmatest_init(void) |
992 | { | |
993 | struct dmatest_info *info = &test_info; | |
2d88ce76 | 994 | struct dmatest_params *params = &info->params; |
e03e93a9 | 995 | |
a310d037 DW |
996 | if (dmatest_run) { |
997 | mutex_lock(&info->lock); | |
a9e55495 | 998 | run_threaded_test(info); |
a310d037 DW |
999 | mutex_unlock(&info->lock); |
1000 | } | |
838cc704 | 1001 | |
2d88ce76 DW |
1002 | if (params->iterations && wait) |
1003 | wait_event(thread_wait, !is_threaded_test_run(info)); | |
95019c8c | 1004 | |
a310d037 DW |
1005 | /* module parameters are stable, inittime tests are started, |
1006 | * let userspace take over 'run' control | |
1007 | */ | |
1008 | info->did_init = true; | |
851b7e16 | 1009 | |
851b7e16 | 1010 | return 0; |
e03e93a9 AS |
1011 | } |
1012 | /* when compiled-in wait for drivers to load first */ | |
1013 | late_initcall(dmatest_init); | |
1014 | ||
1015 | static void __exit dmatest_exit(void) | |
1016 | { | |
1017 | struct dmatest_info *info = &test_info; | |
1018 | ||
a310d037 | 1019 | mutex_lock(&info->lock); |
e03e93a9 | 1020 | stop_threaded_test(info); |
a310d037 | 1021 | mutex_unlock(&info->lock); |
e03e93a9 | 1022 | } |
4a776f0a HS |
1023 | module_exit(dmatest_exit); |
1024 | ||
e05503ef | 1025 | MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); |
4a776f0a | 1026 | MODULE_LICENSE("GPL v2"); |