Commit | Line | Data |
---|---|---|
3bfb1d20 | 1 | /* |
b801479b | 2 | * Core driver for the Synopsys DesignWare DMA Controller |
3bfb1d20 HS |
3 | * |
4 | * Copyright (C) 2007-2008 Atmel Corporation | |
aecb7b64 | 5 | * Copyright (C) 2010-2011 ST Microelectronics |
9cade1a4 | 6 | * Copyright (C) 2013 Intel Corporation |
3bfb1d20 HS |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
b801479b | 12 | |
327e6970 | 13 | #include <linux/bitops.h> |
3bfb1d20 HS |
14 | #include <linux/delay.h> |
15 | #include <linux/dmaengine.h> | |
16 | #include <linux/dma-mapping.h> | |
f8122a82 | 17 | #include <linux/dmapool.h> |
7331205a | 18 | #include <linux/err.h> |
3bfb1d20 HS |
19 | #include <linux/init.h> |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/io.h> | |
22 | #include <linux/mm.h> | |
23 | #include <linux/module.h> | |
3bfb1d20 | 24 | #include <linux/slab.h> |
bb32baf7 | 25 | #include <linux/pm_runtime.h> |
3bfb1d20 | 26 | |
61a76496 | 27 | #include "../dmaengine.h" |
9cade1a4 | 28 | #include "internal.h" |
3bfb1d20 HS |
29 | |
30 | /* | |
31 | * This supports the Synopsys "DesignWare AHB Central DMA Controller", | |
32 | * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all | |
33 | * of which use ARM any more). See the "Databook" from Synopsys for | |
34 | * information beyond what licensees probably provide. | |
35 | * | |
dd5720b3 AS |
36 | * The driver has been tested with the Atmel AT32AP7000, which does not |
37 | * support descriptor writeback. | |
3bfb1d20 HS |
38 | */ |
39 | ||
327e6970 | 40 | #define DWC_DEFAULT_CTLLO(_chan) ({ \ |
327e6970 VK |
41 | struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan); \ |
42 | struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \ | |
495aea4b | 43 | bool _is_slave = is_slave_direction(_dwc->direction); \ |
495aea4b | 44 | u8 _smsize = _is_slave ? _sconfig->src_maxburst : \ |
327e6970 | 45 | DW_DMA_MSIZE_16; \ |
495aea4b | 46 | u8 _dmsize = _is_slave ? _sconfig->dst_maxburst : \ |
327e6970 | 47 | DW_DMA_MSIZE_16; \ |
bb3450ad MR |
48 | u8 _dms = (_dwc->direction == DMA_MEM_TO_DEV) ? \ |
49 | _dwc->p_master : _dwc->m_master; \ | |
50 | u8 _sms = (_dwc->direction == DMA_DEV_TO_MEM) ? \ | |
51 | _dwc->p_master : _dwc->m_master; \ | |
f301c062 | 52 | \ |
327e6970 VK |
53 | (DWC_CTLL_DST_MSIZE(_dmsize) \ |
54 | | DWC_CTLL_SRC_MSIZE(_smsize) \ | |
f301c062 JI |
55 | | DWC_CTLL_LLP_D_EN \ |
56 | | DWC_CTLL_LLP_S_EN \ | |
bb3450ad MR |
57 | | DWC_CTLL_DMS(_dms) \ |
58 | | DWC_CTLL_SMS(_sms)); \ | |
f301c062 | 59 | }) |
3bfb1d20 | 60 | |
029a40e9 AS |
61 | /* The set of bus widths supported by the DMA controller */ |
62 | #define DW_DMA_BUSWIDTHS \ | |
63 | BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \ | |
64 | BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ | |
65 | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ | |
66 | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | |
67 | ||
3bfb1d20 | 68 | /*----------------------------------------------------------------------*/ |
3bfb1d20 | 69 | |
41d5e59c DW |
70 | static struct device *chan2dev(struct dma_chan *chan) |
71 | { | |
72 | return &chan->dev->device; | |
73 | } | |
41d5e59c | 74 | |
3bfb1d20 HS |
75 | static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc) |
76 | { | |
e63a47a3 | 77 | return to_dw_desc(dwc->active_list.next); |
3bfb1d20 HS |
78 | } |
79 | ||
ab703f81 | 80 | static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx) |
3bfb1d20 | 81 | { |
ab703f81 CL |
82 | struct dw_desc *desc = txd_to_dw_desc(tx); |
83 | struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan); | |
84 | dma_cookie_t cookie; | |
85 | unsigned long flags; | |
3bfb1d20 | 86 | |
69cea5a0 | 87 | spin_lock_irqsave(&dwc->lock, flags); |
ab703f81 CL |
88 | cookie = dma_cookie_assign(tx); |
89 | ||
90 | /* | |
91 | * REVISIT: We should attempt to chain as many descriptors as | |
92 | * possible, perhaps even appending to those already submitted | |
93 | * for DMA. But this is hard to do in a race-free manner. | |
94 | */ | |
95 | ||
96 | list_add_tail(&desc->desc_node, &dwc->queue); | |
69cea5a0 | 97 | spin_unlock_irqrestore(&dwc->lock, flags); |
ab703f81 CL |
98 | dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", |
99 | __func__, desc->txd.cookie); | |
3bfb1d20 | 100 | |
ab703f81 CL |
101 | return cookie; |
102 | } | |
3bfb1d20 | 103 | |
ab703f81 CL |
104 | static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc) |
105 | { | |
106 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
107 | struct dw_desc *desc; | |
108 | dma_addr_t phys; | |
109 | ||
110 | desc = dma_pool_zalloc(dw->desc_pool, GFP_ATOMIC, &phys); | |
111 | if (!desc) | |
112 | return NULL; | |
113 | ||
114 | dwc->descs_allocated++; | |
115 | INIT_LIST_HEAD(&desc->tx_list); | |
116 | dma_async_tx_descriptor_init(&desc->txd, &dwc->chan); | |
117 | desc->txd.tx_submit = dwc_tx_submit; | |
118 | desc->txd.flags = DMA_CTRL_ACK; | |
119 | desc->txd.phys = phys; | |
120 | return desc; | |
3bfb1d20 HS |
121 | } |
122 | ||
3bfb1d20 HS |
123 | static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc) |
124 | { | |
ab703f81 CL |
125 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); |
126 | struct dw_desc *child, *_next; | |
69cea5a0 | 127 | |
ab703f81 CL |
128 | if (unlikely(!desc)) |
129 | return; | |
3bfb1d20 | 130 | |
ab703f81 CL |
131 | list_for_each_entry_safe(child, _next, &desc->tx_list, desc_node) { |
132 | list_del(&child->desc_node); | |
133 | dma_pool_free(dw->desc_pool, child, child->txd.phys); | |
134 | dwc->descs_allocated--; | |
3bfb1d20 | 135 | } |
ab703f81 CL |
136 | |
137 | dma_pool_free(dw->desc_pool, desc, desc->txd.phys); | |
138 | dwc->descs_allocated--; | |
3bfb1d20 HS |
139 | } |
140 | ||
61e183f8 VK |
141 | static void dwc_initialize(struct dw_dma_chan *dwc) |
142 | { | |
143 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
61e183f8 VK |
144 | u32 cfghi = DWC_CFGH_FIFO_MODE; |
145 | u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority); | |
146 | ||
423f9cbf | 147 | if (test_bit(DW_DMA_IS_INITIALIZED, &dwc->flags)) |
61e183f8 VK |
148 | return; |
149 | ||
3fe6409c AS |
150 | cfghi |= DWC_CFGH_DST_PER(dwc->dst_id); |
151 | cfghi |= DWC_CFGH_SRC_PER(dwc->src_id); | |
61e183f8 VK |
152 | |
153 | channel_writel(dwc, CFG_LO, cfglo); | |
154 | channel_writel(dwc, CFG_HI, cfghi); | |
155 | ||
156 | /* Enable interrupts */ | |
157 | channel_set_bit(dw, MASK.XFER, dwc->mask); | |
61e183f8 VK |
158 | channel_set_bit(dw, MASK.ERROR, dwc->mask); |
159 | ||
423f9cbf | 160 | set_bit(DW_DMA_IS_INITIALIZED, &dwc->flags); |
61e183f8 VK |
161 | } |
162 | ||
3bfb1d20 HS |
163 | /*----------------------------------------------------------------------*/ |
164 | ||
f52b36d2 | 165 | static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc) |
1d455437 AS |
166 | { |
167 | dev_err(chan2dev(&dwc->chan), | |
168 | " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n", | |
169 | channel_readl(dwc, SAR), | |
170 | channel_readl(dwc, DAR), | |
171 | channel_readl(dwc, LLP), | |
172 | channel_readl(dwc, CTL_HI), | |
173 | channel_readl(dwc, CTL_LO)); | |
174 | } | |
175 | ||
3f936207 AS |
176 | static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc) |
177 | { | |
178 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
179 | while (dma_readl(dw, CH_EN) & dwc->mask) | |
180 | cpu_relax(); | |
181 | } | |
182 | ||
1d455437 AS |
183 | /*----------------------------------------------------------------------*/ |
184 | ||
fed2574b AS |
185 | /* Perform single block transfer */ |
186 | static inline void dwc_do_single_block(struct dw_dma_chan *dwc, | |
187 | struct dw_desc *desc) | |
188 | { | |
189 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
190 | u32 ctllo; | |
191 | ||
1d566f11 AS |
192 | /* |
193 | * Software emulation of LLP mode relies on interrupts to continue | |
194 | * multi block transfer. | |
195 | */ | |
df1f3a23 | 196 | ctllo = lli_read(desc, ctllo) | DWC_CTLL_INT_EN; |
fed2574b | 197 | |
df1f3a23 MR |
198 | channel_writel(dwc, SAR, lli_read(desc, sar)); |
199 | channel_writel(dwc, DAR, lli_read(desc, dar)); | |
fed2574b | 200 | channel_writel(dwc, CTL_LO, ctllo); |
df1f3a23 | 201 | channel_writel(dwc, CTL_HI, lli_read(desc, ctlhi)); |
fed2574b | 202 | channel_set_bit(dw, CH_EN, dwc->mask); |
f5c6a7df AS |
203 | |
204 | /* Move pointer to next descriptor */ | |
205 | dwc->tx_node_active = dwc->tx_node_active->next; | |
fed2574b AS |
206 | } |
207 | ||
3bfb1d20 HS |
208 | /* Called with dwc->lock held and bh disabled */ |
209 | static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first) | |
210 | { | |
211 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
2a0fae02 | 212 | u8 lms = DWC_LLP_LMS(dwc->m_master); |
fed2574b | 213 | unsigned long was_soft_llp; |
3bfb1d20 HS |
214 | |
215 | /* ASSERT: channel is idle */ | |
216 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
41d5e59c | 217 | dev_err(chan2dev(&dwc->chan), |
550da64b JN |
218 | "%s: BUG: Attempted to start non-idle channel\n", |
219 | __func__); | |
1d455437 | 220 | dwc_dump_chan_regs(dwc); |
3bfb1d20 HS |
221 | |
222 | /* The tasklet will hopefully advance the queue... */ | |
223 | return; | |
224 | } | |
225 | ||
fed2574b AS |
226 | if (dwc->nollp) { |
227 | was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP, | |
228 | &dwc->flags); | |
229 | if (was_soft_llp) { | |
230 | dev_err(chan2dev(&dwc->chan), | |
fc61f6b4 | 231 | "BUG: Attempted to start new LLP transfer inside ongoing one\n"); |
fed2574b AS |
232 | return; |
233 | } | |
234 | ||
235 | dwc_initialize(dwc); | |
236 | ||
b68fd097 | 237 | first->residue = first->total_len; |
f5c6a7df | 238 | dwc->tx_node_active = &first->tx_list; |
fed2574b | 239 | |
fdf475fa | 240 | /* Submit first block */ |
fed2574b AS |
241 | dwc_do_single_block(dwc, first); |
242 | ||
243 | return; | |
244 | } | |
245 | ||
61e183f8 VK |
246 | dwc_initialize(dwc); |
247 | ||
2a0fae02 MR |
248 | channel_writel(dwc, LLP, first->txd.phys | lms); |
249 | channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); | |
3bfb1d20 HS |
250 | channel_writel(dwc, CTL_HI, 0); |
251 | channel_set_bit(dw, CH_EN, dwc->mask); | |
252 | } | |
253 | ||
e7637c6c AS |
254 | static void dwc_dostart_first_queued(struct dw_dma_chan *dwc) |
255 | { | |
cba15617 AS |
256 | struct dw_desc *desc; |
257 | ||
e7637c6c AS |
258 | if (list_empty(&dwc->queue)) |
259 | return; | |
260 | ||
261 | list_move(dwc->queue.next, &dwc->active_list); | |
cba15617 AS |
262 | desc = dwc_first_active(dwc); |
263 | dev_vdbg(chan2dev(&dwc->chan), "%s: started %u\n", __func__, desc->txd.cookie); | |
264 | dwc_dostart(dwc, desc); | |
e7637c6c AS |
265 | } |
266 | ||
3bfb1d20 HS |
267 | /*----------------------------------------------------------------------*/ |
268 | ||
269 | static void | |
5fedefb8 VK |
270 | dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc, |
271 | bool callback_required) | |
3bfb1d20 | 272 | { |
5fedefb8 VK |
273 | dma_async_tx_callback callback = NULL; |
274 | void *param = NULL; | |
3bfb1d20 | 275 | struct dma_async_tx_descriptor *txd = &desc->txd; |
e518076e | 276 | struct dw_desc *child; |
69cea5a0 | 277 | unsigned long flags; |
3bfb1d20 | 278 | |
41d5e59c | 279 | dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie); |
3bfb1d20 | 280 | |
69cea5a0 | 281 | spin_lock_irqsave(&dwc->lock, flags); |
f7fbce07 | 282 | dma_cookie_complete(txd); |
5fedefb8 VK |
283 | if (callback_required) { |
284 | callback = txd->callback; | |
285 | param = txd->callback_param; | |
286 | } | |
3bfb1d20 | 287 | |
e518076e VK |
288 | /* async_tx_ack */ |
289 | list_for_each_entry(child, &desc->tx_list, desc_node) | |
290 | async_tx_ack(&child->txd); | |
291 | async_tx_ack(&desc->txd); | |
ab703f81 | 292 | dwc_desc_put(dwc, desc); |
69cea5a0 VK |
293 | spin_unlock_irqrestore(&dwc->lock, flags); |
294 | ||
21e93c1e | 295 | if (callback) |
3bfb1d20 HS |
296 | callback(param); |
297 | } | |
298 | ||
299 | static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
300 | { | |
301 | struct dw_desc *desc, *_desc; | |
302 | LIST_HEAD(list); | |
69cea5a0 | 303 | unsigned long flags; |
3bfb1d20 | 304 | |
69cea5a0 | 305 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 306 | if (dma_readl(dw, CH_EN) & dwc->mask) { |
41d5e59c | 307 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
308 | "BUG: XFER bit set, but channel not idle!\n"); |
309 | ||
310 | /* Try to continue after resetting the channel... */ | |
3f936207 | 311 | dwc_chan_disable(dw, dwc); |
3bfb1d20 HS |
312 | } |
313 | ||
314 | /* | |
315 | * Submit queued descriptors ASAP, i.e. before we go through | |
316 | * the completed ones. | |
317 | */ | |
3bfb1d20 | 318 | list_splice_init(&dwc->active_list, &list); |
e7637c6c | 319 | dwc_dostart_first_queued(dwc); |
3bfb1d20 | 320 | |
69cea5a0 VK |
321 | spin_unlock_irqrestore(&dwc->lock, flags); |
322 | ||
3bfb1d20 | 323 | list_for_each_entry_safe(desc, _desc, &list, desc_node) |
5fedefb8 | 324 | dwc_descriptor_complete(dwc, desc, true); |
3bfb1d20 HS |
325 | } |
326 | ||
4702d524 AS |
327 | /* Returns how many bytes were already received from source */ |
328 | static inline u32 dwc_get_sent(struct dw_dma_chan *dwc) | |
329 | { | |
330 | u32 ctlhi = channel_readl(dwc, CTL_HI); | |
331 | u32 ctllo = channel_readl(dwc, CTL_LO); | |
332 | ||
333 | return (ctlhi & DWC_CTLH_BLOCK_TS_MASK) * (1 << (ctllo >> 4 & 7)); | |
334 | } | |
335 | ||
3bfb1d20 HS |
336 | static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc) |
337 | { | |
338 | dma_addr_t llp; | |
339 | struct dw_desc *desc, *_desc; | |
340 | struct dw_desc *child; | |
341 | u32 status_xfer; | |
69cea5a0 | 342 | unsigned long flags; |
3bfb1d20 | 343 | |
69cea5a0 | 344 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
345 | llp = channel_readl(dwc, LLP); |
346 | status_xfer = dma_readl(dw, RAW.XFER); | |
347 | ||
348 | if (status_xfer & dwc->mask) { | |
349 | /* Everything we've submitted is done */ | |
350 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
77bcc497 AS |
351 | |
352 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { | |
fdf475fa AS |
353 | struct list_head *head, *active = dwc->tx_node_active; |
354 | ||
355 | /* | |
356 | * We are inside first active descriptor. | |
357 | * Otherwise something is really wrong. | |
358 | */ | |
359 | desc = dwc_first_active(dwc); | |
360 | ||
361 | head = &desc->tx_list; | |
362 | if (active != head) { | |
b68fd097 AS |
363 | /* Update residue to reflect last sent descriptor */ |
364 | if (active == head->next) | |
365 | desc->residue -= desc->len; | |
366 | else | |
367 | desc->residue -= to_dw_desc(active->prev)->len; | |
4702d524 | 368 | |
fdf475fa | 369 | child = to_dw_desc(active); |
77bcc497 AS |
370 | |
371 | /* Submit next block */ | |
fdf475fa | 372 | dwc_do_single_block(dwc, child); |
77bcc497 | 373 | |
fdf475fa | 374 | spin_unlock_irqrestore(&dwc->lock, flags); |
77bcc497 AS |
375 | return; |
376 | } | |
fdf475fa | 377 | |
77bcc497 AS |
378 | /* We are done here */ |
379 | clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); | |
380 | } | |
4702d524 | 381 | |
69cea5a0 VK |
382 | spin_unlock_irqrestore(&dwc->lock, flags); |
383 | ||
3bfb1d20 HS |
384 | dwc_complete_all(dw, dwc); |
385 | return; | |
386 | } | |
387 | ||
69cea5a0 VK |
388 | if (list_empty(&dwc->active_list)) { |
389 | spin_unlock_irqrestore(&dwc->lock, flags); | |
087809fc | 390 | return; |
69cea5a0 | 391 | } |
087809fc | 392 | |
77bcc497 AS |
393 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { |
394 | dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__); | |
69cea5a0 | 395 | spin_unlock_irqrestore(&dwc->lock, flags); |
087809fc | 396 | return; |
69cea5a0 | 397 | } |
087809fc | 398 | |
5a87f0e6 | 399 | dev_vdbg(chan2dev(&dwc->chan), "%s: llp=%pad\n", __func__, &llp); |
3bfb1d20 HS |
400 | |
401 | list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) { | |
75c61225 | 402 | /* Initial residue value */ |
b68fd097 | 403 | desc->residue = desc->total_len; |
4702d524 | 404 | |
75c61225 | 405 | /* Check first descriptors addr */ |
2a0fae02 | 406 | if (desc->txd.phys == DWC_LLP_LOC(llp)) { |
69cea5a0 | 407 | spin_unlock_irqrestore(&dwc->lock, flags); |
84adccfb | 408 | return; |
69cea5a0 | 409 | } |
84adccfb | 410 | |
75c61225 | 411 | /* Check first descriptors llp */ |
df1f3a23 | 412 | if (lli_read(desc, llp) == llp) { |
3bfb1d20 | 413 | /* This one is currently in progress */ |
b68fd097 | 414 | desc->residue -= dwc_get_sent(dwc); |
69cea5a0 | 415 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 416 | return; |
69cea5a0 | 417 | } |
3bfb1d20 | 418 | |
b68fd097 | 419 | desc->residue -= desc->len; |
4702d524 | 420 | list_for_each_entry(child, &desc->tx_list, desc_node) { |
df1f3a23 | 421 | if (lli_read(child, llp) == llp) { |
3bfb1d20 | 422 | /* Currently in progress */ |
b68fd097 | 423 | desc->residue -= dwc_get_sent(dwc); |
69cea5a0 | 424 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 425 | return; |
69cea5a0 | 426 | } |
b68fd097 | 427 | desc->residue -= child->len; |
4702d524 | 428 | } |
3bfb1d20 HS |
429 | |
430 | /* | |
431 | * No descriptors so far seem to be in progress, i.e. | |
432 | * this one must be done. | |
433 | */ | |
69cea5a0 | 434 | spin_unlock_irqrestore(&dwc->lock, flags); |
5fedefb8 | 435 | dwc_descriptor_complete(dwc, desc, true); |
69cea5a0 | 436 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 HS |
437 | } |
438 | ||
41d5e59c | 439 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
440 | "BUG: All descriptors done, but channel not idle!\n"); |
441 | ||
442 | /* Try to continue after resetting the channel... */ | |
3f936207 | 443 | dwc_chan_disable(dw, dwc); |
3bfb1d20 | 444 | |
e7637c6c | 445 | dwc_dostart_first_queued(dwc); |
69cea5a0 | 446 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 HS |
447 | } |
448 | ||
df1f3a23 | 449 | static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_desc *desc) |
3bfb1d20 | 450 | { |
21d43f49 | 451 | dev_crit(chan2dev(&dwc->chan), " desc: s0x%x d0x%x l0x%x c0x%x:%x\n", |
df1f3a23 MR |
452 | lli_read(desc, sar), |
453 | lli_read(desc, dar), | |
454 | lli_read(desc, llp), | |
455 | lli_read(desc, ctlhi), | |
456 | lli_read(desc, ctllo)); | |
3bfb1d20 HS |
457 | } |
458 | ||
459 | static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
460 | { | |
461 | struct dw_desc *bad_desc; | |
462 | struct dw_desc *child; | |
69cea5a0 | 463 | unsigned long flags; |
3bfb1d20 HS |
464 | |
465 | dwc_scan_descriptors(dw, dwc); | |
466 | ||
69cea5a0 VK |
467 | spin_lock_irqsave(&dwc->lock, flags); |
468 | ||
3bfb1d20 HS |
469 | /* |
470 | * The descriptor currently at the head of the active list is | |
471 | * borked. Since we don't have any way to report errors, we'll | |
472 | * just have to scream loudly and try to carry on. | |
473 | */ | |
474 | bad_desc = dwc_first_active(dwc); | |
475 | list_del_init(&bad_desc->desc_node); | |
f336e42f | 476 | list_move(dwc->queue.next, dwc->active_list.prev); |
3bfb1d20 HS |
477 | |
478 | /* Clear the error flag and try to restart the controller */ | |
479 | dma_writel(dw, CLEAR.ERROR, dwc->mask); | |
480 | if (!list_empty(&dwc->active_list)) | |
481 | dwc_dostart(dwc, dwc_first_active(dwc)); | |
482 | ||
483 | /* | |
ba84bd71 | 484 | * WARN may seem harsh, but since this only happens |
3bfb1d20 HS |
485 | * when someone submits a bad physical address in a |
486 | * descriptor, we should consider ourselves lucky that the | |
487 | * controller flagged an error instead of scribbling over | |
488 | * random memory locations. | |
489 | */ | |
ba84bd71 AS |
490 | dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n" |
491 | " cookie: %d\n", bad_desc->txd.cookie); | |
df1f3a23 | 492 | dwc_dump_lli(dwc, bad_desc); |
e0bd0f8c | 493 | list_for_each_entry(child, &bad_desc->tx_list, desc_node) |
df1f3a23 | 494 | dwc_dump_lli(dwc, child); |
3bfb1d20 | 495 | |
69cea5a0 VK |
496 | spin_unlock_irqrestore(&dwc->lock, flags); |
497 | ||
3bfb1d20 | 498 | /* Pretend the descriptor completed successfully */ |
5fedefb8 | 499 | dwc_descriptor_complete(dwc, bad_desc, true); |
3bfb1d20 HS |
500 | } |
501 | ||
d9de4519 HCE |
502 | /* --------------------- Cyclic DMA API extensions -------------------- */ |
503 | ||
8004cbb4 | 504 | dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan) |
d9de4519 HCE |
505 | { |
506 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
507 | return channel_readl(dwc, SAR); | |
508 | } | |
509 | EXPORT_SYMBOL(dw_dma_get_src_addr); | |
510 | ||
8004cbb4 | 511 | dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan) |
d9de4519 HCE |
512 | { |
513 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
514 | return channel_readl(dwc, DAR); | |
515 | } | |
516 | EXPORT_SYMBOL(dw_dma_get_dst_addr); | |
517 | ||
75c61225 | 518 | /* Called with dwc->lock held and all DMAC interrupts disabled */ |
d9de4519 | 519 | static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc, |
2895b2ca | 520 | u32 status_block, u32 status_err, u32 status_xfer) |
d9de4519 | 521 | { |
69cea5a0 VK |
522 | unsigned long flags; |
523 | ||
2895b2ca | 524 | if (status_block & dwc->mask) { |
d9de4519 HCE |
525 | void (*callback)(void *param); |
526 | void *callback_param; | |
527 | ||
528 | dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n", | |
529 | channel_readl(dwc, LLP)); | |
2895b2ca | 530 | dma_writel(dw, CLEAR.BLOCK, dwc->mask); |
d9de4519 HCE |
531 | |
532 | callback = dwc->cdesc->period_callback; | |
533 | callback_param = dwc->cdesc->period_callback_param; | |
69cea5a0 VK |
534 | |
535 | if (callback) | |
d9de4519 | 536 | callback(callback_param); |
d9de4519 HCE |
537 | } |
538 | ||
539 | /* | |
540 | * Error and transfer complete are highly unlikely, and will most | |
541 | * likely be due to a configuration error by the user. | |
542 | */ | |
543 | if (unlikely(status_err & dwc->mask) || | |
544 | unlikely(status_xfer & dwc->mask)) { | |
7794e5b9 | 545 | unsigned int i; |
d9de4519 | 546 | |
fc61f6b4 AS |
547 | dev_err(chan2dev(&dwc->chan), |
548 | "cyclic DMA unexpected %s interrupt, stopping DMA transfer\n", | |
549 | status_xfer ? "xfer" : "error"); | |
69cea5a0 VK |
550 | |
551 | spin_lock_irqsave(&dwc->lock, flags); | |
552 | ||
1d455437 | 553 | dwc_dump_chan_regs(dwc); |
d9de4519 | 554 | |
3f936207 | 555 | dwc_chan_disable(dw, dwc); |
d9de4519 | 556 | |
75c61225 | 557 | /* Make sure DMA does not restart by loading a new list */ |
d9de4519 HCE |
558 | channel_writel(dwc, LLP, 0); |
559 | channel_writel(dwc, CTL_LO, 0); | |
560 | channel_writel(dwc, CTL_HI, 0); | |
561 | ||
2895b2ca | 562 | dma_writel(dw, CLEAR.BLOCK, dwc->mask); |
d9de4519 HCE |
563 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
564 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
565 | ||
566 | for (i = 0; i < dwc->cdesc->periods; i++) | |
df1f3a23 | 567 | dwc_dump_lli(dwc, dwc->cdesc->desc[i]); |
69cea5a0 VK |
568 | |
569 | spin_unlock_irqrestore(&dwc->lock, flags); | |
d9de4519 | 570 | } |
ee1cdcda AS |
571 | |
572 | /* Re-enable interrupts */ | |
573 | channel_set_bit(dw, MASK.BLOCK, dwc->mask); | |
d9de4519 HCE |
574 | } |
575 | ||
576 | /* ------------------------------------------------------------------------- */ | |
577 | ||
3bfb1d20 HS |
578 | static void dw_dma_tasklet(unsigned long data) |
579 | { | |
580 | struct dw_dma *dw = (struct dw_dma *)data; | |
581 | struct dw_dma_chan *dwc; | |
2895b2ca | 582 | u32 status_block; |
3bfb1d20 HS |
583 | u32 status_xfer; |
584 | u32 status_err; | |
7794e5b9 | 585 | unsigned int i; |
3bfb1d20 | 586 | |
2895b2ca | 587 | status_block = dma_readl(dw, RAW.BLOCK); |
7fe7b2f4 | 588 | status_xfer = dma_readl(dw, RAW.XFER); |
3bfb1d20 HS |
589 | status_err = dma_readl(dw, RAW.ERROR); |
590 | ||
2e4c364e | 591 | dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err); |
3bfb1d20 HS |
592 | |
593 | for (i = 0; i < dw->dma.chancnt; i++) { | |
594 | dwc = &dw->chan[i]; | |
d9de4519 | 595 | if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) |
2895b2ca MR |
596 | dwc_handle_cyclic(dw, dwc, status_block, status_err, |
597 | status_xfer); | |
d9de4519 | 598 | else if (status_err & (1 << i)) |
3bfb1d20 | 599 | dwc_handle_error(dw, dwc); |
77bcc497 | 600 | else if (status_xfer & (1 << i)) |
3bfb1d20 | 601 | dwc_scan_descriptors(dw, dwc); |
3bfb1d20 HS |
602 | } |
603 | ||
ee1cdcda | 604 | /* Re-enable interrupts */ |
3bfb1d20 | 605 | channel_set_bit(dw, MASK.XFER, dw->all_chan_mask); |
3bfb1d20 HS |
606 | channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask); |
607 | } | |
608 | ||
609 | static irqreturn_t dw_dma_interrupt(int irq, void *dev_id) | |
610 | { | |
611 | struct dw_dma *dw = dev_id; | |
02a21b79 | 612 | u32 status; |
3bfb1d20 | 613 | |
02a21b79 AS |
614 | /* Check if we have any interrupt from the DMAC which is not in use */ |
615 | if (!dw->in_use) | |
616 | return IRQ_NONE; | |
617 | ||
618 | status = dma_readl(dw, STATUS_INT); | |
3783cef8 AS |
619 | dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, status); |
620 | ||
621 | /* Check if we have any interrupt from the DMAC */ | |
02a21b79 | 622 | if (!status) |
3783cef8 | 623 | return IRQ_NONE; |
3bfb1d20 HS |
624 | |
625 | /* | |
626 | * Just disable the interrupts. We'll turn them back on in the | |
627 | * softirq handler. | |
628 | */ | |
629 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
2895b2ca | 630 | channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); |
3bfb1d20 HS |
631 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); |
632 | ||
633 | status = dma_readl(dw, STATUS_INT); | |
634 | if (status) { | |
635 | dev_err(dw->dma.dev, | |
636 | "BUG: Unexpected interrupts pending: 0x%x\n", | |
637 | status); | |
638 | ||
639 | /* Try to recover */ | |
640 | channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1); | |
2895b2ca | 641 | channel_clear_bit(dw, MASK.BLOCK, (1 << 8) - 1); |
3bfb1d20 HS |
642 | channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1); |
643 | channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1); | |
644 | channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1); | |
645 | } | |
646 | ||
647 | tasklet_schedule(&dw->tasklet); | |
648 | ||
649 | return IRQ_HANDLED; | |
650 | } | |
651 | ||
652 | /*----------------------------------------------------------------------*/ | |
653 | ||
3bfb1d20 HS |
654 | static struct dma_async_tx_descriptor * |
655 | dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
656 | size_t len, unsigned long flags) | |
657 | { | |
658 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
f776076b | 659 | struct dw_dma *dw = to_dw_dma(chan->device); |
3bfb1d20 HS |
660 | struct dw_desc *desc; |
661 | struct dw_desc *first; | |
662 | struct dw_desc *prev; | |
663 | size_t xfer_count; | |
664 | size_t offset; | |
2e65060e | 665 | u8 m_master = dwc->m_master; |
3bfb1d20 HS |
666 | unsigned int src_width; |
667 | unsigned int dst_width; | |
161c3d04 | 668 | unsigned int data_width = dw->pdata->data_width[m_master]; |
3bfb1d20 | 669 | u32 ctllo; |
2e65060e | 670 | u8 lms = DWC_LLP_LMS(m_master); |
3bfb1d20 | 671 | |
2f45d613 | 672 | dev_vdbg(chan2dev(chan), |
5a87f0e6 AS |
673 | "%s: d%pad s%pad l0x%zx f0x%lx\n", __func__, |
674 | &dest, &src, len, flags); | |
3bfb1d20 HS |
675 | |
676 | if (unlikely(!len)) { | |
2e4c364e | 677 | dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__); |
3bfb1d20 HS |
678 | return NULL; |
679 | } | |
680 | ||
0fdb567f AS |
681 | dwc->direction = DMA_MEM_TO_MEM; |
682 | ||
2e65060e | 683 | src_width = dst_width = __ffs(data_width | src | dest | len); |
3bfb1d20 | 684 | |
327e6970 | 685 | ctllo = DWC_DEFAULT_CTLLO(chan) |
3bfb1d20 HS |
686 | | DWC_CTLL_DST_WIDTH(dst_width) |
687 | | DWC_CTLL_SRC_WIDTH(src_width) | |
688 | | DWC_CTLL_DST_INC | |
689 | | DWC_CTLL_SRC_INC | |
690 | | DWC_CTLL_FC_M2M; | |
691 | prev = first = NULL; | |
692 | ||
693 | for (offset = 0; offset < len; offset += xfer_count << src_width) { | |
694 | xfer_count = min_t(size_t, (len - offset) >> src_width, | |
4a63a8b3 | 695 | dwc->block_size); |
3bfb1d20 HS |
696 | |
697 | desc = dwc_desc_get(dwc); | |
698 | if (!desc) | |
699 | goto err_desc_get; | |
700 | ||
df1f3a23 MR |
701 | lli_write(desc, sar, src + offset); |
702 | lli_write(desc, dar, dest + offset); | |
703 | lli_write(desc, ctllo, ctllo); | |
704 | lli_write(desc, ctlhi, xfer_count); | |
176dcec5 | 705 | desc->len = xfer_count << src_width; |
3bfb1d20 HS |
706 | |
707 | if (!first) { | |
708 | first = desc; | |
709 | } else { | |
2a0fae02 | 710 | lli_write(prev, llp, desc->txd.phys | lms); |
df1f3a23 | 711 | list_add_tail(&desc->desc_node, &first->tx_list); |
3bfb1d20 HS |
712 | } |
713 | prev = desc; | |
714 | } | |
715 | ||
3bfb1d20 HS |
716 | if (flags & DMA_PREP_INTERRUPT) |
717 | /* Trigger interrupt after last block */ | |
df1f3a23 | 718 | lli_set(prev, ctllo, DWC_CTLL_INT_EN); |
3bfb1d20 HS |
719 | |
720 | prev->lli.llp = 0; | |
a3e55799 | 721 | lli_clear(prev, ctllo, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); |
3bfb1d20 | 722 | first->txd.flags = flags; |
30d38a32 | 723 | first->total_len = len; |
3bfb1d20 HS |
724 | |
725 | return &first->txd; | |
726 | ||
727 | err_desc_get: | |
728 | dwc_desc_put(dwc, first); | |
729 | return NULL; | |
730 | } | |
731 | ||
732 | static struct dma_async_tx_descriptor * | |
733 | dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 734 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 735 | unsigned long flags, void *context) |
3bfb1d20 HS |
736 | { |
737 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
f776076b | 738 | struct dw_dma *dw = to_dw_dma(chan->device); |
327e6970 | 739 | struct dma_slave_config *sconfig = &dwc->dma_sconfig; |
3bfb1d20 HS |
740 | struct dw_desc *prev; |
741 | struct dw_desc *first; | |
742 | u32 ctllo; | |
2e65060e AS |
743 | u8 m_master = dwc->m_master; |
744 | u8 lms = DWC_LLP_LMS(m_master); | |
3bfb1d20 HS |
745 | dma_addr_t reg; |
746 | unsigned int reg_width; | |
747 | unsigned int mem_width; | |
161c3d04 | 748 | unsigned int data_width = dw->pdata->data_width[m_master]; |
3bfb1d20 HS |
749 | unsigned int i; |
750 | struct scatterlist *sg; | |
751 | size_t total_len = 0; | |
752 | ||
2e4c364e | 753 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
3bfb1d20 | 754 | |
495aea4b | 755 | if (unlikely(!is_slave_direction(direction) || !sg_len)) |
3bfb1d20 HS |
756 | return NULL; |
757 | ||
0fdb567f AS |
758 | dwc->direction = direction; |
759 | ||
3bfb1d20 HS |
760 | prev = first = NULL; |
761 | ||
3bfb1d20 | 762 | switch (direction) { |
db8196df | 763 | case DMA_MEM_TO_DEV: |
39416677 | 764 | reg_width = __ffs(sconfig->dst_addr_width); |
327e6970 VK |
765 | reg = sconfig->dst_addr; |
766 | ctllo = (DWC_DEFAULT_CTLLO(chan) | |
3bfb1d20 HS |
767 | | DWC_CTLL_DST_WIDTH(reg_width) |
768 | | DWC_CTLL_DST_FIX | |
327e6970 VK |
769 | | DWC_CTLL_SRC_INC); |
770 | ||
771 | ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) : | |
772 | DWC_CTLL_FC(DW_DMA_FC_D_M2P); | |
773 | ||
3bfb1d20 HS |
774 | for_each_sg(sgl, sg, sg_len, i) { |
775 | struct dw_desc *desc; | |
69dc14b5 | 776 | u32 len, dlen, mem; |
3bfb1d20 | 777 | |
cbb796cc | 778 | mem = sg_dma_address(sg); |
69dc14b5 | 779 | len = sg_dma_len(sg); |
6bc711f6 | 780 | |
2e65060e | 781 | mem_width = __ffs(data_width | mem | len); |
3bfb1d20 | 782 | |
69dc14b5 | 783 | slave_sg_todev_fill_desc: |
3bfb1d20 | 784 | desc = dwc_desc_get(dwc); |
b2607227 | 785 | if (!desc) |
3bfb1d20 | 786 | goto err_desc_get; |
3bfb1d20 | 787 | |
df1f3a23 MR |
788 | lli_write(desc, sar, mem); |
789 | lli_write(desc, dar, reg); | |
790 | lli_write(desc, ctllo, ctllo | DWC_CTLL_SRC_WIDTH(mem_width)); | |
4a63a8b3 AS |
791 | if ((len >> mem_width) > dwc->block_size) { |
792 | dlen = dwc->block_size << mem_width; | |
69dc14b5 VK |
793 | mem += dlen; |
794 | len -= dlen; | |
795 | } else { | |
796 | dlen = len; | |
797 | len = 0; | |
798 | } | |
799 | ||
df1f3a23 | 800 | lli_write(desc, ctlhi, dlen >> mem_width); |
176dcec5 | 801 | desc->len = dlen; |
3bfb1d20 HS |
802 | |
803 | if (!first) { | |
804 | first = desc; | |
805 | } else { | |
2a0fae02 | 806 | lli_write(prev, llp, desc->txd.phys | lms); |
df1f3a23 | 807 | list_add_tail(&desc->desc_node, &first->tx_list); |
3bfb1d20 HS |
808 | } |
809 | prev = desc; | |
69dc14b5 VK |
810 | total_len += dlen; |
811 | ||
812 | if (len) | |
813 | goto slave_sg_todev_fill_desc; | |
3bfb1d20 HS |
814 | } |
815 | break; | |
db8196df | 816 | case DMA_DEV_TO_MEM: |
39416677 | 817 | reg_width = __ffs(sconfig->src_addr_width); |
327e6970 VK |
818 | reg = sconfig->src_addr; |
819 | ctllo = (DWC_DEFAULT_CTLLO(chan) | |
3bfb1d20 HS |
820 | | DWC_CTLL_SRC_WIDTH(reg_width) |
821 | | DWC_CTLL_DST_INC | |
327e6970 VK |
822 | | DWC_CTLL_SRC_FIX); |
823 | ||
824 | ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) : | |
825 | DWC_CTLL_FC(DW_DMA_FC_D_P2M); | |
3bfb1d20 | 826 | |
3bfb1d20 HS |
827 | for_each_sg(sgl, sg, sg_len, i) { |
828 | struct dw_desc *desc; | |
69dc14b5 | 829 | u32 len, dlen, mem; |
3bfb1d20 | 830 | |
cbb796cc | 831 | mem = sg_dma_address(sg); |
3bfb1d20 | 832 | len = sg_dma_len(sg); |
6bc711f6 | 833 | |
2e65060e | 834 | mem_width = __ffs(data_width | mem | len); |
3bfb1d20 | 835 | |
69dc14b5 VK |
836 | slave_sg_fromdev_fill_desc: |
837 | desc = dwc_desc_get(dwc); | |
b2607227 | 838 | if (!desc) |
69dc14b5 | 839 | goto err_desc_get; |
69dc14b5 | 840 | |
df1f3a23 MR |
841 | lli_write(desc, sar, reg); |
842 | lli_write(desc, dar, mem); | |
843 | lli_write(desc, ctllo, ctllo | DWC_CTLL_DST_WIDTH(mem_width)); | |
4a63a8b3 AS |
844 | if ((len >> reg_width) > dwc->block_size) { |
845 | dlen = dwc->block_size << reg_width; | |
69dc14b5 VK |
846 | mem += dlen; |
847 | len -= dlen; | |
848 | } else { | |
849 | dlen = len; | |
850 | len = 0; | |
851 | } | |
df1f3a23 | 852 | lli_write(desc, ctlhi, dlen >> reg_width); |
176dcec5 | 853 | desc->len = dlen; |
3bfb1d20 HS |
854 | |
855 | if (!first) { | |
856 | first = desc; | |
857 | } else { | |
2a0fae02 | 858 | lli_write(prev, llp, desc->txd.phys | lms); |
df1f3a23 | 859 | list_add_tail(&desc->desc_node, &first->tx_list); |
3bfb1d20 HS |
860 | } |
861 | prev = desc; | |
69dc14b5 VK |
862 | total_len += dlen; |
863 | ||
864 | if (len) | |
865 | goto slave_sg_fromdev_fill_desc; | |
3bfb1d20 HS |
866 | } |
867 | break; | |
868 | default: | |
869 | return NULL; | |
870 | } | |
871 | ||
872 | if (flags & DMA_PREP_INTERRUPT) | |
873 | /* Trigger interrupt after last block */ | |
df1f3a23 | 874 | lli_set(prev, ctllo, DWC_CTLL_INT_EN); |
3bfb1d20 HS |
875 | |
876 | prev->lli.llp = 0; | |
a3e55799 | 877 | lli_clear(prev, ctllo, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); |
30d38a32 | 878 | first->total_len = total_len; |
3bfb1d20 HS |
879 | |
880 | return &first->txd; | |
881 | ||
882 | err_desc_get: | |
b2607227 JN |
883 | dev_err(chan2dev(chan), |
884 | "not enough descriptors available. Direction %d\n", direction); | |
3bfb1d20 HS |
885 | dwc_desc_put(dwc, first); |
886 | return NULL; | |
887 | } | |
888 | ||
4d130de2 AS |
889 | bool dw_dma_filter(struct dma_chan *chan, void *param) |
890 | { | |
891 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
892 | struct dw_dma_slave *dws = param; | |
893 | ||
3fe6409c | 894 | if (dws->dma_dev != chan->device->dev) |
4d130de2 AS |
895 | return false; |
896 | ||
897 | /* We have to copy data since dws can be temporary storage */ | |
898 | ||
899 | dwc->src_id = dws->src_id; | |
900 | dwc->dst_id = dws->dst_id; | |
901 | ||
c422025c AS |
902 | dwc->m_master = dws->m_master; |
903 | dwc->p_master = dws->p_master; | |
4d130de2 AS |
904 | |
905 | return true; | |
906 | } | |
907 | EXPORT_SYMBOL_GPL(dw_dma_filter); | |
908 | ||
327e6970 VK |
909 | /* |
910 | * Fix sconfig's burst size according to dw_dmac. We need to convert them as: | |
911 | * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3. | |
912 | * | |
913 | * NOTE: burst size 2 is not supported by controller. | |
914 | * | |
915 | * This can be done by finding least significant bit set: n & (n - 1) | |
916 | */ | |
917 | static inline void convert_burst(u32 *maxburst) | |
918 | { | |
919 | if (*maxburst > 1) | |
920 | *maxburst = fls(*maxburst) - 2; | |
921 | else | |
922 | *maxburst = 0; | |
923 | } | |
924 | ||
a4b0d348 | 925 | static int dwc_config(struct dma_chan *chan, struct dma_slave_config *sconfig) |
327e6970 VK |
926 | { |
927 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
928 | ||
495aea4b AS |
929 | /* Check if chan will be configured for slave transfers */ |
930 | if (!is_slave_direction(sconfig->direction)) | |
327e6970 VK |
931 | return -EINVAL; |
932 | ||
933 | memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig)); | |
0fdb567f | 934 | dwc->direction = sconfig->direction; |
327e6970 VK |
935 | |
936 | convert_burst(&dwc->dma_sconfig.src_maxburst); | |
937 | convert_burst(&dwc->dma_sconfig.dst_maxburst); | |
938 | ||
939 | return 0; | |
940 | } | |
941 | ||
a4b0d348 | 942 | static int dwc_pause(struct dma_chan *chan) |
21fe3c52 | 943 | { |
a4b0d348 MR |
944 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
945 | unsigned long flags; | |
946 | unsigned int count = 20; /* timeout iterations */ | |
947 | u32 cfglo; | |
948 | ||
949 | spin_lock_irqsave(&dwc->lock, flags); | |
21fe3c52 | 950 | |
a4b0d348 | 951 | cfglo = channel_readl(dwc, CFG_LO); |
21fe3c52 | 952 | channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP); |
123b69ab AS |
953 | while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--) |
954 | udelay(2); | |
21fe3c52 | 955 | |
5e09f98e | 956 | set_bit(DW_DMA_IS_PAUSED, &dwc->flags); |
a4b0d348 MR |
957 | |
958 | spin_unlock_irqrestore(&dwc->lock, flags); | |
959 | ||
960 | return 0; | |
21fe3c52 AS |
961 | } |
962 | ||
963 | static inline void dwc_chan_resume(struct dw_dma_chan *dwc) | |
964 | { | |
965 | u32 cfglo = channel_readl(dwc, CFG_LO); | |
966 | ||
967 | channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP); | |
968 | ||
5e09f98e | 969 | clear_bit(DW_DMA_IS_PAUSED, &dwc->flags); |
21fe3c52 AS |
970 | } |
971 | ||
a4b0d348 | 972 | static int dwc_resume(struct dma_chan *chan) |
3bfb1d20 HS |
973 | { |
974 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
69cea5a0 | 975 | unsigned long flags; |
3bfb1d20 | 976 | |
a4b0d348 | 977 | spin_lock_irqsave(&dwc->lock, flags); |
3bfb1d20 | 978 | |
5e09f98e AS |
979 | if (test_bit(DW_DMA_IS_PAUSED, &dwc->flags)) |
980 | dwc_chan_resume(dwc); | |
3bfb1d20 | 981 | |
a4b0d348 | 982 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 983 | |
a4b0d348 MR |
984 | return 0; |
985 | } | |
3bfb1d20 | 986 | |
a4b0d348 MR |
987 | static int dwc_terminate_all(struct dma_chan *chan) |
988 | { | |
989 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
990 | struct dw_dma *dw = to_dw_dma(chan->device); | |
991 | struct dw_desc *desc, *_desc; | |
992 | unsigned long flags; | |
993 | LIST_HEAD(list); | |
3bfb1d20 | 994 | |
a4b0d348 | 995 | spin_lock_irqsave(&dwc->lock, flags); |
fed2574b | 996 | |
a4b0d348 | 997 | clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); |
fed2574b | 998 | |
a4b0d348 | 999 | dwc_chan_disable(dw, dwc); |
a7c57cf7 | 1000 | |
a4b0d348 | 1001 | dwc_chan_resume(dwc); |
a7c57cf7 | 1002 | |
a4b0d348 MR |
1003 | /* active_list entries will end up before queued entries */ |
1004 | list_splice_init(&dwc->queue, &list); | |
1005 | list_splice_init(&dwc->active_list, &list); | |
a7c57cf7 | 1006 | |
a4b0d348 | 1007 | spin_unlock_irqrestore(&dwc->lock, flags); |
a7c57cf7 | 1008 | |
a4b0d348 MR |
1009 | /* Flush all pending and queued descriptors */ |
1010 | list_for_each_entry_safe(desc, _desc, &list, desc_node) | |
1011 | dwc_descriptor_complete(dwc, desc, false); | |
c3635c78 LW |
1012 | |
1013 | return 0; | |
3bfb1d20 HS |
1014 | } |
1015 | ||
b68fd097 AS |
1016 | static struct dw_desc *dwc_find_desc(struct dw_dma_chan *dwc, dma_cookie_t c) |
1017 | { | |
1018 | struct dw_desc *desc; | |
1019 | ||
1020 | list_for_each_entry(desc, &dwc->active_list, desc_node) | |
1021 | if (desc->txd.cookie == c) | |
1022 | return desc; | |
1023 | ||
1024 | return NULL; | |
1025 | } | |
1026 | ||
1027 | static u32 dwc_get_residue(struct dw_dma_chan *dwc, dma_cookie_t cookie) | |
4702d524 | 1028 | { |
b68fd097 | 1029 | struct dw_desc *desc; |
4702d524 AS |
1030 | unsigned long flags; |
1031 | u32 residue; | |
1032 | ||
1033 | spin_lock_irqsave(&dwc->lock, flags); | |
1034 | ||
b68fd097 AS |
1035 | desc = dwc_find_desc(dwc, cookie); |
1036 | if (desc) { | |
1037 | if (desc == dwc_first_active(dwc)) { | |
1038 | residue = desc->residue; | |
1039 | if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue) | |
1040 | residue -= dwc_get_sent(dwc); | |
1041 | } else { | |
1042 | residue = desc->total_len; | |
1043 | } | |
1044 | } else { | |
1045 | residue = 0; | |
1046 | } | |
4702d524 AS |
1047 | |
1048 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1049 | return residue; | |
1050 | } | |
1051 | ||
3bfb1d20 | 1052 | static enum dma_status |
07934481 LW |
1053 | dwc_tx_status(struct dma_chan *chan, |
1054 | dma_cookie_t cookie, | |
1055 | struct dma_tx_state *txstate) | |
3bfb1d20 HS |
1056 | { |
1057 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
96a2af41 | 1058 | enum dma_status ret; |
3bfb1d20 | 1059 | |
96a2af41 | 1060 | ret = dma_cookie_status(chan, cookie, txstate); |
2c40410b | 1061 | if (ret == DMA_COMPLETE) |
12381dc0 | 1062 | return ret; |
3bfb1d20 | 1063 | |
12381dc0 | 1064 | dwc_scan_descriptors(to_dw_dma(chan->device), dwc); |
3bfb1d20 | 1065 | |
12381dc0 | 1066 | ret = dma_cookie_status(chan, cookie, txstate); |
b68fd097 AS |
1067 | if (ret == DMA_COMPLETE) |
1068 | return ret; | |
1069 | ||
1070 | dma_set_residue(txstate, dwc_get_residue(dwc, cookie)); | |
3bfb1d20 | 1071 | |
5e09f98e | 1072 | if (test_bit(DW_DMA_IS_PAUSED, &dwc->flags) && ret == DMA_IN_PROGRESS) |
a7c57cf7 | 1073 | return DMA_PAUSED; |
3bfb1d20 HS |
1074 | |
1075 | return ret; | |
1076 | } | |
1077 | ||
1078 | static void dwc_issue_pending(struct dma_chan *chan) | |
1079 | { | |
1080 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
dd8ecfca | 1081 | unsigned long flags; |
3bfb1d20 | 1082 | |
dd8ecfca AS |
1083 | spin_lock_irqsave(&dwc->lock, flags); |
1084 | if (list_empty(&dwc->active_list)) | |
1085 | dwc_dostart_first_queued(dwc); | |
1086 | spin_unlock_irqrestore(&dwc->lock, flags); | |
3bfb1d20 HS |
1087 | } |
1088 | ||
99d9bf4e AS |
1089 | /*----------------------------------------------------------------------*/ |
1090 | ||
1091 | static void dw_dma_off(struct dw_dma *dw) | |
1092 | { | |
7794e5b9 | 1093 | unsigned int i; |
99d9bf4e AS |
1094 | |
1095 | dma_writel(dw, CFG, 0); | |
1096 | ||
1097 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
2895b2ca | 1098 | channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); |
99d9bf4e AS |
1099 | channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask); |
1100 | channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask); | |
1101 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); | |
1102 | ||
1103 | while (dma_readl(dw, CFG) & DW_CFG_DMA_EN) | |
1104 | cpu_relax(); | |
1105 | ||
1106 | for (i = 0; i < dw->dma.chancnt; i++) | |
423f9cbf | 1107 | clear_bit(DW_DMA_IS_INITIALIZED, &dw->chan[i].flags); |
99d9bf4e AS |
1108 | } |
1109 | ||
1110 | static void dw_dma_on(struct dw_dma *dw) | |
1111 | { | |
1112 | dma_writel(dw, CFG, DW_CFG_DMA_EN); | |
1113 | } | |
1114 | ||
aa1e6f1a | 1115 | static int dwc_alloc_chan_resources(struct dma_chan *chan) |
3bfb1d20 HS |
1116 | { |
1117 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1118 | struct dw_dma *dw = to_dw_dma(chan->device); | |
3bfb1d20 | 1119 | |
2e4c364e | 1120 | dev_vdbg(chan2dev(chan), "%s\n", __func__); |
3bfb1d20 | 1121 | |
3bfb1d20 HS |
1122 | /* ASSERT: channel is idle */ |
1123 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
41d5e59c | 1124 | dev_dbg(chan2dev(chan), "DMA channel not idle?\n"); |
3bfb1d20 HS |
1125 | return -EIO; |
1126 | } | |
1127 | ||
d3ee98cd | 1128 | dma_cookie_init(chan); |
3bfb1d20 | 1129 | |
3bfb1d20 HS |
1130 | /* |
1131 | * NOTE: some controllers may have additional features that we | |
1132 | * need to initialize here, like "scatter-gather" (which | |
1133 | * doesn't mean what you think it means), and status writeback. | |
1134 | */ | |
1135 | ||
3fe6409c AS |
1136 | /* |
1137 | * We need controller-specific data to set up slave transfers. | |
1138 | */ | |
1139 | if (chan->private && !dw_dma_filter(chan, chan->private)) { | |
1140 | dev_warn(chan2dev(chan), "Wrong controller-specific data\n"); | |
1141 | return -EINVAL; | |
1142 | } | |
1143 | ||
99d9bf4e AS |
1144 | /* Enable controller here if needed */ |
1145 | if (!dw->in_use) | |
1146 | dw_dma_on(dw); | |
1147 | dw->in_use |= dwc->mask; | |
1148 | ||
ab703f81 | 1149 | return 0; |
3bfb1d20 HS |
1150 | } |
1151 | ||
1152 | static void dwc_free_chan_resources(struct dma_chan *chan) | |
1153 | { | |
1154 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1155 | struct dw_dma *dw = to_dw_dma(chan->device); | |
69cea5a0 | 1156 | unsigned long flags; |
3bfb1d20 HS |
1157 | LIST_HEAD(list); |
1158 | ||
2e4c364e | 1159 | dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__, |
3bfb1d20 HS |
1160 | dwc->descs_allocated); |
1161 | ||
1162 | /* ASSERT: channel is idle */ | |
1163 | BUG_ON(!list_empty(&dwc->active_list)); | |
1164 | BUG_ON(!list_empty(&dwc->queue)); | |
1165 | BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask); | |
1166 | ||
69cea5a0 | 1167 | spin_lock_irqsave(&dwc->lock, flags); |
3fe6409c AS |
1168 | |
1169 | /* Clear custom channel configuration */ | |
1170 | dwc->src_id = 0; | |
1171 | dwc->dst_id = 0; | |
1172 | ||
c422025c AS |
1173 | dwc->m_master = 0; |
1174 | dwc->p_master = 0; | |
3fe6409c | 1175 | |
423f9cbf | 1176 | clear_bit(DW_DMA_IS_INITIALIZED, &dwc->flags); |
3bfb1d20 HS |
1177 | |
1178 | /* Disable interrupts */ | |
1179 | channel_clear_bit(dw, MASK.XFER, dwc->mask); | |
2895b2ca | 1180 | channel_clear_bit(dw, MASK.BLOCK, dwc->mask); |
3bfb1d20 HS |
1181 | channel_clear_bit(dw, MASK.ERROR, dwc->mask); |
1182 | ||
69cea5a0 | 1183 | spin_unlock_irqrestore(&dwc->lock, flags); |
3bfb1d20 | 1184 | |
99d9bf4e AS |
1185 | /* Disable controller in case it was a last user */ |
1186 | dw->in_use &= ~dwc->mask; | |
1187 | if (!dw->in_use) | |
1188 | dw_dma_off(dw); | |
1189 | ||
2e4c364e | 1190 | dev_vdbg(chan2dev(chan), "%s: done\n", __func__); |
3bfb1d20 HS |
1191 | } |
1192 | ||
d9de4519 HCE |
1193 | /* --------------------- Cyclic DMA API extensions -------------------- */ |
1194 | ||
1195 | /** | |
1196 | * dw_dma_cyclic_start - start the cyclic DMA transfer | |
1197 | * @chan: the DMA channel to start | |
1198 | * | |
1199 | * Must be called with soft interrupts disabled. Returns zero on success or | |
1200 | * -errno on failure. | |
1201 | */ | |
1202 | int dw_dma_cyclic_start(struct dma_chan *chan) | |
1203 | { | |
1204 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
ee1cdcda | 1205 | struct dw_dma *dw = to_dw_dma(chan->device); |
69cea5a0 | 1206 | unsigned long flags; |
d9de4519 HCE |
1207 | |
1208 | if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) { | |
1209 | dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n"); | |
1210 | return -ENODEV; | |
1211 | } | |
1212 | ||
69cea5a0 | 1213 | spin_lock_irqsave(&dwc->lock, flags); |
ee1cdcda AS |
1214 | |
1215 | /* Enable interrupts to perform cyclic transfer */ | |
1216 | channel_set_bit(dw, MASK.BLOCK, dwc->mask); | |
1217 | ||
df3bb8a0 | 1218 | dwc_dostart(dwc, dwc->cdesc->desc[0]); |
ee1cdcda | 1219 | |
69cea5a0 | 1220 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1221 | |
1222 | return 0; | |
1223 | } | |
1224 | EXPORT_SYMBOL(dw_dma_cyclic_start); | |
1225 | ||
1226 | /** | |
1227 | * dw_dma_cyclic_stop - stop the cyclic DMA transfer | |
1228 | * @chan: the DMA channel to stop | |
1229 | * | |
1230 | * Must be called with soft interrupts disabled. | |
1231 | */ | |
1232 | void dw_dma_cyclic_stop(struct dma_chan *chan) | |
1233 | { | |
1234 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1235 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
69cea5a0 | 1236 | unsigned long flags; |
d9de4519 | 1237 | |
69cea5a0 | 1238 | spin_lock_irqsave(&dwc->lock, flags); |
d9de4519 | 1239 | |
3f936207 | 1240 | dwc_chan_disable(dw, dwc); |
d9de4519 | 1241 | |
69cea5a0 | 1242 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1243 | } |
1244 | EXPORT_SYMBOL(dw_dma_cyclic_stop); | |
1245 | ||
1246 | /** | |
1247 | * dw_dma_cyclic_prep - prepare the cyclic DMA transfer | |
1248 | * @chan: the DMA channel to prepare | |
1249 | * @buf_addr: physical DMA address where the buffer starts | |
1250 | * @buf_len: total number of bytes for the entire buffer | |
1251 | * @period_len: number of bytes for each period | |
1252 | * @direction: transfer direction, to or from device | |
1253 | * | |
1254 | * Must be called before trying to start the transfer. Returns a valid struct | |
1255 | * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful. | |
1256 | */ | |
1257 | struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan, | |
1258 | dma_addr_t buf_addr, size_t buf_len, size_t period_len, | |
db8196df | 1259 | enum dma_transfer_direction direction) |
d9de4519 HCE |
1260 | { |
1261 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
327e6970 | 1262 | struct dma_slave_config *sconfig = &dwc->dma_sconfig; |
d9de4519 HCE |
1263 | struct dw_cyclic_desc *cdesc; |
1264 | struct dw_cyclic_desc *retval = NULL; | |
1265 | struct dw_desc *desc; | |
1266 | struct dw_desc *last = NULL; | |
2a0fae02 | 1267 | u8 lms = DWC_LLP_LMS(dwc->m_master); |
d9de4519 HCE |
1268 | unsigned long was_cyclic; |
1269 | unsigned int reg_width; | |
1270 | unsigned int periods; | |
1271 | unsigned int i; | |
69cea5a0 | 1272 | unsigned long flags; |
d9de4519 | 1273 | |
69cea5a0 | 1274 | spin_lock_irqsave(&dwc->lock, flags); |
fed2574b AS |
1275 | if (dwc->nollp) { |
1276 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1277 | dev_dbg(chan2dev(&dwc->chan), | |
1278 | "channel doesn't support LLP transfers\n"); | |
1279 | return ERR_PTR(-EINVAL); | |
1280 | } | |
1281 | ||
d9de4519 | 1282 | if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) { |
69cea5a0 | 1283 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1284 | dev_dbg(chan2dev(&dwc->chan), |
1285 | "queue and/or active list are not empty\n"); | |
1286 | return ERR_PTR(-EBUSY); | |
1287 | } | |
1288 | ||
1289 | was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
69cea5a0 | 1290 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1291 | if (was_cyclic) { |
1292 | dev_dbg(chan2dev(&dwc->chan), | |
1293 | "channel already prepared for cyclic DMA\n"); | |
1294 | return ERR_PTR(-EBUSY); | |
1295 | } | |
1296 | ||
1297 | retval = ERR_PTR(-EINVAL); | |
327e6970 | 1298 | |
f44b92f4 AS |
1299 | if (unlikely(!is_slave_direction(direction))) |
1300 | goto out_err; | |
1301 | ||
0fdb567f AS |
1302 | dwc->direction = direction; |
1303 | ||
327e6970 VK |
1304 | if (direction == DMA_MEM_TO_DEV) |
1305 | reg_width = __ffs(sconfig->dst_addr_width); | |
1306 | else | |
1307 | reg_width = __ffs(sconfig->src_addr_width); | |
1308 | ||
d9de4519 HCE |
1309 | periods = buf_len / period_len; |
1310 | ||
1311 | /* Check for too big/unaligned periods and unaligned DMA buffer. */ | |
4a63a8b3 | 1312 | if (period_len > (dwc->block_size << reg_width)) |
d9de4519 HCE |
1313 | goto out_err; |
1314 | if (unlikely(period_len & ((1 << reg_width) - 1))) | |
1315 | goto out_err; | |
1316 | if (unlikely(buf_addr & ((1 << reg_width) - 1))) | |
1317 | goto out_err; | |
d9de4519 HCE |
1318 | |
1319 | retval = ERR_PTR(-ENOMEM); | |
1320 | ||
d9de4519 HCE |
1321 | cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL); |
1322 | if (!cdesc) | |
1323 | goto out_err; | |
1324 | ||
1325 | cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL); | |
1326 | if (!cdesc->desc) | |
1327 | goto out_err_alloc; | |
1328 | ||
1329 | for (i = 0; i < periods; i++) { | |
1330 | desc = dwc_desc_get(dwc); | |
1331 | if (!desc) | |
1332 | goto out_err_desc_get; | |
1333 | ||
1334 | switch (direction) { | |
db8196df | 1335 | case DMA_MEM_TO_DEV: |
df1f3a23 MR |
1336 | lli_write(desc, dar, sconfig->dst_addr); |
1337 | lli_write(desc, sar, buf_addr + period_len * i); | |
1338 | lli_write(desc, ctllo, (DWC_DEFAULT_CTLLO(chan) | |
1339 | | DWC_CTLL_DST_WIDTH(reg_width) | |
1340 | | DWC_CTLL_SRC_WIDTH(reg_width) | |
1341 | | DWC_CTLL_DST_FIX | |
1342 | | DWC_CTLL_SRC_INC | |
1343 | | DWC_CTLL_INT_EN)); | |
1344 | ||
1345 | lli_set(desc, ctllo, sconfig->device_fc ? | |
1346 | DWC_CTLL_FC(DW_DMA_FC_P_M2P) : | |
1347 | DWC_CTLL_FC(DW_DMA_FC_D_M2P)); | |
327e6970 | 1348 | |
d9de4519 | 1349 | break; |
db8196df | 1350 | case DMA_DEV_TO_MEM: |
df1f3a23 MR |
1351 | lli_write(desc, dar, buf_addr + period_len * i); |
1352 | lli_write(desc, sar, sconfig->src_addr); | |
1353 | lli_write(desc, ctllo, (DWC_DEFAULT_CTLLO(chan) | |
1354 | | DWC_CTLL_SRC_WIDTH(reg_width) | |
1355 | | DWC_CTLL_DST_WIDTH(reg_width) | |
1356 | | DWC_CTLL_DST_INC | |
1357 | | DWC_CTLL_SRC_FIX | |
1358 | | DWC_CTLL_INT_EN)); | |
1359 | ||
1360 | lli_set(desc, ctllo, sconfig->device_fc ? | |
1361 | DWC_CTLL_FC(DW_DMA_FC_P_P2M) : | |
1362 | DWC_CTLL_FC(DW_DMA_FC_D_P2M)); | |
327e6970 | 1363 | |
d9de4519 HCE |
1364 | break; |
1365 | default: | |
1366 | break; | |
1367 | } | |
1368 | ||
df1f3a23 | 1369 | lli_write(desc, ctlhi, period_len >> reg_width); |
d9de4519 HCE |
1370 | cdesc->desc[i] = desc; |
1371 | ||
f8122a82 | 1372 | if (last) |
2a0fae02 | 1373 | lli_write(last, llp, desc->txd.phys | lms); |
d9de4519 HCE |
1374 | |
1375 | last = desc; | |
1376 | } | |
1377 | ||
75c61225 | 1378 | /* Let's make a cyclic list */ |
2a0fae02 | 1379 | lli_write(last, llp, cdesc->desc[0]->txd.phys | lms); |
d9de4519 | 1380 | |
5a87f0e6 AS |
1381 | dev_dbg(chan2dev(&dwc->chan), |
1382 | "cyclic prepared buf %pad len %zu period %zu periods %d\n", | |
1383 | &buf_addr, buf_len, period_len, periods); | |
d9de4519 HCE |
1384 | |
1385 | cdesc->periods = periods; | |
1386 | dwc->cdesc = cdesc; | |
1387 | ||
1388 | return cdesc; | |
1389 | ||
1390 | out_err_desc_get: | |
1391 | while (i--) | |
1392 | dwc_desc_put(dwc, cdesc->desc[i]); | |
1393 | out_err_alloc: | |
1394 | kfree(cdesc); | |
1395 | out_err: | |
1396 | clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
1397 | return (struct dw_cyclic_desc *)retval; | |
1398 | } | |
1399 | EXPORT_SYMBOL(dw_dma_cyclic_prep); | |
1400 | ||
1401 | /** | |
1402 | * dw_dma_cyclic_free - free a prepared cyclic DMA transfer | |
1403 | * @chan: the DMA channel to free | |
1404 | */ | |
1405 | void dw_dma_cyclic_free(struct dma_chan *chan) | |
1406 | { | |
1407 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1408 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
1409 | struct dw_cyclic_desc *cdesc = dwc->cdesc; | |
7794e5b9 | 1410 | unsigned int i; |
69cea5a0 | 1411 | unsigned long flags; |
d9de4519 | 1412 | |
2e4c364e | 1413 | dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__); |
d9de4519 HCE |
1414 | |
1415 | if (!cdesc) | |
1416 | return; | |
1417 | ||
69cea5a0 | 1418 | spin_lock_irqsave(&dwc->lock, flags); |
d9de4519 | 1419 | |
3f936207 | 1420 | dwc_chan_disable(dw, dwc); |
d9de4519 | 1421 | |
2895b2ca | 1422 | dma_writel(dw, CLEAR.BLOCK, dwc->mask); |
d9de4519 HCE |
1423 | dma_writel(dw, CLEAR.ERROR, dwc->mask); |
1424 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
1425 | ||
69cea5a0 | 1426 | spin_unlock_irqrestore(&dwc->lock, flags); |
d9de4519 HCE |
1427 | |
1428 | for (i = 0; i < cdesc->periods; i++) | |
1429 | dwc_desc_put(dwc, cdesc->desc[i]); | |
1430 | ||
1431 | kfree(cdesc->desc); | |
1432 | kfree(cdesc); | |
1433 | ||
925a7d04 AS |
1434 | dwc->cdesc = NULL; |
1435 | ||
d9de4519 HCE |
1436 | clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); |
1437 | } | |
1438 | EXPORT_SYMBOL(dw_dma_cyclic_free); | |
1439 | ||
3bfb1d20 HS |
1440 | /*----------------------------------------------------------------------*/ |
1441 | ||
3a14c66d | 1442 | int dw_dma_probe(struct dw_dma_chip *chip) |
a9ddb575 | 1443 | { |
3a14c66d | 1444 | struct dw_dma_platform_data *pdata; |
3bfb1d20 | 1445 | struct dw_dma *dw; |
30cb2639 | 1446 | bool autocfg = false; |
482c67ea | 1447 | unsigned int dw_params; |
7794e5b9 | 1448 | unsigned int i; |
3bfb1d20 | 1449 | int err; |
3bfb1d20 | 1450 | |
000871ce AS |
1451 | dw = devm_kzalloc(chip->dev, sizeof(*dw), GFP_KERNEL); |
1452 | if (!dw) | |
1453 | return -ENOMEM; | |
1454 | ||
161c3d04 AS |
1455 | dw->pdata = devm_kzalloc(chip->dev, sizeof(*dw->pdata), GFP_KERNEL); |
1456 | if (!dw->pdata) | |
1457 | return -ENOMEM; | |
1458 | ||
000871ce AS |
1459 | dw->regs = chip->regs; |
1460 | chip->dw = dw; | |
1461 | ||
bb32baf7 AS |
1462 | pm_runtime_get_sync(chip->dev); |
1463 | ||
3a14c66d | 1464 | if (!chip->pdata) { |
897e40d3 | 1465 | dw_params = dma_readl(dw, DW_PARAMS); |
30cb2639 | 1466 | dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params); |
482c67ea | 1467 | |
30cb2639 AS |
1468 | autocfg = dw_params >> DW_PARAMS_EN & 1; |
1469 | if (!autocfg) { | |
1470 | err = -EINVAL; | |
1471 | goto err_pdata; | |
1472 | } | |
123de543 | 1473 | |
161c3d04 AS |
1474 | /* Reassign the platform data pointer */ |
1475 | pdata = dw->pdata; | |
123de543 | 1476 | |
30cb2639 AS |
1477 | /* Get hardware configuration parameters */ |
1478 | pdata->nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 7) + 1; | |
1479 | pdata->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1; | |
1480 | for (i = 0; i < pdata->nr_masters; i++) { | |
1481 | pdata->data_width[i] = | |
2e65060e | 1482 | 4 << (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3); |
30cb2639 | 1483 | } |
161c3d04 | 1484 | pdata->block_size = dma_readl(dw, MAX_BLK_SIZE); |
30cb2639 | 1485 | |
123de543 AS |
1486 | /* Fill platform data with the default values */ |
1487 | pdata->is_private = true; | |
df5c7386 | 1488 | pdata->is_memcpy = true; |
123de543 AS |
1489 | pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING; |
1490 | pdata->chan_priority = CHAN_PRIORITY_ASCENDING; | |
3a14c66d | 1491 | } else if (chip->pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) { |
8be4f523 AS |
1492 | err = -EINVAL; |
1493 | goto err_pdata; | |
161c3d04 | 1494 | } else { |
3a14c66d | 1495 | memcpy(dw->pdata, chip->pdata, sizeof(*dw->pdata)); |
161c3d04 AS |
1496 | |
1497 | /* Reassign the platform data pointer */ | |
1498 | pdata = dw->pdata; | |
8be4f523 | 1499 | } |
123de543 | 1500 | |
30cb2639 | 1501 | dw->chan = devm_kcalloc(chip->dev, pdata->nr_channels, sizeof(*dw->chan), |
000871ce | 1502 | GFP_KERNEL); |
8be4f523 AS |
1503 | if (!dw->chan) { |
1504 | err = -ENOMEM; | |
1505 | goto err_pdata; | |
1506 | } | |
3bfb1d20 | 1507 | |
11f932ec | 1508 | /* Calculate all channel mask before DMA setup */ |
30cb2639 | 1509 | dw->all_chan_mask = (1 << pdata->nr_channels) - 1; |
11f932ec | 1510 | |
75c61225 | 1511 | /* Force dma off, just in case */ |
3bfb1d20 HS |
1512 | dw_dma_off(dw); |
1513 | ||
75c61225 | 1514 | /* Create a pool of consistent memory blocks for hardware descriptors */ |
9cade1a4 | 1515 | dw->desc_pool = dmam_pool_create("dw_dmac_desc_pool", chip->dev, |
f8122a82 AS |
1516 | sizeof(struct dw_desc), 4, 0); |
1517 | if (!dw->desc_pool) { | |
9cade1a4 | 1518 | dev_err(chip->dev, "No memory for descriptors dma pool\n"); |
8be4f523 AS |
1519 | err = -ENOMEM; |
1520 | goto err_pdata; | |
f8122a82 AS |
1521 | } |
1522 | ||
3bfb1d20 HS |
1523 | tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw); |
1524 | ||
97977f75 AS |
1525 | err = request_irq(chip->irq, dw_dma_interrupt, IRQF_SHARED, |
1526 | "dw_dmac", dw); | |
1527 | if (err) | |
8be4f523 | 1528 | goto err_pdata; |
97977f75 | 1529 | |
3bfb1d20 | 1530 | INIT_LIST_HEAD(&dw->dma.channels); |
30cb2639 | 1531 | for (i = 0; i < pdata->nr_channels; i++) { |
3bfb1d20 HS |
1532 | struct dw_dma_chan *dwc = &dw->chan[i]; |
1533 | ||
1534 | dwc->chan.device = &dw->dma; | |
d3ee98cd | 1535 | dma_cookie_init(&dwc->chan); |
b0c3130d VK |
1536 | if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING) |
1537 | list_add_tail(&dwc->chan.device_node, | |
1538 | &dw->dma.channels); | |
1539 | else | |
1540 | list_add(&dwc->chan.device_node, &dw->dma.channels); | |
3bfb1d20 | 1541 | |
93317e8e VK |
1542 | /* 7 is highest priority & 0 is lowest. */ |
1543 | if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING) | |
30cb2639 | 1544 | dwc->priority = pdata->nr_channels - i - 1; |
93317e8e VK |
1545 | else |
1546 | dwc->priority = i; | |
1547 | ||
3bfb1d20 HS |
1548 | dwc->ch_regs = &__dw_regs(dw)->CHAN[i]; |
1549 | spin_lock_init(&dwc->lock); | |
1550 | dwc->mask = 1 << i; | |
1551 | ||
1552 | INIT_LIST_HEAD(&dwc->active_list); | |
1553 | INIT_LIST_HEAD(&dwc->queue); | |
3bfb1d20 HS |
1554 | |
1555 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
4a63a8b3 | 1556 | |
0fdb567f | 1557 | dwc->direction = DMA_TRANS_NONE; |
a0982004 | 1558 | |
75c61225 | 1559 | /* Hardware configuration */ |
fed2574b | 1560 | if (autocfg) { |
6bea0f6d | 1561 | unsigned int r = DW_DMA_MAX_NR_CHANNELS - i - 1; |
897e40d3 AS |
1562 | void __iomem *addr = &__dw_regs(dw)->DWC_PARAMS[r]; |
1563 | unsigned int dwc_params = dma_readl_native(addr); | |
fed2574b | 1564 | |
9cade1a4 AS |
1565 | dev_dbg(chip->dev, "DWC_PARAMS[%d]: 0x%08x\n", i, |
1566 | dwc_params); | |
985a6c7d | 1567 | |
1d566f11 AS |
1568 | /* |
1569 | * Decode maximum block size for given channel. The | |
4a63a8b3 | 1570 | * stored 4 bit value represents blocks from 0x00 for 3 |
1d566f11 AS |
1571 | * up to 0x0a for 4095. |
1572 | */ | |
4a63a8b3 | 1573 | dwc->block_size = |
161c3d04 | 1574 | (4 << ((pdata->block_size >> 4 * i) & 0xf)) - 1; |
fed2574b AS |
1575 | dwc->nollp = |
1576 | (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0; | |
1577 | } else { | |
4a63a8b3 | 1578 | dwc->block_size = pdata->block_size; |
fed2574b AS |
1579 | |
1580 | /* Check if channel supports multi block transfer */ | |
2a0fae02 MR |
1581 | channel_writel(dwc, LLP, DWC_LLP_LOC(0xffffffff)); |
1582 | dwc->nollp = DWC_LLP_LOC(channel_readl(dwc, LLP)) == 0; | |
fed2574b AS |
1583 | channel_writel(dwc, LLP, 0); |
1584 | } | |
3bfb1d20 HS |
1585 | } |
1586 | ||
11f932ec | 1587 | /* Clear all interrupts on all channels. */ |
3bfb1d20 | 1588 | dma_writel(dw, CLEAR.XFER, dw->all_chan_mask); |
236b106f | 1589 | dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask); |
3bfb1d20 HS |
1590 | dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask); |
1591 | dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask); | |
1592 | dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask); | |
1593 | ||
df5c7386 | 1594 | /* Set capabilities */ |
3bfb1d20 | 1595 | dma_cap_set(DMA_SLAVE, dw->dma.cap_mask); |
95ea759e JI |
1596 | if (pdata->is_private) |
1597 | dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask); | |
df5c7386 AS |
1598 | if (pdata->is_memcpy) |
1599 | dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask); | |
1600 | ||
9cade1a4 | 1601 | dw->dma.dev = chip->dev; |
3bfb1d20 HS |
1602 | dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources; |
1603 | dw->dma.device_free_chan_resources = dwc_free_chan_resources; | |
1604 | ||
1605 | dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy; | |
3bfb1d20 | 1606 | dw->dma.device_prep_slave_sg = dwc_prep_slave_sg; |
029a40e9 | 1607 | |
a4b0d348 MR |
1608 | dw->dma.device_config = dwc_config; |
1609 | dw->dma.device_pause = dwc_pause; | |
1610 | dw->dma.device_resume = dwc_resume; | |
1611 | dw->dma.device_terminate_all = dwc_terminate_all; | |
3bfb1d20 | 1612 | |
07934481 | 1613 | dw->dma.device_tx_status = dwc_tx_status; |
3bfb1d20 HS |
1614 | dw->dma.device_issue_pending = dwc_issue_pending; |
1615 | ||
029a40e9 AS |
1616 | /* DMA capabilities */ |
1617 | dw->dma.src_addr_widths = DW_DMA_BUSWIDTHS; | |
1618 | dw->dma.dst_addr_widths = DW_DMA_BUSWIDTHS; | |
1619 | dw->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) | | |
1620 | BIT(DMA_MEM_TO_MEM); | |
1621 | dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; | |
1622 | ||
1222934e AS |
1623 | err = dma_async_device_register(&dw->dma); |
1624 | if (err) | |
1625 | goto err_dma_register; | |
1626 | ||
9cade1a4 | 1627 | dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n", |
30cb2639 | 1628 | pdata->nr_channels); |
3bfb1d20 | 1629 | |
bb32baf7 AS |
1630 | pm_runtime_put_sync_suspend(chip->dev); |
1631 | ||
3bfb1d20 | 1632 | return 0; |
8be4f523 | 1633 | |
1222934e AS |
1634 | err_dma_register: |
1635 | free_irq(chip->irq, dw); | |
8be4f523 | 1636 | err_pdata: |
bb32baf7 | 1637 | pm_runtime_put_sync_suspend(chip->dev); |
8be4f523 | 1638 | return err; |
3bfb1d20 | 1639 | } |
9cade1a4 | 1640 | EXPORT_SYMBOL_GPL(dw_dma_probe); |
3bfb1d20 | 1641 | |
9cade1a4 | 1642 | int dw_dma_remove(struct dw_dma_chip *chip) |
3bfb1d20 | 1643 | { |
9cade1a4 | 1644 | struct dw_dma *dw = chip->dw; |
3bfb1d20 | 1645 | struct dw_dma_chan *dwc, *_dwc; |
3bfb1d20 | 1646 | |
bb32baf7 AS |
1647 | pm_runtime_get_sync(chip->dev); |
1648 | ||
3bfb1d20 HS |
1649 | dw_dma_off(dw); |
1650 | dma_async_device_unregister(&dw->dma); | |
1651 | ||
97977f75 | 1652 | free_irq(chip->irq, dw); |
3bfb1d20 HS |
1653 | tasklet_kill(&dw->tasklet); |
1654 | ||
1655 | list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels, | |
1656 | chan.device_node) { | |
1657 | list_del(&dwc->chan.device_node); | |
1658 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
1659 | } | |
1660 | ||
bb32baf7 | 1661 | pm_runtime_put_sync_suspend(chip->dev); |
3bfb1d20 HS |
1662 | return 0; |
1663 | } | |
9cade1a4 | 1664 | EXPORT_SYMBOL_GPL(dw_dma_remove); |
3bfb1d20 | 1665 | |
2540f74b | 1666 | int dw_dma_disable(struct dw_dma_chip *chip) |
3bfb1d20 | 1667 | { |
9cade1a4 | 1668 | struct dw_dma *dw = chip->dw; |
3bfb1d20 | 1669 | |
6168d567 | 1670 | dw_dma_off(dw); |
3bfb1d20 HS |
1671 | return 0; |
1672 | } | |
2540f74b | 1673 | EXPORT_SYMBOL_GPL(dw_dma_disable); |
3bfb1d20 | 1674 | |
2540f74b | 1675 | int dw_dma_enable(struct dw_dma_chip *chip) |
3bfb1d20 | 1676 | { |
9cade1a4 | 1677 | struct dw_dma *dw = chip->dw; |
3bfb1d20 | 1678 | |
7a83c045 | 1679 | dw_dma_on(dw); |
3bfb1d20 | 1680 | return 0; |
3bfb1d20 | 1681 | } |
2540f74b | 1682 | EXPORT_SYMBOL_GPL(dw_dma_enable); |
3bfb1d20 HS |
1683 | |
1684 | MODULE_LICENSE("GPL v2"); | |
9cade1a4 | 1685 | MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller core driver"); |
e05503ef | 1686 | MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); |
da89947b | 1687 | MODULE_AUTHOR("Viresh Kumar <vireshk@kernel.org>"); |