Commit | Line | Data |
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3bfb1d20 HS |
1 | /* |
2 | * Driver for the Synopsys DesignWare DMA Controller (aka DMACA on | |
3 | * AVR32 systems.) | |
4 | * | |
5 | * Copyright (C) 2007-2008 Atmel Corporation | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | #include <linux/clk.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/dmaengine.h> | |
14 | #include <linux/dma-mapping.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/mm.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/slab.h> | |
22 | ||
23 | #include "dw_dmac_regs.h" | |
24 | ||
25 | /* | |
26 | * This supports the Synopsys "DesignWare AHB Central DMA Controller", | |
27 | * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all | |
28 | * of which use ARM any more). See the "Databook" from Synopsys for | |
29 | * information beyond what licensees probably provide. | |
30 | * | |
31 | * The driver has currently been tested only with the Atmel AT32AP7000, | |
32 | * which does not support descriptor writeback. | |
33 | */ | |
34 | ||
35 | /* NOTE: DMS+SMS is system-specific. We should get this information | |
36 | * from the platform code somehow. | |
37 | */ | |
38 | #define DWC_DEFAULT_CTLLO (DWC_CTLL_DST_MSIZE(0) \ | |
39 | | DWC_CTLL_SRC_MSIZE(0) \ | |
40 | | DWC_CTLL_DMS(0) \ | |
41 | | DWC_CTLL_SMS(1) \ | |
42 | | DWC_CTLL_LLP_D_EN \ | |
43 | | DWC_CTLL_LLP_S_EN) | |
44 | ||
45 | /* | |
46 | * This is configuration-dependent and usually a funny size like 4095. | |
47 | * Let's round it down to the nearest power of two. | |
48 | * | |
49 | * Note that this is a transfer count, i.e. if we transfer 32-bit | |
50 | * words, we can do 8192 bytes per descriptor. | |
51 | * | |
52 | * This parameter is also system-specific. | |
53 | */ | |
54 | #define DWC_MAX_COUNT 2048U | |
55 | ||
56 | /* | |
57 | * Number of descriptors to allocate for each channel. This should be | |
58 | * made configurable somehow; preferably, the clients (at least the | |
59 | * ones using slave transfers) should be able to give us a hint. | |
60 | */ | |
61 | #define NR_DESCS_PER_CHANNEL 64 | |
62 | ||
63 | /*----------------------------------------------------------------------*/ | |
64 | ||
65 | /* | |
66 | * Because we're not relying on writeback from the controller (it may not | |
67 | * even be configured into the core!) we don't need to use dma_pool. These | |
68 | * descriptors -- and associated data -- are cacheable. We do need to make | |
69 | * sure their dcache entries are written back before handing them off to | |
70 | * the controller, though. | |
71 | */ | |
72 | ||
41d5e59c DW |
73 | static struct device *chan2dev(struct dma_chan *chan) |
74 | { | |
75 | return &chan->dev->device; | |
76 | } | |
77 | static struct device *chan2parent(struct dma_chan *chan) | |
78 | { | |
79 | return chan->dev->device.parent; | |
80 | } | |
81 | ||
3bfb1d20 HS |
82 | static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc) |
83 | { | |
84 | return list_entry(dwc->active_list.next, struct dw_desc, desc_node); | |
85 | } | |
86 | ||
87 | static struct dw_desc *dwc_first_queued(struct dw_dma_chan *dwc) | |
88 | { | |
89 | return list_entry(dwc->queue.next, struct dw_desc, desc_node); | |
90 | } | |
91 | ||
92 | static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc) | |
93 | { | |
94 | struct dw_desc *desc, *_desc; | |
95 | struct dw_desc *ret = NULL; | |
96 | unsigned int i = 0; | |
97 | ||
98 | spin_lock_bh(&dwc->lock); | |
99 | list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) { | |
100 | if (async_tx_test_ack(&desc->txd)) { | |
101 | list_del(&desc->desc_node); | |
102 | ret = desc; | |
103 | break; | |
104 | } | |
41d5e59c | 105 | dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc); |
3bfb1d20 HS |
106 | i++; |
107 | } | |
108 | spin_unlock_bh(&dwc->lock); | |
109 | ||
41d5e59c | 110 | dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i); |
3bfb1d20 HS |
111 | |
112 | return ret; | |
113 | } | |
114 | ||
115 | static void dwc_sync_desc_for_cpu(struct dw_dma_chan *dwc, struct dw_desc *desc) | |
116 | { | |
117 | struct dw_desc *child; | |
118 | ||
119 | list_for_each_entry(child, &desc->txd.tx_list, desc_node) | |
41d5e59c | 120 | dma_sync_single_for_cpu(chan2parent(&dwc->chan), |
3bfb1d20 HS |
121 | child->txd.phys, sizeof(child->lli), |
122 | DMA_TO_DEVICE); | |
41d5e59c | 123 | dma_sync_single_for_cpu(chan2parent(&dwc->chan), |
3bfb1d20 HS |
124 | desc->txd.phys, sizeof(desc->lli), |
125 | DMA_TO_DEVICE); | |
126 | } | |
127 | ||
128 | /* | |
129 | * Move a descriptor, including any children, to the free list. | |
130 | * `desc' must not be on any lists. | |
131 | */ | |
132 | static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc) | |
133 | { | |
134 | if (desc) { | |
135 | struct dw_desc *child; | |
136 | ||
137 | dwc_sync_desc_for_cpu(dwc, desc); | |
138 | ||
139 | spin_lock_bh(&dwc->lock); | |
140 | list_for_each_entry(child, &desc->txd.tx_list, desc_node) | |
41d5e59c | 141 | dev_vdbg(chan2dev(&dwc->chan), |
3bfb1d20 HS |
142 | "moving child desc %p to freelist\n", |
143 | child); | |
144 | list_splice_init(&desc->txd.tx_list, &dwc->free_list); | |
41d5e59c | 145 | dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc); |
3bfb1d20 HS |
146 | list_add(&desc->desc_node, &dwc->free_list); |
147 | spin_unlock_bh(&dwc->lock); | |
148 | } | |
149 | } | |
150 | ||
151 | /* Called with dwc->lock held and bh disabled */ | |
152 | static dma_cookie_t | |
153 | dwc_assign_cookie(struct dw_dma_chan *dwc, struct dw_desc *desc) | |
154 | { | |
155 | dma_cookie_t cookie = dwc->chan.cookie; | |
156 | ||
157 | if (++cookie < 0) | |
158 | cookie = 1; | |
159 | ||
160 | dwc->chan.cookie = cookie; | |
161 | desc->txd.cookie = cookie; | |
162 | ||
163 | return cookie; | |
164 | } | |
165 | ||
166 | /*----------------------------------------------------------------------*/ | |
167 | ||
168 | /* Called with dwc->lock held and bh disabled */ | |
169 | static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first) | |
170 | { | |
171 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
172 | ||
173 | /* ASSERT: channel is idle */ | |
174 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
41d5e59c | 175 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 | 176 | "BUG: Attempted to start non-idle channel\n"); |
41d5e59c | 177 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
178 | " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n", |
179 | channel_readl(dwc, SAR), | |
180 | channel_readl(dwc, DAR), | |
181 | channel_readl(dwc, LLP), | |
182 | channel_readl(dwc, CTL_HI), | |
183 | channel_readl(dwc, CTL_LO)); | |
184 | ||
185 | /* The tasklet will hopefully advance the queue... */ | |
186 | return; | |
187 | } | |
188 | ||
189 | channel_writel(dwc, LLP, first->txd.phys); | |
190 | channel_writel(dwc, CTL_LO, | |
191 | DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); | |
192 | channel_writel(dwc, CTL_HI, 0); | |
193 | channel_set_bit(dw, CH_EN, dwc->mask); | |
194 | } | |
195 | ||
196 | /*----------------------------------------------------------------------*/ | |
197 | ||
198 | static void | |
199 | dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc) | |
200 | { | |
201 | dma_async_tx_callback callback; | |
202 | void *param; | |
203 | struct dma_async_tx_descriptor *txd = &desc->txd; | |
204 | ||
41d5e59c | 205 | dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie); |
3bfb1d20 HS |
206 | |
207 | dwc->completed = txd->cookie; | |
208 | callback = txd->callback; | |
209 | param = txd->callback_param; | |
210 | ||
211 | dwc_sync_desc_for_cpu(dwc, desc); | |
212 | list_splice_init(&txd->tx_list, &dwc->free_list); | |
213 | list_move(&desc->desc_node, &dwc->free_list); | |
214 | ||
215 | /* | |
216 | * We use dma_unmap_page() regardless of how the buffers were | |
217 | * mapped before they were submitted... | |
218 | */ | |
219 | if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) | |
41d5e59c DW |
220 | dma_unmap_page(chan2parent(&dwc->chan), desc->lli.dar, |
221 | desc->len, DMA_FROM_DEVICE); | |
3bfb1d20 | 222 | if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) |
41d5e59c DW |
223 | dma_unmap_page(chan2parent(&dwc->chan), desc->lli.sar, |
224 | desc->len, DMA_TO_DEVICE); | |
3bfb1d20 HS |
225 | |
226 | /* | |
227 | * The API requires that no submissions are done from a | |
228 | * callback, so we don't need to drop the lock here | |
229 | */ | |
230 | if (callback) | |
231 | callback(param); | |
232 | } | |
233 | ||
234 | static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
235 | { | |
236 | struct dw_desc *desc, *_desc; | |
237 | LIST_HEAD(list); | |
238 | ||
239 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
41d5e59c | 240 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
241 | "BUG: XFER bit set, but channel not idle!\n"); |
242 | ||
243 | /* Try to continue after resetting the channel... */ | |
244 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
245 | while (dma_readl(dw, CH_EN) & dwc->mask) | |
246 | cpu_relax(); | |
247 | } | |
248 | ||
249 | /* | |
250 | * Submit queued descriptors ASAP, i.e. before we go through | |
251 | * the completed ones. | |
252 | */ | |
253 | if (!list_empty(&dwc->queue)) | |
254 | dwc_dostart(dwc, dwc_first_queued(dwc)); | |
255 | list_splice_init(&dwc->active_list, &list); | |
256 | list_splice_init(&dwc->queue, &dwc->active_list); | |
257 | ||
258 | list_for_each_entry_safe(desc, _desc, &list, desc_node) | |
259 | dwc_descriptor_complete(dwc, desc); | |
260 | } | |
261 | ||
262 | static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
263 | { | |
264 | dma_addr_t llp; | |
265 | struct dw_desc *desc, *_desc; | |
266 | struct dw_desc *child; | |
267 | u32 status_xfer; | |
268 | ||
269 | /* | |
270 | * Clear block interrupt flag before scanning so that we don't | |
271 | * miss any, and read LLP before RAW_XFER to ensure it is | |
272 | * valid if we decide to scan the list. | |
273 | */ | |
274 | dma_writel(dw, CLEAR.BLOCK, dwc->mask); | |
275 | llp = channel_readl(dwc, LLP); | |
276 | status_xfer = dma_readl(dw, RAW.XFER); | |
277 | ||
278 | if (status_xfer & dwc->mask) { | |
279 | /* Everything we've submitted is done */ | |
280 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
281 | dwc_complete_all(dw, dwc); | |
282 | return; | |
283 | } | |
284 | ||
41d5e59c | 285 | dev_vdbg(chan2dev(&dwc->chan), "scan_descriptors: llp=0x%x\n", llp); |
3bfb1d20 HS |
286 | |
287 | list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) { | |
288 | if (desc->lli.llp == llp) | |
289 | /* This one is currently in progress */ | |
290 | return; | |
291 | ||
292 | list_for_each_entry(child, &desc->txd.tx_list, desc_node) | |
293 | if (child->lli.llp == llp) | |
294 | /* Currently in progress */ | |
295 | return; | |
296 | ||
297 | /* | |
298 | * No descriptors so far seem to be in progress, i.e. | |
299 | * this one must be done. | |
300 | */ | |
301 | dwc_descriptor_complete(dwc, desc); | |
302 | } | |
303 | ||
41d5e59c | 304 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
305 | "BUG: All descriptors done, but channel not idle!\n"); |
306 | ||
307 | /* Try to continue after resetting the channel... */ | |
308 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
309 | while (dma_readl(dw, CH_EN) & dwc->mask) | |
310 | cpu_relax(); | |
311 | ||
312 | if (!list_empty(&dwc->queue)) { | |
313 | dwc_dostart(dwc, dwc_first_queued(dwc)); | |
314 | list_splice_init(&dwc->queue, &dwc->active_list); | |
315 | } | |
316 | } | |
317 | ||
318 | static void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli) | |
319 | { | |
41d5e59c | 320 | dev_printk(KERN_CRIT, chan2dev(&dwc->chan), |
3bfb1d20 HS |
321 | " desc: s0x%x d0x%x l0x%x c0x%x:%x\n", |
322 | lli->sar, lli->dar, lli->llp, | |
323 | lli->ctlhi, lli->ctllo); | |
324 | } | |
325 | ||
326 | static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
327 | { | |
328 | struct dw_desc *bad_desc; | |
329 | struct dw_desc *child; | |
330 | ||
331 | dwc_scan_descriptors(dw, dwc); | |
332 | ||
333 | /* | |
334 | * The descriptor currently at the head of the active list is | |
335 | * borked. Since we don't have any way to report errors, we'll | |
336 | * just have to scream loudly and try to carry on. | |
337 | */ | |
338 | bad_desc = dwc_first_active(dwc); | |
339 | list_del_init(&bad_desc->desc_node); | |
340 | list_splice_init(&dwc->queue, dwc->active_list.prev); | |
341 | ||
342 | /* Clear the error flag and try to restart the controller */ | |
343 | dma_writel(dw, CLEAR.ERROR, dwc->mask); | |
344 | if (!list_empty(&dwc->active_list)) | |
345 | dwc_dostart(dwc, dwc_first_active(dwc)); | |
346 | ||
347 | /* | |
348 | * KERN_CRITICAL may seem harsh, but since this only happens | |
349 | * when someone submits a bad physical address in a | |
350 | * descriptor, we should consider ourselves lucky that the | |
351 | * controller flagged an error instead of scribbling over | |
352 | * random memory locations. | |
353 | */ | |
41d5e59c | 354 | dev_printk(KERN_CRIT, chan2dev(&dwc->chan), |
3bfb1d20 | 355 | "Bad descriptor submitted for DMA!\n"); |
41d5e59c | 356 | dev_printk(KERN_CRIT, chan2dev(&dwc->chan), |
3bfb1d20 HS |
357 | " cookie: %d\n", bad_desc->txd.cookie); |
358 | dwc_dump_lli(dwc, &bad_desc->lli); | |
359 | list_for_each_entry(child, &bad_desc->txd.tx_list, desc_node) | |
360 | dwc_dump_lli(dwc, &child->lli); | |
361 | ||
362 | /* Pretend the descriptor completed successfully */ | |
363 | dwc_descriptor_complete(dwc, bad_desc); | |
364 | } | |
365 | ||
366 | static void dw_dma_tasklet(unsigned long data) | |
367 | { | |
368 | struct dw_dma *dw = (struct dw_dma *)data; | |
369 | struct dw_dma_chan *dwc; | |
370 | u32 status_block; | |
371 | u32 status_xfer; | |
372 | u32 status_err; | |
373 | int i; | |
374 | ||
375 | status_block = dma_readl(dw, RAW.BLOCK); | |
7fe7b2f4 | 376 | status_xfer = dma_readl(dw, RAW.XFER); |
3bfb1d20 HS |
377 | status_err = dma_readl(dw, RAW.ERROR); |
378 | ||
379 | dev_vdbg(dw->dma.dev, "tasklet: status_block=%x status_err=%x\n", | |
380 | status_block, status_err); | |
381 | ||
382 | for (i = 0; i < dw->dma.chancnt; i++) { | |
383 | dwc = &dw->chan[i]; | |
384 | spin_lock(&dwc->lock); | |
385 | if (status_err & (1 << i)) | |
386 | dwc_handle_error(dw, dwc); | |
387 | else if ((status_block | status_xfer) & (1 << i)) | |
388 | dwc_scan_descriptors(dw, dwc); | |
389 | spin_unlock(&dwc->lock); | |
390 | } | |
391 | ||
392 | /* | |
393 | * Re-enable interrupts. Block Complete interrupts are only | |
394 | * enabled if the INT_EN bit in the descriptor is set. This | |
395 | * will trigger a scan before the whole list is done. | |
396 | */ | |
397 | channel_set_bit(dw, MASK.XFER, dw->all_chan_mask); | |
398 | channel_set_bit(dw, MASK.BLOCK, dw->all_chan_mask); | |
399 | channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask); | |
400 | } | |
401 | ||
402 | static irqreturn_t dw_dma_interrupt(int irq, void *dev_id) | |
403 | { | |
404 | struct dw_dma *dw = dev_id; | |
405 | u32 status; | |
406 | ||
407 | dev_vdbg(dw->dma.dev, "interrupt: status=0x%x\n", | |
408 | dma_readl(dw, STATUS_INT)); | |
409 | ||
410 | /* | |
411 | * Just disable the interrupts. We'll turn them back on in the | |
412 | * softirq handler. | |
413 | */ | |
414 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
415 | channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); | |
416 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); | |
417 | ||
418 | status = dma_readl(dw, STATUS_INT); | |
419 | if (status) { | |
420 | dev_err(dw->dma.dev, | |
421 | "BUG: Unexpected interrupts pending: 0x%x\n", | |
422 | status); | |
423 | ||
424 | /* Try to recover */ | |
425 | channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1); | |
426 | channel_clear_bit(dw, MASK.BLOCK, (1 << 8) - 1); | |
427 | channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1); | |
428 | channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1); | |
429 | channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1); | |
430 | } | |
431 | ||
432 | tasklet_schedule(&dw->tasklet); | |
433 | ||
434 | return IRQ_HANDLED; | |
435 | } | |
436 | ||
437 | /*----------------------------------------------------------------------*/ | |
438 | ||
439 | static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx) | |
440 | { | |
441 | struct dw_desc *desc = txd_to_dw_desc(tx); | |
442 | struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan); | |
443 | dma_cookie_t cookie; | |
444 | ||
445 | spin_lock_bh(&dwc->lock); | |
446 | cookie = dwc_assign_cookie(dwc, desc); | |
447 | ||
448 | /* | |
449 | * REVISIT: We should attempt to chain as many descriptors as | |
450 | * possible, perhaps even appending to those already submitted | |
451 | * for DMA. But this is hard to do in a race-free manner. | |
452 | */ | |
453 | if (list_empty(&dwc->active_list)) { | |
41d5e59c | 454 | dev_vdbg(chan2dev(tx->chan), "tx_submit: started %u\n", |
3bfb1d20 HS |
455 | desc->txd.cookie); |
456 | dwc_dostart(dwc, desc); | |
457 | list_add_tail(&desc->desc_node, &dwc->active_list); | |
458 | } else { | |
41d5e59c | 459 | dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u\n", |
3bfb1d20 HS |
460 | desc->txd.cookie); |
461 | ||
462 | list_add_tail(&desc->desc_node, &dwc->queue); | |
463 | } | |
464 | ||
465 | spin_unlock_bh(&dwc->lock); | |
466 | ||
467 | return cookie; | |
468 | } | |
469 | ||
470 | static struct dma_async_tx_descriptor * | |
471 | dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
472 | size_t len, unsigned long flags) | |
473 | { | |
474 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
475 | struct dw_desc *desc; | |
476 | struct dw_desc *first; | |
477 | struct dw_desc *prev; | |
478 | size_t xfer_count; | |
479 | size_t offset; | |
480 | unsigned int src_width; | |
481 | unsigned int dst_width; | |
482 | u32 ctllo; | |
483 | ||
41d5e59c | 484 | dev_vdbg(chan2dev(chan), "prep_dma_memcpy d0x%x s0x%x l0x%zx f0x%lx\n", |
3bfb1d20 HS |
485 | dest, src, len, flags); |
486 | ||
487 | if (unlikely(!len)) { | |
41d5e59c | 488 | dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n"); |
3bfb1d20 HS |
489 | return NULL; |
490 | } | |
491 | ||
492 | /* | |
493 | * We can be a lot more clever here, but this should take care | |
494 | * of the most common optimization. | |
495 | */ | |
496 | if (!((src | dest | len) & 3)) | |
497 | src_width = dst_width = 2; | |
498 | else if (!((src | dest | len) & 1)) | |
499 | src_width = dst_width = 1; | |
500 | else | |
501 | src_width = dst_width = 0; | |
502 | ||
503 | ctllo = DWC_DEFAULT_CTLLO | |
504 | | DWC_CTLL_DST_WIDTH(dst_width) | |
505 | | DWC_CTLL_SRC_WIDTH(src_width) | |
506 | | DWC_CTLL_DST_INC | |
507 | | DWC_CTLL_SRC_INC | |
508 | | DWC_CTLL_FC_M2M; | |
509 | prev = first = NULL; | |
510 | ||
511 | for (offset = 0; offset < len; offset += xfer_count << src_width) { | |
512 | xfer_count = min_t(size_t, (len - offset) >> src_width, | |
513 | DWC_MAX_COUNT); | |
514 | ||
515 | desc = dwc_desc_get(dwc); | |
516 | if (!desc) | |
517 | goto err_desc_get; | |
518 | ||
519 | desc->lli.sar = src + offset; | |
520 | desc->lli.dar = dest + offset; | |
521 | desc->lli.ctllo = ctllo; | |
522 | desc->lli.ctlhi = xfer_count; | |
523 | ||
524 | if (!first) { | |
525 | first = desc; | |
526 | } else { | |
527 | prev->lli.llp = desc->txd.phys; | |
41d5e59c | 528 | dma_sync_single_for_device(chan2parent(chan), |
3bfb1d20 HS |
529 | prev->txd.phys, sizeof(prev->lli), |
530 | DMA_TO_DEVICE); | |
531 | list_add_tail(&desc->desc_node, | |
532 | &first->txd.tx_list); | |
533 | } | |
534 | prev = desc; | |
535 | } | |
536 | ||
537 | ||
538 | if (flags & DMA_PREP_INTERRUPT) | |
539 | /* Trigger interrupt after last block */ | |
540 | prev->lli.ctllo |= DWC_CTLL_INT_EN; | |
541 | ||
542 | prev->lli.llp = 0; | |
41d5e59c | 543 | dma_sync_single_for_device(chan2parent(chan), |
3bfb1d20 HS |
544 | prev->txd.phys, sizeof(prev->lli), |
545 | DMA_TO_DEVICE); | |
546 | ||
547 | first->txd.flags = flags; | |
548 | first->len = len; | |
549 | ||
550 | return &first->txd; | |
551 | ||
552 | err_desc_get: | |
553 | dwc_desc_put(dwc, first); | |
554 | return NULL; | |
555 | } | |
556 | ||
557 | static struct dma_async_tx_descriptor * | |
558 | dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
559 | unsigned int sg_len, enum dma_data_direction direction, | |
560 | unsigned long flags) | |
561 | { | |
562 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
563 | struct dw_dma_slave *dws = dwc->dws; | |
564 | struct dw_desc *prev; | |
565 | struct dw_desc *first; | |
566 | u32 ctllo; | |
567 | dma_addr_t reg; | |
568 | unsigned int reg_width; | |
569 | unsigned int mem_width; | |
570 | unsigned int i; | |
571 | struct scatterlist *sg; | |
572 | size_t total_len = 0; | |
573 | ||
41d5e59c | 574 | dev_vdbg(chan2dev(chan), "prep_dma_slave\n"); |
3bfb1d20 HS |
575 | |
576 | if (unlikely(!dws || !sg_len)) | |
577 | return NULL; | |
578 | ||
74465b4f | 579 | reg_width = dws->reg_width; |
3bfb1d20 HS |
580 | prev = first = NULL; |
581 | ||
41d5e59c | 582 | sg_len = dma_map_sg(chan2parent(chan), sgl, sg_len, direction); |
3bfb1d20 HS |
583 | |
584 | switch (direction) { | |
585 | case DMA_TO_DEVICE: | |
586 | ctllo = (DWC_DEFAULT_CTLLO | |
587 | | DWC_CTLL_DST_WIDTH(reg_width) | |
588 | | DWC_CTLL_DST_FIX | |
589 | | DWC_CTLL_SRC_INC | |
590 | | DWC_CTLL_FC_M2P); | |
74465b4f | 591 | reg = dws->tx_reg; |
3bfb1d20 HS |
592 | for_each_sg(sgl, sg, sg_len, i) { |
593 | struct dw_desc *desc; | |
594 | u32 len; | |
595 | u32 mem; | |
596 | ||
597 | desc = dwc_desc_get(dwc); | |
598 | if (!desc) { | |
41d5e59c | 599 | dev_err(chan2dev(chan), |
3bfb1d20 HS |
600 | "not enough descriptors available\n"); |
601 | goto err_desc_get; | |
602 | } | |
603 | ||
604 | mem = sg_phys(sg); | |
605 | len = sg_dma_len(sg); | |
606 | mem_width = 2; | |
607 | if (unlikely(mem & 3 || len & 3)) | |
608 | mem_width = 0; | |
609 | ||
610 | desc->lli.sar = mem; | |
611 | desc->lli.dar = reg; | |
612 | desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width); | |
613 | desc->lli.ctlhi = len >> mem_width; | |
614 | ||
615 | if (!first) { | |
616 | first = desc; | |
617 | } else { | |
618 | prev->lli.llp = desc->txd.phys; | |
41d5e59c | 619 | dma_sync_single_for_device(chan2parent(chan), |
3bfb1d20 HS |
620 | prev->txd.phys, |
621 | sizeof(prev->lli), | |
622 | DMA_TO_DEVICE); | |
623 | list_add_tail(&desc->desc_node, | |
624 | &first->txd.tx_list); | |
625 | } | |
626 | prev = desc; | |
627 | total_len += len; | |
628 | } | |
629 | break; | |
630 | case DMA_FROM_DEVICE: | |
631 | ctllo = (DWC_DEFAULT_CTLLO | |
632 | | DWC_CTLL_SRC_WIDTH(reg_width) | |
633 | | DWC_CTLL_DST_INC | |
634 | | DWC_CTLL_SRC_FIX | |
635 | | DWC_CTLL_FC_P2M); | |
636 | ||
74465b4f | 637 | reg = dws->rx_reg; |
3bfb1d20 HS |
638 | for_each_sg(sgl, sg, sg_len, i) { |
639 | struct dw_desc *desc; | |
640 | u32 len; | |
641 | u32 mem; | |
642 | ||
643 | desc = dwc_desc_get(dwc); | |
644 | if (!desc) { | |
41d5e59c | 645 | dev_err(chan2dev(chan), |
3bfb1d20 HS |
646 | "not enough descriptors available\n"); |
647 | goto err_desc_get; | |
648 | } | |
649 | ||
650 | mem = sg_phys(sg); | |
651 | len = sg_dma_len(sg); | |
652 | mem_width = 2; | |
653 | if (unlikely(mem & 3 || len & 3)) | |
654 | mem_width = 0; | |
655 | ||
656 | desc->lli.sar = reg; | |
657 | desc->lli.dar = mem; | |
658 | desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width); | |
659 | desc->lli.ctlhi = len >> reg_width; | |
660 | ||
661 | if (!first) { | |
662 | first = desc; | |
663 | } else { | |
664 | prev->lli.llp = desc->txd.phys; | |
41d5e59c | 665 | dma_sync_single_for_device(chan2parent(chan), |
3bfb1d20 HS |
666 | prev->txd.phys, |
667 | sizeof(prev->lli), | |
668 | DMA_TO_DEVICE); | |
669 | list_add_tail(&desc->desc_node, | |
670 | &first->txd.tx_list); | |
671 | } | |
672 | prev = desc; | |
673 | total_len += len; | |
674 | } | |
675 | break; | |
676 | default: | |
677 | return NULL; | |
678 | } | |
679 | ||
680 | if (flags & DMA_PREP_INTERRUPT) | |
681 | /* Trigger interrupt after last block */ | |
682 | prev->lli.ctllo |= DWC_CTLL_INT_EN; | |
683 | ||
684 | prev->lli.llp = 0; | |
41d5e59c | 685 | dma_sync_single_for_device(chan2parent(chan), |
3bfb1d20 HS |
686 | prev->txd.phys, sizeof(prev->lli), |
687 | DMA_TO_DEVICE); | |
688 | ||
689 | first->len = total_len; | |
690 | ||
691 | return &first->txd; | |
692 | ||
693 | err_desc_get: | |
694 | dwc_desc_put(dwc, first); | |
695 | return NULL; | |
696 | } | |
697 | ||
698 | static void dwc_terminate_all(struct dma_chan *chan) | |
699 | { | |
700 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
701 | struct dw_dma *dw = to_dw_dma(chan->device); | |
702 | struct dw_desc *desc, *_desc; | |
703 | LIST_HEAD(list); | |
704 | ||
705 | /* | |
706 | * This is only called when something went wrong elsewhere, so | |
707 | * we don't really care about the data. Just disable the | |
708 | * channel. We still have to poll the channel enable bit due | |
709 | * to AHB/HSB limitations. | |
710 | */ | |
711 | spin_lock_bh(&dwc->lock); | |
712 | ||
713 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
714 | ||
715 | while (dma_readl(dw, CH_EN) & dwc->mask) | |
716 | cpu_relax(); | |
717 | ||
718 | /* active_list entries will end up before queued entries */ | |
719 | list_splice_init(&dwc->queue, &list); | |
720 | list_splice_init(&dwc->active_list, &list); | |
721 | ||
722 | spin_unlock_bh(&dwc->lock); | |
723 | ||
724 | /* Flush all pending and queued descriptors */ | |
725 | list_for_each_entry_safe(desc, _desc, &list, desc_node) | |
726 | dwc_descriptor_complete(dwc, desc); | |
727 | } | |
728 | ||
729 | static enum dma_status | |
730 | dwc_is_tx_complete(struct dma_chan *chan, | |
731 | dma_cookie_t cookie, | |
732 | dma_cookie_t *done, dma_cookie_t *used) | |
733 | { | |
734 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
735 | dma_cookie_t last_used; | |
736 | dma_cookie_t last_complete; | |
737 | int ret; | |
738 | ||
739 | last_complete = dwc->completed; | |
740 | last_used = chan->cookie; | |
741 | ||
742 | ret = dma_async_is_complete(cookie, last_complete, last_used); | |
743 | if (ret != DMA_SUCCESS) { | |
744 | dwc_scan_descriptors(to_dw_dma(chan->device), dwc); | |
745 | ||
746 | last_complete = dwc->completed; | |
747 | last_used = chan->cookie; | |
748 | ||
749 | ret = dma_async_is_complete(cookie, last_complete, last_used); | |
750 | } | |
751 | ||
752 | if (done) | |
753 | *done = last_complete; | |
754 | if (used) | |
755 | *used = last_used; | |
756 | ||
757 | return ret; | |
758 | } | |
759 | ||
760 | static void dwc_issue_pending(struct dma_chan *chan) | |
761 | { | |
762 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
763 | ||
764 | spin_lock_bh(&dwc->lock); | |
765 | if (!list_empty(&dwc->queue)) | |
766 | dwc_scan_descriptors(to_dw_dma(chan->device), dwc); | |
767 | spin_unlock_bh(&dwc->lock); | |
768 | } | |
769 | ||
aa1e6f1a | 770 | static int dwc_alloc_chan_resources(struct dma_chan *chan) |
3bfb1d20 HS |
771 | { |
772 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
773 | struct dw_dma *dw = to_dw_dma(chan->device); | |
774 | struct dw_desc *desc; | |
3bfb1d20 HS |
775 | struct dw_dma_slave *dws; |
776 | int i; | |
777 | u32 cfghi; | |
778 | u32 cfglo; | |
779 | ||
41d5e59c | 780 | dev_vdbg(chan2dev(chan), "alloc_chan_resources\n"); |
3bfb1d20 | 781 | |
3bfb1d20 HS |
782 | /* ASSERT: channel is idle */ |
783 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
41d5e59c | 784 | dev_dbg(chan2dev(chan), "DMA channel not idle?\n"); |
3bfb1d20 HS |
785 | return -EIO; |
786 | } | |
787 | ||
788 | dwc->completed = chan->cookie = 1; | |
789 | ||
790 | cfghi = DWC_CFGH_FIFO_MODE; | |
791 | cfglo = 0; | |
792 | ||
74465b4f DW |
793 | dws = dwc->dws; |
794 | if (dws) { | |
3bfb1d20 HS |
795 | /* |
796 | * We need controller-specific data to set up slave | |
797 | * transfers. | |
798 | */ | |
74465b4f | 799 | BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev); |
3bfb1d20 | 800 | |
3bfb1d20 HS |
801 | cfghi = dws->cfg_hi; |
802 | cfglo = dws->cfg_lo; | |
3bfb1d20 | 803 | } |
3bfb1d20 HS |
804 | channel_writel(dwc, CFG_LO, cfglo); |
805 | channel_writel(dwc, CFG_HI, cfghi); | |
806 | ||
807 | /* | |
808 | * NOTE: some controllers may have additional features that we | |
809 | * need to initialize here, like "scatter-gather" (which | |
810 | * doesn't mean what you think it means), and status writeback. | |
811 | */ | |
812 | ||
813 | spin_lock_bh(&dwc->lock); | |
814 | i = dwc->descs_allocated; | |
815 | while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) { | |
816 | spin_unlock_bh(&dwc->lock); | |
817 | ||
818 | desc = kzalloc(sizeof(struct dw_desc), GFP_KERNEL); | |
819 | if (!desc) { | |
41d5e59c | 820 | dev_info(chan2dev(chan), |
3bfb1d20 HS |
821 | "only allocated %d descriptors\n", i); |
822 | spin_lock_bh(&dwc->lock); | |
823 | break; | |
824 | } | |
825 | ||
826 | dma_async_tx_descriptor_init(&desc->txd, chan); | |
827 | desc->txd.tx_submit = dwc_tx_submit; | |
828 | desc->txd.flags = DMA_CTRL_ACK; | |
829 | INIT_LIST_HEAD(&desc->txd.tx_list); | |
41d5e59c | 830 | desc->txd.phys = dma_map_single(chan2parent(chan), &desc->lli, |
3bfb1d20 HS |
831 | sizeof(desc->lli), DMA_TO_DEVICE); |
832 | dwc_desc_put(dwc, desc); | |
833 | ||
834 | spin_lock_bh(&dwc->lock); | |
835 | i = ++dwc->descs_allocated; | |
836 | } | |
837 | ||
838 | /* Enable interrupts */ | |
839 | channel_set_bit(dw, MASK.XFER, dwc->mask); | |
840 | channel_set_bit(dw, MASK.BLOCK, dwc->mask); | |
841 | channel_set_bit(dw, MASK.ERROR, dwc->mask); | |
842 | ||
843 | spin_unlock_bh(&dwc->lock); | |
844 | ||
41d5e59c | 845 | dev_dbg(chan2dev(chan), |
3bfb1d20 HS |
846 | "alloc_chan_resources allocated %d descriptors\n", i); |
847 | ||
848 | return i; | |
849 | } | |
850 | ||
851 | static void dwc_free_chan_resources(struct dma_chan *chan) | |
852 | { | |
853 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
854 | struct dw_dma *dw = to_dw_dma(chan->device); | |
855 | struct dw_desc *desc, *_desc; | |
856 | LIST_HEAD(list); | |
857 | ||
41d5e59c | 858 | dev_dbg(chan2dev(chan), "free_chan_resources (descs allocated=%u)\n", |
3bfb1d20 HS |
859 | dwc->descs_allocated); |
860 | ||
861 | /* ASSERT: channel is idle */ | |
862 | BUG_ON(!list_empty(&dwc->active_list)); | |
863 | BUG_ON(!list_empty(&dwc->queue)); | |
864 | BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask); | |
865 | ||
866 | spin_lock_bh(&dwc->lock); | |
867 | list_splice_init(&dwc->free_list, &list); | |
868 | dwc->descs_allocated = 0; | |
869 | dwc->dws = NULL; | |
870 | ||
871 | /* Disable interrupts */ | |
872 | channel_clear_bit(dw, MASK.XFER, dwc->mask); | |
873 | channel_clear_bit(dw, MASK.BLOCK, dwc->mask); | |
874 | channel_clear_bit(dw, MASK.ERROR, dwc->mask); | |
875 | ||
876 | spin_unlock_bh(&dwc->lock); | |
877 | ||
878 | list_for_each_entry_safe(desc, _desc, &list, desc_node) { | |
41d5e59c DW |
879 | dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc); |
880 | dma_unmap_single(chan2parent(chan), desc->txd.phys, | |
3bfb1d20 HS |
881 | sizeof(desc->lli), DMA_TO_DEVICE); |
882 | kfree(desc); | |
883 | } | |
884 | ||
41d5e59c | 885 | dev_vdbg(chan2dev(chan), "free_chan_resources done\n"); |
3bfb1d20 HS |
886 | } |
887 | ||
888 | /*----------------------------------------------------------------------*/ | |
889 | ||
890 | static void dw_dma_off(struct dw_dma *dw) | |
891 | { | |
892 | dma_writel(dw, CFG, 0); | |
893 | ||
894 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
895 | channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); | |
896 | channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask); | |
897 | channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask); | |
898 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); | |
899 | ||
900 | while (dma_readl(dw, CFG) & DW_CFG_DMA_EN) | |
901 | cpu_relax(); | |
902 | } | |
903 | ||
904 | static int __init dw_probe(struct platform_device *pdev) | |
905 | { | |
906 | struct dw_dma_platform_data *pdata; | |
907 | struct resource *io; | |
908 | struct dw_dma *dw; | |
909 | size_t size; | |
910 | int irq; | |
911 | int err; | |
912 | int i; | |
913 | ||
914 | pdata = pdev->dev.platform_data; | |
915 | if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) | |
916 | return -EINVAL; | |
917 | ||
918 | io = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
919 | if (!io) | |
920 | return -EINVAL; | |
921 | ||
922 | irq = platform_get_irq(pdev, 0); | |
923 | if (irq < 0) | |
924 | return irq; | |
925 | ||
926 | size = sizeof(struct dw_dma); | |
927 | size += pdata->nr_channels * sizeof(struct dw_dma_chan); | |
928 | dw = kzalloc(size, GFP_KERNEL); | |
929 | if (!dw) | |
930 | return -ENOMEM; | |
931 | ||
932 | if (!request_mem_region(io->start, DW_REGLEN, pdev->dev.driver->name)) { | |
933 | err = -EBUSY; | |
934 | goto err_kfree; | |
935 | } | |
936 | ||
937 | memset(dw, 0, sizeof *dw); | |
938 | ||
939 | dw->regs = ioremap(io->start, DW_REGLEN); | |
940 | if (!dw->regs) { | |
941 | err = -ENOMEM; | |
942 | goto err_release_r; | |
943 | } | |
944 | ||
945 | dw->clk = clk_get(&pdev->dev, "hclk"); | |
946 | if (IS_ERR(dw->clk)) { | |
947 | err = PTR_ERR(dw->clk); | |
948 | goto err_clk; | |
949 | } | |
950 | clk_enable(dw->clk); | |
951 | ||
952 | /* force dma off, just in case */ | |
953 | dw_dma_off(dw); | |
954 | ||
955 | err = request_irq(irq, dw_dma_interrupt, 0, "dw_dmac", dw); | |
956 | if (err) | |
957 | goto err_irq; | |
958 | ||
959 | platform_set_drvdata(pdev, dw); | |
960 | ||
961 | tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw); | |
962 | ||
963 | dw->all_chan_mask = (1 << pdata->nr_channels) - 1; | |
964 | ||
965 | INIT_LIST_HEAD(&dw->dma.channels); | |
966 | for (i = 0; i < pdata->nr_channels; i++, dw->dma.chancnt++) { | |
967 | struct dw_dma_chan *dwc = &dw->chan[i]; | |
968 | ||
969 | dwc->chan.device = &dw->dma; | |
970 | dwc->chan.cookie = dwc->completed = 1; | |
971 | dwc->chan.chan_id = i; | |
972 | list_add_tail(&dwc->chan.device_node, &dw->dma.channels); | |
973 | ||
974 | dwc->ch_regs = &__dw_regs(dw)->CHAN[i]; | |
975 | spin_lock_init(&dwc->lock); | |
976 | dwc->mask = 1 << i; | |
977 | ||
978 | INIT_LIST_HEAD(&dwc->active_list); | |
979 | INIT_LIST_HEAD(&dwc->queue); | |
980 | INIT_LIST_HEAD(&dwc->free_list); | |
981 | ||
982 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
983 | } | |
984 | ||
985 | /* Clear/disable all interrupts on all channels. */ | |
986 | dma_writel(dw, CLEAR.XFER, dw->all_chan_mask); | |
987 | dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask); | |
988 | dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask); | |
989 | dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask); | |
990 | dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask); | |
991 | ||
992 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
993 | channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); | |
994 | channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask); | |
995 | channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask); | |
996 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); | |
997 | ||
998 | dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask); | |
999 | dma_cap_set(DMA_SLAVE, dw->dma.cap_mask); | |
1000 | dw->dma.dev = &pdev->dev; | |
1001 | dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources; | |
1002 | dw->dma.device_free_chan_resources = dwc_free_chan_resources; | |
1003 | ||
1004 | dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy; | |
1005 | ||
1006 | dw->dma.device_prep_slave_sg = dwc_prep_slave_sg; | |
1007 | dw->dma.device_terminate_all = dwc_terminate_all; | |
1008 | ||
1009 | dw->dma.device_is_tx_complete = dwc_is_tx_complete; | |
1010 | dw->dma.device_issue_pending = dwc_issue_pending; | |
1011 | ||
1012 | dma_writel(dw, CFG, DW_CFG_DMA_EN); | |
1013 | ||
1014 | printk(KERN_INFO "%s: DesignWare DMA Controller, %d channels\n", | |
1015 | pdev->dev.bus_id, dw->dma.chancnt); | |
1016 | ||
1017 | dma_async_device_register(&dw->dma); | |
1018 | ||
1019 | return 0; | |
1020 | ||
1021 | err_irq: | |
1022 | clk_disable(dw->clk); | |
1023 | clk_put(dw->clk); | |
1024 | err_clk: | |
1025 | iounmap(dw->regs); | |
1026 | dw->regs = NULL; | |
1027 | err_release_r: | |
1028 | release_resource(io); | |
1029 | err_kfree: | |
1030 | kfree(dw); | |
1031 | return err; | |
1032 | } | |
1033 | ||
1034 | static int __exit dw_remove(struct platform_device *pdev) | |
1035 | { | |
1036 | struct dw_dma *dw = platform_get_drvdata(pdev); | |
1037 | struct dw_dma_chan *dwc, *_dwc; | |
1038 | struct resource *io; | |
1039 | ||
1040 | dw_dma_off(dw); | |
1041 | dma_async_device_unregister(&dw->dma); | |
1042 | ||
1043 | free_irq(platform_get_irq(pdev, 0), dw); | |
1044 | tasklet_kill(&dw->tasklet); | |
1045 | ||
1046 | list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels, | |
1047 | chan.device_node) { | |
1048 | list_del(&dwc->chan.device_node); | |
1049 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
1050 | } | |
1051 | ||
1052 | clk_disable(dw->clk); | |
1053 | clk_put(dw->clk); | |
1054 | ||
1055 | iounmap(dw->regs); | |
1056 | dw->regs = NULL; | |
1057 | ||
1058 | io = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1059 | release_mem_region(io->start, DW_REGLEN); | |
1060 | ||
1061 | kfree(dw); | |
1062 | ||
1063 | return 0; | |
1064 | } | |
1065 | ||
1066 | static void dw_shutdown(struct platform_device *pdev) | |
1067 | { | |
1068 | struct dw_dma *dw = platform_get_drvdata(pdev); | |
1069 | ||
1070 | dw_dma_off(platform_get_drvdata(pdev)); | |
1071 | clk_disable(dw->clk); | |
1072 | } | |
1073 | ||
1074 | static int dw_suspend_late(struct platform_device *pdev, pm_message_t mesg) | |
1075 | { | |
1076 | struct dw_dma *dw = platform_get_drvdata(pdev); | |
1077 | ||
1078 | dw_dma_off(platform_get_drvdata(pdev)); | |
1079 | clk_disable(dw->clk); | |
1080 | return 0; | |
1081 | } | |
1082 | ||
1083 | static int dw_resume_early(struct platform_device *pdev) | |
1084 | { | |
1085 | struct dw_dma *dw = platform_get_drvdata(pdev); | |
1086 | ||
1087 | clk_enable(dw->clk); | |
1088 | dma_writel(dw, CFG, DW_CFG_DMA_EN); | |
1089 | return 0; | |
1090 | ||
1091 | } | |
1092 | ||
1093 | static struct platform_driver dw_driver = { | |
1094 | .remove = __exit_p(dw_remove), | |
1095 | .shutdown = dw_shutdown, | |
1096 | .suspend_late = dw_suspend_late, | |
1097 | .resume_early = dw_resume_early, | |
1098 | .driver = { | |
1099 | .name = "dw_dmac", | |
1100 | }, | |
1101 | }; | |
1102 | ||
1103 | static int __init dw_init(void) | |
1104 | { | |
1105 | return platform_driver_probe(&dw_driver, dw_probe); | |
1106 | } | |
1107 | module_init(dw_init); | |
1108 | ||
1109 | static void __exit dw_exit(void) | |
1110 | { | |
1111 | platform_driver_unregister(&dw_driver); | |
1112 | } | |
1113 | module_exit(dw_exit); | |
1114 | ||
1115 | MODULE_LICENSE("GPL v2"); | |
1116 | MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller driver"); | |
1117 | MODULE_AUTHOR("Haavard Skinnemoen <haavard.skinnemoen@atmel.com>"); |