Commit | Line | Data |
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3bfb1d20 HS |
1 | /* |
2 | * Driver for the Synopsys DesignWare DMA Controller (aka DMACA on | |
3 | * AVR32 systems.) | |
4 | * | |
5 | * Copyright (C) 2007-2008 Atmel Corporation | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | #include <linux/clk.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/dmaengine.h> | |
14 | #include <linux/dma-mapping.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/mm.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/slab.h> | |
22 | ||
23 | #include "dw_dmac_regs.h" | |
24 | ||
25 | /* | |
26 | * This supports the Synopsys "DesignWare AHB Central DMA Controller", | |
27 | * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all | |
28 | * of which use ARM any more). See the "Databook" from Synopsys for | |
29 | * information beyond what licensees probably provide. | |
30 | * | |
31 | * The driver has currently been tested only with the Atmel AT32AP7000, | |
32 | * which does not support descriptor writeback. | |
33 | */ | |
34 | ||
35 | /* NOTE: DMS+SMS is system-specific. We should get this information | |
36 | * from the platform code somehow. | |
37 | */ | |
38 | #define DWC_DEFAULT_CTLLO (DWC_CTLL_DST_MSIZE(0) \ | |
39 | | DWC_CTLL_SRC_MSIZE(0) \ | |
40 | | DWC_CTLL_DMS(0) \ | |
41 | | DWC_CTLL_SMS(1) \ | |
42 | | DWC_CTLL_LLP_D_EN \ | |
43 | | DWC_CTLL_LLP_S_EN) | |
44 | ||
45 | /* | |
46 | * This is configuration-dependent and usually a funny size like 4095. | |
47 | * Let's round it down to the nearest power of two. | |
48 | * | |
49 | * Note that this is a transfer count, i.e. if we transfer 32-bit | |
50 | * words, we can do 8192 bytes per descriptor. | |
51 | * | |
52 | * This parameter is also system-specific. | |
53 | */ | |
54 | #define DWC_MAX_COUNT 2048U | |
55 | ||
56 | /* | |
57 | * Number of descriptors to allocate for each channel. This should be | |
58 | * made configurable somehow; preferably, the clients (at least the | |
59 | * ones using slave transfers) should be able to give us a hint. | |
60 | */ | |
61 | #define NR_DESCS_PER_CHANNEL 64 | |
62 | ||
63 | /*----------------------------------------------------------------------*/ | |
64 | ||
65 | /* | |
66 | * Because we're not relying on writeback from the controller (it may not | |
67 | * even be configured into the core!) we don't need to use dma_pool. These | |
68 | * descriptors -- and associated data -- are cacheable. We do need to make | |
69 | * sure their dcache entries are written back before handing them off to | |
70 | * the controller, though. | |
71 | */ | |
72 | ||
41d5e59c DW |
73 | static struct device *chan2dev(struct dma_chan *chan) |
74 | { | |
75 | return &chan->dev->device; | |
76 | } | |
77 | static struct device *chan2parent(struct dma_chan *chan) | |
78 | { | |
79 | return chan->dev->device.parent; | |
80 | } | |
81 | ||
3bfb1d20 HS |
82 | static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc) |
83 | { | |
84 | return list_entry(dwc->active_list.next, struct dw_desc, desc_node); | |
85 | } | |
86 | ||
87 | static struct dw_desc *dwc_first_queued(struct dw_dma_chan *dwc) | |
88 | { | |
89 | return list_entry(dwc->queue.next, struct dw_desc, desc_node); | |
90 | } | |
91 | ||
92 | static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc) | |
93 | { | |
94 | struct dw_desc *desc, *_desc; | |
95 | struct dw_desc *ret = NULL; | |
96 | unsigned int i = 0; | |
97 | ||
98 | spin_lock_bh(&dwc->lock); | |
99 | list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) { | |
100 | if (async_tx_test_ack(&desc->txd)) { | |
101 | list_del(&desc->desc_node); | |
102 | ret = desc; | |
103 | break; | |
104 | } | |
41d5e59c | 105 | dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc); |
3bfb1d20 HS |
106 | i++; |
107 | } | |
108 | spin_unlock_bh(&dwc->lock); | |
109 | ||
41d5e59c | 110 | dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i); |
3bfb1d20 HS |
111 | |
112 | return ret; | |
113 | } | |
114 | ||
115 | static void dwc_sync_desc_for_cpu(struct dw_dma_chan *dwc, struct dw_desc *desc) | |
116 | { | |
117 | struct dw_desc *child; | |
118 | ||
e0bd0f8c | 119 | list_for_each_entry(child, &desc->tx_list, desc_node) |
41d5e59c | 120 | dma_sync_single_for_cpu(chan2parent(&dwc->chan), |
3bfb1d20 HS |
121 | child->txd.phys, sizeof(child->lli), |
122 | DMA_TO_DEVICE); | |
41d5e59c | 123 | dma_sync_single_for_cpu(chan2parent(&dwc->chan), |
3bfb1d20 HS |
124 | desc->txd.phys, sizeof(desc->lli), |
125 | DMA_TO_DEVICE); | |
126 | } | |
127 | ||
128 | /* | |
129 | * Move a descriptor, including any children, to the free list. | |
130 | * `desc' must not be on any lists. | |
131 | */ | |
132 | static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc) | |
133 | { | |
134 | if (desc) { | |
135 | struct dw_desc *child; | |
136 | ||
137 | dwc_sync_desc_for_cpu(dwc, desc); | |
138 | ||
139 | spin_lock_bh(&dwc->lock); | |
e0bd0f8c | 140 | list_for_each_entry(child, &desc->tx_list, desc_node) |
41d5e59c | 141 | dev_vdbg(chan2dev(&dwc->chan), |
3bfb1d20 HS |
142 | "moving child desc %p to freelist\n", |
143 | child); | |
e0bd0f8c | 144 | list_splice_init(&desc->tx_list, &dwc->free_list); |
41d5e59c | 145 | dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc); |
3bfb1d20 HS |
146 | list_add(&desc->desc_node, &dwc->free_list); |
147 | spin_unlock_bh(&dwc->lock); | |
148 | } | |
149 | } | |
150 | ||
151 | /* Called with dwc->lock held and bh disabled */ | |
152 | static dma_cookie_t | |
153 | dwc_assign_cookie(struct dw_dma_chan *dwc, struct dw_desc *desc) | |
154 | { | |
155 | dma_cookie_t cookie = dwc->chan.cookie; | |
156 | ||
157 | if (++cookie < 0) | |
158 | cookie = 1; | |
159 | ||
160 | dwc->chan.cookie = cookie; | |
161 | desc->txd.cookie = cookie; | |
162 | ||
163 | return cookie; | |
164 | } | |
165 | ||
166 | /*----------------------------------------------------------------------*/ | |
167 | ||
168 | /* Called with dwc->lock held and bh disabled */ | |
169 | static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first) | |
170 | { | |
171 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
172 | ||
173 | /* ASSERT: channel is idle */ | |
174 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
41d5e59c | 175 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 | 176 | "BUG: Attempted to start non-idle channel\n"); |
41d5e59c | 177 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
178 | " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n", |
179 | channel_readl(dwc, SAR), | |
180 | channel_readl(dwc, DAR), | |
181 | channel_readl(dwc, LLP), | |
182 | channel_readl(dwc, CTL_HI), | |
183 | channel_readl(dwc, CTL_LO)); | |
184 | ||
185 | /* The tasklet will hopefully advance the queue... */ | |
186 | return; | |
187 | } | |
188 | ||
189 | channel_writel(dwc, LLP, first->txd.phys); | |
190 | channel_writel(dwc, CTL_LO, | |
191 | DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); | |
192 | channel_writel(dwc, CTL_HI, 0); | |
193 | channel_set_bit(dw, CH_EN, dwc->mask); | |
194 | } | |
195 | ||
196 | /*----------------------------------------------------------------------*/ | |
197 | ||
198 | static void | |
199 | dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc) | |
200 | { | |
201 | dma_async_tx_callback callback; | |
202 | void *param; | |
203 | struct dma_async_tx_descriptor *txd = &desc->txd; | |
204 | ||
41d5e59c | 205 | dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie); |
3bfb1d20 HS |
206 | |
207 | dwc->completed = txd->cookie; | |
208 | callback = txd->callback; | |
209 | param = txd->callback_param; | |
210 | ||
211 | dwc_sync_desc_for_cpu(dwc, desc); | |
e0bd0f8c | 212 | list_splice_init(&desc->tx_list, &dwc->free_list); |
3bfb1d20 HS |
213 | list_move(&desc->desc_node, &dwc->free_list); |
214 | ||
657a77fa AN |
215 | if (!dwc->chan.private) { |
216 | struct device *parent = chan2parent(&dwc->chan); | |
217 | if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) { | |
218 | if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE) | |
219 | dma_unmap_single(parent, desc->lli.dar, | |
220 | desc->len, DMA_FROM_DEVICE); | |
221 | else | |
222 | dma_unmap_page(parent, desc->lli.dar, | |
223 | desc->len, DMA_FROM_DEVICE); | |
224 | } | |
225 | if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) { | |
226 | if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE) | |
227 | dma_unmap_single(parent, desc->lli.sar, | |
228 | desc->len, DMA_TO_DEVICE); | |
229 | else | |
230 | dma_unmap_page(parent, desc->lli.sar, | |
231 | desc->len, DMA_TO_DEVICE); | |
232 | } | |
233 | } | |
3bfb1d20 HS |
234 | |
235 | /* | |
236 | * The API requires that no submissions are done from a | |
237 | * callback, so we don't need to drop the lock here | |
238 | */ | |
239 | if (callback) | |
240 | callback(param); | |
241 | } | |
242 | ||
243 | static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
244 | { | |
245 | struct dw_desc *desc, *_desc; | |
246 | LIST_HEAD(list); | |
247 | ||
248 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
41d5e59c | 249 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
250 | "BUG: XFER bit set, but channel not idle!\n"); |
251 | ||
252 | /* Try to continue after resetting the channel... */ | |
253 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
254 | while (dma_readl(dw, CH_EN) & dwc->mask) | |
255 | cpu_relax(); | |
256 | } | |
257 | ||
258 | /* | |
259 | * Submit queued descriptors ASAP, i.e. before we go through | |
260 | * the completed ones. | |
261 | */ | |
262 | if (!list_empty(&dwc->queue)) | |
263 | dwc_dostart(dwc, dwc_first_queued(dwc)); | |
264 | list_splice_init(&dwc->active_list, &list); | |
265 | list_splice_init(&dwc->queue, &dwc->active_list); | |
266 | ||
267 | list_for_each_entry_safe(desc, _desc, &list, desc_node) | |
268 | dwc_descriptor_complete(dwc, desc); | |
269 | } | |
270 | ||
271 | static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
272 | { | |
273 | dma_addr_t llp; | |
274 | struct dw_desc *desc, *_desc; | |
275 | struct dw_desc *child; | |
276 | u32 status_xfer; | |
277 | ||
278 | /* | |
279 | * Clear block interrupt flag before scanning so that we don't | |
280 | * miss any, and read LLP before RAW_XFER to ensure it is | |
281 | * valid if we decide to scan the list. | |
282 | */ | |
283 | dma_writel(dw, CLEAR.BLOCK, dwc->mask); | |
284 | llp = channel_readl(dwc, LLP); | |
285 | status_xfer = dma_readl(dw, RAW.XFER); | |
286 | ||
287 | if (status_xfer & dwc->mask) { | |
288 | /* Everything we've submitted is done */ | |
289 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
290 | dwc_complete_all(dw, dwc); | |
291 | return; | |
292 | } | |
293 | ||
41d5e59c | 294 | dev_vdbg(chan2dev(&dwc->chan), "scan_descriptors: llp=0x%x\n", llp); |
3bfb1d20 HS |
295 | |
296 | list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) { | |
297 | if (desc->lli.llp == llp) | |
298 | /* This one is currently in progress */ | |
299 | return; | |
300 | ||
e0bd0f8c | 301 | list_for_each_entry(child, &desc->tx_list, desc_node) |
3bfb1d20 HS |
302 | if (child->lli.llp == llp) |
303 | /* Currently in progress */ | |
304 | return; | |
305 | ||
306 | /* | |
307 | * No descriptors so far seem to be in progress, i.e. | |
308 | * this one must be done. | |
309 | */ | |
310 | dwc_descriptor_complete(dwc, desc); | |
311 | } | |
312 | ||
41d5e59c | 313 | dev_err(chan2dev(&dwc->chan), |
3bfb1d20 HS |
314 | "BUG: All descriptors done, but channel not idle!\n"); |
315 | ||
316 | /* Try to continue after resetting the channel... */ | |
317 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
318 | while (dma_readl(dw, CH_EN) & dwc->mask) | |
319 | cpu_relax(); | |
320 | ||
321 | if (!list_empty(&dwc->queue)) { | |
322 | dwc_dostart(dwc, dwc_first_queued(dwc)); | |
323 | list_splice_init(&dwc->queue, &dwc->active_list); | |
324 | } | |
325 | } | |
326 | ||
327 | static void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli) | |
328 | { | |
41d5e59c | 329 | dev_printk(KERN_CRIT, chan2dev(&dwc->chan), |
3bfb1d20 HS |
330 | " desc: s0x%x d0x%x l0x%x c0x%x:%x\n", |
331 | lli->sar, lli->dar, lli->llp, | |
332 | lli->ctlhi, lli->ctllo); | |
333 | } | |
334 | ||
335 | static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc) | |
336 | { | |
337 | struct dw_desc *bad_desc; | |
338 | struct dw_desc *child; | |
339 | ||
340 | dwc_scan_descriptors(dw, dwc); | |
341 | ||
342 | /* | |
343 | * The descriptor currently at the head of the active list is | |
344 | * borked. Since we don't have any way to report errors, we'll | |
345 | * just have to scream loudly and try to carry on. | |
346 | */ | |
347 | bad_desc = dwc_first_active(dwc); | |
348 | list_del_init(&bad_desc->desc_node); | |
349 | list_splice_init(&dwc->queue, dwc->active_list.prev); | |
350 | ||
351 | /* Clear the error flag and try to restart the controller */ | |
352 | dma_writel(dw, CLEAR.ERROR, dwc->mask); | |
353 | if (!list_empty(&dwc->active_list)) | |
354 | dwc_dostart(dwc, dwc_first_active(dwc)); | |
355 | ||
356 | /* | |
357 | * KERN_CRITICAL may seem harsh, but since this only happens | |
358 | * when someone submits a bad physical address in a | |
359 | * descriptor, we should consider ourselves lucky that the | |
360 | * controller flagged an error instead of scribbling over | |
361 | * random memory locations. | |
362 | */ | |
41d5e59c | 363 | dev_printk(KERN_CRIT, chan2dev(&dwc->chan), |
3bfb1d20 | 364 | "Bad descriptor submitted for DMA!\n"); |
41d5e59c | 365 | dev_printk(KERN_CRIT, chan2dev(&dwc->chan), |
3bfb1d20 HS |
366 | " cookie: %d\n", bad_desc->txd.cookie); |
367 | dwc_dump_lli(dwc, &bad_desc->lli); | |
e0bd0f8c | 368 | list_for_each_entry(child, &bad_desc->tx_list, desc_node) |
3bfb1d20 HS |
369 | dwc_dump_lli(dwc, &child->lli); |
370 | ||
371 | /* Pretend the descriptor completed successfully */ | |
372 | dwc_descriptor_complete(dwc, bad_desc); | |
373 | } | |
374 | ||
d9de4519 HCE |
375 | /* --------------------- Cyclic DMA API extensions -------------------- */ |
376 | ||
377 | inline dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan) | |
378 | { | |
379 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
380 | return channel_readl(dwc, SAR); | |
381 | } | |
382 | EXPORT_SYMBOL(dw_dma_get_src_addr); | |
383 | ||
384 | inline dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan) | |
385 | { | |
386 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
387 | return channel_readl(dwc, DAR); | |
388 | } | |
389 | EXPORT_SYMBOL(dw_dma_get_dst_addr); | |
390 | ||
391 | /* called with dwc->lock held and all DMAC interrupts disabled */ | |
392 | static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc, | |
393 | u32 status_block, u32 status_err, u32 status_xfer) | |
394 | { | |
395 | if (status_block & dwc->mask) { | |
396 | void (*callback)(void *param); | |
397 | void *callback_param; | |
398 | ||
399 | dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n", | |
400 | channel_readl(dwc, LLP)); | |
401 | dma_writel(dw, CLEAR.BLOCK, dwc->mask); | |
402 | ||
403 | callback = dwc->cdesc->period_callback; | |
404 | callback_param = dwc->cdesc->period_callback_param; | |
405 | if (callback) { | |
406 | spin_unlock(&dwc->lock); | |
407 | callback(callback_param); | |
408 | spin_lock(&dwc->lock); | |
409 | } | |
410 | } | |
411 | ||
412 | /* | |
413 | * Error and transfer complete are highly unlikely, and will most | |
414 | * likely be due to a configuration error by the user. | |
415 | */ | |
416 | if (unlikely(status_err & dwc->mask) || | |
417 | unlikely(status_xfer & dwc->mask)) { | |
418 | int i; | |
419 | ||
420 | dev_err(chan2dev(&dwc->chan), "cyclic DMA unexpected %s " | |
421 | "interrupt, stopping DMA transfer\n", | |
422 | status_xfer ? "xfer" : "error"); | |
423 | dev_err(chan2dev(&dwc->chan), | |
424 | " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n", | |
425 | channel_readl(dwc, SAR), | |
426 | channel_readl(dwc, DAR), | |
427 | channel_readl(dwc, LLP), | |
428 | channel_readl(dwc, CTL_HI), | |
429 | channel_readl(dwc, CTL_LO)); | |
430 | ||
431 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
432 | while (dma_readl(dw, CH_EN) & dwc->mask) | |
433 | cpu_relax(); | |
434 | ||
435 | /* make sure DMA does not restart by loading a new list */ | |
436 | channel_writel(dwc, LLP, 0); | |
437 | channel_writel(dwc, CTL_LO, 0); | |
438 | channel_writel(dwc, CTL_HI, 0); | |
439 | ||
440 | dma_writel(dw, CLEAR.BLOCK, dwc->mask); | |
441 | dma_writel(dw, CLEAR.ERROR, dwc->mask); | |
442 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
443 | ||
444 | for (i = 0; i < dwc->cdesc->periods; i++) | |
445 | dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli); | |
446 | } | |
447 | } | |
448 | ||
449 | /* ------------------------------------------------------------------------- */ | |
450 | ||
3bfb1d20 HS |
451 | static void dw_dma_tasklet(unsigned long data) |
452 | { | |
453 | struct dw_dma *dw = (struct dw_dma *)data; | |
454 | struct dw_dma_chan *dwc; | |
455 | u32 status_block; | |
456 | u32 status_xfer; | |
457 | u32 status_err; | |
458 | int i; | |
459 | ||
460 | status_block = dma_readl(dw, RAW.BLOCK); | |
7fe7b2f4 | 461 | status_xfer = dma_readl(dw, RAW.XFER); |
3bfb1d20 HS |
462 | status_err = dma_readl(dw, RAW.ERROR); |
463 | ||
464 | dev_vdbg(dw->dma.dev, "tasklet: status_block=%x status_err=%x\n", | |
465 | status_block, status_err); | |
466 | ||
467 | for (i = 0; i < dw->dma.chancnt; i++) { | |
468 | dwc = &dw->chan[i]; | |
469 | spin_lock(&dwc->lock); | |
d9de4519 HCE |
470 | if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) |
471 | dwc_handle_cyclic(dw, dwc, status_block, status_err, | |
472 | status_xfer); | |
473 | else if (status_err & (1 << i)) | |
3bfb1d20 HS |
474 | dwc_handle_error(dw, dwc); |
475 | else if ((status_block | status_xfer) & (1 << i)) | |
476 | dwc_scan_descriptors(dw, dwc); | |
477 | spin_unlock(&dwc->lock); | |
478 | } | |
479 | ||
480 | /* | |
481 | * Re-enable interrupts. Block Complete interrupts are only | |
482 | * enabled if the INT_EN bit in the descriptor is set. This | |
483 | * will trigger a scan before the whole list is done. | |
484 | */ | |
485 | channel_set_bit(dw, MASK.XFER, dw->all_chan_mask); | |
486 | channel_set_bit(dw, MASK.BLOCK, dw->all_chan_mask); | |
487 | channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask); | |
488 | } | |
489 | ||
490 | static irqreturn_t dw_dma_interrupt(int irq, void *dev_id) | |
491 | { | |
492 | struct dw_dma *dw = dev_id; | |
493 | u32 status; | |
494 | ||
495 | dev_vdbg(dw->dma.dev, "interrupt: status=0x%x\n", | |
496 | dma_readl(dw, STATUS_INT)); | |
497 | ||
498 | /* | |
499 | * Just disable the interrupts. We'll turn them back on in the | |
500 | * softirq handler. | |
501 | */ | |
502 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
503 | channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); | |
504 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); | |
505 | ||
506 | status = dma_readl(dw, STATUS_INT); | |
507 | if (status) { | |
508 | dev_err(dw->dma.dev, | |
509 | "BUG: Unexpected interrupts pending: 0x%x\n", | |
510 | status); | |
511 | ||
512 | /* Try to recover */ | |
513 | channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1); | |
514 | channel_clear_bit(dw, MASK.BLOCK, (1 << 8) - 1); | |
515 | channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1); | |
516 | channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1); | |
517 | channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1); | |
518 | } | |
519 | ||
520 | tasklet_schedule(&dw->tasklet); | |
521 | ||
522 | return IRQ_HANDLED; | |
523 | } | |
524 | ||
525 | /*----------------------------------------------------------------------*/ | |
526 | ||
527 | static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx) | |
528 | { | |
529 | struct dw_desc *desc = txd_to_dw_desc(tx); | |
530 | struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan); | |
531 | dma_cookie_t cookie; | |
532 | ||
533 | spin_lock_bh(&dwc->lock); | |
534 | cookie = dwc_assign_cookie(dwc, desc); | |
535 | ||
536 | /* | |
537 | * REVISIT: We should attempt to chain as many descriptors as | |
538 | * possible, perhaps even appending to those already submitted | |
539 | * for DMA. But this is hard to do in a race-free manner. | |
540 | */ | |
541 | if (list_empty(&dwc->active_list)) { | |
41d5e59c | 542 | dev_vdbg(chan2dev(tx->chan), "tx_submit: started %u\n", |
3bfb1d20 HS |
543 | desc->txd.cookie); |
544 | dwc_dostart(dwc, desc); | |
545 | list_add_tail(&desc->desc_node, &dwc->active_list); | |
546 | } else { | |
41d5e59c | 547 | dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u\n", |
3bfb1d20 HS |
548 | desc->txd.cookie); |
549 | ||
550 | list_add_tail(&desc->desc_node, &dwc->queue); | |
551 | } | |
552 | ||
553 | spin_unlock_bh(&dwc->lock); | |
554 | ||
555 | return cookie; | |
556 | } | |
557 | ||
558 | static struct dma_async_tx_descriptor * | |
559 | dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
560 | size_t len, unsigned long flags) | |
561 | { | |
562 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
563 | struct dw_desc *desc; | |
564 | struct dw_desc *first; | |
565 | struct dw_desc *prev; | |
566 | size_t xfer_count; | |
567 | size_t offset; | |
568 | unsigned int src_width; | |
569 | unsigned int dst_width; | |
570 | u32 ctllo; | |
571 | ||
41d5e59c | 572 | dev_vdbg(chan2dev(chan), "prep_dma_memcpy d0x%x s0x%x l0x%zx f0x%lx\n", |
3bfb1d20 HS |
573 | dest, src, len, flags); |
574 | ||
575 | if (unlikely(!len)) { | |
41d5e59c | 576 | dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n"); |
3bfb1d20 HS |
577 | return NULL; |
578 | } | |
579 | ||
580 | /* | |
581 | * We can be a lot more clever here, but this should take care | |
582 | * of the most common optimization. | |
583 | */ | |
584 | if (!((src | dest | len) & 3)) | |
585 | src_width = dst_width = 2; | |
586 | else if (!((src | dest | len) & 1)) | |
587 | src_width = dst_width = 1; | |
588 | else | |
589 | src_width = dst_width = 0; | |
590 | ||
591 | ctllo = DWC_DEFAULT_CTLLO | |
592 | | DWC_CTLL_DST_WIDTH(dst_width) | |
593 | | DWC_CTLL_SRC_WIDTH(src_width) | |
594 | | DWC_CTLL_DST_INC | |
595 | | DWC_CTLL_SRC_INC | |
596 | | DWC_CTLL_FC_M2M; | |
597 | prev = first = NULL; | |
598 | ||
599 | for (offset = 0; offset < len; offset += xfer_count << src_width) { | |
600 | xfer_count = min_t(size_t, (len - offset) >> src_width, | |
601 | DWC_MAX_COUNT); | |
602 | ||
603 | desc = dwc_desc_get(dwc); | |
604 | if (!desc) | |
605 | goto err_desc_get; | |
606 | ||
607 | desc->lli.sar = src + offset; | |
608 | desc->lli.dar = dest + offset; | |
609 | desc->lli.ctllo = ctllo; | |
610 | desc->lli.ctlhi = xfer_count; | |
611 | ||
612 | if (!first) { | |
613 | first = desc; | |
614 | } else { | |
615 | prev->lli.llp = desc->txd.phys; | |
41d5e59c | 616 | dma_sync_single_for_device(chan2parent(chan), |
3bfb1d20 HS |
617 | prev->txd.phys, sizeof(prev->lli), |
618 | DMA_TO_DEVICE); | |
619 | list_add_tail(&desc->desc_node, | |
e0bd0f8c | 620 | &first->tx_list); |
3bfb1d20 HS |
621 | } |
622 | prev = desc; | |
623 | } | |
624 | ||
625 | ||
626 | if (flags & DMA_PREP_INTERRUPT) | |
627 | /* Trigger interrupt after last block */ | |
628 | prev->lli.ctllo |= DWC_CTLL_INT_EN; | |
629 | ||
630 | prev->lli.llp = 0; | |
41d5e59c | 631 | dma_sync_single_for_device(chan2parent(chan), |
3bfb1d20 HS |
632 | prev->txd.phys, sizeof(prev->lli), |
633 | DMA_TO_DEVICE); | |
634 | ||
635 | first->txd.flags = flags; | |
636 | first->len = len; | |
637 | ||
638 | return &first->txd; | |
639 | ||
640 | err_desc_get: | |
641 | dwc_desc_put(dwc, first); | |
642 | return NULL; | |
643 | } | |
644 | ||
645 | static struct dma_async_tx_descriptor * | |
646 | dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
647 | unsigned int sg_len, enum dma_data_direction direction, | |
648 | unsigned long flags) | |
649 | { | |
650 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
287d8592 | 651 | struct dw_dma_slave *dws = chan->private; |
3bfb1d20 HS |
652 | struct dw_desc *prev; |
653 | struct dw_desc *first; | |
654 | u32 ctllo; | |
655 | dma_addr_t reg; | |
656 | unsigned int reg_width; | |
657 | unsigned int mem_width; | |
658 | unsigned int i; | |
659 | struct scatterlist *sg; | |
660 | size_t total_len = 0; | |
661 | ||
41d5e59c | 662 | dev_vdbg(chan2dev(chan), "prep_dma_slave\n"); |
3bfb1d20 HS |
663 | |
664 | if (unlikely(!dws || !sg_len)) | |
665 | return NULL; | |
666 | ||
74465b4f | 667 | reg_width = dws->reg_width; |
3bfb1d20 HS |
668 | prev = first = NULL; |
669 | ||
3bfb1d20 HS |
670 | switch (direction) { |
671 | case DMA_TO_DEVICE: | |
672 | ctllo = (DWC_DEFAULT_CTLLO | |
673 | | DWC_CTLL_DST_WIDTH(reg_width) | |
674 | | DWC_CTLL_DST_FIX | |
675 | | DWC_CTLL_SRC_INC | |
676 | | DWC_CTLL_FC_M2P); | |
74465b4f | 677 | reg = dws->tx_reg; |
3bfb1d20 HS |
678 | for_each_sg(sgl, sg, sg_len, i) { |
679 | struct dw_desc *desc; | |
680 | u32 len; | |
681 | u32 mem; | |
682 | ||
683 | desc = dwc_desc_get(dwc); | |
684 | if (!desc) { | |
41d5e59c | 685 | dev_err(chan2dev(chan), |
3bfb1d20 HS |
686 | "not enough descriptors available\n"); |
687 | goto err_desc_get; | |
688 | } | |
689 | ||
690 | mem = sg_phys(sg); | |
691 | len = sg_dma_len(sg); | |
692 | mem_width = 2; | |
693 | if (unlikely(mem & 3 || len & 3)) | |
694 | mem_width = 0; | |
695 | ||
696 | desc->lli.sar = mem; | |
697 | desc->lli.dar = reg; | |
698 | desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width); | |
699 | desc->lli.ctlhi = len >> mem_width; | |
700 | ||
701 | if (!first) { | |
702 | first = desc; | |
703 | } else { | |
704 | prev->lli.llp = desc->txd.phys; | |
41d5e59c | 705 | dma_sync_single_for_device(chan2parent(chan), |
3bfb1d20 HS |
706 | prev->txd.phys, |
707 | sizeof(prev->lli), | |
708 | DMA_TO_DEVICE); | |
709 | list_add_tail(&desc->desc_node, | |
e0bd0f8c | 710 | &first->tx_list); |
3bfb1d20 HS |
711 | } |
712 | prev = desc; | |
713 | total_len += len; | |
714 | } | |
715 | break; | |
716 | case DMA_FROM_DEVICE: | |
717 | ctllo = (DWC_DEFAULT_CTLLO | |
718 | | DWC_CTLL_SRC_WIDTH(reg_width) | |
719 | | DWC_CTLL_DST_INC | |
720 | | DWC_CTLL_SRC_FIX | |
721 | | DWC_CTLL_FC_P2M); | |
722 | ||
74465b4f | 723 | reg = dws->rx_reg; |
3bfb1d20 HS |
724 | for_each_sg(sgl, sg, sg_len, i) { |
725 | struct dw_desc *desc; | |
726 | u32 len; | |
727 | u32 mem; | |
728 | ||
729 | desc = dwc_desc_get(dwc); | |
730 | if (!desc) { | |
41d5e59c | 731 | dev_err(chan2dev(chan), |
3bfb1d20 HS |
732 | "not enough descriptors available\n"); |
733 | goto err_desc_get; | |
734 | } | |
735 | ||
736 | mem = sg_phys(sg); | |
737 | len = sg_dma_len(sg); | |
738 | mem_width = 2; | |
739 | if (unlikely(mem & 3 || len & 3)) | |
740 | mem_width = 0; | |
741 | ||
742 | desc->lli.sar = reg; | |
743 | desc->lli.dar = mem; | |
744 | desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width); | |
745 | desc->lli.ctlhi = len >> reg_width; | |
746 | ||
747 | if (!first) { | |
748 | first = desc; | |
749 | } else { | |
750 | prev->lli.llp = desc->txd.phys; | |
41d5e59c | 751 | dma_sync_single_for_device(chan2parent(chan), |
3bfb1d20 HS |
752 | prev->txd.phys, |
753 | sizeof(prev->lli), | |
754 | DMA_TO_DEVICE); | |
755 | list_add_tail(&desc->desc_node, | |
e0bd0f8c | 756 | &first->tx_list); |
3bfb1d20 HS |
757 | } |
758 | prev = desc; | |
759 | total_len += len; | |
760 | } | |
761 | break; | |
762 | default: | |
763 | return NULL; | |
764 | } | |
765 | ||
766 | if (flags & DMA_PREP_INTERRUPT) | |
767 | /* Trigger interrupt after last block */ | |
768 | prev->lli.ctllo |= DWC_CTLL_INT_EN; | |
769 | ||
770 | prev->lli.llp = 0; | |
41d5e59c | 771 | dma_sync_single_for_device(chan2parent(chan), |
3bfb1d20 HS |
772 | prev->txd.phys, sizeof(prev->lli), |
773 | DMA_TO_DEVICE); | |
774 | ||
775 | first->len = total_len; | |
776 | ||
777 | return &first->txd; | |
778 | ||
779 | err_desc_get: | |
780 | dwc_desc_put(dwc, first); | |
781 | return NULL; | |
782 | } | |
783 | ||
c3635c78 | 784 | static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd) |
3bfb1d20 HS |
785 | { |
786 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
787 | struct dw_dma *dw = to_dw_dma(chan->device); | |
788 | struct dw_desc *desc, *_desc; | |
789 | LIST_HEAD(list); | |
790 | ||
c3635c78 LW |
791 | /* Only supports DMA_TERMINATE_ALL */ |
792 | if (cmd != DMA_TERMINATE_ALL) | |
793 | return -ENXIO; | |
794 | ||
3bfb1d20 HS |
795 | /* |
796 | * This is only called when something went wrong elsewhere, so | |
797 | * we don't really care about the data. Just disable the | |
798 | * channel. We still have to poll the channel enable bit due | |
799 | * to AHB/HSB limitations. | |
800 | */ | |
801 | spin_lock_bh(&dwc->lock); | |
802 | ||
803 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
804 | ||
805 | while (dma_readl(dw, CH_EN) & dwc->mask) | |
806 | cpu_relax(); | |
807 | ||
808 | /* active_list entries will end up before queued entries */ | |
809 | list_splice_init(&dwc->queue, &list); | |
810 | list_splice_init(&dwc->active_list, &list); | |
811 | ||
812 | spin_unlock_bh(&dwc->lock); | |
813 | ||
814 | /* Flush all pending and queued descriptors */ | |
815 | list_for_each_entry_safe(desc, _desc, &list, desc_node) | |
816 | dwc_descriptor_complete(dwc, desc); | |
c3635c78 LW |
817 | |
818 | return 0; | |
3bfb1d20 HS |
819 | } |
820 | ||
821 | static enum dma_status | |
822 | dwc_is_tx_complete(struct dma_chan *chan, | |
823 | dma_cookie_t cookie, | |
824 | dma_cookie_t *done, dma_cookie_t *used) | |
825 | { | |
826 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
827 | dma_cookie_t last_used; | |
828 | dma_cookie_t last_complete; | |
829 | int ret; | |
830 | ||
831 | last_complete = dwc->completed; | |
832 | last_used = chan->cookie; | |
833 | ||
834 | ret = dma_async_is_complete(cookie, last_complete, last_used); | |
835 | if (ret != DMA_SUCCESS) { | |
836 | dwc_scan_descriptors(to_dw_dma(chan->device), dwc); | |
837 | ||
838 | last_complete = dwc->completed; | |
839 | last_used = chan->cookie; | |
840 | ||
841 | ret = dma_async_is_complete(cookie, last_complete, last_used); | |
842 | } | |
843 | ||
844 | if (done) | |
845 | *done = last_complete; | |
846 | if (used) | |
847 | *used = last_used; | |
848 | ||
849 | return ret; | |
850 | } | |
851 | ||
852 | static void dwc_issue_pending(struct dma_chan *chan) | |
853 | { | |
854 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
855 | ||
856 | spin_lock_bh(&dwc->lock); | |
857 | if (!list_empty(&dwc->queue)) | |
858 | dwc_scan_descriptors(to_dw_dma(chan->device), dwc); | |
859 | spin_unlock_bh(&dwc->lock); | |
860 | } | |
861 | ||
aa1e6f1a | 862 | static int dwc_alloc_chan_resources(struct dma_chan *chan) |
3bfb1d20 HS |
863 | { |
864 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
865 | struct dw_dma *dw = to_dw_dma(chan->device); | |
866 | struct dw_desc *desc; | |
3bfb1d20 HS |
867 | struct dw_dma_slave *dws; |
868 | int i; | |
869 | u32 cfghi; | |
870 | u32 cfglo; | |
871 | ||
41d5e59c | 872 | dev_vdbg(chan2dev(chan), "alloc_chan_resources\n"); |
3bfb1d20 | 873 | |
3bfb1d20 HS |
874 | /* ASSERT: channel is idle */ |
875 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
41d5e59c | 876 | dev_dbg(chan2dev(chan), "DMA channel not idle?\n"); |
3bfb1d20 HS |
877 | return -EIO; |
878 | } | |
879 | ||
880 | dwc->completed = chan->cookie = 1; | |
881 | ||
882 | cfghi = DWC_CFGH_FIFO_MODE; | |
883 | cfglo = 0; | |
884 | ||
287d8592 | 885 | dws = chan->private; |
74465b4f | 886 | if (dws) { |
3bfb1d20 HS |
887 | /* |
888 | * We need controller-specific data to set up slave | |
889 | * transfers. | |
890 | */ | |
74465b4f | 891 | BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev); |
3bfb1d20 | 892 | |
3bfb1d20 HS |
893 | cfghi = dws->cfg_hi; |
894 | cfglo = dws->cfg_lo; | |
3bfb1d20 | 895 | } |
3bfb1d20 HS |
896 | channel_writel(dwc, CFG_LO, cfglo); |
897 | channel_writel(dwc, CFG_HI, cfghi); | |
898 | ||
899 | /* | |
900 | * NOTE: some controllers may have additional features that we | |
901 | * need to initialize here, like "scatter-gather" (which | |
902 | * doesn't mean what you think it means), and status writeback. | |
903 | */ | |
904 | ||
905 | spin_lock_bh(&dwc->lock); | |
906 | i = dwc->descs_allocated; | |
907 | while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) { | |
908 | spin_unlock_bh(&dwc->lock); | |
909 | ||
910 | desc = kzalloc(sizeof(struct dw_desc), GFP_KERNEL); | |
911 | if (!desc) { | |
41d5e59c | 912 | dev_info(chan2dev(chan), |
3bfb1d20 HS |
913 | "only allocated %d descriptors\n", i); |
914 | spin_lock_bh(&dwc->lock); | |
915 | break; | |
916 | } | |
917 | ||
e0bd0f8c | 918 | INIT_LIST_HEAD(&desc->tx_list); |
3bfb1d20 HS |
919 | dma_async_tx_descriptor_init(&desc->txd, chan); |
920 | desc->txd.tx_submit = dwc_tx_submit; | |
921 | desc->txd.flags = DMA_CTRL_ACK; | |
41d5e59c | 922 | desc->txd.phys = dma_map_single(chan2parent(chan), &desc->lli, |
3bfb1d20 HS |
923 | sizeof(desc->lli), DMA_TO_DEVICE); |
924 | dwc_desc_put(dwc, desc); | |
925 | ||
926 | spin_lock_bh(&dwc->lock); | |
927 | i = ++dwc->descs_allocated; | |
928 | } | |
929 | ||
930 | /* Enable interrupts */ | |
931 | channel_set_bit(dw, MASK.XFER, dwc->mask); | |
932 | channel_set_bit(dw, MASK.BLOCK, dwc->mask); | |
933 | channel_set_bit(dw, MASK.ERROR, dwc->mask); | |
934 | ||
935 | spin_unlock_bh(&dwc->lock); | |
936 | ||
41d5e59c | 937 | dev_dbg(chan2dev(chan), |
3bfb1d20 HS |
938 | "alloc_chan_resources allocated %d descriptors\n", i); |
939 | ||
940 | return i; | |
941 | } | |
942 | ||
943 | static void dwc_free_chan_resources(struct dma_chan *chan) | |
944 | { | |
945 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
946 | struct dw_dma *dw = to_dw_dma(chan->device); | |
947 | struct dw_desc *desc, *_desc; | |
948 | LIST_HEAD(list); | |
949 | ||
41d5e59c | 950 | dev_dbg(chan2dev(chan), "free_chan_resources (descs allocated=%u)\n", |
3bfb1d20 HS |
951 | dwc->descs_allocated); |
952 | ||
953 | /* ASSERT: channel is idle */ | |
954 | BUG_ON(!list_empty(&dwc->active_list)); | |
955 | BUG_ON(!list_empty(&dwc->queue)); | |
956 | BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask); | |
957 | ||
958 | spin_lock_bh(&dwc->lock); | |
959 | list_splice_init(&dwc->free_list, &list); | |
960 | dwc->descs_allocated = 0; | |
3bfb1d20 HS |
961 | |
962 | /* Disable interrupts */ | |
963 | channel_clear_bit(dw, MASK.XFER, dwc->mask); | |
964 | channel_clear_bit(dw, MASK.BLOCK, dwc->mask); | |
965 | channel_clear_bit(dw, MASK.ERROR, dwc->mask); | |
966 | ||
967 | spin_unlock_bh(&dwc->lock); | |
968 | ||
969 | list_for_each_entry_safe(desc, _desc, &list, desc_node) { | |
41d5e59c DW |
970 | dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc); |
971 | dma_unmap_single(chan2parent(chan), desc->txd.phys, | |
3bfb1d20 HS |
972 | sizeof(desc->lli), DMA_TO_DEVICE); |
973 | kfree(desc); | |
974 | } | |
975 | ||
41d5e59c | 976 | dev_vdbg(chan2dev(chan), "free_chan_resources done\n"); |
3bfb1d20 HS |
977 | } |
978 | ||
d9de4519 HCE |
979 | /* --------------------- Cyclic DMA API extensions -------------------- */ |
980 | ||
981 | /** | |
982 | * dw_dma_cyclic_start - start the cyclic DMA transfer | |
983 | * @chan: the DMA channel to start | |
984 | * | |
985 | * Must be called with soft interrupts disabled. Returns zero on success or | |
986 | * -errno on failure. | |
987 | */ | |
988 | int dw_dma_cyclic_start(struct dma_chan *chan) | |
989 | { | |
990 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
991 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
992 | ||
993 | if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) { | |
994 | dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n"); | |
995 | return -ENODEV; | |
996 | } | |
997 | ||
998 | spin_lock(&dwc->lock); | |
999 | ||
1000 | /* assert channel is idle */ | |
1001 | if (dma_readl(dw, CH_EN) & dwc->mask) { | |
1002 | dev_err(chan2dev(&dwc->chan), | |
1003 | "BUG: Attempted to start non-idle channel\n"); | |
1004 | dev_err(chan2dev(&dwc->chan), | |
1005 | " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n", | |
1006 | channel_readl(dwc, SAR), | |
1007 | channel_readl(dwc, DAR), | |
1008 | channel_readl(dwc, LLP), | |
1009 | channel_readl(dwc, CTL_HI), | |
1010 | channel_readl(dwc, CTL_LO)); | |
1011 | spin_unlock(&dwc->lock); | |
1012 | return -EBUSY; | |
1013 | } | |
1014 | ||
1015 | dma_writel(dw, CLEAR.BLOCK, dwc->mask); | |
1016 | dma_writel(dw, CLEAR.ERROR, dwc->mask); | |
1017 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
1018 | ||
1019 | /* setup DMAC channel registers */ | |
1020 | channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys); | |
1021 | channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); | |
1022 | channel_writel(dwc, CTL_HI, 0); | |
1023 | ||
1024 | channel_set_bit(dw, CH_EN, dwc->mask); | |
1025 | ||
1026 | spin_unlock(&dwc->lock); | |
1027 | ||
1028 | return 0; | |
1029 | } | |
1030 | EXPORT_SYMBOL(dw_dma_cyclic_start); | |
1031 | ||
1032 | /** | |
1033 | * dw_dma_cyclic_stop - stop the cyclic DMA transfer | |
1034 | * @chan: the DMA channel to stop | |
1035 | * | |
1036 | * Must be called with soft interrupts disabled. | |
1037 | */ | |
1038 | void dw_dma_cyclic_stop(struct dma_chan *chan) | |
1039 | { | |
1040 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1041 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
1042 | ||
1043 | spin_lock(&dwc->lock); | |
1044 | ||
1045 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
1046 | while (dma_readl(dw, CH_EN) & dwc->mask) | |
1047 | cpu_relax(); | |
1048 | ||
1049 | spin_unlock(&dwc->lock); | |
1050 | } | |
1051 | EXPORT_SYMBOL(dw_dma_cyclic_stop); | |
1052 | ||
1053 | /** | |
1054 | * dw_dma_cyclic_prep - prepare the cyclic DMA transfer | |
1055 | * @chan: the DMA channel to prepare | |
1056 | * @buf_addr: physical DMA address where the buffer starts | |
1057 | * @buf_len: total number of bytes for the entire buffer | |
1058 | * @period_len: number of bytes for each period | |
1059 | * @direction: transfer direction, to or from device | |
1060 | * | |
1061 | * Must be called before trying to start the transfer. Returns a valid struct | |
1062 | * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful. | |
1063 | */ | |
1064 | struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan, | |
1065 | dma_addr_t buf_addr, size_t buf_len, size_t period_len, | |
1066 | enum dma_data_direction direction) | |
1067 | { | |
1068 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1069 | struct dw_cyclic_desc *cdesc; | |
1070 | struct dw_cyclic_desc *retval = NULL; | |
1071 | struct dw_desc *desc; | |
1072 | struct dw_desc *last = NULL; | |
1073 | struct dw_dma_slave *dws = chan->private; | |
1074 | unsigned long was_cyclic; | |
1075 | unsigned int reg_width; | |
1076 | unsigned int periods; | |
1077 | unsigned int i; | |
1078 | ||
1079 | spin_lock_bh(&dwc->lock); | |
1080 | if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) { | |
1081 | spin_unlock_bh(&dwc->lock); | |
1082 | dev_dbg(chan2dev(&dwc->chan), | |
1083 | "queue and/or active list are not empty\n"); | |
1084 | return ERR_PTR(-EBUSY); | |
1085 | } | |
1086 | ||
1087 | was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
1088 | spin_unlock_bh(&dwc->lock); | |
1089 | if (was_cyclic) { | |
1090 | dev_dbg(chan2dev(&dwc->chan), | |
1091 | "channel already prepared for cyclic DMA\n"); | |
1092 | return ERR_PTR(-EBUSY); | |
1093 | } | |
1094 | ||
1095 | retval = ERR_PTR(-EINVAL); | |
1096 | reg_width = dws->reg_width; | |
1097 | periods = buf_len / period_len; | |
1098 | ||
1099 | /* Check for too big/unaligned periods and unaligned DMA buffer. */ | |
1100 | if (period_len > (DWC_MAX_COUNT << reg_width)) | |
1101 | goto out_err; | |
1102 | if (unlikely(period_len & ((1 << reg_width) - 1))) | |
1103 | goto out_err; | |
1104 | if (unlikely(buf_addr & ((1 << reg_width) - 1))) | |
1105 | goto out_err; | |
1106 | if (unlikely(!(direction & (DMA_TO_DEVICE | DMA_FROM_DEVICE)))) | |
1107 | goto out_err; | |
1108 | ||
1109 | retval = ERR_PTR(-ENOMEM); | |
1110 | ||
1111 | if (periods > NR_DESCS_PER_CHANNEL) | |
1112 | goto out_err; | |
1113 | ||
1114 | cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL); | |
1115 | if (!cdesc) | |
1116 | goto out_err; | |
1117 | ||
1118 | cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL); | |
1119 | if (!cdesc->desc) | |
1120 | goto out_err_alloc; | |
1121 | ||
1122 | for (i = 0; i < periods; i++) { | |
1123 | desc = dwc_desc_get(dwc); | |
1124 | if (!desc) | |
1125 | goto out_err_desc_get; | |
1126 | ||
1127 | switch (direction) { | |
1128 | case DMA_TO_DEVICE: | |
1129 | desc->lli.dar = dws->tx_reg; | |
1130 | desc->lli.sar = buf_addr + (period_len * i); | |
1131 | desc->lli.ctllo = (DWC_DEFAULT_CTLLO | |
1132 | | DWC_CTLL_DST_WIDTH(reg_width) | |
1133 | | DWC_CTLL_SRC_WIDTH(reg_width) | |
1134 | | DWC_CTLL_DST_FIX | |
1135 | | DWC_CTLL_SRC_INC | |
1136 | | DWC_CTLL_FC_M2P | |
1137 | | DWC_CTLL_INT_EN); | |
1138 | break; | |
1139 | case DMA_FROM_DEVICE: | |
1140 | desc->lli.dar = buf_addr + (period_len * i); | |
1141 | desc->lli.sar = dws->rx_reg; | |
1142 | desc->lli.ctllo = (DWC_DEFAULT_CTLLO | |
1143 | | DWC_CTLL_SRC_WIDTH(reg_width) | |
1144 | | DWC_CTLL_DST_WIDTH(reg_width) | |
1145 | | DWC_CTLL_DST_INC | |
1146 | | DWC_CTLL_SRC_FIX | |
1147 | | DWC_CTLL_FC_P2M | |
1148 | | DWC_CTLL_INT_EN); | |
1149 | break; | |
1150 | default: | |
1151 | break; | |
1152 | } | |
1153 | ||
1154 | desc->lli.ctlhi = (period_len >> reg_width); | |
1155 | cdesc->desc[i] = desc; | |
1156 | ||
1157 | if (last) { | |
1158 | last->lli.llp = desc->txd.phys; | |
1159 | dma_sync_single_for_device(chan2parent(chan), | |
1160 | last->txd.phys, sizeof(last->lli), | |
1161 | DMA_TO_DEVICE); | |
1162 | } | |
1163 | ||
1164 | last = desc; | |
1165 | } | |
1166 | ||
1167 | /* lets make a cyclic list */ | |
1168 | last->lli.llp = cdesc->desc[0]->txd.phys; | |
1169 | dma_sync_single_for_device(chan2parent(chan), last->txd.phys, | |
1170 | sizeof(last->lli), DMA_TO_DEVICE); | |
1171 | ||
1172 | dev_dbg(chan2dev(&dwc->chan), "cyclic prepared buf 0x%08x len %zu " | |
1173 | "period %zu periods %d\n", buf_addr, buf_len, | |
1174 | period_len, periods); | |
1175 | ||
1176 | cdesc->periods = periods; | |
1177 | dwc->cdesc = cdesc; | |
1178 | ||
1179 | return cdesc; | |
1180 | ||
1181 | out_err_desc_get: | |
1182 | while (i--) | |
1183 | dwc_desc_put(dwc, cdesc->desc[i]); | |
1184 | out_err_alloc: | |
1185 | kfree(cdesc); | |
1186 | out_err: | |
1187 | clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
1188 | return (struct dw_cyclic_desc *)retval; | |
1189 | } | |
1190 | EXPORT_SYMBOL(dw_dma_cyclic_prep); | |
1191 | ||
1192 | /** | |
1193 | * dw_dma_cyclic_free - free a prepared cyclic DMA transfer | |
1194 | * @chan: the DMA channel to free | |
1195 | */ | |
1196 | void dw_dma_cyclic_free(struct dma_chan *chan) | |
1197 | { | |
1198 | struct dw_dma_chan *dwc = to_dw_dma_chan(chan); | |
1199 | struct dw_dma *dw = to_dw_dma(dwc->chan.device); | |
1200 | struct dw_cyclic_desc *cdesc = dwc->cdesc; | |
1201 | int i; | |
1202 | ||
1203 | dev_dbg(chan2dev(&dwc->chan), "cyclic free\n"); | |
1204 | ||
1205 | if (!cdesc) | |
1206 | return; | |
1207 | ||
1208 | spin_lock_bh(&dwc->lock); | |
1209 | ||
1210 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
1211 | while (dma_readl(dw, CH_EN) & dwc->mask) | |
1212 | cpu_relax(); | |
1213 | ||
1214 | dma_writel(dw, CLEAR.BLOCK, dwc->mask); | |
1215 | dma_writel(dw, CLEAR.ERROR, dwc->mask); | |
1216 | dma_writel(dw, CLEAR.XFER, dwc->mask); | |
1217 | ||
1218 | spin_unlock_bh(&dwc->lock); | |
1219 | ||
1220 | for (i = 0; i < cdesc->periods; i++) | |
1221 | dwc_desc_put(dwc, cdesc->desc[i]); | |
1222 | ||
1223 | kfree(cdesc->desc); | |
1224 | kfree(cdesc); | |
1225 | ||
1226 | clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); | |
1227 | } | |
1228 | EXPORT_SYMBOL(dw_dma_cyclic_free); | |
1229 | ||
3bfb1d20 HS |
1230 | /*----------------------------------------------------------------------*/ |
1231 | ||
1232 | static void dw_dma_off(struct dw_dma *dw) | |
1233 | { | |
1234 | dma_writel(dw, CFG, 0); | |
1235 | ||
1236 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
1237 | channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); | |
1238 | channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask); | |
1239 | channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask); | |
1240 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); | |
1241 | ||
1242 | while (dma_readl(dw, CFG) & DW_CFG_DMA_EN) | |
1243 | cpu_relax(); | |
1244 | } | |
1245 | ||
1246 | static int __init dw_probe(struct platform_device *pdev) | |
1247 | { | |
1248 | struct dw_dma_platform_data *pdata; | |
1249 | struct resource *io; | |
1250 | struct dw_dma *dw; | |
1251 | size_t size; | |
1252 | int irq; | |
1253 | int err; | |
1254 | int i; | |
1255 | ||
1256 | pdata = pdev->dev.platform_data; | |
1257 | if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) | |
1258 | return -EINVAL; | |
1259 | ||
1260 | io = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1261 | if (!io) | |
1262 | return -EINVAL; | |
1263 | ||
1264 | irq = platform_get_irq(pdev, 0); | |
1265 | if (irq < 0) | |
1266 | return irq; | |
1267 | ||
1268 | size = sizeof(struct dw_dma); | |
1269 | size += pdata->nr_channels * sizeof(struct dw_dma_chan); | |
1270 | dw = kzalloc(size, GFP_KERNEL); | |
1271 | if (!dw) | |
1272 | return -ENOMEM; | |
1273 | ||
1274 | if (!request_mem_region(io->start, DW_REGLEN, pdev->dev.driver->name)) { | |
1275 | err = -EBUSY; | |
1276 | goto err_kfree; | |
1277 | } | |
1278 | ||
3bfb1d20 HS |
1279 | dw->regs = ioremap(io->start, DW_REGLEN); |
1280 | if (!dw->regs) { | |
1281 | err = -ENOMEM; | |
1282 | goto err_release_r; | |
1283 | } | |
1284 | ||
1285 | dw->clk = clk_get(&pdev->dev, "hclk"); | |
1286 | if (IS_ERR(dw->clk)) { | |
1287 | err = PTR_ERR(dw->clk); | |
1288 | goto err_clk; | |
1289 | } | |
1290 | clk_enable(dw->clk); | |
1291 | ||
1292 | /* force dma off, just in case */ | |
1293 | dw_dma_off(dw); | |
1294 | ||
1295 | err = request_irq(irq, dw_dma_interrupt, 0, "dw_dmac", dw); | |
1296 | if (err) | |
1297 | goto err_irq; | |
1298 | ||
1299 | platform_set_drvdata(pdev, dw); | |
1300 | ||
1301 | tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw); | |
1302 | ||
1303 | dw->all_chan_mask = (1 << pdata->nr_channels) - 1; | |
1304 | ||
1305 | INIT_LIST_HEAD(&dw->dma.channels); | |
1306 | for (i = 0; i < pdata->nr_channels; i++, dw->dma.chancnt++) { | |
1307 | struct dw_dma_chan *dwc = &dw->chan[i]; | |
1308 | ||
1309 | dwc->chan.device = &dw->dma; | |
1310 | dwc->chan.cookie = dwc->completed = 1; | |
1311 | dwc->chan.chan_id = i; | |
1312 | list_add_tail(&dwc->chan.device_node, &dw->dma.channels); | |
1313 | ||
1314 | dwc->ch_regs = &__dw_regs(dw)->CHAN[i]; | |
1315 | spin_lock_init(&dwc->lock); | |
1316 | dwc->mask = 1 << i; | |
1317 | ||
1318 | INIT_LIST_HEAD(&dwc->active_list); | |
1319 | INIT_LIST_HEAD(&dwc->queue); | |
1320 | INIT_LIST_HEAD(&dwc->free_list); | |
1321 | ||
1322 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
1323 | } | |
1324 | ||
1325 | /* Clear/disable all interrupts on all channels. */ | |
1326 | dma_writel(dw, CLEAR.XFER, dw->all_chan_mask); | |
1327 | dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask); | |
1328 | dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask); | |
1329 | dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask); | |
1330 | dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask); | |
1331 | ||
1332 | channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); | |
1333 | channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); | |
1334 | channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask); | |
1335 | channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask); | |
1336 | channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); | |
1337 | ||
1338 | dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask); | |
1339 | dma_cap_set(DMA_SLAVE, dw->dma.cap_mask); | |
1340 | dw->dma.dev = &pdev->dev; | |
1341 | dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources; | |
1342 | dw->dma.device_free_chan_resources = dwc_free_chan_resources; | |
1343 | ||
1344 | dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy; | |
1345 | ||
1346 | dw->dma.device_prep_slave_sg = dwc_prep_slave_sg; | |
c3635c78 | 1347 | dw->dma.device_control = dwc_control; |
3bfb1d20 HS |
1348 | |
1349 | dw->dma.device_is_tx_complete = dwc_is_tx_complete; | |
1350 | dw->dma.device_issue_pending = dwc_issue_pending; | |
1351 | ||
1352 | dma_writel(dw, CFG, DW_CFG_DMA_EN); | |
1353 | ||
1354 | printk(KERN_INFO "%s: DesignWare DMA Controller, %d channels\n", | |
dfbc9019 | 1355 | dev_name(&pdev->dev), dw->dma.chancnt); |
3bfb1d20 HS |
1356 | |
1357 | dma_async_device_register(&dw->dma); | |
1358 | ||
1359 | return 0; | |
1360 | ||
1361 | err_irq: | |
1362 | clk_disable(dw->clk); | |
1363 | clk_put(dw->clk); | |
1364 | err_clk: | |
1365 | iounmap(dw->regs); | |
1366 | dw->regs = NULL; | |
1367 | err_release_r: | |
1368 | release_resource(io); | |
1369 | err_kfree: | |
1370 | kfree(dw); | |
1371 | return err; | |
1372 | } | |
1373 | ||
1374 | static int __exit dw_remove(struct platform_device *pdev) | |
1375 | { | |
1376 | struct dw_dma *dw = platform_get_drvdata(pdev); | |
1377 | struct dw_dma_chan *dwc, *_dwc; | |
1378 | struct resource *io; | |
1379 | ||
1380 | dw_dma_off(dw); | |
1381 | dma_async_device_unregister(&dw->dma); | |
1382 | ||
1383 | free_irq(platform_get_irq(pdev, 0), dw); | |
1384 | tasklet_kill(&dw->tasklet); | |
1385 | ||
1386 | list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels, | |
1387 | chan.device_node) { | |
1388 | list_del(&dwc->chan.device_node); | |
1389 | channel_clear_bit(dw, CH_EN, dwc->mask); | |
1390 | } | |
1391 | ||
1392 | clk_disable(dw->clk); | |
1393 | clk_put(dw->clk); | |
1394 | ||
1395 | iounmap(dw->regs); | |
1396 | dw->regs = NULL; | |
1397 | ||
1398 | io = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1399 | release_mem_region(io->start, DW_REGLEN); | |
1400 | ||
1401 | kfree(dw); | |
1402 | ||
1403 | return 0; | |
1404 | } | |
1405 | ||
1406 | static void dw_shutdown(struct platform_device *pdev) | |
1407 | { | |
1408 | struct dw_dma *dw = platform_get_drvdata(pdev); | |
1409 | ||
1410 | dw_dma_off(platform_get_drvdata(pdev)); | |
1411 | clk_disable(dw->clk); | |
1412 | } | |
1413 | ||
4a256b5f | 1414 | static int dw_suspend_noirq(struct device *dev) |
3bfb1d20 | 1415 | { |
4a256b5f | 1416 | struct platform_device *pdev = to_platform_device(dev); |
3bfb1d20 HS |
1417 | struct dw_dma *dw = platform_get_drvdata(pdev); |
1418 | ||
1419 | dw_dma_off(platform_get_drvdata(pdev)); | |
1420 | clk_disable(dw->clk); | |
1421 | return 0; | |
1422 | } | |
1423 | ||
4a256b5f | 1424 | static int dw_resume_noirq(struct device *dev) |
3bfb1d20 | 1425 | { |
4a256b5f | 1426 | struct platform_device *pdev = to_platform_device(dev); |
3bfb1d20 HS |
1427 | struct dw_dma *dw = platform_get_drvdata(pdev); |
1428 | ||
1429 | clk_enable(dw->clk); | |
1430 | dma_writel(dw, CFG, DW_CFG_DMA_EN); | |
1431 | return 0; | |
3bfb1d20 HS |
1432 | } |
1433 | ||
47145210 | 1434 | static const struct dev_pm_ops dw_dev_pm_ops = { |
4a256b5f MD |
1435 | .suspend_noirq = dw_suspend_noirq, |
1436 | .resume_noirq = dw_resume_noirq, | |
1437 | }; | |
1438 | ||
3bfb1d20 HS |
1439 | static struct platform_driver dw_driver = { |
1440 | .remove = __exit_p(dw_remove), | |
1441 | .shutdown = dw_shutdown, | |
3bfb1d20 HS |
1442 | .driver = { |
1443 | .name = "dw_dmac", | |
4a256b5f | 1444 | .pm = &dw_dev_pm_ops, |
3bfb1d20 HS |
1445 | }, |
1446 | }; | |
1447 | ||
1448 | static int __init dw_init(void) | |
1449 | { | |
1450 | return platform_driver_probe(&dw_driver, dw_probe); | |
1451 | } | |
1452 | module_init(dw_init); | |
1453 | ||
1454 | static void __exit dw_exit(void) | |
1455 | { | |
1456 | platform_driver_unregister(&dw_driver); | |
1457 | } | |
1458 | module_exit(dw_exit); | |
1459 | ||
1460 | MODULE_LICENSE("GPL v2"); | |
1461 | MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller driver"); | |
1462 | MODULE_AUTHOR("Haavard Skinnemoen <haavard.skinnemoen@atmel.com>"); |