Commit | Line | Data |
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173acc7c ZW |
1 | /* |
2 | * Freescale MPC85xx, MPC83xx DMA Engine support | |
3 | * | |
e2c8e425 | 4 | * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved. |
173acc7c ZW |
5 | * |
6 | * Author: | |
7 | * Zhang Wei <wei.zhang@freescale.com>, Jul 2007 | |
8 | * Ebony Zhu <ebony.zhu@freescale.com>, May 2007 | |
9 | * | |
10 | * Description: | |
11 | * DMA engine driver for Freescale MPC8540 DMA controller, which is | |
12 | * also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc. | |
c2e07b3a | 13 | * The support for MPC8349 DMA controller is also added. |
173acc7c | 14 | * |
a7aea373 IS |
15 | * This driver instructs the DMA controller to issue the PCI Read Multiple |
16 | * command for PCI read operations, instead of using the default PCI Read Line | |
17 | * command. Please be aware that this setting may result in read pre-fetching | |
18 | * on some platforms. | |
19 | * | |
173acc7c ZW |
20 | * This is free software; you can redistribute it and/or modify |
21 | * it under the terms of the GNU General Public License as published by | |
22 | * the Free Software Foundation; either version 2 of the License, or | |
23 | * (at your option) any later version. | |
24 | * | |
25 | */ | |
26 | ||
27 | #include <linux/init.h> | |
28 | #include <linux/module.h> | |
29 | #include <linux/pci.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
173acc7c ZW |
31 | #include <linux/interrupt.h> |
32 | #include <linux/dmaengine.h> | |
33 | #include <linux/delay.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | #include <linux/dmapool.h> | |
5af50730 RH |
36 | #include <linux/of_address.h> |
37 | #include <linux/of_irq.h> | |
173acc7c ZW |
38 | #include <linux/of_platform.h> |
39 | ||
d2ebfb33 | 40 | #include "dmaengine.h" |
173acc7c ZW |
41 | #include "fsldma.h" |
42 | ||
b158471e IS |
43 | #define chan_dbg(chan, fmt, arg...) \ |
44 | dev_dbg(chan->dev, "%s: " fmt, chan->name, ##arg) | |
45 | #define chan_err(chan, fmt, arg...) \ | |
46 | dev_err(chan->dev, "%s: " fmt, chan->name, ##arg) | |
c1433041 | 47 | |
b158471e | 48 | static const char msg_ld_oom[] = "No free memory for link descriptor"; |
173acc7c | 49 | |
e8bd84df IS |
50 | /* |
51 | * Register Helpers | |
52 | */ | |
173acc7c | 53 | |
a1c03319 | 54 | static void set_sr(struct fsldma_chan *chan, u32 val) |
173acc7c | 55 | { |
a1c03319 | 56 | DMA_OUT(chan, &chan->regs->sr, val, 32); |
173acc7c ZW |
57 | } |
58 | ||
a1c03319 | 59 | static u32 get_sr(struct fsldma_chan *chan) |
173acc7c | 60 | { |
a1c03319 | 61 | return DMA_IN(chan, &chan->regs->sr, 32); |
173acc7c ZW |
62 | } |
63 | ||
ccdce9a0 HZ |
64 | static void set_mr(struct fsldma_chan *chan, u32 val) |
65 | { | |
66 | DMA_OUT(chan, &chan->regs->mr, val, 32); | |
67 | } | |
68 | ||
69 | static u32 get_mr(struct fsldma_chan *chan) | |
70 | { | |
71 | return DMA_IN(chan, &chan->regs->mr, 32); | |
72 | } | |
73 | ||
e8bd84df IS |
74 | static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr) |
75 | { | |
76 | DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64); | |
77 | } | |
78 | ||
79 | static dma_addr_t get_cdar(struct fsldma_chan *chan) | |
80 | { | |
81 | return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN; | |
82 | } | |
83 | ||
ccdce9a0 HZ |
84 | static void set_bcr(struct fsldma_chan *chan, u32 val) |
85 | { | |
86 | DMA_OUT(chan, &chan->regs->bcr, val, 32); | |
87 | } | |
88 | ||
e8bd84df IS |
89 | static u32 get_bcr(struct fsldma_chan *chan) |
90 | { | |
91 | return DMA_IN(chan, &chan->regs->bcr, 32); | |
92 | } | |
93 | ||
94 | /* | |
95 | * Descriptor Helpers | |
96 | */ | |
97 | ||
a1c03319 | 98 | static void set_desc_cnt(struct fsldma_chan *chan, |
173acc7c ZW |
99 | struct fsl_dma_ld_hw *hw, u32 count) |
100 | { | |
a1c03319 | 101 | hw->count = CPU_TO_DMA(chan, count, 32); |
173acc7c ZW |
102 | } |
103 | ||
a1c03319 | 104 | static void set_desc_src(struct fsldma_chan *chan, |
31f4306c | 105 | struct fsl_dma_ld_hw *hw, dma_addr_t src) |
173acc7c ZW |
106 | { |
107 | u64 snoop_bits; | |
108 | ||
a1c03319 | 109 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) |
173acc7c | 110 | ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0; |
a1c03319 | 111 | hw->src_addr = CPU_TO_DMA(chan, snoop_bits | src, 64); |
173acc7c ZW |
112 | } |
113 | ||
a1c03319 | 114 | static void set_desc_dst(struct fsldma_chan *chan, |
31f4306c | 115 | struct fsl_dma_ld_hw *hw, dma_addr_t dst) |
173acc7c ZW |
116 | { |
117 | u64 snoop_bits; | |
118 | ||
a1c03319 | 119 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) |
173acc7c | 120 | ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0; |
a1c03319 | 121 | hw->dst_addr = CPU_TO_DMA(chan, snoop_bits | dst, 64); |
173acc7c ZW |
122 | } |
123 | ||
a1c03319 | 124 | static void set_desc_next(struct fsldma_chan *chan, |
31f4306c | 125 | struct fsl_dma_ld_hw *hw, dma_addr_t next) |
173acc7c ZW |
126 | { |
127 | u64 snoop_bits; | |
128 | ||
a1c03319 | 129 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) |
173acc7c | 130 | ? FSL_DMA_SNEN : 0; |
a1c03319 | 131 | hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64); |
173acc7c ZW |
132 | } |
133 | ||
31f4306c | 134 | static void set_ld_eol(struct fsldma_chan *chan, struct fsl_desc_sw *desc) |
173acc7c | 135 | { |
e8bd84df | 136 | u64 snoop_bits; |
173acc7c | 137 | |
e8bd84df IS |
138 | snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) |
139 | ? FSL_DMA_SNEN : 0; | |
173acc7c | 140 | |
e8bd84df IS |
141 | desc->hw.next_ln_addr = CPU_TO_DMA(chan, |
142 | DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL | |
143 | | snoop_bits, 64); | |
173acc7c ZW |
144 | } |
145 | ||
e8bd84df IS |
146 | /* |
147 | * DMA Engine Hardware Control Helpers | |
148 | */ | |
149 | ||
150 | static void dma_init(struct fsldma_chan *chan) | |
f79abb62 | 151 | { |
e8bd84df | 152 | /* Reset the channel */ |
ccdce9a0 | 153 | set_mr(chan, 0); |
e8bd84df IS |
154 | |
155 | switch (chan->feature & FSL_DMA_IP_MASK) { | |
156 | case FSL_DMA_IP_85XX: | |
157 | /* Set the channel to below modes: | |
158 | * EIE - Error interrupt enable | |
e8bd84df IS |
159 | * EOLNIE - End of links interrupt enable |
160 | * BWC - Bandwidth sharing among channels | |
161 | */ | |
ccdce9a0 HZ |
162 | set_mr(chan, FSL_DMA_MR_BWC | FSL_DMA_MR_EIE |
163 | | FSL_DMA_MR_EOLNIE); | |
e8bd84df IS |
164 | break; |
165 | case FSL_DMA_IP_83XX: | |
166 | /* Set the channel to below modes: | |
167 | * EOTIE - End-of-transfer interrupt enable | |
168 | * PRC_RM - PCI read multiple | |
169 | */ | |
ccdce9a0 | 170 | set_mr(chan, FSL_DMA_MR_EOTIE | FSL_DMA_MR_PRC_RM); |
e8bd84df IS |
171 | break; |
172 | } | |
f79abb62 ZW |
173 | } |
174 | ||
a1c03319 | 175 | static int dma_is_idle(struct fsldma_chan *chan) |
173acc7c | 176 | { |
a1c03319 | 177 | u32 sr = get_sr(chan); |
173acc7c ZW |
178 | return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH); |
179 | } | |
180 | ||
f04cd407 IS |
181 | /* |
182 | * Start the DMA controller | |
183 | * | |
184 | * Preconditions: | |
185 | * - the CDAR register must point to the start descriptor | |
186 | * - the MRn[CS] bit must be cleared | |
187 | */ | |
a1c03319 | 188 | static void dma_start(struct fsldma_chan *chan) |
173acc7c | 189 | { |
272ca655 IS |
190 | u32 mode; |
191 | ||
ccdce9a0 | 192 | mode = get_mr(chan); |
272ca655 | 193 | |
f04cd407 | 194 | if (chan->feature & FSL_DMA_CHAN_PAUSE_EXT) { |
ccdce9a0 | 195 | set_bcr(chan, 0); |
f04cd407 IS |
196 | mode |= FSL_DMA_MR_EMP_EN; |
197 | } else { | |
198 | mode &= ~FSL_DMA_MR_EMP_EN; | |
43a1a3ed | 199 | } |
173acc7c | 200 | |
f04cd407 | 201 | if (chan->feature & FSL_DMA_CHAN_START_EXT) { |
272ca655 | 202 | mode |= FSL_DMA_MR_EMS_EN; |
f04cd407 IS |
203 | } else { |
204 | mode &= ~FSL_DMA_MR_EMS_EN; | |
272ca655 | 205 | mode |= FSL_DMA_MR_CS; |
f04cd407 | 206 | } |
173acc7c | 207 | |
ccdce9a0 | 208 | set_mr(chan, mode); |
173acc7c ZW |
209 | } |
210 | ||
a1c03319 | 211 | static void dma_halt(struct fsldma_chan *chan) |
173acc7c | 212 | { |
272ca655 | 213 | u32 mode; |
900325a6 DW |
214 | int i; |
215 | ||
a00ae34a | 216 | /* read the mode register */ |
ccdce9a0 | 217 | mode = get_mr(chan); |
272ca655 | 218 | |
a00ae34a IS |
219 | /* |
220 | * The 85xx controller supports channel abort, which will stop | |
221 | * the current transfer. On 83xx, this bit is the transfer error | |
222 | * mask bit, which should not be changed. | |
223 | */ | |
224 | if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) { | |
225 | mode |= FSL_DMA_MR_CA; | |
ccdce9a0 | 226 | set_mr(chan, mode); |
a00ae34a IS |
227 | |
228 | mode &= ~FSL_DMA_MR_CA; | |
229 | } | |
230 | ||
231 | /* stop the DMA controller */ | |
232 | mode &= ~(FSL_DMA_MR_CS | FSL_DMA_MR_EMS_EN); | |
ccdce9a0 | 233 | set_mr(chan, mode); |
173acc7c | 234 | |
a00ae34a | 235 | /* wait for the DMA controller to become idle */ |
900325a6 | 236 | for (i = 0; i < 100; i++) { |
a1c03319 | 237 | if (dma_is_idle(chan)) |
9c3a50b7 IS |
238 | return; |
239 | ||
173acc7c | 240 | udelay(10); |
900325a6 | 241 | } |
272ca655 | 242 | |
9c3a50b7 | 243 | if (!dma_is_idle(chan)) |
b158471e | 244 | chan_err(chan, "DMA halt timeout!\n"); |
173acc7c ZW |
245 | } |
246 | ||
173acc7c ZW |
247 | /** |
248 | * fsl_chan_set_src_loop_size - Set source address hold transfer size | |
a1c03319 | 249 | * @chan : Freescale DMA channel |
173acc7c ZW |
250 | * @size : Address loop size, 0 for disable loop |
251 | * | |
252 | * The set source address hold transfer size. The source | |
253 | * address hold or loop transfer size is when the DMA transfer | |
254 | * data from source address (SA), if the loop size is 4, the DMA will | |
255 | * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA, | |
256 | * SA + 1 ... and so on. | |
257 | */ | |
a1c03319 | 258 | static void fsl_chan_set_src_loop_size(struct fsldma_chan *chan, int size) |
173acc7c | 259 | { |
272ca655 IS |
260 | u32 mode; |
261 | ||
ccdce9a0 | 262 | mode = get_mr(chan); |
272ca655 | 263 | |
173acc7c ZW |
264 | switch (size) { |
265 | case 0: | |
272ca655 | 266 | mode &= ~FSL_DMA_MR_SAHE; |
173acc7c ZW |
267 | break; |
268 | case 1: | |
269 | case 2: | |
270 | case 4: | |
271 | case 8: | |
272ca655 | 272 | mode |= FSL_DMA_MR_SAHE | (__ilog2(size) << 14); |
173acc7c ZW |
273 | break; |
274 | } | |
272ca655 | 275 | |
ccdce9a0 | 276 | set_mr(chan, mode); |
173acc7c ZW |
277 | } |
278 | ||
279 | /** | |
738f5f7e | 280 | * fsl_chan_set_dst_loop_size - Set destination address hold transfer size |
a1c03319 | 281 | * @chan : Freescale DMA channel |
173acc7c ZW |
282 | * @size : Address loop size, 0 for disable loop |
283 | * | |
284 | * The set destination address hold transfer size. The destination | |
285 | * address hold or loop transfer size is when the DMA transfer | |
286 | * data to destination address (TA), if the loop size is 4, the DMA will | |
287 | * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA, | |
288 | * TA + 1 ... and so on. | |
289 | */ | |
a1c03319 | 290 | static void fsl_chan_set_dst_loop_size(struct fsldma_chan *chan, int size) |
173acc7c | 291 | { |
272ca655 IS |
292 | u32 mode; |
293 | ||
ccdce9a0 | 294 | mode = get_mr(chan); |
272ca655 | 295 | |
173acc7c ZW |
296 | switch (size) { |
297 | case 0: | |
272ca655 | 298 | mode &= ~FSL_DMA_MR_DAHE; |
173acc7c ZW |
299 | break; |
300 | case 1: | |
301 | case 2: | |
302 | case 4: | |
303 | case 8: | |
272ca655 | 304 | mode |= FSL_DMA_MR_DAHE | (__ilog2(size) << 16); |
173acc7c ZW |
305 | break; |
306 | } | |
272ca655 | 307 | |
ccdce9a0 | 308 | set_mr(chan, mode); |
173acc7c ZW |
309 | } |
310 | ||
311 | /** | |
e6c7ecb6 | 312 | * fsl_chan_set_request_count - Set DMA Request Count for external control |
a1c03319 | 313 | * @chan : Freescale DMA channel |
e6c7ecb6 IS |
314 | * @size : Number of bytes to transfer in a single request |
315 | * | |
316 | * The Freescale DMA channel can be controlled by the external signal DREQ#. | |
317 | * The DMA request count is how many bytes are allowed to transfer before | |
318 | * pausing the channel, after which a new assertion of DREQ# resumes channel | |
319 | * operation. | |
173acc7c | 320 | * |
e6c7ecb6 | 321 | * A size of 0 disables external pause control. The maximum size is 1024. |
173acc7c | 322 | */ |
a1c03319 | 323 | static void fsl_chan_set_request_count(struct fsldma_chan *chan, int size) |
173acc7c | 324 | { |
272ca655 IS |
325 | u32 mode; |
326 | ||
e6c7ecb6 | 327 | BUG_ON(size > 1024); |
272ca655 | 328 | |
ccdce9a0 | 329 | mode = get_mr(chan); |
272ca655 IS |
330 | mode |= (__ilog2(size) << 24) & 0x0f000000; |
331 | ||
ccdce9a0 | 332 | set_mr(chan, mode); |
e6c7ecb6 | 333 | } |
173acc7c | 334 | |
e6c7ecb6 IS |
335 | /** |
336 | * fsl_chan_toggle_ext_pause - Toggle channel external pause status | |
a1c03319 | 337 | * @chan : Freescale DMA channel |
e6c7ecb6 IS |
338 | * @enable : 0 is disabled, 1 is enabled. |
339 | * | |
340 | * The Freescale DMA channel can be controlled by the external signal DREQ#. | |
341 | * The DMA Request Count feature should be used in addition to this feature | |
342 | * to set the number of bytes to transfer before pausing the channel. | |
343 | */ | |
a1c03319 | 344 | static void fsl_chan_toggle_ext_pause(struct fsldma_chan *chan, int enable) |
e6c7ecb6 IS |
345 | { |
346 | if (enable) | |
a1c03319 | 347 | chan->feature |= FSL_DMA_CHAN_PAUSE_EXT; |
e6c7ecb6 | 348 | else |
a1c03319 | 349 | chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT; |
173acc7c ZW |
350 | } |
351 | ||
352 | /** | |
353 | * fsl_chan_toggle_ext_start - Toggle channel external start status | |
a1c03319 | 354 | * @chan : Freescale DMA channel |
173acc7c ZW |
355 | * @enable : 0 is disabled, 1 is enabled. |
356 | * | |
357 | * If enable the external start, the channel can be started by an | |
358 | * external DMA start pin. So the dma_start() does not start the | |
359 | * transfer immediately. The DMA channel will wait for the | |
360 | * control pin asserted. | |
361 | */ | |
a1c03319 | 362 | static void fsl_chan_toggle_ext_start(struct fsldma_chan *chan, int enable) |
173acc7c ZW |
363 | { |
364 | if (enable) | |
a1c03319 | 365 | chan->feature |= FSL_DMA_CHAN_START_EXT; |
173acc7c | 366 | else |
a1c03319 | 367 | chan->feature &= ~FSL_DMA_CHAN_START_EXT; |
173acc7c ZW |
368 | } |
369 | ||
31f4306c | 370 | static void append_ld_queue(struct fsldma_chan *chan, struct fsl_desc_sw *desc) |
9c3a50b7 IS |
371 | { |
372 | struct fsl_desc_sw *tail = to_fsl_desc(chan->ld_pending.prev); | |
373 | ||
374 | if (list_empty(&chan->ld_pending)) | |
375 | goto out_splice; | |
376 | ||
377 | /* | |
378 | * Add the hardware descriptor to the chain of hardware descriptors | |
379 | * that already exists in memory. | |
380 | * | |
381 | * This will un-set the EOL bit of the existing transaction, and the | |
382 | * last link in this transaction will become the EOL descriptor. | |
383 | */ | |
384 | set_desc_next(chan, &tail->hw, desc->async_tx.phys); | |
385 | ||
386 | /* | |
387 | * Add the software descriptor and all children to the list | |
388 | * of pending transactions | |
389 | */ | |
390 | out_splice: | |
391 | list_splice_tail_init(&desc->tx_list, &chan->ld_pending); | |
392 | } | |
393 | ||
173acc7c ZW |
394 | static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx) |
395 | { | |
a1c03319 | 396 | struct fsldma_chan *chan = to_fsl_chan(tx->chan); |
eda34234 DW |
397 | struct fsl_desc_sw *desc = tx_to_fsl_desc(tx); |
398 | struct fsl_desc_sw *child; | |
173acc7c | 399 | unsigned long flags; |
bbc76560 | 400 | dma_cookie_t cookie = -EINVAL; |
173acc7c | 401 | |
a1c03319 | 402 | spin_lock_irqsave(&chan->desc_lock, flags); |
173acc7c | 403 | |
9c3a50b7 IS |
404 | /* |
405 | * assign cookies to all of the software descriptors | |
406 | * that make up this transaction | |
407 | */ | |
eda34234 | 408 | list_for_each_entry(child, &desc->tx_list, node) { |
884485e1 | 409 | cookie = dma_cookie_assign(&child->async_tx); |
bcfb7465 IS |
410 | } |
411 | ||
9c3a50b7 | 412 | /* put this transaction onto the tail of the pending queue */ |
a1c03319 | 413 | append_ld_queue(chan, desc); |
173acc7c | 414 | |
a1c03319 | 415 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
173acc7c ZW |
416 | |
417 | return cookie; | |
418 | } | |
419 | ||
86d19a54 HZ |
420 | /** |
421 | * fsl_dma_free_descriptor - Free descriptor from channel's DMA pool. | |
422 | * @chan : Freescale DMA channel | |
423 | * @desc: descriptor to be freed | |
424 | */ | |
425 | static void fsl_dma_free_descriptor(struct fsldma_chan *chan, | |
426 | struct fsl_desc_sw *desc) | |
427 | { | |
428 | list_del(&desc->node); | |
429 | chan_dbg(chan, "LD %p free\n", desc); | |
430 | dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); | |
431 | } | |
432 | ||
173acc7c ZW |
433 | /** |
434 | * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool. | |
a1c03319 | 435 | * @chan : Freescale DMA channel |
173acc7c ZW |
436 | * |
437 | * Return - The descriptor allocated. NULL for failed. | |
438 | */ | |
31f4306c | 439 | static struct fsl_desc_sw *fsl_dma_alloc_descriptor(struct fsldma_chan *chan) |
173acc7c | 440 | { |
9c3a50b7 | 441 | struct fsl_desc_sw *desc; |
173acc7c | 442 | dma_addr_t pdesc; |
9c3a50b7 IS |
443 | |
444 | desc = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &pdesc); | |
445 | if (!desc) { | |
b158471e | 446 | chan_dbg(chan, "out of memory for link descriptor\n"); |
9c3a50b7 | 447 | return NULL; |
173acc7c ZW |
448 | } |
449 | ||
9c3a50b7 IS |
450 | memset(desc, 0, sizeof(*desc)); |
451 | INIT_LIST_HEAD(&desc->tx_list); | |
452 | dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); | |
453 | desc->async_tx.tx_submit = fsl_dma_tx_submit; | |
454 | desc->async_tx.phys = pdesc; | |
455 | ||
0ab09c36 | 456 | chan_dbg(chan, "LD %p allocated\n", desc); |
0ab09c36 | 457 | |
9c3a50b7 | 458 | return desc; |
173acc7c ZW |
459 | } |
460 | ||
2a5ecb79 HZ |
461 | /** |
462 | * fsl_chan_xfer_ld_queue - transfer any pending transactions | |
463 | * @chan : Freescale DMA channel | |
464 | * | |
465 | * HARDWARE STATE: idle | |
466 | * LOCKING: must hold chan->desc_lock | |
467 | */ | |
468 | static void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan) | |
469 | { | |
470 | struct fsl_desc_sw *desc; | |
471 | ||
472 | /* | |
473 | * If the list of pending descriptors is empty, then we | |
474 | * don't need to do any work at all | |
475 | */ | |
476 | if (list_empty(&chan->ld_pending)) { | |
477 | chan_dbg(chan, "no pending LDs\n"); | |
478 | return; | |
479 | } | |
480 | ||
481 | /* | |
482 | * The DMA controller is not idle, which means that the interrupt | |
483 | * handler will start any queued transactions when it runs after | |
484 | * this transaction finishes | |
485 | */ | |
486 | if (!chan->idle) { | |
487 | chan_dbg(chan, "DMA controller still busy\n"); | |
488 | return; | |
489 | } | |
490 | ||
491 | /* | |
492 | * If there are some link descriptors which have not been | |
493 | * transferred, we need to start the controller | |
494 | */ | |
495 | ||
496 | /* | |
497 | * Move all elements from the queue of pending transactions | |
498 | * onto the list of running transactions | |
499 | */ | |
500 | chan_dbg(chan, "idle, starting controller\n"); | |
501 | desc = list_first_entry(&chan->ld_pending, struct fsl_desc_sw, node); | |
502 | list_splice_tail_init(&chan->ld_pending, &chan->ld_running); | |
503 | ||
504 | /* | |
505 | * The 85xx DMA controller doesn't clear the channel start bit | |
506 | * automatically at the end of a transfer. Therefore we must clear | |
507 | * it in software before starting the transfer. | |
508 | */ | |
509 | if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) { | |
510 | u32 mode; | |
511 | ||
512 | mode = get_mr(chan); | |
513 | mode &= ~FSL_DMA_MR_CS; | |
514 | set_mr(chan, mode); | |
515 | } | |
516 | ||
517 | /* | |
518 | * Program the descriptor's address into the DMA controller, | |
519 | * then start the DMA transaction | |
520 | */ | |
521 | set_cdar(chan, desc->async_tx.phys); | |
522 | get_cdar(chan); | |
523 | ||
524 | dma_start(chan); | |
525 | chan->idle = false; | |
526 | } | |
527 | ||
528 | /** | |
529 | * fsldma_cleanup_descriptor - cleanup and free a single link descriptor | |
530 | * @chan: Freescale DMA channel | |
531 | * @desc: descriptor to cleanup and free | |
532 | * | |
533 | * This function is used on a descriptor which has been executed by the DMA | |
534 | * controller. It will run any callbacks, submit any dependencies, and then | |
535 | * free the descriptor. | |
536 | */ | |
537 | static void fsldma_cleanup_descriptor(struct fsldma_chan *chan, | |
538 | struct fsl_desc_sw *desc) | |
539 | { | |
540 | struct dma_async_tx_descriptor *txd = &desc->async_tx; | |
541 | ||
542 | /* Run the link descriptor callback function */ | |
543 | if (txd->callback) { | |
544 | chan_dbg(chan, "LD %p callback\n", desc); | |
545 | txd->callback(txd->callback_param); | |
546 | } | |
547 | ||
548 | /* Run any dependencies */ | |
549 | dma_run_dependencies(txd); | |
550 | ||
551 | dma_descriptor_unmap(txd); | |
552 | chan_dbg(chan, "LD %p free\n", desc); | |
553 | dma_pool_free(chan->desc_pool, desc, txd->phys); | |
554 | } | |
555 | ||
173acc7c ZW |
556 | /** |
557 | * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel. | |
a1c03319 | 558 | * @chan : Freescale DMA channel |
173acc7c ZW |
559 | * |
560 | * This function will create a dma pool for descriptor allocation. | |
561 | * | |
562 | * Return - The number of descriptors allocated. | |
563 | */ | |
a1c03319 | 564 | static int fsl_dma_alloc_chan_resources(struct dma_chan *dchan) |
173acc7c | 565 | { |
a1c03319 | 566 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
77cd62e8 TT |
567 | |
568 | /* Has this channel already been allocated? */ | |
a1c03319 | 569 | if (chan->desc_pool) |
77cd62e8 | 570 | return 1; |
173acc7c | 571 | |
9c3a50b7 IS |
572 | /* |
573 | * We need the descriptor to be aligned to 32bytes | |
173acc7c ZW |
574 | * for meeting FSL DMA specification requirement. |
575 | */ | |
b158471e | 576 | chan->desc_pool = dma_pool_create(chan->name, chan->dev, |
9c3a50b7 IS |
577 | sizeof(struct fsl_desc_sw), |
578 | __alignof__(struct fsl_desc_sw), 0); | |
a1c03319 | 579 | if (!chan->desc_pool) { |
b158471e | 580 | chan_err(chan, "unable to allocate descriptor pool\n"); |
9c3a50b7 | 581 | return -ENOMEM; |
173acc7c ZW |
582 | } |
583 | ||
9c3a50b7 | 584 | /* there is at least one descriptor free to be allocated */ |
173acc7c ZW |
585 | return 1; |
586 | } | |
587 | ||
9c3a50b7 IS |
588 | /** |
589 | * fsldma_free_desc_list - Free all descriptors in a queue | |
590 | * @chan: Freescae DMA channel | |
591 | * @list: the list to free | |
592 | * | |
593 | * LOCKING: must hold chan->desc_lock | |
594 | */ | |
595 | static void fsldma_free_desc_list(struct fsldma_chan *chan, | |
596 | struct list_head *list) | |
597 | { | |
598 | struct fsl_desc_sw *desc, *_desc; | |
599 | ||
86d19a54 HZ |
600 | list_for_each_entry_safe(desc, _desc, list, node) |
601 | fsl_dma_free_descriptor(chan, desc); | |
9c3a50b7 IS |
602 | } |
603 | ||
604 | static void fsldma_free_desc_list_reverse(struct fsldma_chan *chan, | |
605 | struct list_head *list) | |
606 | { | |
607 | struct fsl_desc_sw *desc, *_desc; | |
608 | ||
86d19a54 HZ |
609 | list_for_each_entry_safe_reverse(desc, _desc, list, node) |
610 | fsl_dma_free_descriptor(chan, desc); | |
9c3a50b7 IS |
611 | } |
612 | ||
173acc7c ZW |
613 | /** |
614 | * fsl_dma_free_chan_resources - Free all resources of the channel. | |
a1c03319 | 615 | * @chan : Freescale DMA channel |
173acc7c | 616 | */ |
a1c03319 | 617 | static void fsl_dma_free_chan_resources(struct dma_chan *dchan) |
173acc7c | 618 | { |
a1c03319 | 619 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
173acc7c ZW |
620 | unsigned long flags; |
621 | ||
b158471e | 622 | chan_dbg(chan, "free all channel resources\n"); |
a1c03319 | 623 | spin_lock_irqsave(&chan->desc_lock, flags); |
9c3a50b7 IS |
624 | fsldma_free_desc_list(chan, &chan->ld_pending); |
625 | fsldma_free_desc_list(chan, &chan->ld_running); | |
a1c03319 | 626 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
77cd62e8 | 627 | |
9c3a50b7 | 628 | dma_pool_destroy(chan->desc_pool); |
a1c03319 | 629 | chan->desc_pool = NULL; |
173acc7c ZW |
630 | } |
631 | ||
31f4306c IS |
632 | static struct dma_async_tx_descriptor * |
633 | fsl_dma_prep_memcpy(struct dma_chan *dchan, | |
634 | dma_addr_t dma_dst, dma_addr_t dma_src, | |
173acc7c ZW |
635 | size_t len, unsigned long flags) |
636 | { | |
a1c03319 | 637 | struct fsldma_chan *chan; |
173acc7c ZW |
638 | struct fsl_desc_sw *first = NULL, *prev = NULL, *new; |
639 | size_t copy; | |
173acc7c | 640 | |
a1c03319 | 641 | if (!dchan) |
173acc7c ZW |
642 | return NULL; |
643 | ||
644 | if (!len) | |
645 | return NULL; | |
646 | ||
a1c03319 | 647 | chan = to_fsl_chan(dchan); |
173acc7c ZW |
648 | |
649 | do { | |
650 | ||
651 | /* Allocate the link descriptor from DMA pool */ | |
a1c03319 | 652 | new = fsl_dma_alloc_descriptor(chan); |
173acc7c | 653 | if (!new) { |
b158471e | 654 | chan_err(chan, "%s\n", msg_ld_oom); |
2e077f8e | 655 | goto fail; |
173acc7c | 656 | } |
173acc7c | 657 | |
56822843 | 658 | copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT); |
173acc7c | 659 | |
a1c03319 IS |
660 | set_desc_cnt(chan, &new->hw, copy); |
661 | set_desc_src(chan, &new->hw, dma_src); | |
662 | set_desc_dst(chan, &new->hw, dma_dst); | |
173acc7c ZW |
663 | |
664 | if (!first) | |
665 | first = new; | |
666 | else | |
a1c03319 | 667 | set_desc_next(chan, &prev->hw, new->async_tx.phys); |
173acc7c ZW |
668 | |
669 | new->async_tx.cookie = 0; | |
636bdeaa | 670 | async_tx_ack(&new->async_tx); |
173acc7c ZW |
671 | |
672 | prev = new; | |
673 | len -= copy; | |
674 | dma_src += copy; | |
738f5f7e | 675 | dma_dst += copy; |
173acc7c ZW |
676 | |
677 | /* Insert the link descriptor to the LD ring */ | |
eda34234 | 678 | list_add_tail(&new->node, &first->tx_list); |
173acc7c ZW |
679 | } while (len); |
680 | ||
636bdeaa | 681 | new->async_tx.flags = flags; /* client is in control of this ack */ |
173acc7c ZW |
682 | new->async_tx.cookie = -EBUSY; |
683 | ||
31f4306c | 684 | /* Set End-of-link to the last link descriptor of new list */ |
a1c03319 | 685 | set_ld_eol(chan, new); |
173acc7c | 686 | |
2e077f8e IS |
687 | return &first->async_tx; |
688 | ||
689 | fail: | |
690 | if (!first) | |
691 | return NULL; | |
692 | ||
9c3a50b7 | 693 | fsldma_free_desc_list_reverse(chan, &first->tx_list); |
2e077f8e | 694 | return NULL; |
173acc7c ZW |
695 | } |
696 | ||
c1433041 IS |
697 | static struct dma_async_tx_descriptor *fsl_dma_prep_sg(struct dma_chan *dchan, |
698 | struct scatterlist *dst_sg, unsigned int dst_nents, | |
699 | struct scatterlist *src_sg, unsigned int src_nents, | |
700 | unsigned long flags) | |
701 | { | |
702 | struct fsl_desc_sw *first = NULL, *prev = NULL, *new = NULL; | |
703 | struct fsldma_chan *chan = to_fsl_chan(dchan); | |
704 | size_t dst_avail, src_avail; | |
705 | dma_addr_t dst, src; | |
706 | size_t len; | |
707 | ||
708 | /* basic sanity checks */ | |
709 | if (dst_nents == 0 || src_nents == 0) | |
710 | return NULL; | |
711 | ||
712 | if (dst_sg == NULL || src_sg == NULL) | |
713 | return NULL; | |
714 | ||
715 | /* | |
716 | * TODO: should we check that both scatterlists have the same | |
717 | * TODO: number of bytes in total? Is that really an error? | |
718 | */ | |
719 | ||
720 | /* get prepared for the loop */ | |
721 | dst_avail = sg_dma_len(dst_sg); | |
722 | src_avail = sg_dma_len(src_sg); | |
723 | ||
724 | /* run until we are out of scatterlist entries */ | |
725 | while (true) { | |
726 | ||
727 | /* create the largest transaction possible */ | |
728 | len = min_t(size_t, src_avail, dst_avail); | |
729 | len = min_t(size_t, len, FSL_DMA_BCR_MAX_CNT); | |
730 | if (len == 0) | |
731 | goto fetch; | |
732 | ||
733 | dst = sg_dma_address(dst_sg) + sg_dma_len(dst_sg) - dst_avail; | |
734 | src = sg_dma_address(src_sg) + sg_dma_len(src_sg) - src_avail; | |
735 | ||
736 | /* allocate and populate the descriptor */ | |
737 | new = fsl_dma_alloc_descriptor(chan); | |
738 | if (!new) { | |
b158471e | 739 | chan_err(chan, "%s\n", msg_ld_oom); |
c1433041 IS |
740 | goto fail; |
741 | } | |
c1433041 IS |
742 | |
743 | set_desc_cnt(chan, &new->hw, len); | |
744 | set_desc_src(chan, &new->hw, src); | |
745 | set_desc_dst(chan, &new->hw, dst); | |
746 | ||
747 | if (!first) | |
748 | first = new; | |
749 | else | |
750 | set_desc_next(chan, &prev->hw, new->async_tx.phys); | |
751 | ||
752 | new->async_tx.cookie = 0; | |
753 | async_tx_ack(&new->async_tx); | |
754 | prev = new; | |
755 | ||
756 | /* Insert the link descriptor to the LD ring */ | |
757 | list_add_tail(&new->node, &first->tx_list); | |
758 | ||
759 | /* update metadata */ | |
760 | dst_avail -= len; | |
761 | src_avail -= len; | |
762 | ||
763 | fetch: | |
764 | /* fetch the next dst scatterlist entry */ | |
765 | if (dst_avail == 0) { | |
766 | ||
767 | /* no more entries: we're done */ | |
768 | if (dst_nents == 0) | |
769 | break; | |
770 | ||
771 | /* fetch the next entry: if there are no more: done */ | |
772 | dst_sg = sg_next(dst_sg); | |
773 | if (dst_sg == NULL) | |
774 | break; | |
775 | ||
776 | dst_nents--; | |
777 | dst_avail = sg_dma_len(dst_sg); | |
778 | } | |
779 | ||
780 | /* fetch the next src scatterlist entry */ | |
781 | if (src_avail == 0) { | |
782 | ||
783 | /* no more entries: we're done */ | |
784 | if (src_nents == 0) | |
785 | break; | |
786 | ||
787 | /* fetch the next entry: if there are no more: done */ | |
788 | src_sg = sg_next(src_sg); | |
789 | if (src_sg == NULL) | |
790 | break; | |
791 | ||
792 | src_nents--; | |
793 | src_avail = sg_dma_len(src_sg); | |
794 | } | |
795 | } | |
796 | ||
797 | new->async_tx.flags = flags; /* client is in control of this ack */ | |
798 | new->async_tx.cookie = -EBUSY; | |
799 | ||
800 | /* Set End-of-link to the last link descriptor of new list */ | |
801 | set_ld_eol(chan, new); | |
802 | ||
803 | return &first->async_tx; | |
804 | ||
805 | fail: | |
806 | if (!first) | |
807 | return NULL; | |
808 | ||
809 | fsldma_free_desc_list_reverse(chan, &first->tx_list); | |
810 | return NULL; | |
811 | } | |
812 | ||
bbea0b6e IS |
813 | /** |
814 | * fsl_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction | |
815 | * @chan: DMA channel | |
816 | * @sgl: scatterlist to transfer to/from | |
817 | * @sg_len: number of entries in @scatterlist | |
818 | * @direction: DMA direction | |
819 | * @flags: DMAEngine flags | |
185ecb5f | 820 | * @context: transaction context (ignored) |
bbea0b6e IS |
821 | * |
822 | * Prepare a set of descriptors for a DMA_SLAVE transaction. Following the | |
823 | * DMA_SLAVE API, this gets the device-specific information from the | |
824 | * chan->private variable. | |
825 | */ | |
826 | static struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg( | |
a1c03319 | 827 | struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len, |
185ecb5f AB |
828 | enum dma_transfer_direction direction, unsigned long flags, |
829 | void *context) | |
bbea0b6e | 830 | { |
bbea0b6e | 831 | /* |
968f19ae | 832 | * This operation is not supported on the Freescale DMA controller |
bbea0b6e | 833 | * |
968f19ae IS |
834 | * However, we need to provide the function pointer to allow the |
835 | * device_control() method to work. | |
bbea0b6e | 836 | */ |
bbea0b6e IS |
837 | return NULL; |
838 | } | |
839 | ||
c3635c78 | 840 | static int fsl_dma_device_control(struct dma_chan *dchan, |
05827630 | 841 | enum dma_ctrl_cmd cmd, unsigned long arg) |
bbea0b6e | 842 | { |
968f19ae | 843 | struct dma_slave_config *config; |
a1c03319 | 844 | struct fsldma_chan *chan; |
bbea0b6e | 845 | unsigned long flags; |
968f19ae | 846 | int size; |
c3635c78 | 847 | |
a1c03319 | 848 | if (!dchan) |
c3635c78 | 849 | return -EINVAL; |
bbea0b6e | 850 | |
a1c03319 | 851 | chan = to_fsl_chan(dchan); |
bbea0b6e | 852 | |
968f19ae IS |
853 | switch (cmd) { |
854 | case DMA_TERMINATE_ALL: | |
f04cd407 IS |
855 | spin_lock_irqsave(&chan->desc_lock, flags); |
856 | ||
968f19ae IS |
857 | /* Halt the DMA engine */ |
858 | dma_halt(chan); | |
bbea0b6e | 859 | |
968f19ae IS |
860 | /* Remove and free all of the descriptors in the LD queue */ |
861 | fsldma_free_desc_list(chan, &chan->ld_pending); | |
862 | fsldma_free_desc_list(chan, &chan->ld_running); | |
f04cd407 | 863 | chan->idle = true; |
bbea0b6e | 864 | |
968f19ae IS |
865 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
866 | return 0; | |
867 | ||
868 | case DMA_SLAVE_CONFIG: | |
869 | config = (struct dma_slave_config *)arg; | |
870 | ||
871 | /* make sure the channel supports setting burst size */ | |
872 | if (!chan->set_request_count) | |
873 | return -ENXIO; | |
874 | ||
875 | /* we set the controller burst size depending on direction */ | |
db8196df | 876 | if (config->direction == DMA_MEM_TO_DEV) |
968f19ae IS |
877 | size = config->dst_addr_width * config->dst_maxburst; |
878 | else | |
879 | size = config->src_addr_width * config->src_maxburst; | |
880 | ||
881 | chan->set_request_count(chan, size); | |
882 | return 0; | |
883 | ||
884 | case FSLDMA_EXTERNAL_START: | |
885 | ||
886 | /* make sure the channel supports external start */ | |
887 | if (!chan->toggle_ext_start) | |
888 | return -ENXIO; | |
889 | ||
890 | chan->toggle_ext_start(chan, arg); | |
891 | return 0; | |
892 | ||
893 | default: | |
894 | return -ENXIO; | |
895 | } | |
c3635c78 LW |
896 | |
897 | return 0; | |
bbea0b6e IS |
898 | } |
899 | ||
173acc7c ZW |
900 | /** |
901 | * fsl_dma_memcpy_issue_pending - Issue the DMA start command | |
a1c03319 | 902 | * @chan : Freescale DMA channel |
173acc7c | 903 | */ |
a1c03319 | 904 | static void fsl_dma_memcpy_issue_pending(struct dma_chan *dchan) |
173acc7c | 905 | { |
a1c03319 | 906 | struct fsldma_chan *chan = to_fsl_chan(dchan); |
dc8d4091 IS |
907 | unsigned long flags; |
908 | ||
909 | spin_lock_irqsave(&chan->desc_lock, flags); | |
a1c03319 | 910 | fsl_chan_xfer_ld_queue(chan); |
dc8d4091 | 911 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
173acc7c ZW |
912 | } |
913 | ||
173acc7c | 914 | /** |
07934481 | 915 | * fsl_tx_status - Determine the DMA status |
a1c03319 | 916 | * @chan : Freescale DMA channel |
173acc7c | 917 | */ |
07934481 | 918 | static enum dma_status fsl_tx_status(struct dma_chan *dchan, |
173acc7c | 919 | dma_cookie_t cookie, |
07934481 | 920 | struct dma_tx_state *txstate) |
173acc7c | 921 | { |
9b0b0bdc | 922 | return dma_cookie_status(dchan, cookie, txstate); |
173acc7c ZW |
923 | } |
924 | ||
d3f620b2 IS |
925 | /*----------------------------------------------------------------------------*/ |
926 | /* Interrupt Handling */ | |
927 | /*----------------------------------------------------------------------------*/ | |
928 | ||
e7a29151 | 929 | static irqreturn_t fsldma_chan_irq(int irq, void *data) |
173acc7c | 930 | { |
a1c03319 | 931 | struct fsldma_chan *chan = data; |
a1c03319 | 932 | u32 stat; |
173acc7c | 933 | |
9c3a50b7 | 934 | /* save and clear the status register */ |
a1c03319 | 935 | stat = get_sr(chan); |
9c3a50b7 | 936 | set_sr(chan, stat); |
b158471e | 937 | chan_dbg(chan, "irq: stat = 0x%x\n", stat); |
173acc7c | 938 | |
f04cd407 | 939 | /* check that this was really our device */ |
173acc7c ZW |
940 | stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH); |
941 | if (!stat) | |
942 | return IRQ_NONE; | |
943 | ||
944 | if (stat & FSL_DMA_SR_TE) | |
b158471e | 945 | chan_err(chan, "Transfer Error!\n"); |
173acc7c | 946 | |
9c3a50b7 IS |
947 | /* |
948 | * Programming Error | |
f79abb62 | 949 | * The DMA_INTERRUPT async_tx is a NULL transfer, which will |
d73111c6 | 950 | * trigger a PE interrupt. |
f79abb62 ZW |
951 | */ |
952 | if (stat & FSL_DMA_SR_PE) { | |
b158471e | 953 | chan_dbg(chan, "irq: Programming Error INT\n"); |
f79abb62 | 954 | stat &= ~FSL_DMA_SR_PE; |
f04cd407 IS |
955 | if (get_bcr(chan) != 0) |
956 | chan_err(chan, "Programming Error!\n"); | |
1c62979e ZW |
957 | } |
958 | ||
9c3a50b7 IS |
959 | /* |
960 | * For MPC8349, EOCDI event need to update cookie | |
1c62979e ZW |
961 | * and start the next transfer if it exist. |
962 | */ | |
963 | if (stat & FSL_DMA_SR_EOCDI) { | |
b158471e | 964 | chan_dbg(chan, "irq: End-of-Chain link INT\n"); |
1c62979e | 965 | stat &= ~FSL_DMA_SR_EOCDI; |
173acc7c ZW |
966 | } |
967 | ||
9c3a50b7 IS |
968 | /* |
969 | * If it current transfer is the end-of-transfer, | |
173acc7c ZW |
970 | * we should clear the Channel Start bit for |
971 | * prepare next transfer. | |
972 | */ | |
1c62979e | 973 | if (stat & FSL_DMA_SR_EOLNI) { |
b158471e | 974 | chan_dbg(chan, "irq: End-of-link INT\n"); |
173acc7c | 975 | stat &= ~FSL_DMA_SR_EOLNI; |
173acc7c ZW |
976 | } |
977 | ||
f04cd407 IS |
978 | /* check that the DMA controller is really idle */ |
979 | if (!dma_is_idle(chan)) | |
980 | chan_err(chan, "irq: controller not idle!\n"); | |
981 | ||
982 | /* check that we handled all of the bits */ | |
173acc7c | 983 | if (stat) |
f04cd407 | 984 | chan_err(chan, "irq: unhandled sr 0x%08x\n", stat); |
173acc7c | 985 | |
f04cd407 IS |
986 | /* |
987 | * Schedule the tasklet to handle all cleanup of the current | |
988 | * transaction. It will start a new transaction if there is | |
989 | * one pending. | |
990 | */ | |
a1c03319 | 991 | tasklet_schedule(&chan->tasklet); |
f04cd407 | 992 | chan_dbg(chan, "irq: Exit\n"); |
173acc7c ZW |
993 | return IRQ_HANDLED; |
994 | } | |
995 | ||
d3f620b2 IS |
996 | static void dma_do_tasklet(unsigned long data) |
997 | { | |
a1c03319 | 998 | struct fsldma_chan *chan = (struct fsldma_chan *)data; |
dc8d4091 IS |
999 | struct fsl_desc_sw *desc, *_desc; |
1000 | LIST_HEAD(ld_cleanup); | |
f04cd407 IS |
1001 | unsigned long flags; |
1002 | ||
1003 | chan_dbg(chan, "tasklet entry\n"); | |
1004 | ||
f04cd407 | 1005 | spin_lock_irqsave(&chan->desc_lock, flags); |
dc8d4091 IS |
1006 | |
1007 | /* update the cookie if we have some descriptors to cleanup */ | |
1008 | if (!list_empty(&chan->ld_running)) { | |
1009 | dma_cookie_t cookie; | |
1010 | ||
1011 | desc = to_fsl_desc(chan->ld_running.prev); | |
1012 | cookie = desc->async_tx.cookie; | |
f7fbce07 | 1013 | dma_cookie_complete(&desc->async_tx); |
dc8d4091 | 1014 | |
dc8d4091 IS |
1015 | chan_dbg(chan, "completed_cookie=%d\n", cookie); |
1016 | } | |
1017 | ||
1018 | /* | |
1019 | * move the descriptors to a temporary list so we can drop the lock | |
1020 | * during the entire cleanup operation | |
1021 | */ | |
1022 | list_splice_tail_init(&chan->ld_running, &ld_cleanup); | |
1023 | ||
1024 | /* the hardware is now idle and ready for more */ | |
f04cd407 | 1025 | chan->idle = true; |
f04cd407 | 1026 | |
dc8d4091 IS |
1027 | /* |
1028 | * Start any pending transactions automatically | |
1029 | * | |
1030 | * In the ideal case, we keep the DMA controller busy while we go | |
1031 | * ahead and free the descriptors below. | |
1032 | */ | |
f04cd407 | 1033 | fsl_chan_xfer_ld_queue(chan); |
dc8d4091 IS |
1034 | spin_unlock_irqrestore(&chan->desc_lock, flags); |
1035 | ||
1036 | /* Run the callback for each descriptor, in order */ | |
1037 | list_for_each_entry_safe(desc, _desc, &ld_cleanup, node) { | |
1038 | ||
1039 | /* Remove from the list of transactions */ | |
1040 | list_del(&desc->node); | |
1041 | ||
1042 | /* Run all cleanup for this descriptor */ | |
1043 | fsldma_cleanup_descriptor(chan, desc); | |
1044 | } | |
1045 | ||
f04cd407 | 1046 | chan_dbg(chan, "tasklet exit\n"); |
d3f620b2 IS |
1047 | } |
1048 | ||
1049 | static irqreturn_t fsldma_ctrl_irq(int irq, void *data) | |
173acc7c | 1050 | { |
a4f56d4b | 1051 | struct fsldma_device *fdev = data; |
d3f620b2 IS |
1052 | struct fsldma_chan *chan; |
1053 | unsigned int handled = 0; | |
1054 | u32 gsr, mask; | |
1055 | int i; | |
173acc7c | 1056 | |
e7a29151 | 1057 | gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->regs) |
d3f620b2 IS |
1058 | : in_le32(fdev->regs); |
1059 | mask = 0xff000000; | |
1060 | dev_dbg(fdev->dev, "IRQ: gsr 0x%.8x\n", gsr); | |
173acc7c | 1061 | |
d3f620b2 IS |
1062 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { |
1063 | chan = fdev->chan[i]; | |
1064 | if (!chan) | |
1065 | continue; | |
1066 | ||
1067 | if (gsr & mask) { | |
1068 | dev_dbg(fdev->dev, "IRQ: chan %d\n", chan->id); | |
1069 | fsldma_chan_irq(irq, chan); | |
1070 | handled++; | |
1071 | } | |
1072 | ||
1073 | gsr &= ~mask; | |
1074 | mask >>= 8; | |
1075 | } | |
1076 | ||
1077 | return IRQ_RETVAL(handled); | |
173acc7c ZW |
1078 | } |
1079 | ||
d3f620b2 | 1080 | static void fsldma_free_irqs(struct fsldma_device *fdev) |
173acc7c | 1081 | { |
d3f620b2 IS |
1082 | struct fsldma_chan *chan; |
1083 | int i; | |
1084 | ||
1085 | if (fdev->irq != NO_IRQ) { | |
1086 | dev_dbg(fdev->dev, "free per-controller IRQ\n"); | |
1087 | free_irq(fdev->irq, fdev); | |
1088 | return; | |
1089 | } | |
1090 | ||
1091 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { | |
1092 | chan = fdev->chan[i]; | |
1093 | if (chan && chan->irq != NO_IRQ) { | |
b158471e | 1094 | chan_dbg(chan, "free per-channel IRQ\n"); |
d3f620b2 IS |
1095 | free_irq(chan->irq, chan); |
1096 | } | |
1097 | } | |
1098 | } | |
1099 | ||
1100 | static int fsldma_request_irqs(struct fsldma_device *fdev) | |
1101 | { | |
1102 | struct fsldma_chan *chan; | |
1103 | int ret; | |
1104 | int i; | |
1105 | ||
1106 | /* if we have a per-controller IRQ, use that */ | |
1107 | if (fdev->irq != NO_IRQ) { | |
1108 | dev_dbg(fdev->dev, "request per-controller IRQ\n"); | |
1109 | ret = request_irq(fdev->irq, fsldma_ctrl_irq, IRQF_SHARED, | |
1110 | "fsldma-controller", fdev); | |
1111 | return ret; | |
1112 | } | |
1113 | ||
1114 | /* no per-controller IRQ, use the per-channel IRQs */ | |
1115 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { | |
1116 | chan = fdev->chan[i]; | |
1117 | if (!chan) | |
1118 | continue; | |
1119 | ||
1120 | if (chan->irq == NO_IRQ) { | |
b158471e | 1121 | chan_err(chan, "interrupts property missing in device tree\n"); |
d3f620b2 IS |
1122 | ret = -ENODEV; |
1123 | goto out_unwind; | |
1124 | } | |
1125 | ||
b158471e | 1126 | chan_dbg(chan, "request per-channel IRQ\n"); |
d3f620b2 IS |
1127 | ret = request_irq(chan->irq, fsldma_chan_irq, IRQF_SHARED, |
1128 | "fsldma-chan", chan); | |
1129 | if (ret) { | |
b158471e | 1130 | chan_err(chan, "unable to request per-channel IRQ\n"); |
d3f620b2 IS |
1131 | goto out_unwind; |
1132 | } | |
1133 | } | |
1134 | ||
1135 | return 0; | |
1136 | ||
1137 | out_unwind: | |
1138 | for (/* none */; i >= 0; i--) { | |
1139 | chan = fdev->chan[i]; | |
1140 | if (!chan) | |
1141 | continue; | |
1142 | ||
1143 | if (chan->irq == NO_IRQ) | |
1144 | continue; | |
1145 | ||
1146 | free_irq(chan->irq, chan); | |
1147 | } | |
1148 | ||
1149 | return ret; | |
173acc7c ZW |
1150 | } |
1151 | ||
a4f56d4b IS |
1152 | /*----------------------------------------------------------------------------*/ |
1153 | /* OpenFirmware Subsystem */ | |
1154 | /*----------------------------------------------------------------------------*/ | |
1155 | ||
463a1f8b | 1156 | static int fsl_dma_chan_probe(struct fsldma_device *fdev, |
77cd62e8 | 1157 | struct device_node *node, u32 feature, const char *compatible) |
173acc7c | 1158 | { |
a1c03319 | 1159 | struct fsldma_chan *chan; |
4ce0e953 | 1160 | struct resource res; |
173acc7c ZW |
1161 | int err; |
1162 | ||
173acc7c | 1163 | /* alloc channel */ |
a1c03319 IS |
1164 | chan = kzalloc(sizeof(*chan), GFP_KERNEL); |
1165 | if (!chan) { | |
e7a29151 IS |
1166 | dev_err(fdev->dev, "no free memory for DMA channels!\n"); |
1167 | err = -ENOMEM; | |
1168 | goto out_return; | |
1169 | } | |
1170 | ||
1171 | /* ioremap registers for use */ | |
a1c03319 IS |
1172 | chan->regs = of_iomap(node, 0); |
1173 | if (!chan->regs) { | |
e7a29151 IS |
1174 | dev_err(fdev->dev, "unable to ioremap registers\n"); |
1175 | err = -ENOMEM; | |
a1c03319 | 1176 | goto out_free_chan; |
173acc7c ZW |
1177 | } |
1178 | ||
4ce0e953 | 1179 | err = of_address_to_resource(node, 0, &res); |
173acc7c | 1180 | if (err) { |
e7a29151 IS |
1181 | dev_err(fdev->dev, "unable to find 'reg' property\n"); |
1182 | goto out_iounmap_regs; | |
173acc7c ZW |
1183 | } |
1184 | ||
a1c03319 | 1185 | chan->feature = feature; |
173acc7c | 1186 | if (!fdev->feature) |
a1c03319 | 1187 | fdev->feature = chan->feature; |
173acc7c | 1188 | |
e7a29151 IS |
1189 | /* |
1190 | * If the DMA device's feature is different than the feature | |
1191 | * of its channels, report the bug | |
173acc7c | 1192 | */ |
a1c03319 | 1193 | WARN_ON(fdev->feature != chan->feature); |
e7a29151 | 1194 | |
a1c03319 | 1195 | chan->dev = fdev->dev; |
8de7a7d9 HZ |
1196 | chan->id = (res.start & 0xfff) < 0x300 ? |
1197 | ((res.start - 0x100) & 0xfff) >> 7 : | |
1198 | ((res.start - 0x200) & 0xfff) >> 7; | |
a1c03319 | 1199 | if (chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) { |
e7a29151 | 1200 | dev_err(fdev->dev, "too many channels for device\n"); |
173acc7c | 1201 | err = -EINVAL; |
e7a29151 | 1202 | goto out_iounmap_regs; |
173acc7c | 1203 | } |
173acc7c | 1204 | |
a1c03319 IS |
1205 | fdev->chan[chan->id] = chan; |
1206 | tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan); | |
b158471e | 1207 | snprintf(chan->name, sizeof(chan->name), "chan%d", chan->id); |
e7a29151 IS |
1208 | |
1209 | /* Initialize the channel */ | |
a1c03319 | 1210 | dma_init(chan); |
173acc7c ZW |
1211 | |
1212 | /* Clear cdar registers */ | |
a1c03319 | 1213 | set_cdar(chan, 0); |
173acc7c | 1214 | |
a1c03319 | 1215 | switch (chan->feature & FSL_DMA_IP_MASK) { |
173acc7c | 1216 | case FSL_DMA_IP_85XX: |
a1c03319 | 1217 | chan->toggle_ext_pause = fsl_chan_toggle_ext_pause; |
173acc7c | 1218 | case FSL_DMA_IP_83XX: |
a1c03319 IS |
1219 | chan->toggle_ext_start = fsl_chan_toggle_ext_start; |
1220 | chan->set_src_loop_size = fsl_chan_set_src_loop_size; | |
1221 | chan->set_dst_loop_size = fsl_chan_set_dst_loop_size; | |
1222 | chan->set_request_count = fsl_chan_set_request_count; | |
173acc7c ZW |
1223 | } |
1224 | ||
a1c03319 | 1225 | spin_lock_init(&chan->desc_lock); |
9c3a50b7 IS |
1226 | INIT_LIST_HEAD(&chan->ld_pending); |
1227 | INIT_LIST_HEAD(&chan->ld_running); | |
f04cd407 | 1228 | chan->idle = true; |
173acc7c | 1229 | |
a1c03319 | 1230 | chan->common.device = &fdev->common; |
8ac69546 | 1231 | dma_cookie_init(&chan->common); |
173acc7c | 1232 | |
d3f620b2 | 1233 | /* find the IRQ line, if it exists in the device tree */ |
a1c03319 | 1234 | chan->irq = irq_of_parse_and_map(node, 0); |
d3f620b2 | 1235 | |
173acc7c | 1236 | /* Add the channel to DMA device channel list */ |
a1c03319 | 1237 | list_add_tail(&chan->common.device_node, &fdev->common.channels); |
173acc7c ZW |
1238 | fdev->common.chancnt++; |
1239 | ||
a1c03319 IS |
1240 | dev_info(fdev->dev, "#%d (%s), irq %d\n", chan->id, compatible, |
1241 | chan->irq != NO_IRQ ? chan->irq : fdev->irq); | |
173acc7c ZW |
1242 | |
1243 | return 0; | |
51ee87f2 | 1244 | |
e7a29151 | 1245 | out_iounmap_regs: |
a1c03319 IS |
1246 | iounmap(chan->regs); |
1247 | out_free_chan: | |
1248 | kfree(chan); | |
e7a29151 | 1249 | out_return: |
173acc7c ZW |
1250 | return err; |
1251 | } | |
1252 | ||
a1c03319 | 1253 | static void fsl_dma_chan_remove(struct fsldma_chan *chan) |
173acc7c | 1254 | { |
a1c03319 IS |
1255 | irq_dispose_mapping(chan->irq); |
1256 | list_del(&chan->common.device_node); | |
1257 | iounmap(chan->regs); | |
1258 | kfree(chan); | |
173acc7c ZW |
1259 | } |
1260 | ||
463a1f8b | 1261 | static int fsldma_of_probe(struct platform_device *op) |
173acc7c | 1262 | { |
a4f56d4b | 1263 | struct fsldma_device *fdev; |
77cd62e8 | 1264 | struct device_node *child; |
e7a29151 | 1265 | int err; |
173acc7c | 1266 | |
a4f56d4b | 1267 | fdev = kzalloc(sizeof(*fdev), GFP_KERNEL); |
173acc7c | 1268 | if (!fdev) { |
e7a29151 IS |
1269 | dev_err(&op->dev, "No enough memory for 'priv'\n"); |
1270 | err = -ENOMEM; | |
1271 | goto out_return; | |
173acc7c | 1272 | } |
e7a29151 IS |
1273 | |
1274 | fdev->dev = &op->dev; | |
173acc7c ZW |
1275 | INIT_LIST_HEAD(&fdev->common.channels); |
1276 | ||
e7a29151 | 1277 | /* ioremap the registers for use */ |
61c7a080 | 1278 | fdev->regs = of_iomap(op->dev.of_node, 0); |
e7a29151 IS |
1279 | if (!fdev->regs) { |
1280 | dev_err(&op->dev, "unable to ioremap registers\n"); | |
1281 | err = -ENOMEM; | |
1282 | goto out_free_fdev; | |
173acc7c ZW |
1283 | } |
1284 | ||
d3f620b2 | 1285 | /* map the channel IRQ if it exists, but don't hookup the handler yet */ |
61c7a080 | 1286 | fdev->irq = irq_of_parse_and_map(op->dev.of_node, 0); |
d3f620b2 | 1287 | |
173acc7c | 1288 | dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask); |
c1433041 | 1289 | dma_cap_set(DMA_SG, fdev->common.cap_mask); |
bbea0b6e | 1290 | dma_cap_set(DMA_SLAVE, fdev->common.cap_mask); |
173acc7c ZW |
1291 | fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources; |
1292 | fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources; | |
1293 | fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy; | |
c1433041 | 1294 | fdev->common.device_prep_dma_sg = fsl_dma_prep_sg; |
07934481 | 1295 | fdev->common.device_tx_status = fsl_tx_status; |
173acc7c | 1296 | fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending; |
bbea0b6e | 1297 | fdev->common.device_prep_slave_sg = fsl_dma_prep_slave_sg; |
c3635c78 | 1298 | fdev->common.device_control = fsl_dma_device_control; |
e7a29151 | 1299 | fdev->common.dev = &op->dev; |
173acc7c | 1300 | |
e2c8e425 LY |
1301 | dma_set_mask(&(op->dev), DMA_BIT_MASK(36)); |
1302 | ||
dd3daca1 | 1303 | platform_set_drvdata(op, fdev); |
77cd62e8 | 1304 | |
e7a29151 IS |
1305 | /* |
1306 | * We cannot use of_platform_bus_probe() because there is no | |
1307 | * of_platform_bus_remove(). Instead, we manually instantiate every DMA | |
77cd62e8 TT |
1308 | * channel object. |
1309 | */ | |
61c7a080 | 1310 | for_each_child_of_node(op->dev.of_node, child) { |
e7a29151 | 1311 | if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) { |
77cd62e8 TT |
1312 | fsl_dma_chan_probe(fdev, child, |
1313 | FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN, | |
1314 | "fsl,eloplus-dma-channel"); | |
e7a29151 IS |
1315 | } |
1316 | ||
1317 | if (of_device_is_compatible(child, "fsl,elo-dma-channel")) { | |
77cd62e8 TT |
1318 | fsl_dma_chan_probe(fdev, child, |
1319 | FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN, | |
1320 | "fsl,elo-dma-channel"); | |
e7a29151 | 1321 | } |
77cd62e8 | 1322 | } |
173acc7c | 1323 | |
d3f620b2 IS |
1324 | /* |
1325 | * Hookup the IRQ handler(s) | |
1326 | * | |
1327 | * If we have a per-controller interrupt, we prefer that to the | |
1328 | * per-channel interrupts to reduce the number of shared interrupt | |
1329 | * handlers on the same IRQ line | |
1330 | */ | |
1331 | err = fsldma_request_irqs(fdev); | |
1332 | if (err) { | |
1333 | dev_err(fdev->dev, "unable to request IRQs\n"); | |
1334 | goto out_free_fdev; | |
1335 | } | |
1336 | ||
173acc7c ZW |
1337 | dma_async_device_register(&fdev->common); |
1338 | return 0; | |
1339 | ||
e7a29151 | 1340 | out_free_fdev: |
d3f620b2 | 1341 | irq_dispose_mapping(fdev->irq); |
173acc7c | 1342 | kfree(fdev); |
e7a29151 | 1343 | out_return: |
173acc7c ZW |
1344 | return err; |
1345 | } | |
1346 | ||
2dc11581 | 1347 | static int fsldma_of_remove(struct platform_device *op) |
77cd62e8 | 1348 | { |
a4f56d4b | 1349 | struct fsldma_device *fdev; |
77cd62e8 TT |
1350 | unsigned int i; |
1351 | ||
dd3daca1 | 1352 | fdev = platform_get_drvdata(op); |
77cd62e8 TT |
1353 | dma_async_device_unregister(&fdev->common); |
1354 | ||
d3f620b2 IS |
1355 | fsldma_free_irqs(fdev); |
1356 | ||
e7a29151 | 1357 | for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { |
77cd62e8 TT |
1358 | if (fdev->chan[i]) |
1359 | fsl_dma_chan_remove(fdev->chan[i]); | |
e7a29151 | 1360 | } |
77cd62e8 | 1361 | |
e7a29151 | 1362 | iounmap(fdev->regs); |
77cd62e8 | 1363 | kfree(fdev); |
77cd62e8 TT |
1364 | |
1365 | return 0; | |
1366 | } | |
1367 | ||
4b1cf1fa | 1368 | static const struct of_device_id fsldma_of_ids[] = { |
8de7a7d9 | 1369 | { .compatible = "fsl,elo3-dma", }, |
049c9d45 KG |
1370 | { .compatible = "fsl,eloplus-dma", }, |
1371 | { .compatible = "fsl,elo-dma", }, | |
173acc7c ZW |
1372 | {} |
1373 | }; | |
1374 | ||
8faa7cf8 | 1375 | static struct platform_driver fsldma_of_driver = { |
4018294b GL |
1376 | .driver = { |
1377 | .name = "fsl-elo-dma", | |
1378 | .owner = THIS_MODULE, | |
1379 | .of_match_table = fsldma_of_ids, | |
1380 | }, | |
1381 | .probe = fsldma_of_probe, | |
1382 | .remove = fsldma_of_remove, | |
173acc7c ZW |
1383 | }; |
1384 | ||
a4f56d4b IS |
1385 | /*----------------------------------------------------------------------------*/ |
1386 | /* Module Init / Exit */ | |
1387 | /*----------------------------------------------------------------------------*/ | |
1388 | ||
1389 | static __init int fsldma_init(void) | |
173acc7c | 1390 | { |
8de7a7d9 | 1391 | pr_info("Freescale Elo series DMA driver\n"); |
00006124 | 1392 | return platform_driver_register(&fsldma_of_driver); |
77cd62e8 TT |
1393 | } |
1394 | ||
a4f56d4b | 1395 | static void __exit fsldma_exit(void) |
77cd62e8 | 1396 | { |
00006124 | 1397 | platform_driver_unregister(&fsldma_of_driver); |
173acc7c ZW |
1398 | } |
1399 | ||
a4f56d4b IS |
1400 | subsys_initcall(fsldma_init); |
1401 | module_exit(fsldma_exit); | |
77cd62e8 | 1402 | |
8de7a7d9 | 1403 | MODULE_DESCRIPTION("Freescale Elo series DMA driver"); |
77cd62e8 | 1404 | MODULE_LICENSE("GPL"); |