Commit | Line | Data |
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2b49e0c5 AS |
1 | /* |
2 | * Driver for the High Speed UART DMA | |
3 | * | |
4 | * Copyright (C) 2015 Intel Corporation | |
5 | * | |
6 | * Partially based on the bits found in drivers/tty/serial/mfd.c. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #ifndef __DMA_HSU_H__ | |
14 | #define __DMA_HSU_H__ | |
15 | ||
16 | #include <linux/spinlock.h> | |
17 | #include <linux/dma/hsu.h> | |
18 | ||
19 | #include "../virt-dma.h" | |
20 | ||
21 | #define HSU_CH_SR 0x00 /* channel status */ | |
22 | #define HSU_CH_CR 0x04 /* channel control */ | |
23 | #define HSU_CH_DCR 0x08 /* descriptor control */ | |
24 | #define HSU_CH_BSR 0x10 /* FIFO buffer size */ | |
25 | #define HSU_CH_MTSR 0x14 /* minimum transfer size */ | |
26 | #define HSU_CH_DxSAR(x) (0x20 + 8 * (x)) /* desc start addr */ | |
27 | #define HSU_CH_DxTSR(x) (0x24 + 8 * (x)) /* desc transfer size */ | |
28 | #define HSU_CH_D0SAR 0x20 /* desc 0 start addr */ | |
29 | #define HSU_CH_D0TSR 0x24 /* desc 0 transfer size */ | |
30 | #define HSU_CH_D1SAR 0x28 | |
31 | #define HSU_CH_D1TSR 0x2c | |
32 | #define HSU_CH_D2SAR 0x30 | |
33 | #define HSU_CH_D2TSR 0x34 | |
34 | #define HSU_CH_D3SAR 0x38 | |
35 | #define HSU_CH_D3TSR 0x3c | |
36 | ||
37 | #define HSU_DMA_CHAN_NR_DESC 4 | |
38 | #define HSU_DMA_CHAN_LENGTH 0x40 | |
39 | ||
40 | /* Bits in HSU_CH_SR */ | |
41 | #define HSU_CH_SR_DESCTO(x) BIT(8 + (x)) | |
42 | #define HSU_CH_SR_DESCTO_ANY (BIT(11) | BIT(10) | BIT(9) | BIT(8)) | |
43 | #define HSU_CH_SR_CHE BIT(15) | |
4f4bc0ab AS |
44 | #define HSU_CH_SR_DESCE(x) BIT(16 + (x)) |
45 | #define HSU_CH_SR_DESCE_ANY (BIT(19) | BIT(18) | BIT(17) | BIT(16)) | |
46 | #define HSU_CH_SR_CDESC_ANY (BIT(31) | BIT(30)) | |
2b49e0c5 AS |
47 | |
48 | /* Bits in HSU_CH_CR */ | |
49 | #define HSU_CH_CR_CHA BIT(0) | |
50 | #define HSU_CH_CR_CHD BIT(1) | |
51 | ||
52 | /* Bits in HSU_CH_DCR */ | |
53 | #define HSU_CH_DCR_DESCA(x) BIT(0 + (x)) | |
54 | #define HSU_CH_DCR_CHSOD(x) BIT(8 + (x)) | |
55 | #define HSU_CH_DCR_CHSOTO BIT(14) | |
56 | #define HSU_CH_DCR_CHSOE BIT(15) | |
57 | #define HSU_CH_DCR_CHDI(x) BIT(16 + (x)) | |
58 | #define HSU_CH_DCR_CHEI BIT(23) | |
59 | #define HSU_CH_DCR_CHTOI(x) BIT(24 + (x)) | |
60 | ||
17b3cf42 AS |
61 | /* Bits in HSU_CH_DxTSR */ |
62 | #define HSU_CH_DxTSR_MASK GENMASK(15, 0) | |
63 | #define HSU_CH_DxTSR_TSR(x) ((x) & HSU_CH_DxTSR_MASK) | |
64 | ||
2b49e0c5 AS |
65 | struct hsu_dma_sg { |
66 | dma_addr_t addr; | |
67 | unsigned int len; | |
68 | }; | |
69 | ||
70 | struct hsu_dma_desc { | |
71 | struct virt_dma_desc vdesc; | |
72 | enum dma_transfer_direction direction; | |
73 | struct hsu_dma_sg *sg; | |
74 | unsigned int nents; | |
f0579c8c | 75 | size_t length; |
2b49e0c5 AS |
76 | unsigned int active; |
77 | enum dma_status status; | |
78 | }; | |
79 | ||
80 | static inline struct hsu_dma_desc *to_hsu_dma_desc(struct virt_dma_desc *vdesc) | |
81 | { | |
82 | return container_of(vdesc, struct hsu_dma_desc, vdesc); | |
83 | } | |
84 | ||
85 | struct hsu_dma_chan { | |
86 | struct virt_dma_chan vchan; | |
87 | ||
88 | void __iomem *reg; | |
2b49e0c5 AS |
89 | |
90 | /* hardware configuration */ | |
91 | enum dma_transfer_direction direction; | |
92 | struct dma_slave_config config; | |
93 | ||
94 | struct hsu_dma_desc *desc; | |
95 | }; | |
96 | ||
97 | static inline struct hsu_dma_chan *to_hsu_dma_chan(struct dma_chan *chan) | |
98 | { | |
99 | return container_of(chan, struct hsu_dma_chan, vchan.chan); | |
100 | } | |
101 | ||
102 | static inline u32 hsu_chan_readl(struct hsu_dma_chan *hsuc, int offset) | |
103 | { | |
104 | return readl(hsuc->reg + offset); | |
105 | } | |
106 | ||
107 | static inline void hsu_chan_writel(struct hsu_dma_chan *hsuc, int offset, | |
108 | u32 value) | |
109 | { | |
110 | writel(value, hsuc->reg + offset); | |
111 | } | |
112 | ||
113 | struct hsu_dma { | |
114 | struct dma_device dma; | |
115 | ||
116 | /* channels */ | |
117 | struct hsu_dma_chan *chan; | |
4c97ad99 | 118 | unsigned short nr_channels; |
2b49e0c5 AS |
119 | }; |
120 | ||
121 | static inline struct hsu_dma *to_hsu_dma(struct dma_device *ddev) | |
122 | { | |
123 | return container_of(ddev, struct hsu_dma, dma); | |
124 | } | |
125 | ||
126 | #endif /* __DMA_HSU_H__ */ |