Commit | Line | Data |
---|---|---|
0bbd5f4e | 1 | /* |
43d6e369 | 2 | * Intel I/OAT DMA Linux driver |
85596a19 | 3 | * Copyright(c) 2004 - 2015 Intel Corporation. |
0bbd5f4e CL |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
43d6e369 SN |
6 | * under the terms and conditions of the GNU General Public License, |
7 | * version 2, as published by the Free Software Foundation. | |
0bbd5f4e CL |
8 | * |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
43d6e369 SN |
14 | * The full GNU General Public License is included in this distribution in |
15 | * the file called "COPYING". | |
0bbd5f4e | 16 | * |
0bbd5f4e CL |
17 | */ |
18 | ||
19 | /* | |
20 | * This driver supports an Intel I/OAT DMA engine, which does asynchronous | |
21 | * copy operations. | |
22 | */ | |
23 | ||
24 | #include <linux/init.h> | |
25 | #include <linux/module.h> | |
5a0e3ad6 | 26 | #include <linux/slab.h> |
0bbd5f4e CL |
27 | #include <linux/pci.h> |
28 | #include <linux/interrupt.h> | |
29 | #include <linux/dmaengine.h> | |
30 | #include <linux/delay.h> | |
6b00c92c | 31 | #include <linux/dma-mapping.h> |
09177e85 | 32 | #include <linux/workqueue.h> |
70c71606 | 33 | #include <linux/prefetch.h> |
dd4645eb | 34 | #include <linux/sizes.h> |
584ec227 DW |
35 | #include "dma.h" |
36 | #include "registers.h" | |
37 | #include "hw.h" | |
0bbd5f4e | 38 | |
d2ebfb33 RKAL |
39 | #include "../dmaengine.h" |
40 | ||
3372de58 DJ |
41 | static void ioat_eh(struct ioatdma_chan *ioat_chan); |
42 | ||
3e037454 SN |
43 | /** |
44 | * ioat_dma_do_interrupt - handler used for single vector interrupt mode | |
45 | * @irq: interrupt id | |
46 | * @data: interrupt data | |
47 | */ | |
c0f28ce6 | 48 | irqreturn_t ioat_dma_do_interrupt(int irq, void *data) |
3e037454 SN |
49 | { |
50 | struct ioatdma_device *instance = data; | |
5a976888 | 51 | struct ioatdma_chan *ioat_chan; |
3e037454 SN |
52 | unsigned long attnstatus; |
53 | int bit; | |
54 | u8 intrctrl; | |
55 | ||
56 | intrctrl = readb(instance->reg_base + IOAT_INTRCTRL_OFFSET); | |
57 | ||
58 | if (!(intrctrl & IOAT_INTRCTRL_MASTER_INT_EN)) | |
59 | return IRQ_NONE; | |
60 | ||
61 | if (!(intrctrl & IOAT_INTRCTRL_INT_STATUS)) { | |
62 | writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET); | |
63 | return IRQ_NONE; | |
64 | } | |
65 | ||
66 | attnstatus = readl(instance->reg_base + IOAT_ATTNSTATUS_OFFSET); | |
984b3f57 | 67 | for_each_set_bit(bit, &attnstatus, BITS_PER_LONG) { |
5a976888 DJ |
68 | ioat_chan = ioat_chan_by_index(instance, bit); |
69 | if (test_bit(IOAT_RUN, &ioat_chan->state)) | |
70 | tasklet_schedule(&ioat_chan->cleanup_task); | |
3e037454 SN |
71 | } |
72 | ||
73 | writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET); | |
74 | return IRQ_HANDLED; | |
75 | } | |
76 | ||
77 | /** | |
78 | * ioat_dma_do_interrupt_msix - handler used for vector-per-channel interrupt mode | |
79 | * @irq: interrupt id | |
80 | * @data: interrupt data | |
81 | */ | |
c0f28ce6 | 82 | irqreturn_t ioat_dma_do_interrupt_msix(int irq, void *data) |
3e037454 | 83 | { |
5a976888 | 84 | struct ioatdma_chan *ioat_chan = data; |
3e037454 | 85 | |
5a976888 DJ |
86 | if (test_bit(IOAT_RUN, &ioat_chan->state)) |
87 | tasklet_schedule(&ioat_chan->cleanup_task); | |
3e037454 SN |
88 | |
89 | return IRQ_HANDLED; | |
90 | } | |
91 | ||
5a976888 | 92 | void ioat_stop(struct ioatdma_chan *ioat_chan) |
da87ca4d | 93 | { |
55f878ec DJ |
94 | struct ioatdma_device *ioat_dma = ioat_chan->ioat_dma; |
95 | struct pci_dev *pdev = ioat_dma->pdev; | |
5a976888 | 96 | int chan_id = chan_num(ioat_chan); |
da87ca4d DW |
97 | struct msix_entry *msix; |
98 | ||
99 | /* 1/ stop irq from firing tasklets | |
100 | * 2/ stop the tasklet from re-arming irqs | |
101 | */ | |
5a976888 | 102 | clear_bit(IOAT_RUN, &ioat_chan->state); |
da87ca4d DW |
103 | |
104 | /* flush inflight interrupts */ | |
55f878ec | 105 | switch (ioat_dma->irq_mode) { |
da87ca4d | 106 | case IOAT_MSIX: |
55f878ec | 107 | msix = &ioat_dma->msix_entries[chan_id]; |
da87ca4d DW |
108 | synchronize_irq(msix->vector); |
109 | break; | |
110 | case IOAT_MSI: | |
111 | case IOAT_INTX: | |
112 | synchronize_irq(pdev->irq); | |
113 | break; | |
114 | default: | |
115 | break; | |
116 | } | |
117 | ||
118 | /* flush inflight timers */ | |
5a976888 | 119 | del_timer_sync(&ioat_chan->timer); |
da87ca4d DW |
120 | |
121 | /* flush inflight tasklet runs */ | |
5a976888 | 122 | tasklet_kill(&ioat_chan->cleanup_task); |
da87ca4d DW |
123 | |
124 | /* final cleanup now that everything is quiesced and can't re-arm */ | |
ef97bd0f | 125 | ioat_cleanup_event((unsigned long)&ioat_chan->dma_chan); |
da87ca4d DW |
126 | } |
127 | ||
3372de58 | 128 | static void __ioat_issue_pending(struct ioatdma_chan *ioat_chan) |
885b2010 DJ |
129 | { |
130 | ioat_chan->dmacount += ioat_ring_pending(ioat_chan); | |
131 | ioat_chan->issued = ioat_chan->head; | |
132 | writew(ioat_chan->dmacount, | |
133 | ioat_chan->reg_base + IOAT_CHAN_DMACOUNT_OFFSET); | |
134 | dev_dbg(to_dev(ioat_chan), | |
135 | "%s: head: %#x tail: %#x issued: %#x count: %#x\n", | |
136 | __func__, ioat_chan->head, ioat_chan->tail, | |
137 | ioat_chan->issued, ioat_chan->dmacount); | |
138 | } | |
139 | ||
140 | void ioat_issue_pending(struct dma_chan *c) | |
141 | { | |
142 | struct ioatdma_chan *ioat_chan = to_ioat_chan(c); | |
143 | ||
144 | if (ioat_ring_pending(ioat_chan)) { | |
145 | spin_lock_bh(&ioat_chan->prep_lock); | |
146 | __ioat_issue_pending(ioat_chan); | |
147 | spin_unlock_bh(&ioat_chan->prep_lock); | |
148 | } | |
149 | } | |
150 | ||
151 | /** | |
152 | * ioat_update_pending - log pending descriptors | |
153 | * @ioat: ioat+ channel | |
154 | * | |
155 | * Check if the number of unsubmitted descriptors has exceeded the | |
156 | * watermark. Called with prep_lock held | |
157 | */ | |
158 | static void ioat_update_pending(struct ioatdma_chan *ioat_chan) | |
159 | { | |
160 | if (ioat_ring_pending(ioat_chan) > ioat_pending_level) | |
161 | __ioat_issue_pending(ioat_chan); | |
162 | } | |
163 | ||
164 | static void __ioat_start_null_desc(struct ioatdma_chan *ioat_chan) | |
165 | { | |
166 | struct ioat_ring_ent *desc; | |
167 | struct ioat_dma_descriptor *hw; | |
168 | ||
169 | if (ioat_ring_space(ioat_chan) < 1) { | |
170 | dev_err(to_dev(ioat_chan), | |
171 | "Unable to start null desc - ring full\n"); | |
172 | return; | |
173 | } | |
174 | ||
175 | dev_dbg(to_dev(ioat_chan), | |
176 | "%s: head: %#x tail: %#x issued: %#x\n", | |
177 | __func__, ioat_chan->head, ioat_chan->tail, ioat_chan->issued); | |
178 | desc = ioat_get_ring_ent(ioat_chan, ioat_chan->head); | |
179 | ||
180 | hw = desc->hw; | |
181 | hw->ctl = 0; | |
182 | hw->ctl_f.null = 1; | |
183 | hw->ctl_f.int_en = 1; | |
184 | hw->ctl_f.compl_write = 1; | |
185 | /* set size to non-zero value (channel returns error when size is 0) */ | |
186 | hw->size = NULL_DESC_BUFFER_SIZE; | |
187 | hw->src_addr = 0; | |
188 | hw->dst_addr = 0; | |
189 | async_tx_ack(&desc->txd); | |
190 | ioat_set_chainaddr(ioat_chan, desc->txd.phys); | |
191 | dump_desc_dbg(ioat_chan, desc); | |
192 | /* make sure descriptors are written before we submit */ | |
193 | wmb(); | |
194 | ioat_chan->head += 1; | |
195 | __ioat_issue_pending(ioat_chan); | |
196 | } | |
197 | ||
c0f28ce6 | 198 | void ioat_start_null_desc(struct ioatdma_chan *ioat_chan) |
885b2010 DJ |
199 | { |
200 | spin_lock_bh(&ioat_chan->prep_lock); | |
ad4a7b50 DJ |
201 | if (!test_bit(IOAT_CHAN_DOWN, &ioat_chan->state)) |
202 | __ioat_start_null_desc(ioat_chan); | |
885b2010 DJ |
203 | spin_unlock_bh(&ioat_chan->prep_lock); |
204 | } | |
205 | ||
3372de58 | 206 | static void __ioat_restart_chan(struct ioatdma_chan *ioat_chan) |
885b2010 DJ |
207 | { |
208 | /* set the tail to be re-issued */ | |
209 | ioat_chan->issued = ioat_chan->tail; | |
210 | ioat_chan->dmacount = 0; | |
885b2010 DJ |
211 | mod_timer(&ioat_chan->timer, jiffies + COMPLETION_TIMEOUT); |
212 | ||
213 | dev_dbg(to_dev(ioat_chan), | |
214 | "%s: head: %#x tail: %#x issued: %#x count: %#x\n", | |
215 | __func__, ioat_chan->head, ioat_chan->tail, | |
216 | ioat_chan->issued, ioat_chan->dmacount); | |
217 | ||
218 | if (ioat_ring_pending(ioat_chan)) { | |
219 | struct ioat_ring_ent *desc; | |
220 | ||
221 | desc = ioat_get_ring_ent(ioat_chan, ioat_chan->tail); | |
222 | ioat_set_chainaddr(ioat_chan, desc->txd.phys); | |
223 | __ioat_issue_pending(ioat_chan); | |
224 | } else | |
225 | __ioat_start_null_desc(ioat_chan); | |
226 | } | |
227 | ||
3372de58 | 228 | static int ioat_quiesce(struct ioatdma_chan *ioat_chan, unsigned long tmo) |
885b2010 DJ |
229 | { |
230 | unsigned long end = jiffies + tmo; | |
231 | int err = 0; | |
232 | u32 status; | |
233 | ||
234 | status = ioat_chansts(ioat_chan); | |
235 | if (is_ioat_active(status) || is_ioat_idle(status)) | |
236 | ioat_suspend(ioat_chan); | |
237 | while (is_ioat_active(status) || is_ioat_idle(status)) { | |
238 | if (tmo && time_after(jiffies, end)) { | |
239 | err = -ETIMEDOUT; | |
240 | break; | |
241 | } | |
242 | status = ioat_chansts(ioat_chan); | |
243 | cpu_relax(); | |
244 | } | |
245 | ||
246 | return err; | |
247 | } | |
248 | ||
3372de58 | 249 | static int ioat_reset_sync(struct ioatdma_chan *ioat_chan, unsigned long tmo) |
885b2010 DJ |
250 | { |
251 | unsigned long end = jiffies + tmo; | |
252 | int err = 0; | |
253 | ||
254 | ioat_reset(ioat_chan); | |
255 | while (ioat_reset_pending(ioat_chan)) { | |
256 | if (end && time_after(jiffies, end)) { | |
257 | err = -ETIMEDOUT; | |
258 | break; | |
259 | } | |
260 | cpu_relax(); | |
261 | } | |
262 | ||
263 | return err; | |
264 | } | |
265 | ||
885b2010 | 266 | static dma_cookie_t ioat_tx_submit_unlock(struct dma_async_tx_descriptor *tx) |
5c65cb93 | 267 | __releases(&ioat_chan->prep_lock) |
885b2010 DJ |
268 | { |
269 | struct dma_chan *c = tx->chan; | |
270 | struct ioatdma_chan *ioat_chan = to_ioat_chan(c); | |
271 | dma_cookie_t cookie; | |
272 | ||
273 | cookie = dma_cookie_assign(tx); | |
274 | dev_dbg(to_dev(ioat_chan), "%s: cookie: %d\n", __func__, cookie); | |
275 | ||
276 | if (!test_and_set_bit(IOAT_CHAN_ACTIVE, &ioat_chan->state)) | |
277 | mod_timer(&ioat_chan->timer, jiffies + COMPLETION_TIMEOUT); | |
278 | ||
279 | /* make descriptor updates visible before advancing ioat->head, | |
280 | * this is purposefully not smp_wmb() since we are also | |
281 | * publishing the descriptor updates to a dma device | |
282 | */ | |
283 | wmb(); | |
284 | ||
285 | ioat_chan->head += ioat_chan->produce; | |
286 | ||
287 | ioat_update_pending(ioat_chan); | |
288 | spin_unlock_bh(&ioat_chan->prep_lock); | |
289 | ||
290 | return cookie; | |
291 | } | |
292 | ||
293 | static struct ioat_ring_ent * | |
dd4645eb | 294 | ioat_alloc_ring_ent(struct dma_chan *chan, int idx, gfp_t flags) |
885b2010 DJ |
295 | { |
296 | struct ioat_dma_descriptor *hw; | |
297 | struct ioat_ring_ent *desc; | |
298 | struct ioatdma_device *ioat_dma; | |
dd4645eb DJ |
299 | struct ioatdma_chan *ioat_chan = to_ioat_chan(chan); |
300 | int chunk; | |
885b2010 | 301 | dma_addr_t phys; |
dd4645eb DJ |
302 | u8 *pos; |
303 | off_t offs; | |
885b2010 DJ |
304 | |
305 | ioat_dma = to_ioatdma_device(chan->device); | |
dd4645eb DJ |
306 | |
307 | chunk = idx / IOAT_DESCS_PER_2M; | |
308 | idx &= (IOAT_DESCS_PER_2M - 1); | |
309 | offs = idx * IOAT_DESC_SZ; | |
310 | pos = (u8 *)ioat_chan->descs[chunk].virt + offs; | |
311 | phys = ioat_chan->descs[chunk].hw + offs; | |
312 | hw = (struct ioat_dma_descriptor *)pos; | |
885b2010 DJ |
313 | memset(hw, 0, sizeof(*hw)); |
314 | ||
315 | desc = kmem_cache_zalloc(ioat_cache, flags); | |
dd4645eb | 316 | if (!desc) |
885b2010 | 317 | return NULL; |
885b2010 DJ |
318 | |
319 | dma_async_tx_descriptor_init(&desc->txd, chan); | |
320 | desc->txd.tx_submit = ioat_tx_submit_unlock; | |
321 | desc->hw = hw; | |
322 | desc->txd.phys = phys; | |
323 | return desc; | |
324 | } | |
325 | ||
c0f28ce6 | 326 | void ioat_free_ring_ent(struct ioat_ring_ent *desc, struct dma_chan *chan) |
885b2010 | 327 | { |
885b2010 DJ |
328 | kmem_cache_free(ioat_cache, desc); |
329 | } | |
330 | ||
c0f28ce6 | 331 | struct ioat_ring_ent ** |
885b2010 DJ |
332 | ioat_alloc_ring(struct dma_chan *c, int order, gfp_t flags) |
333 | { | |
dd4645eb | 334 | struct ioatdma_chan *ioat_chan = to_ioat_chan(c); |
885b2010 | 335 | struct ioat_ring_ent **ring; |
dd4645eb DJ |
336 | int total_descs = 1 << order; |
337 | int i, chunks; | |
885b2010 DJ |
338 | |
339 | /* allocate the array to hold the software ring */ | |
dd4645eb | 340 | ring = kcalloc(total_descs, sizeof(*ring), flags); |
885b2010 DJ |
341 | if (!ring) |
342 | return NULL; | |
dd4645eb DJ |
343 | |
344 | ioat_chan->desc_chunks = chunks = (total_descs * IOAT_DESC_SZ) / SZ_2M; | |
345 | ||
346 | for (i = 0; i < chunks; i++) { | |
347 | struct ioat_descs *descs = &ioat_chan->descs[i]; | |
348 | ||
349 | descs->virt = dma_alloc_coherent(to_dev(ioat_chan), | |
350 | SZ_2M, &descs->hw, flags); | |
351 | if (!descs->virt && (i > 0)) { | |
352 | int idx; | |
353 | ||
354 | for (idx = 0; idx < i; idx++) { | |
355 | dma_free_coherent(to_dev(ioat_chan), SZ_2M, | |
356 | descs->virt, descs->hw); | |
357 | descs->virt = NULL; | |
358 | descs->hw = 0; | |
359 | } | |
360 | ||
361 | ioat_chan->desc_chunks = 0; | |
362 | kfree(ring); | |
363 | return NULL; | |
364 | } | |
365 | } | |
366 | ||
367 | for (i = 0; i < total_descs; i++) { | |
368 | ring[i] = ioat_alloc_ring_ent(c, i, flags); | |
885b2010 | 369 | if (!ring[i]) { |
dd4645eb DJ |
370 | int idx; |
371 | ||
885b2010 DJ |
372 | while (i--) |
373 | ioat_free_ring_ent(ring[i], c); | |
dd4645eb DJ |
374 | |
375 | for (idx = 0; idx < ioat_chan->desc_chunks; idx++) { | |
376 | dma_free_coherent(to_dev(ioat_chan), | |
377 | SZ_2M, | |
378 | ioat_chan->descs[idx].virt, | |
379 | ioat_chan->descs[idx].hw); | |
380 | ioat_chan->descs[idx].virt = NULL; | |
381 | ioat_chan->descs[idx].hw = 0; | |
382 | } | |
383 | ||
384 | ioat_chan->desc_chunks = 0; | |
885b2010 DJ |
385 | kfree(ring); |
386 | return NULL; | |
387 | } | |
388 | set_desc_id(ring[i], i); | |
389 | } | |
390 | ||
391 | /* link descs */ | |
dd4645eb | 392 | for (i = 0; i < total_descs-1; i++) { |
885b2010 DJ |
393 | struct ioat_ring_ent *next = ring[i+1]; |
394 | struct ioat_dma_descriptor *hw = ring[i]->hw; | |
395 | ||
396 | hw->next = next->txd.phys; | |
397 | } | |
398 | ring[i]->hw->next = ring[0]->txd.phys; | |
399 | ||
400 | return ring; | |
401 | } | |
402 | ||
885b2010 DJ |
403 | /** |
404 | * ioat_check_space_lock - verify space and grab ring producer lock | |
405 | * @ioat: ioat,3 channel (ring) to operate on | |
406 | * @num_descs: allocation length | |
407 | */ | |
408 | int ioat_check_space_lock(struct ioatdma_chan *ioat_chan, int num_descs) | |
5c65cb93 | 409 | __acquires(&ioat_chan->prep_lock) |
885b2010 | 410 | { |
885b2010 DJ |
411 | spin_lock_bh(&ioat_chan->prep_lock); |
412 | /* never allow the last descriptor to be consumed, we need at | |
413 | * least one free at all times to allow for on-the-fly ring | |
414 | * resizing. | |
415 | */ | |
416 | if (likely(ioat_ring_space(ioat_chan) > num_descs)) { | |
417 | dev_dbg(to_dev(ioat_chan), "%s: num_descs: %d (%x:%x:%x)\n", | |
418 | __func__, num_descs, ioat_chan->head, | |
419 | ioat_chan->tail, ioat_chan->issued); | |
420 | ioat_chan->produce = num_descs; | |
421 | return 0; /* with ioat->prep_lock held */ | |
422 | } | |
885b2010 DJ |
423 | spin_unlock_bh(&ioat_chan->prep_lock); |
424 | ||
885b2010 DJ |
425 | dev_dbg_ratelimited(to_dev(ioat_chan), |
426 | "%s: ring full! num_descs: %d (%x:%x:%x)\n", | |
427 | __func__, num_descs, ioat_chan->head, | |
428 | ioat_chan->tail, ioat_chan->issued); | |
429 | ||
430 | /* progress reclaim in the allocation failure case we may be | |
431 | * called under bh_disabled so we need to trigger the timer | |
432 | * event directly | |
433 | */ | |
434 | if (time_is_before_jiffies(ioat_chan->timer.expires) | |
435 | && timer_pending(&ioat_chan->timer)) { | |
885b2010 | 436 | mod_timer(&ioat_chan->timer, jiffies + COMPLETION_TIMEOUT); |
ef97bd0f | 437 | ioat_timer_event((unsigned long)ioat_chan); |
885b2010 DJ |
438 | } |
439 | ||
440 | return -ENOMEM; | |
441 | } | |
3372de58 DJ |
442 | |
443 | static bool desc_has_ext(struct ioat_ring_ent *desc) | |
444 | { | |
445 | struct ioat_dma_descriptor *hw = desc->hw; | |
446 | ||
447 | if (hw->ctl_f.op == IOAT_OP_XOR || | |
448 | hw->ctl_f.op == IOAT_OP_XOR_VAL) { | |
449 | struct ioat_xor_descriptor *xor = desc->xor; | |
450 | ||
451 | if (src_cnt_to_sw(xor->ctl_f.src_cnt) > 5) | |
452 | return true; | |
453 | } else if (hw->ctl_f.op == IOAT_OP_PQ || | |
454 | hw->ctl_f.op == IOAT_OP_PQ_VAL) { | |
455 | struct ioat_pq_descriptor *pq = desc->pq; | |
456 | ||
457 | if (src_cnt_to_sw(pq->ctl_f.src_cnt) > 3) | |
458 | return true; | |
459 | } | |
460 | ||
461 | return false; | |
462 | } | |
463 | ||
464 | static void | |
465 | ioat_free_sed(struct ioatdma_device *ioat_dma, struct ioat_sed_ent *sed) | |
466 | { | |
467 | if (!sed) | |
468 | return; | |
469 | ||
470 | dma_pool_free(ioat_dma->sed_hw_pool[sed->hw_pool], sed->hw, sed->dma); | |
471 | kmem_cache_free(ioat_sed_cache, sed); | |
472 | } | |
473 | ||
474 | static u64 ioat_get_current_completion(struct ioatdma_chan *ioat_chan) | |
475 | { | |
476 | u64 phys_complete; | |
477 | u64 completion; | |
478 | ||
479 | completion = *ioat_chan->completion; | |
480 | phys_complete = ioat_chansts_to_addr(completion); | |
481 | ||
482 | dev_dbg(to_dev(ioat_chan), "%s: phys_complete: %#llx\n", __func__, | |
483 | (unsigned long long) phys_complete); | |
484 | ||
485 | return phys_complete; | |
486 | } | |
487 | ||
488 | static bool ioat_cleanup_preamble(struct ioatdma_chan *ioat_chan, | |
489 | u64 *phys_complete) | |
490 | { | |
491 | *phys_complete = ioat_get_current_completion(ioat_chan); | |
492 | if (*phys_complete == ioat_chan->last_completion) | |
493 | return false; | |
494 | ||
495 | clear_bit(IOAT_COMPLETION_ACK, &ioat_chan->state); | |
496 | mod_timer(&ioat_chan->timer, jiffies + COMPLETION_TIMEOUT); | |
497 | ||
498 | return true; | |
499 | } | |
500 | ||
501 | static void | |
502 | desc_get_errstat(struct ioatdma_chan *ioat_chan, struct ioat_ring_ent *desc) | |
503 | { | |
504 | struct ioat_dma_descriptor *hw = desc->hw; | |
505 | ||
506 | switch (hw->ctl_f.op) { | |
507 | case IOAT_OP_PQ_VAL: | |
508 | case IOAT_OP_PQ_VAL_16S: | |
509 | { | |
510 | struct ioat_pq_descriptor *pq = desc->pq; | |
511 | ||
512 | /* check if there's error written */ | |
513 | if (!pq->dwbes_f.wbes) | |
514 | return; | |
515 | ||
516 | /* need to set a chanerr var for checking to clear later */ | |
517 | ||
518 | if (pq->dwbes_f.p_val_err) | |
519 | *desc->result |= SUM_CHECK_P_RESULT; | |
520 | ||
521 | if (pq->dwbes_f.q_val_err) | |
522 | *desc->result |= SUM_CHECK_Q_RESULT; | |
523 | ||
524 | return; | |
525 | } | |
526 | default: | |
527 | return; | |
528 | } | |
529 | } | |
530 | ||
531 | /** | |
532 | * __cleanup - reclaim used descriptors | |
533 | * @ioat: channel (ring) to clean | |
534 | */ | |
535 | static void __cleanup(struct ioatdma_chan *ioat_chan, dma_addr_t phys_complete) | |
536 | { | |
537 | struct ioatdma_device *ioat_dma = ioat_chan->ioat_dma; | |
538 | struct ioat_ring_ent *desc; | |
539 | bool seen_current = false; | |
540 | int idx = ioat_chan->tail, i; | |
541 | u16 active; | |
542 | ||
543 | dev_dbg(to_dev(ioat_chan), "%s: head: %#x tail: %#x issued: %#x\n", | |
544 | __func__, ioat_chan->head, ioat_chan->tail, ioat_chan->issued); | |
545 | ||
546 | /* | |
547 | * At restart of the channel, the completion address and the | |
548 | * channel status will be 0 due to starting a new chain. Since | |
549 | * it's new chain and the first descriptor "fails", there is | |
550 | * nothing to clean up. We do not want to reap the entire submitted | |
551 | * chain due to this 0 address value and then BUG. | |
552 | */ | |
553 | if (!phys_complete) | |
554 | return; | |
555 | ||
556 | active = ioat_ring_active(ioat_chan); | |
557 | for (i = 0; i < active && !seen_current; i++) { | |
558 | struct dma_async_tx_descriptor *tx; | |
559 | ||
560 | smp_read_barrier_depends(); | |
561 | prefetch(ioat_get_ring_ent(ioat_chan, idx + i + 1)); | |
562 | desc = ioat_get_ring_ent(ioat_chan, idx + i); | |
563 | dump_desc_dbg(ioat_chan, desc); | |
564 | ||
565 | /* set err stat if we are using dwbes */ | |
566 | if (ioat_dma->cap & IOAT_CAP_DWBES) | |
567 | desc_get_errstat(ioat_chan, desc); | |
568 | ||
569 | tx = &desc->txd; | |
570 | if (tx->cookie) { | |
571 | dma_cookie_complete(tx); | |
572 | dma_descriptor_unmap(tx); | |
573 | if (tx->callback) { | |
574 | tx->callback(tx->callback_param); | |
575 | tx->callback = NULL; | |
576 | } | |
577 | } | |
578 | ||
579 | if (tx->phys == phys_complete) | |
580 | seen_current = true; | |
581 | ||
582 | /* skip extended descriptors */ | |
583 | if (desc_has_ext(desc)) { | |
584 | BUG_ON(i + 1 >= active); | |
585 | i++; | |
586 | } | |
587 | ||
588 | /* cleanup super extended descriptors */ | |
589 | if (desc->sed) { | |
590 | ioat_free_sed(ioat_dma, desc->sed); | |
591 | desc->sed = NULL; | |
592 | } | |
593 | } | |
594 | ||
595 | /* finish all descriptor reads before incrementing tail */ | |
596 | smp_mb(); | |
597 | ioat_chan->tail = idx + i; | |
598 | /* no active descs have written a completion? */ | |
599 | BUG_ON(active && !seen_current); | |
600 | ioat_chan->last_completion = phys_complete; | |
601 | ||
602 | if (active - i == 0) { | |
603 | dev_dbg(to_dev(ioat_chan), "%s: cancel completion timeout\n", | |
604 | __func__); | |
3372de58 DJ |
605 | mod_timer(&ioat_chan->timer, jiffies + IDLE_TIMEOUT); |
606 | } | |
607 | ||
608 | /* 5 microsecond delay per pending descriptor */ | |
609 | writew(min((5 * (active - i)), IOAT_INTRDELAY_MASK), | |
610 | ioat_chan->ioat_dma->reg_base + IOAT_INTRDELAY_OFFSET); | |
611 | } | |
612 | ||
613 | static void ioat_cleanup(struct ioatdma_chan *ioat_chan) | |
614 | { | |
615 | u64 phys_complete; | |
616 | ||
617 | spin_lock_bh(&ioat_chan->cleanup_lock); | |
618 | ||
619 | if (ioat_cleanup_preamble(ioat_chan, &phys_complete)) | |
620 | __cleanup(ioat_chan, phys_complete); | |
621 | ||
622 | if (is_ioat_halted(*ioat_chan->completion)) { | |
623 | u32 chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); | |
624 | ||
625 | if (chanerr & IOAT_CHANERR_HANDLE_MASK) { | |
626 | mod_timer(&ioat_chan->timer, jiffies + IDLE_TIMEOUT); | |
627 | ioat_eh(ioat_chan); | |
628 | } | |
629 | } | |
630 | ||
631 | spin_unlock_bh(&ioat_chan->cleanup_lock); | |
632 | } | |
633 | ||
634 | void ioat_cleanup_event(unsigned long data) | |
635 | { | |
636 | struct ioatdma_chan *ioat_chan = to_ioat_chan((void *)data); | |
637 | ||
638 | ioat_cleanup(ioat_chan); | |
639 | if (!test_bit(IOAT_RUN, &ioat_chan->state)) | |
640 | return; | |
641 | writew(IOAT_CHANCTRL_RUN, ioat_chan->reg_base + IOAT_CHANCTRL_OFFSET); | |
642 | } | |
643 | ||
644 | static void ioat_restart_channel(struct ioatdma_chan *ioat_chan) | |
645 | { | |
646 | u64 phys_complete; | |
647 | ||
648 | ioat_quiesce(ioat_chan, 0); | |
649 | if (ioat_cleanup_preamble(ioat_chan, &phys_complete)) | |
650 | __cleanup(ioat_chan, phys_complete); | |
651 | ||
652 | __ioat_restart_chan(ioat_chan); | |
653 | } | |
654 | ||
655 | static void ioat_eh(struct ioatdma_chan *ioat_chan) | |
656 | { | |
657 | struct pci_dev *pdev = to_pdev(ioat_chan); | |
658 | struct ioat_dma_descriptor *hw; | |
659 | struct dma_async_tx_descriptor *tx; | |
660 | u64 phys_complete; | |
661 | struct ioat_ring_ent *desc; | |
662 | u32 err_handled = 0; | |
663 | u32 chanerr_int; | |
664 | u32 chanerr; | |
665 | ||
666 | /* cleanup so tail points to descriptor that caused the error */ | |
667 | if (ioat_cleanup_preamble(ioat_chan, &phys_complete)) | |
668 | __cleanup(ioat_chan, phys_complete); | |
669 | ||
670 | chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); | |
671 | pci_read_config_dword(pdev, IOAT_PCI_CHANERR_INT_OFFSET, &chanerr_int); | |
672 | ||
673 | dev_dbg(to_dev(ioat_chan), "%s: error = %x:%x\n", | |
674 | __func__, chanerr, chanerr_int); | |
675 | ||
676 | desc = ioat_get_ring_ent(ioat_chan, ioat_chan->tail); | |
677 | hw = desc->hw; | |
678 | dump_desc_dbg(ioat_chan, desc); | |
679 | ||
680 | switch (hw->ctl_f.op) { | |
681 | case IOAT_OP_XOR_VAL: | |
682 | if (chanerr & IOAT_CHANERR_XOR_P_OR_CRC_ERR) { | |
683 | *desc->result |= SUM_CHECK_P_RESULT; | |
684 | err_handled |= IOAT_CHANERR_XOR_P_OR_CRC_ERR; | |
685 | } | |
686 | break; | |
687 | case IOAT_OP_PQ_VAL: | |
688 | case IOAT_OP_PQ_VAL_16S: | |
689 | if (chanerr & IOAT_CHANERR_XOR_P_OR_CRC_ERR) { | |
690 | *desc->result |= SUM_CHECK_P_RESULT; | |
691 | err_handled |= IOAT_CHANERR_XOR_P_OR_CRC_ERR; | |
692 | } | |
693 | if (chanerr & IOAT_CHANERR_XOR_Q_ERR) { | |
694 | *desc->result |= SUM_CHECK_Q_RESULT; | |
695 | err_handled |= IOAT_CHANERR_XOR_Q_ERR; | |
696 | } | |
697 | break; | |
698 | } | |
699 | ||
700 | /* fault on unhandled error or spurious halt */ | |
701 | if (chanerr ^ err_handled || chanerr == 0) { | |
702 | dev_err(to_dev(ioat_chan), "%s: fatal error (%x:%x)\n", | |
703 | __func__, chanerr, err_handled); | |
704 | BUG(); | |
705 | } else { /* cleanup the faulty descriptor */ | |
706 | tx = &desc->txd; | |
707 | if (tx->cookie) { | |
708 | dma_cookie_complete(tx); | |
709 | dma_descriptor_unmap(tx); | |
710 | if (tx->callback) { | |
711 | tx->callback(tx->callback_param); | |
712 | tx->callback = NULL; | |
713 | } | |
714 | } | |
715 | } | |
716 | ||
717 | writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET); | |
718 | pci_write_config_dword(pdev, IOAT_PCI_CHANERR_INT_OFFSET, chanerr_int); | |
719 | ||
720 | /* mark faulting descriptor as complete */ | |
721 | *ioat_chan->completion = desc->txd.phys; | |
722 | ||
723 | spin_lock_bh(&ioat_chan->prep_lock); | |
724 | ioat_restart_channel(ioat_chan); | |
725 | spin_unlock_bh(&ioat_chan->prep_lock); | |
726 | } | |
727 | ||
728 | static void check_active(struct ioatdma_chan *ioat_chan) | |
729 | { | |
730 | if (ioat_ring_active(ioat_chan)) { | |
731 | mod_timer(&ioat_chan->timer, jiffies + COMPLETION_TIMEOUT); | |
732 | return; | |
733 | } | |
734 | ||
735 | if (test_and_clear_bit(IOAT_CHAN_ACTIVE, &ioat_chan->state)) | |
736 | mod_timer(&ioat_chan->timer, jiffies + IDLE_TIMEOUT); | |
3372de58 DJ |
737 | } |
738 | ||
739 | void ioat_timer_event(unsigned long data) | |
740 | { | |
741 | struct ioatdma_chan *ioat_chan = to_ioat_chan((void *)data); | |
742 | dma_addr_t phys_complete; | |
743 | u64 status; | |
744 | ||
745 | status = ioat_chansts(ioat_chan); | |
746 | ||
747 | /* when halted due to errors check for channel | |
748 | * programming errors before advancing the completion state | |
749 | */ | |
750 | if (is_ioat_halted(status)) { | |
751 | u32 chanerr; | |
752 | ||
753 | chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); | |
754 | dev_err(to_dev(ioat_chan), "%s: Channel halted (%x)\n", | |
755 | __func__, chanerr); | |
756 | if (test_bit(IOAT_RUN, &ioat_chan->state)) | |
757 | BUG_ON(is_ioat_bug(chanerr)); | |
758 | else /* we never got off the ground */ | |
759 | return; | |
760 | } | |
761 | ||
8a695db0 DJ |
762 | spin_lock_bh(&ioat_chan->cleanup_lock); |
763 | ||
764 | /* handle the no-actives case */ | |
765 | if (!ioat_ring_active(ioat_chan)) { | |
766 | spin_lock_bh(&ioat_chan->prep_lock); | |
767 | check_active(ioat_chan); | |
768 | spin_unlock_bh(&ioat_chan->prep_lock); | |
769 | spin_unlock_bh(&ioat_chan->cleanup_lock); | |
770 | return; | |
771 | } | |
772 | ||
3372de58 DJ |
773 | /* if we haven't made progress and we have already |
774 | * acknowledged a pending completion once, then be more | |
775 | * forceful with a restart | |
776 | */ | |
3372de58 DJ |
777 | if (ioat_cleanup_preamble(ioat_chan, &phys_complete)) |
778 | __cleanup(ioat_chan, phys_complete); | |
779 | else if (test_bit(IOAT_COMPLETION_ACK, &ioat_chan->state)) { | |
8a695db0 DJ |
780 | u32 chanerr; |
781 | ||
782 | chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); | |
783 | dev_warn(to_dev(ioat_chan), "Restarting channel...\n"); | |
784 | dev_warn(to_dev(ioat_chan), "CHANSTS: %#Lx CHANERR: %#x\n", | |
785 | status, chanerr); | |
786 | dev_warn(to_dev(ioat_chan), "Active descriptors: %d\n", | |
787 | ioat_ring_active(ioat_chan)); | |
788 | ||
3372de58 DJ |
789 | spin_lock_bh(&ioat_chan->prep_lock); |
790 | ioat_restart_channel(ioat_chan); | |
791 | spin_unlock_bh(&ioat_chan->prep_lock); | |
792 | spin_unlock_bh(&ioat_chan->cleanup_lock); | |
793 | return; | |
8a695db0 | 794 | } else |
3372de58 | 795 | set_bit(IOAT_COMPLETION_ACK, &ioat_chan->state); |
3372de58 | 796 | |
8a695db0 | 797 | mod_timer(&ioat_chan->timer, jiffies + COMPLETION_TIMEOUT); |
3372de58 DJ |
798 | spin_unlock_bh(&ioat_chan->cleanup_lock); |
799 | } | |
800 | ||
801 | enum dma_status | |
802 | ioat_tx_status(struct dma_chan *c, dma_cookie_t cookie, | |
803 | struct dma_tx_state *txstate) | |
804 | { | |
805 | struct ioatdma_chan *ioat_chan = to_ioat_chan(c); | |
806 | enum dma_status ret; | |
807 | ||
808 | ret = dma_cookie_status(c, cookie, txstate); | |
809 | if (ret == DMA_COMPLETE) | |
810 | return ret; | |
811 | ||
812 | ioat_cleanup(ioat_chan); | |
813 | ||
814 | return dma_cookie_status(c, cookie, txstate); | |
815 | } | |
816 | ||
3372de58 DJ |
817 | int ioat_reset_hw(struct ioatdma_chan *ioat_chan) |
818 | { | |
819 | /* throw away whatever the channel was doing and get it | |
820 | * initialized, with ioat3 specific workarounds | |
821 | */ | |
822 | struct ioatdma_device *ioat_dma = ioat_chan->ioat_dma; | |
823 | struct pci_dev *pdev = ioat_dma->pdev; | |
824 | u32 chanerr; | |
825 | u16 dev_id; | |
826 | int err; | |
827 | ||
828 | ioat_quiesce(ioat_chan, msecs_to_jiffies(100)); | |
829 | ||
830 | chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET); | |
831 | writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET); | |
832 | ||
833 | if (ioat_dma->version < IOAT_VER_3_3) { | |
834 | /* clear any pending errors */ | |
835 | err = pci_read_config_dword(pdev, | |
836 | IOAT_PCI_CHANERR_INT_OFFSET, &chanerr); | |
837 | if (err) { | |
838 | dev_err(&pdev->dev, | |
839 | "channel error register unreachable\n"); | |
840 | return err; | |
841 | } | |
842 | pci_write_config_dword(pdev, | |
843 | IOAT_PCI_CHANERR_INT_OFFSET, chanerr); | |
844 | ||
845 | /* Clear DMAUNCERRSTS Cfg-Reg Parity Error status bit | |
846 | * (workaround for spurious config parity error after restart) | |
847 | */ | |
848 | pci_read_config_word(pdev, IOAT_PCI_DEVICE_ID_OFFSET, &dev_id); | |
849 | if (dev_id == PCI_DEVICE_ID_INTEL_IOAT_TBG0) { | |
850 | pci_write_config_dword(pdev, | |
851 | IOAT_PCI_DMAUNCERRSTS_OFFSET, | |
852 | 0x10); | |
853 | } | |
854 | } | |
855 | ||
c997e30e DJ |
856 | if (is_bwd_ioat(pdev) && (ioat_dma->irq_mode == IOAT_MSIX)) { |
857 | ioat_dma->msixtba0 = readq(ioat_dma->reg_base + 0x1000); | |
858 | ioat_dma->msixdata0 = readq(ioat_dma->reg_base + 0x1008); | |
859 | ioat_dma->msixpba = readq(ioat_dma->reg_base + 0x1800); | |
860 | } | |
861 | ||
862 | ||
3372de58 | 863 | err = ioat_reset_sync(ioat_chan, msecs_to_jiffies(200)); |
c997e30e DJ |
864 | if (!err) { |
865 | if (is_bwd_ioat(pdev) && (ioat_dma->irq_mode == IOAT_MSIX)) { | |
866 | writeq(ioat_dma->msixtba0, ioat_dma->reg_base + 0x1000); | |
867 | writeq(ioat_dma->msixdata0, ioat_dma->reg_base + 0x1008); | |
868 | writeq(ioat_dma->msixpba, ioat_dma->reg_base + 0x1800); | |
869 | } | |
870 | } | |
3372de58 DJ |
871 | |
872 | if (err) | |
873 | dev_err(&pdev->dev, "Failed to reset: %d\n", err); | |
874 | ||
875 | return err; | |
876 | } |