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5cbafa65 DW |
1 | /* |
2 | * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms of the GNU General Public License as published by the Free | |
6 | * Software Foundation; either version 2 of the License, or (at your option) | |
7 | * any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
5cbafa65 DW |
14 | * The full GNU General Public License is included in this distribution in the |
15 | * file called COPYING. | |
16 | */ | |
17 | #ifndef IOATDMA_V2_H | |
18 | #define IOATDMA_V2_H | |
19 | ||
20 | #include <linux/dmaengine.h> | |
abb12dfd | 21 | #include <linux/circ_buf.h> |
5cbafa65 DW |
22 | #include "dma.h" |
23 | #include "hw.h" | |
24 | ||
25 | ||
26 | extern int ioat_pending_level; | |
bf40a686 | 27 | extern int ioat_ring_alloc_order; |
5cbafa65 DW |
28 | |
29 | /* | |
30 | * workaround for IOAT ver.3.0 null descriptor issue | |
31 | * (channel returns error when size is 0) | |
32 | */ | |
33 | #define NULL_DESC_BUFFER_SIZE 1 | |
34 | ||
35 | #define IOAT_MAX_ORDER 16 | |
36 | #define ioat_get_alloc_order() \ | |
37 | (min(ioat_ring_alloc_order, IOAT_MAX_ORDER)) | |
a309218a DW |
38 | #define ioat_get_max_alloc_order() \ |
39 | (min(ioat_ring_max_alloc_order, IOAT_MAX_ORDER)) | |
5cbafa65 DW |
40 | |
41 | /* struct ioat2_dma_chan - ioat v2 / v3 channel attributes | |
42 | * @base: common ioat channel parameters | |
43 | * @xfercap_log; log2 of channel max transfer length (for fast division) | |
44 | * @head: allocated index | |
45 | * @issued: hardware notification point | |
46 | * @tail: cleanup index | |
5cbafa65 DW |
47 | * @dmacount: identical to 'head' except for occasionally resetting to zero |
48 | * @alloc_order: log2 of the number of allocated descriptors | |
074cc476 | 49 | * @produce: number of descriptors to produce at submit time |
5cbafa65 | 50 | * @ring: software ring buffer implementation of hardware ring |
074cc476 | 51 | * @prep_lock: serializes descriptor preparation (producers) |
5cbafa65 DW |
52 | */ |
53 | struct ioat2_dma_chan { | |
54 | struct ioat_chan_common base; | |
55 | size_t xfercap_log; | |
56 | u16 head; | |
57 | u16 issued; | |
58 | u16 tail; | |
59 | u16 dmacount; | |
60 | u16 alloc_order; | |
074cc476 | 61 | u16 produce; |
5cbafa65 | 62 | struct ioat_ring_ent **ring; |
074cc476 | 63 | spinlock_t prep_lock; |
5cbafa65 DW |
64 | }; |
65 | ||
66 | static inline struct ioat2_dma_chan *to_ioat2_chan(struct dma_chan *c) | |
67 | { | |
68 | struct ioat_chan_common *chan = to_chan_common(c); | |
69 | ||
70 | return container_of(chan, struct ioat2_dma_chan, base); | |
71 | } | |
72 | ||
21b764e0 | 73 | static inline u32 ioat2_ring_size(struct ioat2_dma_chan *ioat) |
5cbafa65 | 74 | { |
abb12dfd | 75 | return 1 << ioat->alloc_order; |
5cbafa65 DW |
76 | } |
77 | ||
78 | /* count of descriptors in flight with the engine */ | |
79 | static inline u16 ioat2_ring_active(struct ioat2_dma_chan *ioat) | |
80 | { | |
abb12dfd | 81 | return CIRC_CNT(ioat->head, ioat->tail, ioat2_ring_size(ioat)); |
5cbafa65 DW |
82 | } |
83 | ||
84 | /* count of descriptors pending submission to hardware */ | |
85 | static inline u16 ioat2_ring_pending(struct ioat2_dma_chan *ioat) | |
86 | { | |
abb12dfd | 87 | return CIRC_CNT(ioat->head, ioat->issued, ioat2_ring_size(ioat)); |
5cbafa65 DW |
88 | } |
89 | ||
21b764e0 | 90 | static inline u32 ioat2_ring_space(struct ioat2_dma_chan *ioat) |
5cbafa65 | 91 | { |
abb12dfd | 92 | return ioat2_ring_size(ioat) - ioat2_ring_active(ioat); |
5cbafa65 DW |
93 | } |
94 | ||
5cbafa65 DW |
95 | static inline u16 ioat2_xferlen_to_descs(struct ioat2_dma_chan *ioat, size_t len) |
96 | { | |
97 | u16 num_descs = len >> ioat->xfercap_log; | |
98 | ||
99 | num_descs += !!(len & ((1 << ioat->xfercap_log) - 1)); | |
100 | return num_descs; | |
101 | } | |
102 | ||
2aec048c DW |
103 | /** |
104 | * struct ioat_ring_ent - wrapper around hardware descriptor | |
105 | * @hw: hardware DMA descriptor (for memcpy) | |
106 | * @fill: hardware fill descriptor | |
107 | * @xor: hardware xor descriptor | |
108 | * @xor_ex: hardware xor extension descriptor | |
109 | * @pq: hardware pq descriptor | |
110 | * @pq_ex: hardware pq extension descriptor | |
111 | * @pqu: hardware pq update descriptor | |
112 | * @raw: hardware raw (un-typed) descriptor | |
113 | * @txd: the generic software descriptor for all engines | |
114 | * @len: total transaction length for unmap | |
b094ad3b | 115 | * @result: asynchronous result of validate operations |
2aec048c DW |
116 | * @id: identifier for debug |
117 | */ | |
118 | ||
5cbafa65 | 119 | struct ioat_ring_ent { |
2aec048c DW |
120 | union { |
121 | struct ioat_dma_descriptor *hw; | |
2aec048c DW |
122 | struct ioat_xor_descriptor *xor; |
123 | struct ioat_xor_ext_descriptor *xor_ex; | |
124 | struct ioat_pq_descriptor *pq; | |
125 | struct ioat_pq_ext_descriptor *pq_ex; | |
126 | struct ioat_pq_update_descriptor *pqu; | |
127 | struct ioat_raw_descriptor *raw; | |
128 | }; | |
5cbafa65 | 129 | size_t len; |
162b96e6 | 130 | struct dma_async_tx_descriptor txd; |
b094ad3b | 131 | enum sum_check_flags *result; |
6df9183a DW |
132 | #ifdef DEBUG |
133 | int id; | |
134 | #endif | |
7727eaa4 | 135 | struct ioat_sed_ent *sed; |
5cbafa65 DW |
136 | }; |
137 | ||
138 | static inline struct ioat_ring_ent * | |
139 | ioat2_get_ring_ent(struct ioat2_dma_chan *ioat, u16 idx) | |
140 | { | |
abb12dfd | 141 | return ioat->ring[idx & (ioat2_ring_size(ioat) - 1)]; |
5cbafa65 DW |
142 | } |
143 | ||
09c8a5b8 DW |
144 | static inline void ioat2_set_chainaddr(struct ioat2_dma_chan *ioat, u64 addr) |
145 | { | |
146 | struct ioat_chan_common *chan = &ioat->base; | |
147 | ||
148 | writel(addr & 0x00000000FFFFFFFF, | |
149 | chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW); | |
150 | writel(addr >> 32, | |
151 | chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH); | |
152 | } | |
153 | ||
4bf27b8b GKH |
154 | int ioat2_dma_probe(struct ioatdma_device *dev, int dca); |
155 | int ioat3_dma_probe(struct ioatdma_device *dev, int dca); | |
4bf27b8b | 156 | struct dca_provider *ioat3_dca_init(struct pci_dev *pdev, void __iomem *iobase); |
074cc476 | 157 | int ioat2_check_space_lock(struct ioat2_dma_chan *ioat, int num_descs); |
bf40a686 DW |
158 | int ioat2_enumerate_channels(struct ioatdma_device *device); |
159 | struct dma_async_tx_descriptor * | |
160 | ioat2_dma_prep_memcpy_lock(struct dma_chan *c, dma_addr_t dma_dest, | |
161 | dma_addr_t dma_src, size_t len, unsigned long flags); | |
162 | void ioat2_issue_pending(struct dma_chan *chan); | |
163 | int ioat2_alloc_chan_resources(struct dma_chan *c); | |
164 | void ioat2_free_chan_resources(struct dma_chan *c); | |
bf40a686 DW |
165 | void __ioat2_restart_chan(struct ioat2_dma_chan *ioat); |
166 | bool reshape_ring(struct ioat2_dma_chan *ioat, int order); | |
b094ad3b | 167 | void __ioat2_issue_pending(struct ioat2_dma_chan *ioat); |
e3232714 | 168 | void ioat2_timer_event(unsigned long data); |
a6d52d70 DW |
169 | int ioat2_quiesce(struct ioat_chan_common *chan, unsigned long tmo); |
170 | int ioat2_reset_sync(struct ioat_chan_common *chan, unsigned long tmo); | |
5669e31c | 171 | extern struct kobj_type ioat2_ktype; |
162b96e6 | 172 | extern struct kmem_cache *ioat2_cache; |
5cbafa65 | 173 | #endif /* IOATDMA_V2_H */ |