Commit | Line | Data |
---|---|---|
c2110923 DW |
1 | /* |
2 | * offload engine driver for the Intel Xscale series of i/o processors | |
3 | * Copyright © 2006, Intel Corporation. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
17 | * | |
18 | */ | |
19 | ||
20 | /* | |
21 | * This driver supports the asynchrounous DMA copy and RAID engines available | |
22 | * on the Intel Xscale(R) family of I/O Processors (IOP 32x, 33x, 134x) | |
23 | */ | |
24 | ||
25 | #include <linux/init.h> | |
26 | #include <linux/module.h> | |
c2110923 DW |
27 | #include <linux/delay.h> |
28 | #include <linux/dma-mapping.h> | |
29 | #include <linux/spinlock.h> | |
30 | #include <linux/interrupt.h> | |
31 | #include <linux/platform_device.h> | |
32 | #include <linux/memory.h> | |
33 | #include <linux/ioport.h> | |
34 | ||
a09e64fb | 35 | #include <mach/adma.h> |
c2110923 DW |
36 | |
37 | #define to_iop_adma_chan(chan) container_of(chan, struct iop_adma_chan, common) | |
38 | #define to_iop_adma_device(dev) \ | |
39 | container_of(dev, struct iop_adma_device, common) | |
40 | #define tx_to_iop_adma_slot(tx) \ | |
41 | container_of(tx, struct iop_adma_desc_slot, async_tx) | |
42 | ||
43 | /** | |
44 | * iop_adma_free_slots - flags descriptor slots for reuse | |
45 | * @slot: Slot to free | |
46 | * Caller must hold &iop_chan->lock while calling this function | |
47 | */ | |
48 | static void iop_adma_free_slots(struct iop_adma_desc_slot *slot) | |
49 | { | |
50 | int stride = slot->slots_per_op; | |
51 | ||
52 | while (stride--) { | |
53 | slot->slots_per_op = 0; | |
54 | slot = list_entry(slot->slot_node.next, | |
55 | struct iop_adma_desc_slot, | |
56 | slot_node); | |
57 | } | |
58 | } | |
59 | ||
60 | static dma_cookie_t | |
61 | iop_adma_run_tx_complete_actions(struct iop_adma_desc_slot *desc, | |
62 | struct iop_adma_chan *iop_chan, dma_cookie_t cookie) | |
63 | { | |
64 | BUG_ON(desc->async_tx.cookie < 0); | |
c2110923 DW |
65 | if (desc->async_tx.cookie > 0) { |
66 | cookie = desc->async_tx.cookie; | |
67 | desc->async_tx.cookie = 0; | |
68 | ||
69 | /* call the callback (must not sleep or submit new | |
70 | * operations to this channel) | |
71 | */ | |
72 | if (desc->async_tx.callback) | |
73 | desc->async_tx.callback( | |
74 | desc->async_tx.callback_param); | |
75 | ||
76 | /* unmap dma addresses | |
77 | * (unmap_single vs unmap_page?) | |
78 | */ | |
79 | if (desc->group_head && desc->unmap_len) { | |
80 | struct iop_adma_desc_slot *unmap = desc->group_head; | |
81 | struct device *dev = | |
82 | &iop_chan->device->pdev->dev; | |
83 | u32 len = unmap->unmap_len; | |
e1d181ef DW |
84 | enum dma_ctrl_flags flags = desc->async_tx.flags; |
85 | u32 src_cnt; | |
86 | dma_addr_t addr; | |
a06d568f | 87 | dma_addr_t dest; |
c2110923 | 88 | |
a06d568f DW |
89 | src_cnt = unmap->unmap_src_cnt; |
90 | dest = iop_desc_get_dest_addr(unmap, iop_chan); | |
e1d181ef | 91 | if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) { |
a06d568f DW |
92 | enum dma_data_direction dir; |
93 | ||
94 | if (src_cnt > 1) /* is xor? */ | |
95 | dir = DMA_BIDIRECTIONAL; | |
96 | else | |
97 | dir = DMA_FROM_DEVICE; | |
98 | ||
99 | dma_unmap_page(dev, dest, len, dir); | |
e1d181ef DW |
100 | } |
101 | ||
102 | if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) { | |
e1d181ef DW |
103 | while (src_cnt--) { |
104 | addr = iop_desc_get_src_addr(unmap, | |
105 | iop_chan, | |
106 | src_cnt); | |
a06d568f DW |
107 | if (addr == dest) |
108 | continue; | |
e1d181ef DW |
109 | dma_unmap_page(dev, addr, len, |
110 | DMA_TO_DEVICE); | |
111 | } | |
c2110923 DW |
112 | } |
113 | desc->group_head = NULL; | |
114 | } | |
115 | } | |
116 | ||
117 | /* run dependent operations */ | |
07f2211e | 118 | dma_run_dependencies(&desc->async_tx); |
c2110923 DW |
119 | |
120 | return cookie; | |
121 | } | |
122 | ||
123 | static int | |
124 | iop_adma_clean_slot(struct iop_adma_desc_slot *desc, | |
125 | struct iop_adma_chan *iop_chan) | |
126 | { | |
127 | /* the client is allowed to attach dependent operations | |
128 | * until 'ack' is set | |
129 | */ | |
636bdeaa | 130 | if (!async_tx_test_ack(&desc->async_tx)) |
c2110923 DW |
131 | return 0; |
132 | ||
133 | /* leave the last descriptor in the chain | |
134 | * so we can append to it | |
135 | */ | |
136 | if (desc->chain_node.next == &iop_chan->chain) | |
137 | return 1; | |
138 | ||
139 | dev_dbg(iop_chan->device->common.dev, | |
140 | "\tfree slot: %d slots_per_op: %d\n", | |
141 | desc->idx, desc->slots_per_op); | |
142 | ||
143 | list_del(&desc->chain_node); | |
144 | iop_adma_free_slots(desc); | |
145 | ||
146 | return 0; | |
147 | } | |
148 | ||
149 | static void __iop_adma_slot_cleanup(struct iop_adma_chan *iop_chan) | |
150 | { | |
151 | struct iop_adma_desc_slot *iter, *_iter, *grp_start = NULL; | |
152 | dma_cookie_t cookie = 0; | |
153 | u32 current_desc = iop_chan_get_current_descriptor(iop_chan); | |
154 | int busy = iop_chan_is_busy(iop_chan); | |
155 | int seen_current = 0, slot_cnt = 0, slots_per_op = 0; | |
156 | ||
3d9b525b | 157 | dev_dbg(iop_chan->device->common.dev, "%s\n", __func__); |
c2110923 DW |
158 | /* free completed slots from the chain starting with |
159 | * the oldest descriptor | |
160 | */ | |
161 | list_for_each_entry_safe(iter, _iter, &iop_chan->chain, | |
162 | chain_node) { | |
163 | pr_debug("\tcookie: %d slot: %d busy: %d " | |
164 | "this_desc: %#x next_desc: %#x ack: %d\n", | |
165 | iter->async_tx.cookie, iter->idx, busy, | |
166 | iter->async_tx.phys, iop_desc_get_next_desc(iter), | |
636bdeaa | 167 | async_tx_test_ack(&iter->async_tx)); |
c2110923 DW |
168 | prefetch(_iter); |
169 | prefetch(&_iter->async_tx); | |
170 | ||
171 | /* do not advance past the current descriptor loaded into the | |
172 | * hardware channel, subsequent descriptors are either in | |
173 | * process or have not been submitted | |
174 | */ | |
175 | if (seen_current) | |
176 | break; | |
177 | ||
178 | /* stop the search if we reach the current descriptor and the | |
179 | * channel is busy, or if it appears that the current descriptor | |
180 | * needs to be re-read (i.e. has been appended to) | |
181 | */ | |
182 | if (iter->async_tx.phys == current_desc) { | |
183 | BUG_ON(seen_current++); | |
184 | if (busy || iop_desc_get_next_desc(iter)) | |
185 | break; | |
186 | } | |
187 | ||
188 | /* detect the start of a group transaction */ | |
189 | if (!slot_cnt && !slots_per_op) { | |
190 | slot_cnt = iter->slot_cnt; | |
191 | slots_per_op = iter->slots_per_op; | |
192 | if (slot_cnt <= slots_per_op) { | |
193 | slot_cnt = 0; | |
194 | slots_per_op = 0; | |
195 | } | |
196 | } | |
197 | ||
198 | if (slot_cnt) { | |
199 | pr_debug("\tgroup++\n"); | |
200 | if (!grp_start) | |
201 | grp_start = iter; | |
202 | slot_cnt -= slots_per_op; | |
203 | } | |
204 | ||
205 | /* all the members of a group are complete */ | |
206 | if (slots_per_op != 0 && slot_cnt == 0) { | |
207 | struct iop_adma_desc_slot *grp_iter, *_grp_iter; | |
208 | int end_of_chain = 0; | |
209 | pr_debug("\tgroup end\n"); | |
210 | ||
211 | /* collect the total results */ | |
212 | if (grp_start->xor_check_result) { | |
213 | u32 zero_sum_result = 0; | |
214 | slot_cnt = grp_start->slot_cnt; | |
215 | grp_iter = grp_start; | |
216 | ||
217 | list_for_each_entry_from(grp_iter, | |
218 | &iop_chan->chain, chain_node) { | |
219 | zero_sum_result |= | |
220 | iop_desc_get_zero_result(grp_iter); | |
221 | pr_debug("\titer%d result: %d\n", | |
222 | grp_iter->idx, zero_sum_result); | |
223 | slot_cnt -= slots_per_op; | |
224 | if (slot_cnt == 0) | |
225 | break; | |
226 | } | |
227 | pr_debug("\tgrp_start->xor_check_result: %p\n", | |
228 | grp_start->xor_check_result); | |
229 | *grp_start->xor_check_result = zero_sum_result; | |
230 | } | |
231 | ||
232 | /* clean up the group */ | |
233 | slot_cnt = grp_start->slot_cnt; | |
234 | grp_iter = grp_start; | |
235 | list_for_each_entry_safe_from(grp_iter, _grp_iter, | |
236 | &iop_chan->chain, chain_node) { | |
237 | cookie = iop_adma_run_tx_complete_actions( | |
238 | grp_iter, iop_chan, cookie); | |
239 | ||
240 | slot_cnt -= slots_per_op; | |
241 | end_of_chain = iop_adma_clean_slot(grp_iter, | |
242 | iop_chan); | |
243 | ||
244 | if (slot_cnt == 0 || end_of_chain) | |
245 | break; | |
246 | } | |
247 | ||
248 | /* the group should be complete at this point */ | |
249 | BUG_ON(slot_cnt); | |
250 | ||
251 | slots_per_op = 0; | |
252 | grp_start = NULL; | |
253 | if (end_of_chain) | |
254 | break; | |
255 | else | |
256 | continue; | |
257 | } else if (slots_per_op) /* wait for group completion */ | |
258 | continue; | |
259 | ||
260 | /* write back zero sum results (single descriptor case) */ | |
261 | if (iter->xor_check_result && iter->async_tx.cookie) | |
262 | *iter->xor_check_result = | |
263 | iop_desc_get_zero_result(iter); | |
264 | ||
265 | cookie = iop_adma_run_tx_complete_actions( | |
266 | iter, iop_chan, cookie); | |
267 | ||
268 | if (iop_adma_clean_slot(iter, iop_chan)) | |
269 | break; | |
270 | } | |
271 | ||
272 | BUG_ON(!seen_current); | |
273 | ||
c2110923 DW |
274 | if (cookie > 0) { |
275 | iop_chan->completed_cookie = cookie; | |
276 | pr_debug("\tcompleted cookie %d\n", cookie); | |
277 | } | |
278 | } | |
279 | ||
280 | static void | |
281 | iop_adma_slot_cleanup(struct iop_adma_chan *iop_chan) | |
282 | { | |
283 | spin_lock_bh(&iop_chan->lock); | |
284 | __iop_adma_slot_cleanup(iop_chan); | |
285 | spin_unlock_bh(&iop_chan->lock); | |
286 | } | |
287 | ||
288 | static void iop_adma_tasklet(unsigned long data) | |
289 | { | |
19242d72 DW |
290 | struct iop_adma_chan *iop_chan = (struct iop_adma_chan *) data; |
291 | ||
292 | spin_lock(&iop_chan->lock); | |
293 | __iop_adma_slot_cleanup(iop_chan); | |
294 | spin_unlock(&iop_chan->lock); | |
c2110923 DW |
295 | } |
296 | ||
297 | static struct iop_adma_desc_slot * | |
298 | iop_adma_alloc_slots(struct iop_adma_chan *iop_chan, int num_slots, | |
299 | int slots_per_op) | |
300 | { | |
301 | struct iop_adma_desc_slot *iter, *_iter, *alloc_start = NULL; | |
e73ef9ac | 302 | LIST_HEAD(chain); |
c2110923 DW |
303 | int slots_found, retry = 0; |
304 | ||
305 | /* start search from the last allocated descrtiptor | |
306 | * if a contiguous allocation can not be found start searching | |
307 | * from the beginning of the list | |
308 | */ | |
309 | retry: | |
310 | slots_found = 0; | |
311 | if (retry == 0) | |
312 | iter = iop_chan->last_used; | |
313 | else | |
314 | iter = list_entry(&iop_chan->all_slots, | |
315 | struct iop_adma_desc_slot, | |
316 | slot_node); | |
317 | ||
318 | list_for_each_entry_safe_continue( | |
319 | iter, _iter, &iop_chan->all_slots, slot_node) { | |
320 | prefetch(_iter); | |
321 | prefetch(&_iter->async_tx); | |
322 | if (iter->slots_per_op) { | |
323 | /* give up after finding the first busy slot | |
324 | * on the second pass through the list | |
325 | */ | |
326 | if (retry) | |
327 | break; | |
328 | ||
329 | slots_found = 0; | |
330 | continue; | |
331 | } | |
332 | ||
333 | /* start the allocation if the slot is correctly aligned */ | |
334 | if (!slots_found++) { | |
335 | if (iop_desc_is_aligned(iter, slots_per_op)) | |
336 | alloc_start = iter; | |
337 | else { | |
338 | slots_found = 0; | |
339 | continue; | |
340 | } | |
341 | } | |
342 | ||
343 | if (slots_found == num_slots) { | |
344 | struct iop_adma_desc_slot *alloc_tail = NULL; | |
345 | struct iop_adma_desc_slot *last_used = NULL; | |
346 | iter = alloc_start; | |
347 | while (num_slots) { | |
348 | int i; | |
349 | dev_dbg(iop_chan->device->common.dev, | |
350 | "allocated slot: %d " | |
351 | "(desc %p phys: %#x) slots_per_op %d\n", | |
352 | iter->idx, iter->hw_desc, | |
353 | iter->async_tx.phys, slots_per_op); | |
354 | ||
355 | /* pre-ack all but the last descriptor */ | |
356 | if (num_slots != slots_per_op) | |
636bdeaa | 357 | async_tx_ack(&iter->async_tx); |
c2110923 DW |
358 | |
359 | list_add_tail(&iter->chain_node, &chain); | |
360 | alloc_tail = iter; | |
361 | iter->async_tx.cookie = 0; | |
362 | iter->slot_cnt = num_slots; | |
363 | iter->xor_check_result = NULL; | |
364 | for (i = 0; i < slots_per_op; i++) { | |
365 | iter->slots_per_op = slots_per_op - i; | |
366 | last_used = iter; | |
367 | iter = list_entry(iter->slot_node.next, | |
368 | struct iop_adma_desc_slot, | |
369 | slot_node); | |
370 | } | |
371 | num_slots -= slots_per_op; | |
372 | } | |
373 | alloc_tail->group_head = alloc_start; | |
374 | alloc_tail->async_tx.cookie = -EBUSY; | |
375 | list_splice(&chain, &alloc_tail->async_tx.tx_list); | |
376 | iop_chan->last_used = last_used; | |
377 | iop_desc_clear_next_desc(alloc_start); | |
378 | iop_desc_clear_next_desc(alloc_tail); | |
379 | return alloc_tail; | |
380 | } | |
381 | } | |
382 | if (!retry++) | |
383 | goto retry; | |
384 | ||
c7141d00 DW |
385 | /* perform direct reclaim if the allocation fails */ |
386 | __iop_adma_slot_cleanup(iop_chan); | |
c2110923 DW |
387 | |
388 | return NULL; | |
389 | } | |
390 | ||
391 | static dma_cookie_t | |
392 | iop_desc_assign_cookie(struct iop_adma_chan *iop_chan, | |
393 | struct iop_adma_desc_slot *desc) | |
394 | { | |
395 | dma_cookie_t cookie = iop_chan->common.cookie; | |
396 | cookie++; | |
397 | if (cookie < 0) | |
398 | cookie = 1; | |
399 | iop_chan->common.cookie = desc->async_tx.cookie = cookie; | |
400 | return cookie; | |
401 | } | |
402 | ||
403 | static void iop_adma_check_threshold(struct iop_adma_chan *iop_chan) | |
404 | { | |
405 | dev_dbg(iop_chan->device->common.dev, "pending: %d\n", | |
406 | iop_chan->pending); | |
407 | ||
408 | if (iop_chan->pending >= IOP_ADMA_THRESHOLD) { | |
409 | iop_chan->pending = 0; | |
410 | iop_chan_append(iop_chan); | |
411 | } | |
412 | } | |
413 | ||
414 | static dma_cookie_t | |
415 | iop_adma_tx_submit(struct dma_async_tx_descriptor *tx) | |
416 | { | |
417 | struct iop_adma_desc_slot *sw_desc = tx_to_iop_adma_slot(tx); | |
418 | struct iop_adma_chan *iop_chan = to_iop_adma_chan(tx->chan); | |
419 | struct iop_adma_desc_slot *grp_start, *old_chain_tail; | |
420 | int slot_cnt; | |
421 | int slots_per_op; | |
422 | dma_cookie_t cookie; | |
137cb55c | 423 | dma_addr_t next_dma; |
c2110923 DW |
424 | |
425 | grp_start = sw_desc->group_head; | |
426 | slot_cnt = grp_start->slot_cnt; | |
427 | slots_per_op = grp_start->slots_per_op; | |
428 | ||
429 | spin_lock_bh(&iop_chan->lock); | |
430 | cookie = iop_desc_assign_cookie(iop_chan, sw_desc); | |
431 | ||
432 | old_chain_tail = list_entry(iop_chan->chain.prev, | |
433 | struct iop_adma_desc_slot, chain_node); | |
434 | list_splice_init(&sw_desc->async_tx.tx_list, | |
435 | &old_chain_tail->chain_node); | |
436 | ||
437 | /* fix up the hardware chain */ | |
137cb55c DW |
438 | next_dma = grp_start->async_tx.phys; |
439 | iop_desc_set_next_desc(old_chain_tail, next_dma); | |
440 | BUG_ON(iop_desc_get_next_desc(old_chain_tail) != next_dma); /* flush */ | |
c2110923 | 441 | |
137cb55c | 442 | /* check for pre-chained descriptors */ |
65e50381 | 443 | iop_paranoia(iop_desc_get_next_desc(sw_desc)); |
c2110923 DW |
444 | |
445 | /* increment the pending count by the number of slots | |
446 | * memcpy operations have a 1:1 (slot:operation) relation | |
447 | * other operations are heavier and will pop the threshold | |
448 | * more often. | |
449 | */ | |
450 | iop_chan->pending += slot_cnt; | |
451 | iop_adma_check_threshold(iop_chan); | |
452 | spin_unlock_bh(&iop_chan->lock); | |
453 | ||
454 | dev_dbg(iop_chan->device->common.dev, "%s cookie: %d slot: %d\n", | |
3d9b525b | 455 | __func__, sw_desc->async_tx.cookie, sw_desc->idx); |
c2110923 DW |
456 | |
457 | return cookie; | |
458 | } | |
459 | ||
c2110923 DW |
460 | static void iop_chan_start_null_memcpy(struct iop_adma_chan *iop_chan); |
461 | static void iop_chan_start_null_xor(struct iop_adma_chan *iop_chan); | |
462 | ||
5eb907aa DW |
463 | /** |
464 | * iop_adma_alloc_chan_resources - returns the number of allocated descriptors | |
465 | * @chan - allocate descriptor resources for this channel | |
466 | * @client - current client requesting the channel be ready for requests | |
467 | * | |
468 | * Note: We keep the slots for 1 operation on iop_chan->chain at all times. To | |
469 | * avoid deadlock, via async_xor, num_descs_in_pool must at a minimum be | |
470 | * greater than 2x the number slots needed to satisfy a device->max_xor | |
471 | * request. | |
472 | * */ | |
848c536a HS |
473 | static int iop_adma_alloc_chan_resources(struct dma_chan *chan, |
474 | struct dma_client *client) | |
c2110923 DW |
475 | { |
476 | char *hw_desc; | |
477 | int idx; | |
478 | struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); | |
479 | struct iop_adma_desc_slot *slot = NULL; | |
480 | int init = iop_chan->slots_allocated ? 0 : 1; | |
481 | struct iop_adma_platform_data *plat_data = | |
482 | iop_chan->device->pdev->dev.platform_data; | |
483 | int num_descs_in_pool = plat_data->pool_size/IOP_ADMA_SLOT_SIZE; | |
484 | ||
485 | /* Allocate descriptor slots */ | |
486 | do { | |
487 | idx = iop_chan->slots_allocated; | |
488 | if (idx == num_descs_in_pool) | |
489 | break; | |
490 | ||
491 | slot = kzalloc(sizeof(*slot), GFP_KERNEL); | |
492 | if (!slot) { | |
493 | printk(KERN_INFO "IOP ADMA Channel only initialized" | |
494 | " %d descriptor slots", idx); | |
495 | break; | |
496 | } | |
497 | hw_desc = (char *) iop_chan->device->dma_desc_pool_virt; | |
498 | slot->hw_desc = (void *) &hw_desc[idx * IOP_ADMA_SLOT_SIZE]; | |
499 | ||
500 | dma_async_tx_descriptor_init(&slot->async_tx, chan); | |
501 | slot->async_tx.tx_submit = iop_adma_tx_submit; | |
c2110923 DW |
502 | INIT_LIST_HEAD(&slot->chain_node); |
503 | INIT_LIST_HEAD(&slot->slot_node); | |
504 | INIT_LIST_HEAD(&slot->async_tx.tx_list); | |
505 | hw_desc = (char *) iop_chan->device->dma_desc_pool; | |
506 | slot->async_tx.phys = | |
507 | (dma_addr_t) &hw_desc[idx * IOP_ADMA_SLOT_SIZE]; | |
508 | slot->idx = idx; | |
509 | ||
510 | spin_lock_bh(&iop_chan->lock); | |
511 | iop_chan->slots_allocated++; | |
512 | list_add_tail(&slot->slot_node, &iop_chan->all_slots); | |
513 | spin_unlock_bh(&iop_chan->lock); | |
514 | } while (iop_chan->slots_allocated < num_descs_in_pool); | |
515 | ||
516 | if (idx && !iop_chan->last_used) | |
517 | iop_chan->last_used = list_entry(iop_chan->all_slots.next, | |
518 | struct iop_adma_desc_slot, | |
519 | slot_node); | |
520 | ||
521 | dev_dbg(iop_chan->device->common.dev, | |
522 | "allocated %d descriptor slots last_used: %p\n", | |
523 | iop_chan->slots_allocated, iop_chan->last_used); | |
524 | ||
525 | /* initialize the channel and the chain with a null operation */ | |
526 | if (init) { | |
527 | if (dma_has_cap(DMA_MEMCPY, | |
528 | iop_chan->device->common.cap_mask)) | |
529 | iop_chan_start_null_memcpy(iop_chan); | |
530 | else if (dma_has_cap(DMA_XOR, | |
531 | iop_chan->device->common.cap_mask)) | |
532 | iop_chan_start_null_xor(iop_chan); | |
533 | else | |
534 | BUG(); | |
535 | } | |
536 | ||
537 | return (idx > 0) ? idx : -ENOMEM; | |
538 | } | |
539 | ||
540 | static struct dma_async_tx_descriptor * | |
636bdeaa | 541 | iop_adma_prep_dma_interrupt(struct dma_chan *chan, unsigned long flags) |
c2110923 DW |
542 | { |
543 | struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); | |
544 | struct iop_adma_desc_slot *sw_desc, *grp_start; | |
545 | int slot_cnt, slots_per_op; | |
546 | ||
3d9b525b | 547 | dev_dbg(iop_chan->device->common.dev, "%s\n", __func__); |
c2110923 DW |
548 | |
549 | spin_lock_bh(&iop_chan->lock); | |
550 | slot_cnt = iop_chan_interrupt_slot_count(&slots_per_op, iop_chan); | |
551 | sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op); | |
552 | if (sw_desc) { | |
553 | grp_start = sw_desc->group_head; | |
554 | iop_desc_init_interrupt(grp_start, iop_chan); | |
555 | grp_start->unmap_len = 0; | |
636bdeaa | 556 | sw_desc->async_tx.flags = flags; |
c2110923 DW |
557 | } |
558 | spin_unlock_bh(&iop_chan->lock); | |
559 | ||
560 | return sw_desc ? &sw_desc->async_tx : NULL; | |
561 | } | |
562 | ||
c2110923 | 563 | static struct dma_async_tx_descriptor * |
0036731c | 564 | iop_adma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dma_dest, |
d4c56f97 | 565 | dma_addr_t dma_src, size_t len, unsigned long flags) |
c2110923 DW |
566 | { |
567 | struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); | |
568 | struct iop_adma_desc_slot *sw_desc, *grp_start; | |
569 | int slot_cnt, slots_per_op; | |
570 | ||
571 | if (unlikely(!len)) | |
572 | return NULL; | |
573 | BUG_ON(unlikely(len > IOP_ADMA_MAX_BYTE_COUNT)); | |
574 | ||
575 | dev_dbg(iop_chan->device->common.dev, "%s len: %u\n", | |
3d9b525b | 576 | __func__, len); |
c2110923 DW |
577 | |
578 | spin_lock_bh(&iop_chan->lock); | |
579 | slot_cnt = iop_chan_memcpy_slot_count(len, &slots_per_op); | |
580 | sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op); | |
581 | if (sw_desc) { | |
582 | grp_start = sw_desc->group_head; | |
d4c56f97 | 583 | iop_desc_init_memcpy(grp_start, flags); |
c2110923 | 584 | iop_desc_set_byte_count(grp_start, iop_chan, len); |
0036731c DW |
585 | iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest); |
586 | iop_desc_set_memcpy_src_addr(grp_start, dma_src); | |
c2110923 DW |
587 | sw_desc->unmap_src_cnt = 1; |
588 | sw_desc->unmap_len = len; | |
636bdeaa | 589 | sw_desc->async_tx.flags = flags; |
c2110923 DW |
590 | } |
591 | spin_unlock_bh(&iop_chan->lock); | |
592 | ||
593 | return sw_desc ? &sw_desc->async_tx : NULL; | |
594 | } | |
595 | ||
596 | static struct dma_async_tx_descriptor * | |
0036731c | 597 | iop_adma_prep_dma_memset(struct dma_chan *chan, dma_addr_t dma_dest, |
d4c56f97 | 598 | int value, size_t len, unsigned long flags) |
c2110923 DW |
599 | { |
600 | struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); | |
601 | struct iop_adma_desc_slot *sw_desc, *grp_start; | |
602 | int slot_cnt, slots_per_op; | |
603 | ||
604 | if (unlikely(!len)) | |
605 | return NULL; | |
606 | BUG_ON(unlikely(len > IOP_ADMA_MAX_BYTE_COUNT)); | |
607 | ||
608 | dev_dbg(iop_chan->device->common.dev, "%s len: %u\n", | |
3d9b525b | 609 | __func__, len); |
c2110923 DW |
610 | |
611 | spin_lock_bh(&iop_chan->lock); | |
612 | slot_cnt = iop_chan_memset_slot_count(len, &slots_per_op); | |
613 | sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op); | |
614 | if (sw_desc) { | |
615 | grp_start = sw_desc->group_head; | |
d4c56f97 | 616 | iop_desc_init_memset(grp_start, flags); |
c2110923 DW |
617 | iop_desc_set_byte_count(grp_start, iop_chan, len); |
618 | iop_desc_set_block_fill_val(grp_start, value); | |
0036731c | 619 | iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest); |
c2110923 DW |
620 | sw_desc->unmap_src_cnt = 1; |
621 | sw_desc->unmap_len = len; | |
636bdeaa | 622 | sw_desc->async_tx.flags = flags; |
c2110923 DW |
623 | } |
624 | spin_unlock_bh(&iop_chan->lock); | |
625 | ||
626 | return sw_desc ? &sw_desc->async_tx : NULL; | |
627 | } | |
628 | ||
c2110923 | 629 | static struct dma_async_tx_descriptor * |
0036731c DW |
630 | iop_adma_prep_dma_xor(struct dma_chan *chan, dma_addr_t dma_dest, |
631 | dma_addr_t *dma_src, unsigned int src_cnt, size_t len, | |
d4c56f97 | 632 | unsigned long flags) |
c2110923 DW |
633 | { |
634 | struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); | |
635 | struct iop_adma_desc_slot *sw_desc, *grp_start; | |
636 | int slot_cnt, slots_per_op; | |
637 | ||
638 | if (unlikely(!len)) | |
639 | return NULL; | |
640 | BUG_ON(unlikely(len > IOP_ADMA_XOR_MAX_BYTE_COUNT)); | |
641 | ||
642 | dev_dbg(iop_chan->device->common.dev, | |
d4c56f97 | 643 | "%s src_cnt: %d len: %u flags: %lx\n", |
3d9b525b | 644 | __func__, src_cnt, len, flags); |
c2110923 DW |
645 | |
646 | spin_lock_bh(&iop_chan->lock); | |
647 | slot_cnt = iop_chan_xor_slot_count(len, src_cnt, &slots_per_op); | |
648 | sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op); | |
649 | if (sw_desc) { | |
650 | grp_start = sw_desc->group_head; | |
d4c56f97 | 651 | iop_desc_init_xor(grp_start, src_cnt, flags); |
c2110923 | 652 | iop_desc_set_byte_count(grp_start, iop_chan, len); |
0036731c | 653 | iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest); |
c2110923 DW |
654 | sw_desc->unmap_src_cnt = src_cnt; |
655 | sw_desc->unmap_len = len; | |
636bdeaa | 656 | sw_desc->async_tx.flags = flags; |
0036731c DW |
657 | while (src_cnt--) |
658 | iop_desc_set_xor_src_addr(grp_start, src_cnt, | |
659 | dma_src[src_cnt]); | |
c2110923 DW |
660 | } |
661 | spin_unlock_bh(&iop_chan->lock); | |
662 | ||
663 | return sw_desc ? &sw_desc->async_tx : NULL; | |
664 | } | |
665 | ||
c2110923 | 666 | static struct dma_async_tx_descriptor * |
0036731c DW |
667 | iop_adma_prep_dma_zero_sum(struct dma_chan *chan, dma_addr_t *dma_src, |
668 | unsigned int src_cnt, size_t len, u32 *result, | |
d4c56f97 | 669 | unsigned long flags) |
c2110923 DW |
670 | { |
671 | struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); | |
672 | struct iop_adma_desc_slot *sw_desc, *grp_start; | |
673 | int slot_cnt, slots_per_op; | |
674 | ||
675 | if (unlikely(!len)) | |
676 | return NULL; | |
677 | ||
678 | dev_dbg(iop_chan->device->common.dev, "%s src_cnt: %d len: %u\n", | |
3d9b525b | 679 | __func__, src_cnt, len); |
c2110923 DW |
680 | |
681 | spin_lock_bh(&iop_chan->lock); | |
682 | slot_cnt = iop_chan_zero_sum_slot_count(len, src_cnt, &slots_per_op); | |
683 | sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op); | |
684 | if (sw_desc) { | |
685 | grp_start = sw_desc->group_head; | |
d4c56f97 | 686 | iop_desc_init_zero_sum(grp_start, src_cnt, flags); |
c2110923 DW |
687 | iop_desc_set_zero_sum_byte_count(grp_start, len); |
688 | grp_start->xor_check_result = result; | |
689 | pr_debug("\t%s: grp_start->xor_check_result: %p\n", | |
3d9b525b | 690 | __func__, grp_start->xor_check_result); |
c2110923 DW |
691 | sw_desc->unmap_src_cnt = src_cnt; |
692 | sw_desc->unmap_len = len; | |
636bdeaa | 693 | sw_desc->async_tx.flags = flags; |
0036731c DW |
694 | while (src_cnt--) |
695 | iop_desc_set_zero_sum_src_addr(grp_start, src_cnt, | |
696 | dma_src[src_cnt]); | |
c2110923 DW |
697 | } |
698 | spin_unlock_bh(&iop_chan->lock); | |
699 | ||
700 | return sw_desc ? &sw_desc->async_tx : NULL; | |
701 | } | |
702 | ||
c2110923 DW |
703 | static void iop_adma_free_chan_resources(struct dma_chan *chan) |
704 | { | |
705 | struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); | |
706 | struct iop_adma_desc_slot *iter, *_iter; | |
707 | int in_use_descs = 0; | |
708 | ||
709 | iop_adma_slot_cleanup(iop_chan); | |
710 | ||
711 | spin_lock_bh(&iop_chan->lock); | |
712 | list_for_each_entry_safe(iter, _iter, &iop_chan->chain, | |
713 | chain_node) { | |
714 | in_use_descs++; | |
715 | list_del(&iter->chain_node); | |
716 | } | |
717 | list_for_each_entry_safe_reverse( | |
718 | iter, _iter, &iop_chan->all_slots, slot_node) { | |
719 | list_del(&iter->slot_node); | |
720 | kfree(iter); | |
721 | iop_chan->slots_allocated--; | |
722 | } | |
723 | iop_chan->last_used = NULL; | |
724 | ||
725 | dev_dbg(iop_chan->device->common.dev, "%s slots_allocated %d\n", | |
3d9b525b | 726 | __func__, iop_chan->slots_allocated); |
c2110923 DW |
727 | spin_unlock_bh(&iop_chan->lock); |
728 | ||
729 | /* one is ok since we left it on there on purpose */ | |
730 | if (in_use_descs > 1) | |
731 | printk(KERN_ERR "IOP: Freeing %d in use descriptors!\n", | |
732 | in_use_descs - 1); | |
733 | } | |
734 | ||
735 | /** | |
736 | * iop_adma_is_complete - poll the status of an ADMA transaction | |
737 | * @chan: ADMA channel handle | |
738 | * @cookie: ADMA transaction identifier | |
739 | */ | |
740 | static enum dma_status iop_adma_is_complete(struct dma_chan *chan, | |
741 | dma_cookie_t cookie, | |
742 | dma_cookie_t *done, | |
743 | dma_cookie_t *used) | |
744 | { | |
745 | struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); | |
746 | dma_cookie_t last_used; | |
747 | dma_cookie_t last_complete; | |
748 | enum dma_status ret; | |
749 | ||
750 | last_used = chan->cookie; | |
751 | last_complete = iop_chan->completed_cookie; | |
752 | ||
753 | if (done) | |
754 | *done = last_complete; | |
755 | if (used) | |
756 | *used = last_used; | |
757 | ||
758 | ret = dma_async_is_complete(cookie, last_complete, last_used); | |
759 | if (ret == DMA_SUCCESS) | |
760 | return ret; | |
761 | ||
762 | iop_adma_slot_cleanup(iop_chan); | |
763 | ||
764 | last_used = chan->cookie; | |
765 | last_complete = iop_chan->completed_cookie; | |
766 | ||
767 | if (done) | |
768 | *done = last_complete; | |
769 | if (used) | |
770 | *used = last_used; | |
771 | ||
772 | return dma_async_is_complete(cookie, last_complete, last_used); | |
773 | } | |
774 | ||
775 | static irqreturn_t iop_adma_eot_handler(int irq, void *data) | |
776 | { | |
777 | struct iop_adma_chan *chan = data; | |
778 | ||
3d9b525b | 779 | dev_dbg(chan->device->common.dev, "%s\n", __func__); |
c2110923 DW |
780 | |
781 | tasklet_schedule(&chan->irq_tasklet); | |
782 | ||
783 | iop_adma_device_clear_eot_status(chan); | |
784 | ||
785 | return IRQ_HANDLED; | |
786 | } | |
787 | ||
788 | static irqreturn_t iop_adma_eoc_handler(int irq, void *data) | |
789 | { | |
790 | struct iop_adma_chan *chan = data; | |
791 | ||
3d9b525b | 792 | dev_dbg(chan->device->common.dev, "%s\n", __func__); |
c2110923 DW |
793 | |
794 | tasklet_schedule(&chan->irq_tasklet); | |
795 | ||
796 | iop_adma_device_clear_eoc_status(chan); | |
797 | ||
798 | return IRQ_HANDLED; | |
799 | } | |
800 | ||
801 | static irqreturn_t iop_adma_err_handler(int irq, void *data) | |
802 | { | |
803 | struct iop_adma_chan *chan = data; | |
804 | unsigned long status = iop_chan_get_status(chan); | |
805 | ||
806 | dev_printk(KERN_ERR, chan->device->common.dev, | |
807 | "error ( %s%s%s%s%s%s%s)\n", | |
808 | iop_is_err_int_parity(status, chan) ? "int_parity " : "", | |
809 | iop_is_err_mcu_abort(status, chan) ? "mcu_abort " : "", | |
810 | iop_is_err_int_tabort(status, chan) ? "int_tabort " : "", | |
811 | iop_is_err_int_mabort(status, chan) ? "int_mabort " : "", | |
812 | iop_is_err_pci_tabort(status, chan) ? "pci_tabort " : "", | |
813 | iop_is_err_pci_mabort(status, chan) ? "pci_mabort " : "", | |
814 | iop_is_err_split_tx(status, chan) ? "split_tx " : ""); | |
815 | ||
816 | iop_adma_device_clear_err_status(chan); | |
817 | ||
818 | BUG(); | |
819 | ||
820 | return IRQ_HANDLED; | |
821 | } | |
822 | ||
823 | static void iop_adma_issue_pending(struct dma_chan *chan) | |
824 | { | |
825 | struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); | |
826 | ||
827 | if (iop_chan->pending) { | |
828 | iop_chan->pending = 0; | |
829 | iop_chan_append(iop_chan); | |
830 | } | |
831 | } | |
832 | ||
833 | /* | |
834 | * Perform a transaction to verify the HW works. | |
835 | */ | |
836 | #define IOP_ADMA_TEST_SIZE 2000 | |
837 | ||
838 | static int __devinit iop_adma_memcpy_self_test(struct iop_adma_device *device) | |
839 | { | |
840 | int i; | |
841 | void *src, *dest; | |
842 | dma_addr_t src_dma, dest_dma; | |
843 | struct dma_chan *dma_chan; | |
844 | dma_cookie_t cookie; | |
845 | struct dma_async_tx_descriptor *tx; | |
846 | int err = 0; | |
847 | struct iop_adma_chan *iop_chan; | |
848 | ||
3d9b525b | 849 | dev_dbg(device->common.dev, "%s\n", __func__); |
c2110923 | 850 | |
eccf2144 | 851 | src = kmalloc(IOP_ADMA_TEST_SIZE, GFP_KERNEL); |
c2110923 DW |
852 | if (!src) |
853 | return -ENOMEM; | |
eccf2144 | 854 | dest = kzalloc(IOP_ADMA_TEST_SIZE, GFP_KERNEL); |
c2110923 DW |
855 | if (!dest) { |
856 | kfree(src); | |
857 | return -ENOMEM; | |
858 | } | |
859 | ||
860 | /* Fill in src buffer */ | |
861 | for (i = 0; i < IOP_ADMA_TEST_SIZE; i++) | |
862 | ((u8 *) src)[i] = (u8)i; | |
863 | ||
c2110923 DW |
864 | /* Start copy, using first DMA channel */ |
865 | dma_chan = container_of(device->common.channels.next, | |
866 | struct dma_chan, | |
867 | device_node); | |
848c536a | 868 | if (iop_adma_alloc_chan_resources(dma_chan, NULL) < 1) { |
c2110923 DW |
869 | err = -ENODEV; |
870 | goto out; | |
871 | } | |
872 | ||
c2110923 DW |
873 | dest_dma = dma_map_single(dma_chan->device->dev, dest, |
874 | IOP_ADMA_TEST_SIZE, DMA_FROM_DEVICE); | |
c2110923 DW |
875 | src_dma = dma_map_single(dma_chan->device->dev, src, |
876 | IOP_ADMA_TEST_SIZE, DMA_TO_DEVICE); | |
0036731c | 877 | tx = iop_adma_prep_dma_memcpy(dma_chan, dest_dma, src_dma, |
636bdeaa DW |
878 | IOP_ADMA_TEST_SIZE, |
879 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
c2110923 DW |
880 | |
881 | cookie = iop_adma_tx_submit(tx); | |
882 | iop_adma_issue_pending(dma_chan); | |
c2110923 DW |
883 | msleep(1); |
884 | ||
885 | if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != | |
886 | DMA_SUCCESS) { | |
887 | dev_printk(KERN_ERR, dma_chan->device->dev, | |
888 | "Self-test copy timed out, disabling\n"); | |
889 | err = -ENODEV; | |
890 | goto free_resources; | |
891 | } | |
892 | ||
893 | iop_chan = to_iop_adma_chan(dma_chan); | |
894 | dma_sync_single_for_cpu(&iop_chan->device->pdev->dev, dest_dma, | |
895 | IOP_ADMA_TEST_SIZE, DMA_FROM_DEVICE); | |
896 | if (memcmp(src, dest, IOP_ADMA_TEST_SIZE)) { | |
897 | dev_printk(KERN_ERR, dma_chan->device->dev, | |
898 | "Self-test copy failed compare, disabling\n"); | |
899 | err = -ENODEV; | |
900 | goto free_resources; | |
901 | } | |
902 | ||
903 | free_resources: | |
904 | iop_adma_free_chan_resources(dma_chan); | |
905 | out: | |
906 | kfree(src); | |
907 | kfree(dest); | |
908 | return err; | |
909 | } | |
910 | ||
911 | #define IOP_ADMA_NUM_SRC_TEST 4 /* must be <= 15 */ | |
912 | static int __devinit | |
913 | iop_adma_xor_zero_sum_self_test(struct iop_adma_device *device) | |
914 | { | |
915 | int i, src_idx; | |
916 | struct page *dest; | |
917 | struct page *xor_srcs[IOP_ADMA_NUM_SRC_TEST]; | |
918 | struct page *zero_sum_srcs[IOP_ADMA_NUM_SRC_TEST + 1]; | |
0036731c | 919 | dma_addr_t dma_srcs[IOP_ADMA_NUM_SRC_TEST + 1]; |
c2110923 DW |
920 | dma_addr_t dma_addr, dest_dma; |
921 | struct dma_async_tx_descriptor *tx; | |
922 | struct dma_chan *dma_chan; | |
923 | dma_cookie_t cookie; | |
924 | u8 cmp_byte = 0; | |
925 | u32 cmp_word; | |
926 | u32 zero_sum_result; | |
927 | int err = 0; | |
928 | struct iop_adma_chan *iop_chan; | |
929 | ||
3d9b525b | 930 | dev_dbg(device->common.dev, "%s\n", __func__); |
c2110923 DW |
931 | |
932 | for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) { | |
933 | xor_srcs[src_idx] = alloc_page(GFP_KERNEL); | |
934 | if (!xor_srcs[src_idx]) | |
935 | while (src_idx--) { | |
936 | __free_page(xor_srcs[src_idx]); | |
937 | return -ENOMEM; | |
938 | } | |
939 | } | |
940 | ||
941 | dest = alloc_page(GFP_KERNEL); | |
942 | if (!dest) | |
943 | while (src_idx--) { | |
944 | __free_page(xor_srcs[src_idx]); | |
945 | return -ENOMEM; | |
946 | } | |
947 | ||
948 | /* Fill in src buffers */ | |
949 | for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) { | |
950 | u8 *ptr = page_address(xor_srcs[src_idx]); | |
951 | for (i = 0; i < PAGE_SIZE; i++) | |
952 | ptr[i] = (1 << src_idx); | |
953 | } | |
954 | ||
955 | for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) | |
956 | cmp_byte ^= (u8) (1 << src_idx); | |
957 | ||
958 | cmp_word = (cmp_byte << 24) | (cmp_byte << 16) | | |
959 | (cmp_byte << 8) | cmp_byte; | |
960 | ||
961 | memset(page_address(dest), 0, PAGE_SIZE); | |
962 | ||
963 | dma_chan = container_of(device->common.channels.next, | |
964 | struct dma_chan, | |
965 | device_node); | |
848c536a | 966 | if (iop_adma_alloc_chan_resources(dma_chan, NULL) < 1) { |
c2110923 DW |
967 | err = -ENODEV; |
968 | goto out; | |
969 | } | |
970 | ||
971 | /* test xor */ | |
c2110923 DW |
972 | dest_dma = dma_map_page(dma_chan->device->dev, dest, 0, |
973 | PAGE_SIZE, DMA_FROM_DEVICE); | |
0036731c DW |
974 | for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++) |
975 | dma_srcs[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i], | |
976 | 0, PAGE_SIZE, DMA_TO_DEVICE); | |
977 | tx = iop_adma_prep_dma_xor(dma_chan, dest_dma, dma_srcs, | |
636bdeaa DW |
978 | IOP_ADMA_NUM_SRC_TEST, PAGE_SIZE, |
979 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
c2110923 DW |
980 | |
981 | cookie = iop_adma_tx_submit(tx); | |
982 | iop_adma_issue_pending(dma_chan); | |
c2110923 DW |
983 | msleep(8); |
984 | ||
985 | if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != | |
986 | DMA_SUCCESS) { | |
987 | dev_printk(KERN_ERR, dma_chan->device->dev, | |
988 | "Self-test xor timed out, disabling\n"); | |
989 | err = -ENODEV; | |
990 | goto free_resources; | |
991 | } | |
992 | ||
993 | iop_chan = to_iop_adma_chan(dma_chan); | |
994 | dma_sync_single_for_cpu(&iop_chan->device->pdev->dev, dest_dma, | |
995 | PAGE_SIZE, DMA_FROM_DEVICE); | |
996 | for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) { | |
997 | u32 *ptr = page_address(dest); | |
998 | if (ptr[i] != cmp_word) { | |
999 | dev_printk(KERN_ERR, dma_chan->device->dev, | |
1000 | "Self-test xor failed compare, disabling\n"); | |
1001 | err = -ENODEV; | |
1002 | goto free_resources; | |
1003 | } | |
1004 | } | |
1005 | dma_sync_single_for_device(&iop_chan->device->pdev->dev, dest_dma, | |
1006 | PAGE_SIZE, DMA_TO_DEVICE); | |
1007 | ||
1008 | /* skip zero sum if the capability is not present */ | |
1009 | if (!dma_has_cap(DMA_ZERO_SUM, dma_chan->device->cap_mask)) | |
1010 | goto free_resources; | |
1011 | ||
1012 | /* zero sum the sources with the destintation page */ | |
1013 | for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++) | |
1014 | zero_sum_srcs[i] = xor_srcs[i]; | |
1015 | zero_sum_srcs[i] = dest; | |
1016 | ||
1017 | zero_sum_result = 1; | |
1018 | ||
0036731c DW |
1019 | for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 1; i++) |
1020 | dma_srcs[i] = dma_map_page(dma_chan->device->dev, | |
1021 | zero_sum_srcs[i], 0, PAGE_SIZE, | |
1022 | DMA_TO_DEVICE); | |
1023 | tx = iop_adma_prep_dma_zero_sum(dma_chan, dma_srcs, | |
1024 | IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE, | |
636bdeaa DW |
1025 | &zero_sum_result, |
1026 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
c2110923 DW |
1027 | |
1028 | cookie = iop_adma_tx_submit(tx); | |
1029 | iop_adma_issue_pending(dma_chan); | |
c2110923 DW |
1030 | msleep(8); |
1031 | ||
1032 | if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) { | |
1033 | dev_printk(KERN_ERR, dma_chan->device->dev, | |
1034 | "Self-test zero sum timed out, disabling\n"); | |
1035 | err = -ENODEV; | |
1036 | goto free_resources; | |
1037 | } | |
1038 | ||
1039 | if (zero_sum_result != 0) { | |
1040 | dev_printk(KERN_ERR, dma_chan->device->dev, | |
1041 | "Self-test zero sum failed compare, disabling\n"); | |
1042 | err = -ENODEV; | |
1043 | goto free_resources; | |
1044 | } | |
1045 | ||
1046 | /* test memset */ | |
c2110923 DW |
1047 | dma_addr = dma_map_page(dma_chan->device->dev, dest, 0, |
1048 | PAGE_SIZE, DMA_FROM_DEVICE); | |
636bdeaa DW |
1049 | tx = iop_adma_prep_dma_memset(dma_chan, dma_addr, 0, PAGE_SIZE, |
1050 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
c2110923 DW |
1051 | |
1052 | cookie = iop_adma_tx_submit(tx); | |
1053 | iop_adma_issue_pending(dma_chan); | |
c2110923 DW |
1054 | msleep(8); |
1055 | ||
1056 | if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) { | |
1057 | dev_printk(KERN_ERR, dma_chan->device->dev, | |
1058 | "Self-test memset timed out, disabling\n"); | |
1059 | err = -ENODEV; | |
1060 | goto free_resources; | |
1061 | } | |
1062 | ||
1063 | for (i = 0; i < PAGE_SIZE/sizeof(u32); i++) { | |
1064 | u32 *ptr = page_address(dest); | |
1065 | if (ptr[i]) { | |
1066 | dev_printk(KERN_ERR, dma_chan->device->dev, | |
1067 | "Self-test memset failed compare, disabling\n"); | |
1068 | err = -ENODEV; | |
1069 | goto free_resources; | |
1070 | } | |
1071 | } | |
1072 | ||
1073 | /* test for non-zero parity sum */ | |
1074 | zero_sum_result = 0; | |
0036731c DW |
1075 | for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 1; i++) |
1076 | dma_srcs[i] = dma_map_page(dma_chan->device->dev, | |
1077 | zero_sum_srcs[i], 0, PAGE_SIZE, | |
1078 | DMA_TO_DEVICE); | |
1079 | tx = iop_adma_prep_dma_zero_sum(dma_chan, dma_srcs, | |
1080 | IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE, | |
636bdeaa DW |
1081 | &zero_sum_result, |
1082 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
c2110923 DW |
1083 | |
1084 | cookie = iop_adma_tx_submit(tx); | |
1085 | iop_adma_issue_pending(dma_chan); | |
c2110923 DW |
1086 | msleep(8); |
1087 | ||
1088 | if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) { | |
1089 | dev_printk(KERN_ERR, dma_chan->device->dev, | |
1090 | "Self-test non-zero sum timed out, disabling\n"); | |
1091 | err = -ENODEV; | |
1092 | goto free_resources; | |
1093 | } | |
1094 | ||
1095 | if (zero_sum_result != 1) { | |
1096 | dev_printk(KERN_ERR, dma_chan->device->dev, | |
1097 | "Self-test non-zero sum failed compare, disabling\n"); | |
1098 | err = -ENODEV; | |
1099 | goto free_resources; | |
1100 | } | |
1101 | ||
1102 | free_resources: | |
1103 | iop_adma_free_chan_resources(dma_chan); | |
1104 | out: | |
1105 | src_idx = IOP_ADMA_NUM_SRC_TEST; | |
1106 | while (src_idx--) | |
1107 | __free_page(xor_srcs[src_idx]); | |
1108 | __free_page(dest); | |
1109 | return err; | |
1110 | } | |
1111 | ||
1112 | static int __devexit iop_adma_remove(struct platform_device *dev) | |
1113 | { | |
1114 | struct iop_adma_device *device = platform_get_drvdata(dev); | |
1115 | struct dma_chan *chan, *_chan; | |
1116 | struct iop_adma_chan *iop_chan; | |
1117 | int i; | |
1118 | struct iop_adma_platform_data *plat_data = dev->dev.platform_data; | |
1119 | ||
1120 | dma_async_device_unregister(&device->common); | |
1121 | ||
1122 | for (i = 0; i < 3; i++) { | |
1123 | unsigned int irq; | |
1124 | irq = platform_get_irq(dev, i); | |
1125 | free_irq(irq, device); | |
1126 | } | |
1127 | ||
1128 | dma_free_coherent(&dev->dev, plat_data->pool_size, | |
1129 | device->dma_desc_pool_virt, device->dma_desc_pool); | |
1130 | ||
1131 | do { | |
1132 | struct resource *res; | |
1133 | res = platform_get_resource(dev, IORESOURCE_MEM, 0); | |
1134 | release_mem_region(res->start, res->end - res->start); | |
1135 | } while (0); | |
1136 | ||
1137 | list_for_each_entry_safe(chan, _chan, &device->common.channels, | |
1138 | device_node) { | |
1139 | iop_chan = to_iop_adma_chan(chan); | |
1140 | list_del(&chan->device_node); | |
1141 | kfree(iop_chan); | |
1142 | } | |
1143 | kfree(device); | |
1144 | ||
1145 | return 0; | |
1146 | } | |
1147 | ||
1148 | static int __devinit iop_adma_probe(struct platform_device *pdev) | |
1149 | { | |
1150 | struct resource *res; | |
1151 | int ret = 0, i; | |
1152 | struct iop_adma_device *adev; | |
1153 | struct iop_adma_chan *iop_chan; | |
1154 | struct dma_device *dma_dev; | |
1155 | struct iop_adma_platform_data *plat_data = pdev->dev.platform_data; | |
1156 | ||
1157 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1158 | if (!res) | |
1159 | return -ENODEV; | |
1160 | ||
1161 | if (!devm_request_mem_region(&pdev->dev, res->start, | |
1162 | res->end - res->start, pdev->name)) | |
1163 | return -EBUSY; | |
1164 | ||
1165 | adev = kzalloc(sizeof(*adev), GFP_KERNEL); | |
1166 | if (!adev) | |
1167 | return -ENOMEM; | |
1168 | dma_dev = &adev->common; | |
1169 | ||
1170 | /* allocate coherent memory for hardware descriptors | |
1171 | * note: writecombine gives slightly better performance, but | |
1172 | * requires that we explicitly flush the writes | |
1173 | */ | |
1174 | if ((adev->dma_desc_pool_virt = dma_alloc_writecombine(&pdev->dev, | |
1175 | plat_data->pool_size, | |
1176 | &adev->dma_desc_pool, | |
1177 | GFP_KERNEL)) == NULL) { | |
1178 | ret = -ENOMEM; | |
1179 | goto err_free_adev; | |
1180 | } | |
1181 | ||
1182 | dev_dbg(&pdev->dev, "%s: allocted descriptor pool virt %p phys %p\n", | |
3d9b525b | 1183 | __func__, adev->dma_desc_pool_virt, |
c2110923 DW |
1184 | (void *) adev->dma_desc_pool); |
1185 | ||
1186 | adev->id = plat_data->hw_id; | |
1187 | ||
1188 | /* discover transaction capabilites from the platform data */ | |
1189 | dma_dev->cap_mask = plat_data->cap_mask; | |
1190 | ||
1191 | adev->pdev = pdev; | |
1192 | platform_set_drvdata(pdev, adev); | |
1193 | ||
1194 | INIT_LIST_HEAD(&dma_dev->channels); | |
1195 | ||
1196 | /* set base routines */ | |
1197 | dma_dev->device_alloc_chan_resources = iop_adma_alloc_chan_resources; | |
1198 | dma_dev->device_free_chan_resources = iop_adma_free_chan_resources; | |
1199 | dma_dev->device_is_tx_complete = iop_adma_is_complete; | |
1200 | dma_dev->device_issue_pending = iop_adma_issue_pending; | |
c2110923 DW |
1201 | dma_dev->dev = &pdev->dev; |
1202 | ||
1203 | /* set prep routines based on capability */ | |
1204 | if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) | |
1205 | dma_dev->device_prep_dma_memcpy = iop_adma_prep_dma_memcpy; | |
1206 | if (dma_has_cap(DMA_MEMSET, dma_dev->cap_mask)) | |
1207 | dma_dev->device_prep_dma_memset = iop_adma_prep_dma_memset; | |
1208 | if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) { | |
1209 | dma_dev->max_xor = iop_adma_get_max_xor(); | |
1210 | dma_dev->device_prep_dma_xor = iop_adma_prep_dma_xor; | |
1211 | } | |
1212 | if (dma_has_cap(DMA_ZERO_SUM, dma_dev->cap_mask)) | |
1213 | dma_dev->device_prep_dma_zero_sum = | |
1214 | iop_adma_prep_dma_zero_sum; | |
1215 | if (dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask)) | |
1216 | dma_dev->device_prep_dma_interrupt = | |
1217 | iop_adma_prep_dma_interrupt; | |
1218 | ||
1219 | iop_chan = kzalloc(sizeof(*iop_chan), GFP_KERNEL); | |
1220 | if (!iop_chan) { | |
1221 | ret = -ENOMEM; | |
1222 | goto err_free_dma; | |
1223 | } | |
1224 | iop_chan->device = adev; | |
1225 | ||
1226 | iop_chan->mmr_base = devm_ioremap(&pdev->dev, res->start, | |
1227 | res->end - res->start); | |
1228 | if (!iop_chan->mmr_base) { | |
1229 | ret = -ENOMEM; | |
1230 | goto err_free_iop_chan; | |
1231 | } | |
1232 | tasklet_init(&iop_chan->irq_tasklet, iop_adma_tasklet, (unsigned long) | |
1233 | iop_chan); | |
1234 | ||
1235 | /* clear errors before enabling interrupts */ | |
1236 | iop_adma_device_clear_err_status(iop_chan); | |
1237 | ||
1238 | for (i = 0; i < 3; i++) { | |
1239 | irq_handler_t handler[] = { iop_adma_eot_handler, | |
1240 | iop_adma_eoc_handler, | |
1241 | iop_adma_err_handler }; | |
1242 | int irq = platform_get_irq(pdev, i); | |
1243 | if (irq < 0) { | |
1244 | ret = -ENXIO; | |
1245 | goto err_free_iop_chan; | |
1246 | } else { | |
1247 | ret = devm_request_irq(&pdev->dev, irq, | |
1248 | handler[i], 0, pdev->name, iop_chan); | |
1249 | if (ret) | |
1250 | goto err_free_iop_chan; | |
1251 | } | |
1252 | } | |
1253 | ||
1254 | spin_lock_init(&iop_chan->lock); | |
c2110923 DW |
1255 | INIT_LIST_HEAD(&iop_chan->chain); |
1256 | INIT_LIST_HEAD(&iop_chan->all_slots); | |
1257 | INIT_RCU_HEAD(&iop_chan->common.rcu); | |
1258 | iop_chan->common.device = dma_dev; | |
1259 | list_add_tail(&iop_chan->common.device_node, &dma_dev->channels); | |
1260 | ||
1261 | if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) { | |
1262 | ret = iop_adma_memcpy_self_test(adev); | |
1263 | dev_dbg(&pdev->dev, "memcpy self test returned %d\n", ret); | |
1264 | if (ret) | |
1265 | goto err_free_iop_chan; | |
1266 | } | |
1267 | ||
1268 | if (dma_has_cap(DMA_XOR, dma_dev->cap_mask) || | |
1269 | dma_has_cap(DMA_MEMSET, dma_dev->cap_mask)) { | |
1270 | ret = iop_adma_xor_zero_sum_self_test(adev); | |
1271 | dev_dbg(&pdev->dev, "xor self test returned %d\n", ret); | |
1272 | if (ret) | |
1273 | goto err_free_iop_chan; | |
1274 | } | |
1275 | ||
1276 | dev_printk(KERN_INFO, &pdev->dev, "Intel(R) IOP: " | |
1277 | "( %s%s%s%s%s%s%s%s%s%s)\n", | |
1278 | dma_has_cap(DMA_PQ_XOR, dma_dev->cap_mask) ? "pq_xor " : "", | |
1279 | dma_has_cap(DMA_PQ_UPDATE, dma_dev->cap_mask) ? "pq_update " : "", | |
1280 | dma_has_cap(DMA_PQ_ZERO_SUM, dma_dev->cap_mask) ? "pq_zero_sum " : "", | |
1281 | dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "", | |
1282 | dma_has_cap(DMA_DUAL_XOR, dma_dev->cap_mask) ? "dual_xor " : "", | |
1283 | dma_has_cap(DMA_ZERO_SUM, dma_dev->cap_mask) ? "xor_zero_sum " : "", | |
1284 | dma_has_cap(DMA_MEMSET, dma_dev->cap_mask) ? "fill " : "", | |
1285 | dma_has_cap(DMA_MEMCPY_CRC32C, dma_dev->cap_mask) ? "cpy+crc " : "", | |
1286 | dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "", | |
1287 | dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : ""); | |
1288 | ||
1289 | dma_async_device_register(dma_dev); | |
1290 | goto out; | |
1291 | ||
1292 | err_free_iop_chan: | |
1293 | kfree(iop_chan); | |
1294 | err_free_dma: | |
1295 | dma_free_coherent(&adev->pdev->dev, plat_data->pool_size, | |
1296 | adev->dma_desc_pool_virt, adev->dma_desc_pool); | |
1297 | err_free_adev: | |
1298 | kfree(adev); | |
1299 | out: | |
1300 | return ret; | |
1301 | } | |
1302 | ||
1303 | static void iop_chan_start_null_memcpy(struct iop_adma_chan *iop_chan) | |
1304 | { | |
1305 | struct iop_adma_desc_slot *sw_desc, *grp_start; | |
1306 | dma_cookie_t cookie; | |
1307 | int slot_cnt, slots_per_op; | |
1308 | ||
3d9b525b | 1309 | dev_dbg(iop_chan->device->common.dev, "%s\n", __func__); |
c2110923 DW |
1310 | |
1311 | spin_lock_bh(&iop_chan->lock); | |
1312 | slot_cnt = iop_chan_memcpy_slot_count(0, &slots_per_op); | |
1313 | sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op); | |
1314 | if (sw_desc) { | |
1315 | grp_start = sw_desc->group_head; | |
1316 | ||
1317 | list_splice_init(&sw_desc->async_tx.tx_list, &iop_chan->chain); | |
636bdeaa | 1318 | async_tx_ack(&sw_desc->async_tx); |
c2110923 DW |
1319 | iop_desc_init_memcpy(grp_start, 0); |
1320 | iop_desc_set_byte_count(grp_start, iop_chan, 0); | |
1321 | iop_desc_set_dest_addr(grp_start, iop_chan, 0); | |
1322 | iop_desc_set_memcpy_src_addr(grp_start, 0); | |
1323 | ||
1324 | cookie = iop_chan->common.cookie; | |
1325 | cookie++; | |
1326 | if (cookie <= 1) | |
1327 | cookie = 2; | |
1328 | ||
1329 | /* initialize the completed cookie to be less than | |
1330 | * the most recently used cookie | |
1331 | */ | |
1332 | iop_chan->completed_cookie = cookie - 1; | |
1333 | iop_chan->common.cookie = sw_desc->async_tx.cookie = cookie; | |
1334 | ||
1335 | /* channel should not be busy */ | |
1336 | BUG_ON(iop_chan_is_busy(iop_chan)); | |
1337 | ||
1338 | /* clear any prior error-status bits */ | |
1339 | iop_adma_device_clear_err_status(iop_chan); | |
1340 | ||
1341 | /* disable operation */ | |
1342 | iop_chan_disable(iop_chan); | |
1343 | ||
1344 | /* set the descriptor address */ | |
1345 | iop_chan_set_next_descriptor(iop_chan, sw_desc->async_tx.phys); | |
1346 | ||
1347 | /* 1/ don't add pre-chained descriptors | |
1348 | * 2/ dummy read to flush next_desc write | |
1349 | */ | |
1350 | BUG_ON(iop_desc_get_next_desc(sw_desc)); | |
1351 | ||
1352 | /* run the descriptor */ | |
1353 | iop_chan_enable(iop_chan); | |
1354 | } else | |
1355 | dev_printk(KERN_ERR, iop_chan->device->common.dev, | |
1356 | "failed to allocate null descriptor\n"); | |
1357 | spin_unlock_bh(&iop_chan->lock); | |
1358 | } | |
1359 | ||
1360 | static void iop_chan_start_null_xor(struct iop_adma_chan *iop_chan) | |
1361 | { | |
1362 | struct iop_adma_desc_slot *sw_desc, *grp_start; | |
1363 | dma_cookie_t cookie; | |
1364 | int slot_cnt, slots_per_op; | |
1365 | ||
3d9b525b | 1366 | dev_dbg(iop_chan->device->common.dev, "%s\n", __func__); |
c2110923 DW |
1367 | |
1368 | spin_lock_bh(&iop_chan->lock); | |
1369 | slot_cnt = iop_chan_xor_slot_count(0, 2, &slots_per_op); | |
1370 | sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op); | |
1371 | if (sw_desc) { | |
1372 | grp_start = sw_desc->group_head; | |
1373 | list_splice_init(&sw_desc->async_tx.tx_list, &iop_chan->chain); | |
636bdeaa | 1374 | async_tx_ack(&sw_desc->async_tx); |
c2110923 DW |
1375 | iop_desc_init_null_xor(grp_start, 2, 0); |
1376 | iop_desc_set_byte_count(grp_start, iop_chan, 0); | |
1377 | iop_desc_set_dest_addr(grp_start, iop_chan, 0); | |
1378 | iop_desc_set_xor_src_addr(grp_start, 0, 0); | |
1379 | iop_desc_set_xor_src_addr(grp_start, 1, 0); | |
1380 | ||
1381 | cookie = iop_chan->common.cookie; | |
1382 | cookie++; | |
1383 | if (cookie <= 1) | |
1384 | cookie = 2; | |
1385 | ||
1386 | /* initialize the completed cookie to be less than | |
1387 | * the most recently used cookie | |
1388 | */ | |
1389 | iop_chan->completed_cookie = cookie - 1; | |
1390 | iop_chan->common.cookie = sw_desc->async_tx.cookie = cookie; | |
1391 | ||
1392 | /* channel should not be busy */ | |
1393 | BUG_ON(iop_chan_is_busy(iop_chan)); | |
1394 | ||
1395 | /* clear any prior error-status bits */ | |
1396 | iop_adma_device_clear_err_status(iop_chan); | |
1397 | ||
1398 | /* disable operation */ | |
1399 | iop_chan_disable(iop_chan); | |
1400 | ||
1401 | /* set the descriptor address */ | |
1402 | iop_chan_set_next_descriptor(iop_chan, sw_desc->async_tx.phys); | |
1403 | ||
1404 | /* 1/ don't add pre-chained descriptors | |
1405 | * 2/ dummy read to flush next_desc write | |
1406 | */ | |
1407 | BUG_ON(iop_desc_get_next_desc(sw_desc)); | |
1408 | ||
1409 | /* run the descriptor */ | |
1410 | iop_chan_enable(iop_chan); | |
1411 | } else | |
1412 | dev_printk(KERN_ERR, iop_chan->device->common.dev, | |
1413 | "failed to allocate null descriptor\n"); | |
1414 | spin_unlock_bh(&iop_chan->lock); | |
1415 | } | |
1416 | ||
ebabe276 KS |
1417 | MODULE_ALIAS("platform:iop-adma"); |
1418 | ||
c2110923 DW |
1419 | static struct platform_driver iop_adma_driver = { |
1420 | .probe = iop_adma_probe, | |
1421 | .remove = iop_adma_remove, | |
1422 | .driver = { | |
1423 | .owner = THIS_MODULE, | |
1424 | .name = "iop-adma", | |
1425 | }, | |
1426 | }; | |
1427 | ||
1428 | static int __init iop_adma_init (void) | |
1429 | { | |
c2110923 DW |
1430 | return platform_driver_register(&iop_adma_driver); |
1431 | } | |
1432 | ||
af49d924 RR |
1433 | /* it's currently unsafe to unload this module */ |
1434 | #if 0 | |
c2110923 DW |
1435 | static void __exit iop_adma_exit (void) |
1436 | { | |
1437 | platform_driver_unregister(&iop_adma_driver); | |
1438 | return; | |
1439 | } | |
af49d924 RR |
1440 | module_exit(iop_adma_exit); |
1441 | #endif | |
c2110923 DW |
1442 | |
1443 | module_init(iop_adma_init); | |
c2110923 DW |
1444 | |
1445 | MODULE_AUTHOR("Intel Corporation"); | |
1446 | MODULE_DESCRIPTION("IOP ADMA Engine Driver"); | |
1447 | MODULE_LICENSE("GPL"); |