Commit | Line | Data |
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c6da0ba8 ZG |
1 | /* |
2 | * Driver For Marvell Two-channel DMA Engine | |
3 | * | |
4 | * Copyright: Marvell International Ltd. | |
5 | * | |
6 | * The code contained herein is licensed under the GNU General Public | |
7 | * License. You may obtain a copy of the GNU General Public License | |
8 | * Version 2 or later at the following locations: | |
9 | * | |
10 | */ | |
11 | ||
7331205a | 12 | #include <linux/err.h> |
c6da0ba8 ZG |
13 | #include <linux/module.h> |
14 | #include <linux/init.h> | |
15 | #include <linux/types.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/dma-mapping.h> | |
18 | #include <linux/slab.h> | |
19 | #include <linux/dmaengine.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/device.h> | |
22 | #include <mach/regs-icu.h> | |
293b2da1 | 23 | #include <linux/platform_data/dma-mmp_tdma.h> |
f1a77570 | 24 | #include <linux/of_device.h> |
c6da0ba8 ZG |
25 | |
26 | #include "dmaengine.h" | |
27 | ||
28 | /* | |
29 | * Two-Channel DMA registers | |
30 | */ | |
31 | #define TDBCR 0x00 /* Byte Count */ | |
32 | #define TDSAR 0x10 /* Src Addr */ | |
33 | #define TDDAR 0x20 /* Dst Addr */ | |
34 | #define TDNDPR 0x30 /* Next Desc */ | |
35 | #define TDCR 0x40 /* Control */ | |
36 | #define TDCP 0x60 /* Priority*/ | |
37 | #define TDCDPR 0x70 /* Current Desc */ | |
38 | #define TDIMR 0x80 /* Int Mask */ | |
39 | #define TDISR 0xa0 /* Int Status */ | |
40 | ||
41 | /* Two-Channel DMA Control Register */ | |
42 | #define TDCR_SSZ_8_BITS (0x0 << 22) /* Sample Size */ | |
43 | #define TDCR_SSZ_12_BITS (0x1 << 22) | |
44 | #define TDCR_SSZ_16_BITS (0x2 << 22) | |
45 | #define TDCR_SSZ_20_BITS (0x3 << 22) | |
46 | #define TDCR_SSZ_24_BITS (0x4 << 22) | |
47 | #define TDCR_SSZ_32_BITS (0x5 << 22) | |
48 | #define TDCR_SSZ_SHIFT (0x1 << 22) | |
49 | #define TDCR_SSZ_MASK (0x7 << 22) | |
50 | #define TDCR_SSPMOD (0x1 << 21) /* SSP MOD */ | |
51 | #define TDCR_ABR (0x1 << 20) /* Channel Abort */ | |
52 | #define TDCR_CDE (0x1 << 17) /* Close Desc Enable */ | |
53 | #define TDCR_PACKMOD (0x1 << 16) /* Pack Mode (ADMA Only) */ | |
54 | #define TDCR_CHANACT (0x1 << 14) /* Channel Active */ | |
55 | #define TDCR_FETCHND (0x1 << 13) /* Fetch Next Desc */ | |
56 | #define TDCR_CHANEN (0x1 << 12) /* Channel Enable */ | |
57 | #define TDCR_INTMODE (0x1 << 10) /* Interrupt Mode */ | |
58 | #define TDCR_CHAINMOD (0x1 << 9) /* Chain Mode */ | |
59 | #define TDCR_BURSTSZ_MSK (0x7 << 6) /* Burst Size */ | |
60 | #define TDCR_BURSTSZ_4B (0x0 << 6) | |
61 | #define TDCR_BURSTSZ_8B (0x1 << 6) | |
62 | #define TDCR_BURSTSZ_16B (0x3 << 6) | |
63 | #define TDCR_BURSTSZ_32B (0x6 << 6) | |
64 | #define TDCR_BURSTSZ_64B (0x7 << 6) | |
20a90b0e QZ |
65 | #define TDCR_BURSTSZ_SQU_1B (0x5 << 6) |
66 | #define TDCR_BURSTSZ_SQU_2B (0x6 << 6) | |
67 | #define TDCR_BURSTSZ_SQU_4B (0x0 << 6) | |
68 | #define TDCR_BURSTSZ_SQU_8B (0x1 << 6) | |
69 | #define TDCR_BURSTSZ_SQU_16B (0x3 << 6) | |
c6da0ba8 ZG |
70 | #define TDCR_BURSTSZ_SQU_32B (0x7 << 6) |
71 | #define TDCR_BURSTSZ_128B (0x5 << 6) | |
72 | #define TDCR_DSTDIR_MSK (0x3 << 4) /* Dst Direction */ | |
73 | #define TDCR_DSTDIR_ADDR_HOLD (0x2 << 4) /* Dst Addr Hold */ | |
74 | #define TDCR_DSTDIR_ADDR_INC (0x0 << 4) /* Dst Addr Increment */ | |
75 | #define TDCR_SRCDIR_MSK (0x3 << 2) /* Src Direction */ | |
76 | #define TDCR_SRCDIR_ADDR_HOLD (0x2 << 2) /* Src Addr Hold */ | |
77 | #define TDCR_SRCDIR_ADDR_INC (0x0 << 2) /* Src Addr Increment */ | |
78 | #define TDCR_DSTDESCCONT (0x1 << 1) | |
79 | #define TDCR_SRCDESTCONT (0x1 << 0) | |
80 | ||
81 | /* Two-Channel DMA Int Mask Register */ | |
82 | #define TDIMR_COMP (0x1 << 0) | |
83 | ||
84 | /* Two-Channel DMA Int Status Register */ | |
85 | #define TDISR_COMP (0x1 << 0) | |
86 | ||
87 | /* | |
88 | * Two-Channel DMA Descriptor Struct | |
89 | * NOTE: desc's buf must be aligned to 16 bytes. | |
90 | */ | |
91 | struct mmp_tdma_desc { | |
92 | u32 byte_cnt; | |
93 | u32 src_addr; | |
94 | u32 dst_addr; | |
95 | u32 nxt_desc; | |
96 | }; | |
97 | ||
98 | enum mmp_tdma_type { | |
99 | MMP_AUD_TDMA = 0, | |
100 | PXA910_SQU, | |
101 | }; | |
102 | ||
103 | #define TDMA_ALIGNMENT 3 | |
104 | #define TDMA_MAX_XFER_BYTES SZ_64K | |
105 | ||
106 | struct mmp_tdma_chan { | |
107 | struct device *dev; | |
108 | struct dma_chan chan; | |
109 | struct dma_async_tx_descriptor desc; | |
110 | struct tasklet_struct tasklet; | |
111 | ||
112 | struct mmp_tdma_desc *desc_arr; | |
113 | phys_addr_t desc_arr_phys; | |
114 | int desc_num; | |
115 | enum dma_transfer_direction dir; | |
116 | dma_addr_t dev_addr; | |
117 | u32 burst_sz; | |
118 | enum dma_slave_buswidth buswidth; | |
119 | enum dma_status status; | |
120 | ||
121 | int idx; | |
122 | enum mmp_tdma_type type; | |
123 | int irq; | |
124 | unsigned long reg_base; | |
125 | ||
126 | size_t buf_len; | |
127 | size_t period_len; | |
128 | size_t pos; | |
129 | }; | |
130 | ||
131 | #define TDMA_CHANNEL_NUM 2 | |
132 | struct mmp_tdma_device { | |
133 | struct device *dev; | |
134 | void __iomem *base; | |
135 | struct dma_device device; | |
136 | struct mmp_tdma_chan *tdmac[TDMA_CHANNEL_NUM]; | |
c6da0ba8 ZG |
137 | }; |
138 | ||
139 | #define to_mmp_tdma_chan(dchan) container_of(dchan, struct mmp_tdma_chan, chan) | |
140 | ||
141 | static void mmp_tdma_chan_set_desc(struct mmp_tdma_chan *tdmac, dma_addr_t phys) | |
142 | { | |
143 | writel(phys, tdmac->reg_base + TDNDPR); | |
144 | writel(readl(tdmac->reg_base + TDCR) | TDCR_FETCHND, | |
145 | tdmac->reg_base + TDCR); | |
146 | } | |
147 | ||
148 | static void mmp_tdma_enable_chan(struct mmp_tdma_chan *tdmac) | |
149 | { | |
150 | /* enable irq */ | |
151 | writel(TDIMR_COMP, tdmac->reg_base + TDIMR); | |
152 | /* enable dma chan */ | |
153 | writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN, | |
154 | tdmac->reg_base + TDCR); | |
155 | tdmac->status = DMA_IN_PROGRESS; | |
156 | } | |
157 | ||
158 | static void mmp_tdma_disable_chan(struct mmp_tdma_chan *tdmac) | |
159 | { | |
160 | writel(readl(tdmac->reg_base + TDCR) & ~TDCR_CHANEN, | |
161 | tdmac->reg_base + TDCR); | |
8e3c518f QZ |
162 | |
163 | /* disable irq */ | |
164 | writel(0, tdmac->reg_base + TDIMR); | |
165 | ||
f64eabd0 | 166 | tdmac->status = DMA_COMPLETE; |
c6da0ba8 ZG |
167 | } |
168 | ||
169 | static void mmp_tdma_resume_chan(struct mmp_tdma_chan *tdmac) | |
170 | { | |
171 | writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN, | |
172 | tdmac->reg_base + TDCR); | |
173 | tdmac->status = DMA_IN_PROGRESS; | |
174 | } | |
175 | ||
176 | static void mmp_tdma_pause_chan(struct mmp_tdma_chan *tdmac) | |
177 | { | |
178 | writel(readl(tdmac->reg_base + TDCR) & ~TDCR_CHANEN, | |
179 | tdmac->reg_base + TDCR); | |
180 | tdmac->status = DMA_PAUSED; | |
181 | } | |
182 | ||
183 | static int mmp_tdma_config_chan(struct mmp_tdma_chan *tdmac) | |
184 | { | |
185 | unsigned int tdcr; | |
186 | ||
187 | mmp_tdma_disable_chan(tdmac); | |
188 | ||
189 | if (tdmac->dir == DMA_MEM_TO_DEV) | |
190 | tdcr = TDCR_DSTDIR_ADDR_HOLD | TDCR_SRCDIR_ADDR_INC; | |
191 | else if (tdmac->dir == DMA_DEV_TO_MEM) | |
192 | tdcr = TDCR_SRCDIR_ADDR_HOLD | TDCR_DSTDIR_ADDR_INC; | |
193 | ||
194 | if (tdmac->type == MMP_AUD_TDMA) { | |
195 | tdcr |= TDCR_PACKMOD; | |
196 | ||
197 | switch (tdmac->burst_sz) { | |
198 | case 4: | |
199 | tdcr |= TDCR_BURSTSZ_4B; | |
200 | break; | |
201 | case 8: | |
202 | tdcr |= TDCR_BURSTSZ_8B; | |
203 | break; | |
204 | case 16: | |
205 | tdcr |= TDCR_BURSTSZ_16B; | |
206 | break; | |
207 | case 32: | |
208 | tdcr |= TDCR_BURSTSZ_32B; | |
209 | break; | |
210 | case 64: | |
211 | tdcr |= TDCR_BURSTSZ_64B; | |
212 | break; | |
213 | case 128: | |
214 | tdcr |= TDCR_BURSTSZ_128B; | |
215 | break; | |
216 | default: | |
217 | dev_err(tdmac->dev, "mmp_tdma: unknown burst size.\n"); | |
218 | return -EINVAL; | |
219 | } | |
220 | ||
221 | switch (tdmac->buswidth) { | |
222 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
223 | tdcr |= TDCR_SSZ_8_BITS; | |
224 | break; | |
225 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
226 | tdcr |= TDCR_SSZ_16_BITS; | |
227 | break; | |
228 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
229 | tdcr |= TDCR_SSZ_32_BITS; | |
230 | break; | |
231 | default: | |
232 | dev_err(tdmac->dev, "mmp_tdma: unknown bus size.\n"); | |
233 | return -EINVAL; | |
234 | } | |
235 | } else if (tdmac->type == PXA910_SQU) { | |
c6da0ba8 | 236 | tdcr |= TDCR_SSPMOD; |
20a90b0e QZ |
237 | |
238 | switch (tdmac->burst_sz) { | |
239 | case 1: | |
240 | tdcr |= TDCR_BURSTSZ_SQU_1B; | |
241 | break; | |
242 | case 2: | |
243 | tdcr |= TDCR_BURSTSZ_SQU_2B; | |
244 | break; | |
245 | case 4: | |
246 | tdcr |= TDCR_BURSTSZ_SQU_4B; | |
247 | break; | |
248 | case 8: | |
249 | tdcr |= TDCR_BURSTSZ_SQU_8B; | |
250 | break; | |
251 | case 16: | |
252 | tdcr |= TDCR_BURSTSZ_SQU_16B; | |
253 | break; | |
254 | case 32: | |
255 | tdcr |= TDCR_BURSTSZ_SQU_32B; | |
256 | break; | |
257 | default: | |
258 | dev_err(tdmac->dev, "mmp_tdma: unknown burst size.\n"); | |
259 | return -EINVAL; | |
260 | } | |
c6da0ba8 ZG |
261 | } |
262 | ||
263 | writel(tdcr, tdmac->reg_base + TDCR); | |
264 | return 0; | |
265 | } | |
266 | ||
267 | static int mmp_tdma_clear_chan_irq(struct mmp_tdma_chan *tdmac) | |
268 | { | |
269 | u32 reg = readl(tdmac->reg_base + TDISR); | |
270 | ||
271 | if (reg & TDISR_COMP) { | |
272 | /* clear irq */ | |
273 | reg &= ~TDISR_COMP; | |
274 | writel(reg, tdmac->reg_base + TDISR); | |
275 | ||
276 | return 0; | |
277 | } | |
278 | return -EAGAIN; | |
279 | } | |
280 | ||
281 | static irqreturn_t mmp_tdma_chan_handler(int irq, void *dev_id) | |
282 | { | |
283 | struct mmp_tdma_chan *tdmac = dev_id; | |
284 | ||
285 | if (mmp_tdma_clear_chan_irq(tdmac) == 0) { | |
286 | tdmac->pos = (tdmac->pos + tdmac->period_len) % tdmac->buf_len; | |
287 | tasklet_schedule(&tdmac->tasklet); | |
288 | return IRQ_HANDLED; | |
289 | } else | |
290 | return IRQ_NONE; | |
291 | } | |
292 | ||
293 | static irqreturn_t mmp_tdma_int_handler(int irq, void *dev_id) | |
294 | { | |
295 | struct mmp_tdma_device *tdev = dev_id; | |
296 | int i, ret; | |
297 | int irq_num = 0; | |
298 | ||
299 | for (i = 0; i < TDMA_CHANNEL_NUM; i++) { | |
300 | struct mmp_tdma_chan *tdmac = tdev->tdmac[i]; | |
301 | ||
302 | ret = mmp_tdma_chan_handler(irq, tdmac); | |
303 | if (ret == IRQ_HANDLED) | |
304 | irq_num++; | |
305 | } | |
306 | ||
307 | if (irq_num) | |
308 | return IRQ_HANDLED; | |
309 | else | |
310 | return IRQ_NONE; | |
311 | } | |
312 | ||
313 | static void dma_do_tasklet(unsigned long data) | |
314 | { | |
315 | struct mmp_tdma_chan *tdmac = (struct mmp_tdma_chan *)data; | |
316 | ||
317 | if (tdmac->desc.callback) | |
318 | tdmac->desc.callback(tdmac->desc.callback_param); | |
319 | ||
320 | } | |
321 | ||
322 | static void mmp_tdma_free_descriptor(struct mmp_tdma_chan *tdmac) | |
323 | { | |
324 | struct gen_pool *gpool; | |
325 | int size = tdmac->desc_num * sizeof(struct mmp_tdma_desc); | |
326 | ||
327 | gpool = sram_get_gpool("asram"); | |
328 | if (tdmac->desc_arr) | |
329 | gen_pool_free(gpool, (unsigned long)tdmac->desc_arr, | |
330 | size); | |
331 | tdmac->desc_arr = NULL; | |
332 | ||
333 | return; | |
334 | } | |
335 | ||
336 | static dma_cookie_t mmp_tdma_tx_submit(struct dma_async_tx_descriptor *tx) | |
337 | { | |
338 | struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(tx->chan); | |
339 | ||
340 | mmp_tdma_chan_set_desc(tdmac, tdmac->desc_arr_phys); | |
341 | ||
342 | return 0; | |
343 | } | |
344 | ||
345 | static int mmp_tdma_alloc_chan_resources(struct dma_chan *chan) | |
346 | { | |
347 | struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); | |
348 | int ret; | |
349 | ||
350 | dma_async_tx_descriptor_init(&tdmac->desc, chan); | |
351 | tdmac->desc.tx_submit = mmp_tdma_tx_submit; | |
352 | ||
353 | if (tdmac->irq) { | |
354 | ret = devm_request_irq(tdmac->dev, tdmac->irq, | |
174b537a | 355 | mmp_tdma_chan_handler, 0, "tdma", tdmac); |
c6da0ba8 ZG |
356 | if (ret) |
357 | return ret; | |
358 | } | |
359 | return 1; | |
360 | } | |
361 | ||
362 | static void mmp_tdma_free_chan_resources(struct dma_chan *chan) | |
363 | { | |
364 | struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); | |
365 | ||
366 | if (tdmac->irq) | |
367 | devm_free_irq(tdmac->dev, tdmac->irq, tdmac); | |
368 | mmp_tdma_free_descriptor(tdmac); | |
369 | return; | |
370 | } | |
371 | ||
372 | struct mmp_tdma_desc *mmp_tdma_alloc_descriptor(struct mmp_tdma_chan *tdmac) | |
373 | { | |
374 | struct gen_pool *gpool; | |
375 | int size = tdmac->desc_num * sizeof(struct mmp_tdma_desc); | |
376 | ||
377 | gpool = sram_get_gpool("asram"); | |
378 | if (!gpool) | |
379 | return NULL; | |
380 | ||
a6dd30e2 | 381 | tdmac->desc_arr = gen_pool_dma_alloc(gpool, size, &tdmac->desc_arr_phys); |
c6da0ba8 ZG |
382 | |
383 | return tdmac->desc_arr; | |
384 | } | |
385 | ||
386 | static struct dma_async_tx_descriptor *mmp_tdma_prep_dma_cyclic( | |
387 | struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, | |
388 | size_t period_len, enum dma_transfer_direction direction, | |
ec8b5e48 | 389 | unsigned long flags, void *context) |
c6da0ba8 ZG |
390 | { |
391 | struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); | |
392 | struct mmp_tdma_desc *desc; | |
393 | int num_periods = buf_len / period_len; | |
394 | int i = 0, buf = 0; | |
395 | ||
f64eabd0 | 396 | if (tdmac->status != DMA_COMPLETE) |
c6da0ba8 ZG |
397 | return NULL; |
398 | ||
399 | if (period_len > TDMA_MAX_XFER_BYTES) { | |
400 | dev_err(tdmac->dev, | |
401 | "maximum period size exceeded: %d > %d\n", | |
402 | period_len, TDMA_MAX_XFER_BYTES); | |
403 | goto err_out; | |
404 | } | |
405 | ||
406 | tdmac->status = DMA_IN_PROGRESS; | |
407 | tdmac->desc_num = num_periods; | |
408 | desc = mmp_tdma_alloc_descriptor(tdmac); | |
409 | if (!desc) | |
410 | goto err_out; | |
411 | ||
412 | while (buf < buf_len) { | |
413 | desc = &tdmac->desc_arr[i]; | |
414 | ||
415 | if (i + 1 == num_periods) | |
416 | desc->nxt_desc = tdmac->desc_arr_phys; | |
417 | else | |
418 | desc->nxt_desc = tdmac->desc_arr_phys + | |
419 | sizeof(*desc) * (i + 1); | |
420 | ||
421 | if (direction == DMA_MEM_TO_DEV) { | |
422 | desc->src_addr = dma_addr; | |
423 | desc->dst_addr = tdmac->dev_addr; | |
424 | } else { | |
425 | desc->src_addr = tdmac->dev_addr; | |
426 | desc->dst_addr = dma_addr; | |
427 | } | |
428 | desc->byte_cnt = period_len; | |
429 | dma_addr += period_len; | |
430 | buf += period_len; | |
431 | i++; | |
432 | } | |
433 | ||
434 | tdmac->buf_len = buf_len; | |
435 | tdmac->period_len = period_len; | |
436 | tdmac->pos = 0; | |
437 | ||
438 | return &tdmac->desc; | |
439 | ||
440 | err_out: | |
441 | tdmac->status = DMA_ERROR; | |
442 | return NULL; | |
443 | } | |
444 | ||
445 | static int mmp_tdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, | |
446 | unsigned long arg) | |
447 | { | |
448 | struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); | |
449 | struct dma_slave_config *dmaengine_cfg = (void *)arg; | |
450 | int ret = 0; | |
451 | ||
452 | switch (cmd) { | |
453 | case DMA_TERMINATE_ALL: | |
454 | mmp_tdma_disable_chan(tdmac); | |
455 | break; | |
456 | case DMA_PAUSE: | |
457 | mmp_tdma_pause_chan(tdmac); | |
458 | break; | |
459 | case DMA_RESUME: | |
460 | mmp_tdma_resume_chan(tdmac); | |
461 | break; | |
462 | case DMA_SLAVE_CONFIG: | |
463 | if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) { | |
464 | tdmac->dev_addr = dmaengine_cfg->src_addr; | |
465 | tdmac->burst_sz = dmaengine_cfg->src_maxburst; | |
466 | tdmac->buswidth = dmaengine_cfg->src_addr_width; | |
467 | } else { | |
468 | tdmac->dev_addr = dmaengine_cfg->dst_addr; | |
469 | tdmac->burst_sz = dmaengine_cfg->dst_maxburst; | |
470 | tdmac->buswidth = dmaengine_cfg->dst_addr_width; | |
471 | } | |
472 | tdmac->dir = dmaengine_cfg->direction; | |
473 | return mmp_tdma_config_chan(tdmac); | |
474 | default: | |
475 | ret = -ENOSYS; | |
476 | } | |
477 | ||
478 | return ret; | |
479 | } | |
480 | ||
481 | static enum dma_status mmp_tdma_tx_status(struct dma_chan *chan, | |
482 | dma_cookie_t cookie, struct dma_tx_state *txstate) | |
483 | { | |
484 | struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); | |
485 | ||
c14d2bc4 AS |
486 | dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie, |
487 | tdmac->buf_len - tdmac->pos); | |
c6da0ba8 ZG |
488 | |
489 | return tdmac->status; | |
490 | } | |
491 | ||
492 | static void mmp_tdma_issue_pending(struct dma_chan *chan) | |
493 | { | |
494 | struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); | |
495 | ||
496 | mmp_tdma_enable_chan(tdmac); | |
497 | } | |
498 | ||
4bf27b8b | 499 | static int mmp_tdma_remove(struct platform_device *pdev) |
c6da0ba8 ZG |
500 | { |
501 | struct mmp_tdma_device *tdev = platform_get_drvdata(pdev); | |
502 | ||
503 | dma_async_device_unregister(&tdev->device); | |
504 | return 0; | |
505 | } | |
506 | ||
463a1f8b | 507 | static int mmp_tdma_chan_init(struct mmp_tdma_device *tdev, |
c6da0ba8 ZG |
508 | int idx, int irq, int type) |
509 | { | |
510 | struct mmp_tdma_chan *tdmac; | |
511 | ||
512 | if (idx >= TDMA_CHANNEL_NUM) { | |
513 | dev_err(tdev->dev, "too many channels for device!\n"); | |
514 | return -EINVAL; | |
515 | } | |
516 | ||
517 | /* alloc channel */ | |
518 | tdmac = devm_kzalloc(tdev->dev, sizeof(*tdmac), GFP_KERNEL); | |
519 | if (!tdmac) { | |
520 | dev_err(tdev->dev, "no free memory for DMA channels!\n"); | |
521 | return -ENOMEM; | |
522 | } | |
523 | if (irq) | |
f1a77570 | 524 | tdmac->irq = irq; |
c6da0ba8 ZG |
525 | tdmac->dev = tdev->dev; |
526 | tdmac->chan.device = &tdev->device; | |
527 | tdmac->idx = idx; | |
528 | tdmac->type = type; | |
529 | tdmac->reg_base = (unsigned long)tdev->base + idx * 4; | |
f64eabd0 | 530 | tdmac->status = DMA_COMPLETE; |
c6da0ba8 ZG |
531 | tdev->tdmac[tdmac->idx] = tdmac; |
532 | tasklet_init(&tdmac->tasklet, dma_do_tasklet, (unsigned long)tdmac); | |
533 | ||
534 | /* add the channel to tdma_chan list */ | |
535 | list_add_tail(&tdmac->chan.device_node, | |
536 | &tdev->device.channels); | |
c6da0ba8 ZG |
537 | return 0; |
538 | } | |
539 | ||
f1a77570 ZG |
540 | static struct of_device_id mmp_tdma_dt_ids[] = { |
541 | { .compatible = "marvell,adma-1.0", .data = (void *)MMP_AUD_TDMA}, | |
542 | { .compatible = "marvell,pxa910-squ", .data = (void *)PXA910_SQU}, | |
543 | {} | |
544 | }; | |
545 | MODULE_DEVICE_TABLE(of, mmp_tdma_dt_ids); | |
546 | ||
463a1f8b | 547 | static int mmp_tdma_probe(struct platform_device *pdev) |
c6da0ba8 | 548 | { |
f1a77570 ZG |
549 | enum mmp_tdma_type type; |
550 | const struct of_device_id *of_id; | |
c6da0ba8 ZG |
551 | struct mmp_tdma_device *tdev; |
552 | struct resource *iores; | |
553 | int i, ret; | |
f1a77570 | 554 | int irq = 0, irq_num = 0; |
c6da0ba8 ZG |
555 | int chan_num = TDMA_CHANNEL_NUM; |
556 | ||
f1a77570 ZG |
557 | of_id = of_match_device(mmp_tdma_dt_ids, &pdev->dev); |
558 | if (of_id) | |
559 | type = (enum mmp_tdma_type) of_id->data; | |
560 | else | |
561 | type = platform_get_device_id(pdev)->driver_data; | |
562 | ||
c6da0ba8 ZG |
563 | /* always have couple channels */ |
564 | tdev = devm_kzalloc(&pdev->dev, sizeof(*tdev), GFP_KERNEL); | |
565 | if (!tdev) | |
566 | return -ENOMEM; | |
567 | ||
568 | tdev->dev = &pdev->dev; | |
c6da0ba8 | 569 | |
f1a77570 ZG |
570 | for (i = 0; i < chan_num; i++) { |
571 | if (platform_get_irq(pdev, i) > 0) | |
572 | irq_num++; | |
573 | } | |
c6da0ba8 ZG |
574 | |
575 | iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
7331205a TR |
576 | tdev->base = devm_ioremap_resource(&pdev->dev, iores); |
577 | if (IS_ERR(tdev->base)) | |
578 | return PTR_ERR(tdev->base); | |
c6da0ba8 | 579 | |
f1a77570 ZG |
580 | INIT_LIST_HEAD(&tdev->device.channels); |
581 | ||
582 | if (irq_num != chan_num) { | |
583 | irq = platform_get_irq(pdev, 0); | |
584 | ret = devm_request_irq(&pdev->dev, irq, | |
174b537a | 585 | mmp_tdma_int_handler, 0, "tdma", tdev); |
c6da0ba8 ZG |
586 | if (ret) |
587 | return ret; | |
588 | } | |
589 | ||
c6da0ba8 ZG |
590 | /* initialize channel parameters */ |
591 | for (i = 0; i < chan_num; i++) { | |
f1a77570 | 592 | irq = (irq_num != chan_num) ? 0 : platform_get_irq(pdev, i); |
c6da0ba8 ZG |
593 | ret = mmp_tdma_chan_init(tdev, i, irq, type); |
594 | if (ret) | |
595 | return ret; | |
596 | } | |
597 | ||
f1a77570 ZG |
598 | dma_cap_set(DMA_SLAVE, tdev->device.cap_mask); |
599 | dma_cap_set(DMA_CYCLIC, tdev->device.cap_mask); | |
c6da0ba8 ZG |
600 | tdev->device.dev = &pdev->dev; |
601 | tdev->device.device_alloc_chan_resources = | |
602 | mmp_tdma_alloc_chan_resources; | |
603 | tdev->device.device_free_chan_resources = | |
604 | mmp_tdma_free_chan_resources; | |
605 | tdev->device.device_prep_dma_cyclic = mmp_tdma_prep_dma_cyclic; | |
606 | tdev->device.device_tx_status = mmp_tdma_tx_status; | |
607 | tdev->device.device_issue_pending = mmp_tdma_issue_pending; | |
608 | tdev->device.device_control = mmp_tdma_control; | |
609 | tdev->device.copy_align = TDMA_ALIGNMENT; | |
610 | ||
611 | dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); | |
612 | platform_set_drvdata(pdev, tdev); | |
613 | ||
614 | ret = dma_async_device_register(&tdev->device); | |
615 | if (ret) { | |
616 | dev_err(tdev->device.dev, "unable to register\n"); | |
617 | return ret; | |
618 | } | |
619 | ||
620 | dev_info(tdev->device.dev, "initialized\n"); | |
621 | return 0; | |
622 | } | |
623 | ||
624 | static const struct platform_device_id mmp_tdma_id_table[] = { | |
625 | { "mmp-adma", MMP_AUD_TDMA }, | |
626 | { "pxa910-squ", PXA910_SQU }, | |
627 | { }, | |
628 | }; | |
629 | ||
630 | static struct platform_driver mmp_tdma_driver = { | |
631 | .driver = { | |
632 | .name = "mmp-tdma", | |
633 | .owner = THIS_MODULE, | |
f1a77570 | 634 | .of_match_table = mmp_tdma_dt_ids, |
c6da0ba8 ZG |
635 | }, |
636 | .id_table = mmp_tdma_id_table, | |
637 | .probe = mmp_tdma_probe, | |
a7d6e3ec | 638 | .remove = mmp_tdma_remove, |
c6da0ba8 ZG |
639 | }; |
640 | ||
641 | module_platform_driver(mmp_tdma_driver); | |
642 | ||
643 | MODULE_LICENSE("GPL"); | |
644 | MODULE_DESCRIPTION("MMP Two-Channel DMA Driver"); | |
645 | MODULE_ALIAS("platform:mmp-tdma"); | |
646 | MODULE_AUTHOR("Leo Yan <leoy@marvell.com>"); | |
647 | MODULE_AUTHOR("Zhangfei Gao <zhangfei.gao@marvell.com>"); |