Commit | Line | Data |
---|---|---|
ff7b0479 SB |
1 | /* |
2 | * offload engine driver for the Marvell XOR engine | |
3 | * Copyright (C) 2007, 2008, Marvell International Ltd. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
17 | */ | |
18 | ||
19 | #include <linux/init.h> | |
20 | #include <linux/module.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
ff7b0479 SB |
22 | #include <linux/delay.h> |
23 | #include <linux/dma-mapping.h> | |
24 | #include <linux/spinlock.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/platform_device.h> | |
27 | #include <linux/memory.h> | |
c510182b | 28 | #include <linux/clk.h> |
f7d12ef5 TP |
29 | #include <linux/of.h> |
30 | #include <linux/of_irq.h> | |
31 | #include <linux/irqdomain.h> | |
c02cecb9 | 32 | #include <linux/platform_data/dma-mv_xor.h> |
d2ebfb33 RKAL |
33 | |
34 | #include "dmaengine.h" | |
ff7b0479 SB |
35 | #include "mv_xor.h" |
36 | ||
37 | static void mv_xor_issue_pending(struct dma_chan *chan); | |
38 | ||
39 | #define to_mv_xor_chan(chan) \ | |
98817b99 | 40 | container_of(chan, struct mv_xor_chan, dmachan) |
ff7b0479 SB |
41 | |
42 | #define to_mv_xor_slot(tx) \ | |
43 | container_of(tx, struct mv_xor_desc_slot, async_tx) | |
44 | ||
c98c1781 | 45 | #define mv_chan_to_devp(chan) \ |
1ef48a26 | 46 | ((chan)->dmadev.dev) |
c98c1781 | 47 | |
dfc97661 | 48 | static void mv_desc_init(struct mv_xor_desc_slot *desc, |
ba87d137 LA |
49 | dma_addr_t addr, u32 byte_count, |
50 | enum dma_ctrl_flags flags) | |
ff7b0479 SB |
51 | { |
52 | struct mv_xor_desc *hw_desc = desc->hw_desc; | |
53 | ||
0e7488ed | 54 | hw_desc->status = XOR_DESC_DMA_OWNED; |
ff7b0479 | 55 | hw_desc->phy_next_desc = 0; |
ba87d137 LA |
56 | /* Enable end-of-descriptor interrupts only for DMA_PREP_INTERRUPT */ |
57 | hw_desc->desc_command = (flags & DMA_PREP_INTERRUPT) ? | |
58 | XOR_DESC_EOD_INT_EN : 0; | |
dfc97661 | 59 | hw_desc->phy_dest_addr = addr; |
ff7b0479 SB |
60 | hw_desc->byte_count = byte_count; |
61 | } | |
62 | ||
63 | static void mv_desc_set_next_desc(struct mv_xor_desc_slot *desc, | |
64 | u32 next_desc_addr) | |
65 | { | |
66 | struct mv_xor_desc *hw_desc = desc->hw_desc; | |
67 | BUG_ON(hw_desc->phy_next_desc); | |
68 | hw_desc->phy_next_desc = next_desc_addr; | |
69 | } | |
70 | ||
71 | static void mv_desc_clear_next_desc(struct mv_xor_desc_slot *desc) | |
72 | { | |
73 | struct mv_xor_desc *hw_desc = desc->hw_desc; | |
74 | hw_desc->phy_next_desc = 0; | |
75 | } | |
76 | ||
ff7b0479 SB |
77 | static void mv_desc_set_src_addr(struct mv_xor_desc_slot *desc, |
78 | int index, dma_addr_t addr) | |
79 | { | |
80 | struct mv_xor_desc *hw_desc = desc->hw_desc; | |
e03bc654 | 81 | hw_desc->phy_src_addr[mv_phy_src_idx(index)] = addr; |
ff7b0479 SB |
82 | if (desc->type == DMA_XOR) |
83 | hw_desc->desc_command |= (1 << index); | |
84 | } | |
85 | ||
86 | static u32 mv_chan_get_current_desc(struct mv_xor_chan *chan) | |
87 | { | |
5733c38a | 88 | return readl_relaxed(XOR_CURR_DESC(chan)); |
ff7b0479 SB |
89 | } |
90 | ||
91 | static void mv_chan_set_next_descriptor(struct mv_xor_chan *chan, | |
92 | u32 next_desc_addr) | |
93 | { | |
5733c38a | 94 | writel_relaxed(next_desc_addr, XOR_NEXT_DESC(chan)); |
ff7b0479 SB |
95 | } |
96 | ||
ff7b0479 SB |
97 | static void mv_chan_unmask_interrupts(struct mv_xor_chan *chan) |
98 | { | |
5733c38a | 99 | u32 val = readl_relaxed(XOR_INTR_MASK(chan)); |
ff7b0479 | 100 | val |= XOR_INTR_MASK_VALUE << (chan->idx * 16); |
5733c38a | 101 | writel_relaxed(val, XOR_INTR_MASK(chan)); |
ff7b0479 SB |
102 | } |
103 | ||
104 | static u32 mv_chan_get_intr_cause(struct mv_xor_chan *chan) | |
105 | { | |
5733c38a | 106 | u32 intr_cause = readl_relaxed(XOR_INTR_CAUSE(chan)); |
ff7b0479 SB |
107 | intr_cause = (intr_cause >> (chan->idx * 16)) & 0xFFFF; |
108 | return intr_cause; | |
109 | } | |
110 | ||
ff7b0479 SB |
111 | static void mv_xor_device_clear_eoc_cause(struct mv_xor_chan *chan) |
112 | { | |
ba87d137 LA |
113 | u32 val; |
114 | ||
115 | val = XOR_INT_END_OF_DESC | XOR_INT_END_OF_CHAIN | XOR_INT_STOPPED; | |
116 | val = ~(val << (chan->idx * 16)); | |
c98c1781 | 117 | dev_dbg(mv_chan_to_devp(chan), "%s, val 0x%08x\n", __func__, val); |
5733c38a | 118 | writel_relaxed(val, XOR_INTR_CAUSE(chan)); |
ff7b0479 SB |
119 | } |
120 | ||
121 | static void mv_xor_device_clear_err_status(struct mv_xor_chan *chan) | |
122 | { | |
123 | u32 val = 0xFFFF0000 >> (chan->idx * 16); | |
5733c38a | 124 | writel_relaxed(val, XOR_INTR_CAUSE(chan)); |
ff7b0479 SB |
125 | } |
126 | ||
ff7b0479 SB |
127 | static void mv_set_mode(struct mv_xor_chan *chan, |
128 | enum dma_transaction_type type) | |
129 | { | |
130 | u32 op_mode; | |
5733c38a | 131 | u32 config = readl_relaxed(XOR_CONFIG(chan)); |
ff7b0479 SB |
132 | |
133 | switch (type) { | |
134 | case DMA_XOR: | |
135 | op_mode = XOR_OPERATION_MODE_XOR; | |
136 | break; | |
137 | case DMA_MEMCPY: | |
138 | op_mode = XOR_OPERATION_MODE_MEMCPY; | |
139 | break; | |
ff7b0479 | 140 | default: |
c98c1781 | 141 | dev_err(mv_chan_to_devp(chan), |
1ba151cd | 142 | "error: unsupported operation %d\n", |
a3fc74bc | 143 | type); |
ff7b0479 SB |
144 | BUG(); |
145 | return; | |
146 | } | |
147 | ||
148 | config &= ~0x7; | |
149 | config |= op_mode; | |
e03bc654 TP |
150 | |
151 | #if defined(__BIG_ENDIAN) | |
152 | config |= XOR_DESCRIPTOR_SWAP; | |
153 | #else | |
154 | config &= ~XOR_DESCRIPTOR_SWAP; | |
155 | #endif | |
156 | ||
5733c38a | 157 | writel_relaxed(config, XOR_CONFIG(chan)); |
ff7b0479 SB |
158 | chan->current_type = type; |
159 | } | |
160 | ||
161 | static void mv_chan_activate(struct mv_xor_chan *chan) | |
162 | { | |
c98c1781 | 163 | dev_dbg(mv_chan_to_devp(chan), " activate chan.\n"); |
5a9a55bf EG |
164 | |
165 | /* writel ensures all descriptors are flushed before activation */ | |
166 | writel(BIT(0), XOR_ACTIVATION(chan)); | |
ff7b0479 SB |
167 | } |
168 | ||
169 | static char mv_chan_is_busy(struct mv_xor_chan *chan) | |
170 | { | |
5733c38a | 171 | u32 state = readl_relaxed(XOR_ACTIVATION(chan)); |
ff7b0479 SB |
172 | |
173 | state = (state >> 4) & 0x3; | |
174 | ||
175 | return (state == 1) ? 1 : 0; | |
176 | } | |
177 | ||
ff7b0479 SB |
178 | /** |
179 | * mv_xor_free_slots - flags descriptor slots for reuse | |
180 | * @slot: Slot to free | |
181 | * Caller must hold &mv_chan->lock while calling this function | |
182 | */ | |
183 | static void mv_xor_free_slots(struct mv_xor_chan *mv_chan, | |
184 | struct mv_xor_desc_slot *slot) | |
185 | { | |
c98c1781 | 186 | dev_dbg(mv_chan_to_devp(mv_chan), "%s %d slot %p\n", |
ff7b0479 SB |
187 | __func__, __LINE__, slot); |
188 | ||
dfc97661 | 189 | slot->slot_used = 0; |
ff7b0479 SB |
190 | |
191 | } | |
192 | ||
193 | /* | |
194 | * mv_xor_start_new_chain - program the engine to operate on new chain headed by | |
195 | * sw_desc | |
196 | * Caller must hold &mv_chan->lock while calling this function | |
197 | */ | |
198 | static void mv_xor_start_new_chain(struct mv_xor_chan *mv_chan, | |
199 | struct mv_xor_desc_slot *sw_desc) | |
200 | { | |
c98c1781 | 201 | dev_dbg(mv_chan_to_devp(mv_chan), "%s %d: sw_desc %p\n", |
ff7b0479 | 202 | __func__, __LINE__, sw_desc); |
ff7b0479 | 203 | |
48a9db46 BZ |
204 | /* set the hardware chain */ |
205 | mv_chan_set_next_descriptor(mv_chan, sw_desc->async_tx.phys); | |
206 | ||
dfc97661 | 207 | mv_chan->pending++; |
98817b99 | 208 | mv_xor_issue_pending(&mv_chan->dmachan); |
ff7b0479 SB |
209 | } |
210 | ||
211 | static dma_cookie_t | |
212 | mv_xor_run_tx_complete_actions(struct mv_xor_desc_slot *desc, | |
213 | struct mv_xor_chan *mv_chan, dma_cookie_t cookie) | |
214 | { | |
215 | BUG_ON(desc->async_tx.cookie < 0); | |
216 | ||
217 | if (desc->async_tx.cookie > 0) { | |
218 | cookie = desc->async_tx.cookie; | |
219 | ||
220 | /* call the callback (must not sleep or submit new | |
221 | * operations to this channel) | |
222 | */ | |
223 | if (desc->async_tx.callback) | |
224 | desc->async_tx.callback( | |
225 | desc->async_tx.callback_param); | |
226 | ||
d38a8c62 | 227 | dma_descriptor_unmap(&desc->async_tx); |
ff7b0479 SB |
228 | } |
229 | ||
230 | /* run dependent operations */ | |
07f2211e | 231 | dma_run_dependencies(&desc->async_tx); |
ff7b0479 SB |
232 | |
233 | return cookie; | |
234 | } | |
235 | ||
236 | static int | |
237 | mv_xor_clean_completed_slots(struct mv_xor_chan *mv_chan) | |
238 | { | |
239 | struct mv_xor_desc_slot *iter, *_iter; | |
240 | ||
c98c1781 | 241 | dev_dbg(mv_chan_to_devp(mv_chan), "%s %d\n", __func__, __LINE__); |
ff7b0479 SB |
242 | list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots, |
243 | completed_node) { | |
244 | ||
245 | if (async_tx_test_ack(&iter->async_tx)) { | |
246 | list_del(&iter->completed_node); | |
247 | mv_xor_free_slots(mv_chan, iter); | |
248 | } | |
249 | } | |
250 | return 0; | |
251 | } | |
252 | ||
253 | static int | |
254 | mv_xor_clean_slot(struct mv_xor_desc_slot *desc, | |
255 | struct mv_xor_chan *mv_chan) | |
256 | { | |
c98c1781 | 257 | dev_dbg(mv_chan_to_devp(mv_chan), "%s %d: desc %p flags %d\n", |
ff7b0479 SB |
258 | __func__, __LINE__, desc, desc->async_tx.flags); |
259 | list_del(&desc->chain_node); | |
260 | /* the client is allowed to attach dependent operations | |
261 | * until 'ack' is set | |
262 | */ | |
263 | if (!async_tx_test_ack(&desc->async_tx)) { | |
264 | /* move this slot to the completed_slots */ | |
265 | list_add_tail(&desc->completed_node, &mv_chan->completed_slots); | |
266 | return 0; | |
267 | } | |
268 | ||
269 | mv_xor_free_slots(mv_chan, desc); | |
270 | return 0; | |
271 | } | |
272 | ||
273 | static void __mv_xor_slot_cleanup(struct mv_xor_chan *mv_chan) | |
274 | { | |
275 | struct mv_xor_desc_slot *iter, *_iter; | |
276 | dma_cookie_t cookie = 0; | |
277 | int busy = mv_chan_is_busy(mv_chan); | |
278 | u32 current_desc = mv_chan_get_current_desc(mv_chan); | |
279 | int seen_current = 0; | |
280 | ||
c98c1781 TP |
281 | dev_dbg(mv_chan_to_devp(mv_chan), "%s %d\n", __func__, __LINE__); |
282 | dev_dbg(mv_chan_to_devp(mv_chan), "current_desc %x\n", current_desc); | |
ff7b0479 SB |
283 | mv_xor_clean_completed_slots(mv_chan); |
284 | ||
285 | /* free completed slots from the chain starting with | |
286 | * the oldest descriptor | |
287 | */ | |
288 | ||
289 | list_for_each_entry_safe(iter, _iter, &mv_chan->chain, | |
290 | chain_node) { | |
291 | prefetch(_iter); | |
292 | prefetch(&_iter->async_tx); | |
293 | ||
294 | /* do not advance past the current descriptor loaded into the | |
295 | * hardware channel, subsequent descriptors are either in | |
296 | * process or have not been submitted | |
297 | */ | |
298 | if (seen_current) | |
299 | break; | |
300 | ||
301 | /* stop the search if we reach the current descriptor and the | |
302 | * channel is busy | |
303 | */ | |
304 | if (iter->async_tx.phys == current_desc) { | |
305 | seen_current = 1; | |
306 | if (busy) | |
307 | break; | |
308 | } | |
309 | ||
310 | cookie = mv_xor_run_tx_complete_actions(iter, mv_chan, cookie); | |
311 | ||
312 | if (mv_xor_clean_slot(iter, mv_chan)) | |
313 | break; | |
314 | } | |
315 | ||
316 | if ((busy == 0) && !list_empty(&mv_chan->chain)) { | |
317 | struct mv_xor_desc_slot *chain_head; | |
318 | chain_head = list_entry(mv_chan->chain.next, | |
319 | struct mv_xor_desc_slot, | |
320 | chain_node); | |
321 | ||
322 | mv_xor_start_new_chain(mv_chan, chain_head); | |
323 | } | |
324 | ||
325 | if (cookie > 0) | |
98817b99 | 326 | mv_chan->dmachan.completed_cookie = cookie; |
ff7b0479 SB |
327 | } |
328 | ||
329 | static void | |
330 | mv_xor_slot_cleanup(struct mv_xor_chan *mv_chan) | |
331 | { | |
332 | spin_lock_bh(&mv_chan->lock); | |
333 | __mv_xor_slot_cleanup(mv_chan); | |
334 | spin_unlock_bh(&mv_chan->lock); | |
335 | } | |
336 | ||
337 | static void mv_xor_tasklet(unsigned long data) | |
338 | { | |
339 | struct mv_xor_chan *chan = (struct mv_xor_chan *) data; | |
8333f65e | 340 | mv_xor_slot_cleanup(chan); |
ff7b0479 SB |
341 | } |
342 | ||
343 | static struct mv_xor_desc_slot * | |
dfc97661 | 344 | mv_xor_alloc_slot(struct mv_xor_chan *mv_chan) |
ff7b0479 | 345 | { |
dfc97661 LA |
346 | struct mv_xor_desc_slot *iter, *_iter; |
347 | int retry = 0; | |
ff7b0479 SB |
348 | |
349 | /* start search from the last allocated descrtiptor | |
350 | * if a contiguous allocation can not be found start searching | |
351 | * from the beginning of the list | |
352 | */ | |
353 | retry: | |
ff7b0479 SB |
354 | if (retry == 0) |
355 | iter = mv_chan->last_used; | |
356 | else | |
357 | iter = list_entry(&mv_chan->all_slots, | |
358 | struct mv_xor_desc_slot, | |
359 | slot_node); | |
360 | ||
361 | list_for_each_entry_safe_continue( | |
362 | iter, _iter, &mv_chan->all_slots, slot_node) { | |
dfc97661 | 363 | |
ff7b0479 SB |
364 | prefetch(_iter); |
365 | prefetch(&_iter->async_tx); | |
dfc97661 | 366 | if (iter->slot_used) { |
ff7b0479 SB |
367 | /* give up after finding the first busy slot |
368 | * on the second pass through the list | |
369 | */ | |
370 | if (retry) | |
371 | break; | |
ff7b0479 SB |
372 | continue; |
373 | } | |
374 | ||
dfc97661 LA |
375 | /* pre-ack descriptor */ |
376 | async_tx_ack(&iter->async_tx); | |
377 | ||
378 | iter->slot_used = 1; | |
379 | INIT_LIST_HEAD(&iter->chain_node); | |
380 | iter->async_tx.cookie = -EBUSY; | |
381 | mv_chan->last_used = iter; | |
382 | mv_desc_clear_next_desc(iter); | |
383 | ||
384 | return iter; | |
385 | ||
ff7b0479 SB |
386 | } |
387 | if (!retry++) | |
388 | goto retry; | |
389 | ||
390 | /* try to free some slots if the allocation fails */ | |
391 | tasklet_schedule(&mv_chan->irq_tasklet); | |
392 | ||
393 | return NULL; | |
394 | } | |
395 | ||
ff7b0479 SB |
396 | /************************ DMA engine API functions ****************************/ |
397 | static dma_cookie_t | |
398 | mv_xor_tx_submit(struct dma_async_tx_descriptor *tx) | |
399 | { | |
400 | struct mv_xor_desc_slot *sw_desc = to_mv_xor_slot(tx); | |
401 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(tx->chan); | |
dfc97661 | 402 | struct mv_xor_desc_slot *old_chain_tail; |
ff7b0479 SB |
403 | dma_cookie_t cookie; |
404 | int new_hw_chain = 1; | |
405 | ||
c98c1781 | 406 | dev_dbg(mv_chan_to_devp(mv_chan), |
ff7b0479 SB |
407 | "%s sw_desc %p: async_tx %p\n", |
408 | __func__, sw_desc, &sw_desc->async_tx); | |
409 | ||
ff7b0479 | 410 | spin_lock_bh(&mv_chan->lock); |
884485e1 | 411 | cookie = dma_cookie_assign(tx); |
ff7b0479 SB |
412 | |
413 | if (list_empty(&mv_chan->chain)) | |
dfc97661 | 414 | list_add_tail(&sw_desc->chain_node, &mv_chan->chain); |
ff7b0479 SB |
415 | else { |
416 | new_hw_chain = 0; | |
417 | ||
418 | old_chain_tail = list_entry(mv_chan->chain.prev, | |
419 | struct mv_xor_desc_slot, | |
420 | chain_node); | |
dfc97661 | 421 | list_add_tail(&sw_desc->chain_node, &mv_chan->chain); |
ff7b0479 | 422 | |
31fd8f5b OJ |
423 | dev_dbg(mv_chan_to_devp(mv_chan), "Append to last desc %pa\n", |
424 | &old_chain_tail->async_tx.phys); | |
ff7b0479 SB |
425 | |
426 | /* fix up the hardware chain */ | |
dfc97661 | 427 | mv_desc_set_next_desc(old_chain_tail, sw_desc->async_tx.phys); |
ff7b0479 SB |
428 | |
429 | /* if the channel is not busy */ | |
430 | if (!mv_chan_is_busy(mv_chan)) { | |
431 | u32 current_desc = mv_chan_get_current_desc(mv_chan); | |
432 | /* | |
433 | * and the curren desc is the end of the chain before | |
434 | * the append, then we need to start the channel | |
435 | */ | |
436 | if (current_desc == old_chain_tail->async_tx.phys) | |
437 | new_hw_chain = 1; | |
438 | } | |
439 | } | |
440 | ||
441 | if (new_hw_chain) | |
dfc97661 | 442 | mv_xor_start_new_chain(mv_chan, sw_desc); |
ff7b0479 | 443 | |
ff7b0479 SB |
444 | spin_unlock_bh(&mv_chan->lock); |
445 | ||
446 | return cookie; | |
447 | } | |
448 | ||
449 | /* returns the number of allocated descriptors */ | |
aa1e6f1a | 450 | static int mv_xor_alloc_chan_resources(struct dma_chan *chan) |
ff7b0479 | 451 | { |
31fd8f5b OJ |
452 | void *virt_desc; |
453 | dma_addr_t dma_desc; | |
ff7b0479 SB |
454 | int idx; |
455 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); | |
456 | struct mv_xor_desc_slot *slot = NULL; | |
b503fa01 | 457 | int num_descs_in_pool = MV_XOR_POOL_SIZE/MV_XOR_SLOT_SIZE; |
ff7b0479 SB |
458 | |
459 | /* Allocate descriptor slots */ | |
460 | idx = mv_chan->slots_allocated; | |
461 | while (idx < num_descs_in_pool) { | |
462 | slot = kzalloc(sizeof(*slot), GFP_KERNEL); | |
463 | if (!slot) { | |
b8291dde EG |
464 | dev_info(mv_chan_to_devp(mv_chan), |
465 | "channel only initialized %d descriptor slots", | |
466 | idx); | |
ff7b0479 SB |
467 | break; |
468 | } | |
31fd8f5b OJ |
469 | virt_desc = mv_chan->dma_desc_pool_virt; |
470 | slot->hw_desc = virt_desc + idx * MV_XOR_SLOT_SIZE; | |
ff7b0479 SB |
471 | |
472 | dma_async_tx_descriptor_init(&slot->async_tx, chan); | |
473 | slot->async_tx.tx_submit = mv_xor_tx_submit; | |
474 | INIT_LIST_HEAD(&slot->chain_node); | |
475 | INIT_LIST_HEAD(&slot->slot_node); | |
31fd8f5b OJ |
476 | dma_desc = mv_chan->dma_desc_pool; |
477 | slot->async_tx.phys = dma_desc + idx * MV_XOR_SLOT_SIZE; | |
ff7b0479 SB |
478 | slot->idx = idx++; |
479 | ||
480 | spin_lock_bh(&mv_chan->lock); | |
481 | mv_chan->slots_allocated = idx; | |
482 | list_add_tail(&slot->slot_node, &mv_chan->all_slots); | |
483 | spin_unlock_bh(&mv_chan->lock); | |
484 | } | |
485 | ||
486 | if (mv_chan->slots_allocated && !mv_chan->last_used) | |
487 | mv_chan->last_used = list_entry(mv_chan->all_slots.next, | |
488 | struct mv_xor_desc_slot, | |
489 | slot_node); | |
490 | ||
c98c1781 | 491 | dev_dbg(mv_chan_to_devp(mv_chan), |
ff7b0479 SB |
492 | "allocated %d descriptor slots last_used: %p\n", |
493 | mv_chan->slots_allocated, mv_chan->last_used); | |
494 | ||
495 | return mv_chan->slots_allocated ? : -ENOMEM; | |
496 | } | |
497 | ||
ff7b0479 SB |
498 | static struct dma_async_tx_descriptor * |
499 | mv_xor_prep_dma_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, | |
500 | unsigned int src_cnt, size_t len, unsigned long flags) | |
501 | { | |
502 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); | |
dfc97661 | 503 | struct mv_xor_desc_slot *sw_desc; |
ff7b0479 SB |
504 | |
505 | if (unlikely(len < MV_XOR_MIN_BYTE_COUNT)) | |
506 | return NULL; | |
507 | ||
7912d300 | 508 | BUG_ON(len > MV_XOR_MAX_BYTE_COUNT); |
ff7b0479 | 509 | |
c98c1781 | 510 | dev_dbg(mv_chan_to_devp(mv_chan), |
31fd8f5b OJ |
511 | "%s src_cnt: %d len: %u dest %pad flags: %ld\n", |
512 | __func__, src_cnt, len, &dest, flags); | |
ff7b0479 SB |
513 | |
514 | spin_lock_bh(&mv_chan->lock); | |
dfc97661 | 515 | sw_desc = mv_xor_alloc_slot(mv_chan); |
ff7b0479 SB |
516 | if (sw_desc) { |
517 | sw_desc->type = DMA_XOR; | |
518 | sw_desc->async_tx.flags = flags; | |
ba87d137 | 519 | mv_desc_init(sw_desc, dest, len, flags); |
ff7b0479 | 520 | while (src_cnt--) |
dfc97661 | 521 | mv_desc_set_src_addr(sw_desc, src_cnt, src[src_cnt]); |
ff7b0479 SB |
522 | } |
523 | spin_unlock_bh(&mv_chan->lock); | |
c98c1781 | 524 | dev_dbg(mv_chan_to_devp(mv_chan), |
ff7b0479 SB |
525 | "%s sw_desc %p async_tx %p \n", |
526 | __func__, sw_desc, &sw_desc->async_tx); | |
527 | return sw_desc ? &sw_desc->async_tx : NULL; | |
528 | } | |
529 | ||
3e4f52e2 LA |
530 | static struct dma_async_tx_descriptor * |
531 | mv_xor_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
532 | size_t len, unsigned long flags) | |
533 | { | |
534 | /* | |
535 | * A MEMCPY operation is identical to an XOR operation with only | |
536 | * a single source address. | |
537 | */ | |
538 | return mv_xor_prep_dma_xor(chan, dest, &src, 1, len, flags); | |
539 | } | |
540 | ||
22843545 LA |
541 | static struct dma_async_tx_descriptor * |
542 | mv_xor_prep_dma_interrupt(struct dma_chan *chan, unsigned long flags) | |
543 | { | |
544 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); | |
545 | dma_addr_t src, dest; | |
546 | size_t len; | |
547 | ||
548 | src = mv_chan->dummy_src_addr; | |
549 | dest = mv_chan->dummy_dst_addr; | |
550 | len = MV_XOR_MIN_BYTE_COUNT; | |
551 | ||
552 | /* | |
553 | * We implement the DMA_INTERRUPT operation as a minimum sized | |
554 | * XOR operation with a single dummy source address. | |
555 | */ | |
556 | return mv_xor_prep_dma_xor(chan, dest, &src, 1, len, flags); | |
557 | } | |
558 | ||
ff7b0479 SB |
559 | static void mv_xor_free_chan_resources(struct dma_chan *chan) |
560 | { | |
561 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); | |
562 | struct mv_xor_desc_slot *iter, *_iter; | |
563 | int in_use_descs = 0; | |
564 | ||
565 | mv_xor_slot_cleanup(mv_chan); | |
566 | ||
567 | spin_lock_bh(&mv_chan->lock); | |
568 | list_for_each_entry_safe(iter, _iter, &mv_chan->chain, | |
569 | chain_node) { | |
570 | in_use_descs++; | |
571 | list_del(&iter->chain_node); | |
572 | } | |
573 | list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots, | |
574 | completed_node) { | |
575 | in_use_descs++; | |
576 | list_del(&iter->completed_node); | |
577 | } | |
578 | list_for_each_entry_safe_reverse( | |
579 | iter, _iter, &mv_chan->all_slots, slot_node) { | |
580 | list_del(&iter->slot_node); | |
581 | kfree(iter); | |
582 | mv_chan->slots_allocated--; | |
583 | } | |
584 | mv_chan->last_used = NULL; | |
585 | ||
c98c1781 | 586 | dev_dbg(mv_chan_to_devp(mv_chan), "%s slots_allocated %d\n", |
ff7b0479 SB |
587 | __func__, mv_chan->slots_allocated); |
588 | spin_unlock_bh(&mv_chan->lock); | |
589 | ||
590 | if (in_use_descs) | |
c98c1781 | 591 | dev_err(mv_chan_to_devp(mv_chan), |
ff7b0479 SB |
592 | "freeing %d in use descriptors!\n", in_use_descs); |
593 | } | |
594 | ||
595 | /** | |
07934481 | 596 | * mv_xor_status - poll the status of an XOR transaction |
ff7b0479 SB |
597 | * @chan: XOR channel handle |
598 | * @cookie: XOR transaction identifier | |
07934481 | 599 | * @txstate: XOR transactions state holder (or NULL) |
ff7b0479 | 600 | */ |
07934481 | 601 | static enum dma_status mv_xor_status(struct dma_chan *chan, |
ff7b0479 | 602 | dma_cookie_t cookie, |
07934481 | 603 | struct dma_tx_state *txstate) |
ff7b0479 SB |
604 | { |
605 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); | |
ff7b0479 SB |
606 | enum dma_status ret; |
607 | ||
96a2af41 | 608 | ret = dma_cookie_status(chan, cookie, txstate); |
b3efb8fc | 609 | if (ret == DMA_COMPLETE) { |
ff7b0479 SB |
610 | mv_xor_clean_completed_slots(mv_chan); |
611 | return ret; | |
612 | } | |
613 | mv_xor_slot_cleanup(mv_chan); | |
614 | ||
96a2af41 | 615 | return dma_cookie_status(chan, cookie, txstate); |
ff7b0479 SB |
616 | } |
617 | ||
618 | static void mv_dump_xor_regs(struct mv_xor_chan *chan) | |
619 | { | |
620 | u32 val; | |
621 | ||
5733c38a | 622 | val = readl_relaxed(XOR_CONFIG(chan)); |
1ba151cd | 623 | dev_err(mv_chan_to_devp(chan), "config 0x%08x\n", val); |
ff7b0479 | 624 | |
5733c38a | 625 | val = readl_relaxed(XOR_ACTIVATION(chan)); |
1ba151cd | 626 | dev_err(mv_chan_to_devp(chan), "activation 0x%08x\n", val); |
ff7b0479 | 627 | |
5733c38a | 628 | val = readl_relaxed(XOR_INTR_CAUSE(chan)); |
1ba151cd | 629 | dev_err(mv_chan_to_devp(chan), "intr cause 0x%08x\n", val); |
ff7b0479 | 630 | |
5733c38a | 631 | val = readl_relaxed(XOR_INTR_MASK(chan)); |
1ba151cd | 632 | dev_err(mv_chan_to_devp(chan), "intr mask 0x%08x\n", val); |
ff7b0479 | 633 | |
5733c38a | 634 | val = readl_relaxed(XOR_ERROR_CAUSE(chan)); |
1ba151cd | 635 | dev_err(mv_chan_to_devp(chan), "error cause 0x%08x\n", val); |
ff7b0479 | 636 | |
5733c38a | 637 | val = readl_relaxed(XOR_ERROR_ADDR(chan)); |
1ba151cd | 638 | dev_err(mv_chan_to_devp(chan), "error addr 0x%08x\n", val); |
ff7b0479 SB |
639 | } |
640 | ||
641 | static void mv_xor_err_interrupt_handler(struct mv_xor_chan *chan, | |
642 | u32 intr_cause) | |
643 | { | |
0e7488ed EG |
644 | if (intr_cause & XOR_INT_ERR_DECODE) { |
645 | dev_dbg(mv_chan_to_devp(chan), "ignoring address decode error\n"); | |
646 | return; | |
ff7b0479 SB |
647 | } |
648 | ||
0e7488ed | 649 | dev_err(mv_chan_to_devp(chan), "error on chan %d. intr cause 0x%08x\n", |
a3fc74bc | 650 | chan->idx, intr_cause); |
ff7b0479 SB |
651 | |
652 | mv_dump_xor_regs(chan); | |
0e7488ed | 653 | WARN_ON(1); |
ff7b0479 SB |
654 | } |
655 | ||
656 | static irqreturn_t mv_xor_interrupt_handler(int irq, void *data) | |
657 | { | |
658 | struct mv_xor_chan *chan = data; | |
659 | u32 intr_cause = mv_chan_get_intr_cause(chan); | |
660 | ||
c98c1781 | 661 | dev_dbg(mv_chan_to_devp(chan), "intr cause %x\n", intr_cause); |
ff7b0479 | 662 | |
0e7488ed | 663 | if (intr_cause & XOR_INTR_ERRORS) |
ff7b0479 SB |
664 | mv_xor_err_interrupt_handler(chan, intr_cause); |
665 | ||
666 | tasklet_schedule(&chan->irq_tasklet); | |
667 | ||
668 | mv_xor_device_clear_eoc_cause(chan); | |
669 | ||
670 | return IRQ_HANDLED; | |
671 | } | |
672 | ||
673 | static void mv_xor_issue_pending(struct dma_chan *chan) | |
674 | { | |
675 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); | |
676 | ||
677 | if (mv_chan->pending >= MV_XOR_THRESHOLD) { | |
678 | mv_chan->pending = 0; | |
679 | mv_chan_activate(mv_chan); | |
680 | } | |
681 | } | |
682 | ||
683 | /* | |
684 | * Perform a transaction to verify the HW works. | |
685 | */ | |
ff7b0479 | 686 | |
c2714334 | 687 | static int mv_xor_memcpy_self_test(struct mv_xor_chan *mv_chan) |
ff7b0479 SB |
688 | { |
689 | int i; | |
690 | void *src, *dest; | |
691 | dma_addr_t src_dma, dest_dma; | |
692 | struct dma_chan *dma_chan; | |
693 | dma_cookie_t cookie; | |
694 | struct dma_async_tx_descriptor *tx; | |
d16695a7 | 695 | struct dmaengine_unmap_data *unmap; |
ff7b0479 | 696 | int err = 0; |
ff7b0479 | 697 | |
d16695a7 | 698 | src = kmalloc(sizeof(u8) * PAGE_SIZE, GFP_KERNEL); |
ff7b0479 SB |
699 | if (!src) |
700 | return -ENOMEM; | |
701 | ||
d16695a7 | 702 | dest = kzalloc(sizeof(u8) * PAGE_SIZE, GFP_KERNEL); |
ff7b0479 SB |
703 | if (!dest) { |
704 | kfree(src); | |
705 | return -ENOMEM; | |
706 | } | |
707 | ||
708 | /* Fill in src buffer */ | |
d16695a7 | 709 | for (i = 0; i < PAGE_SIZE; i++) |
ff7b0479 SB |
710 | ((u8 *) src)[i] = (u8)i; |
711 | ||
275cc0c8 | 712 | dma_chan = &mv_chan->dmachan; |
aa1e6f1a | 713 | if (mv_xor_alloc_chan_resources(dma_chan) < 1) { |
ff7b0479 SB |
714 | err = -ENODEV; |
715 | goto out; | |
716 | } | |
717 | ||
d16695a7 EG |
718 | unmap = dmaengine_get_unmap_data(dma_chan->device->dev, 2, GFP_KERNEL); |
719 | if (!unmap) { | |
720 | err = -ENOMEM; | |
721 | goto free_resources; | |
722 | } | |
723 | ||
724 | src_dma = dma_map_page(dma_chan->device->dev, virt_to_page(src), 0, | |
725 | PAGE_SIZE, DMA_TO_DEVICE); | |
726 | unmap->to_cnt = 1; | |
727 | unmap->addr[0] = src_dma; | |
ff7b0479 | 728 | |
d16695a7 EG |
729 | dest_dma = dma_map_page(dma_chan->device->dev, virt_to_page(dest), 0, |
730 | PAGE_SIZE, DMA_FROM_DEVICE); | |
731 | unmap->from_cnt = 1; | |
732 | unmap->addr[1] = dest_dma; | |
733 | ||
734 | unmap->len = PAGE_SIZE; | |
ff7b0479 SB |
735 | |
736 | tx = mv_xor_prep_dma_memcpy(dma_chan, dest_dma, src_dma, | |
d16695a7 | 737 | PAGE_SIZE, 0); |
ff7b0479 SB |
738 | cookie = mv_xor_tx_submit(tx); |
739 | mv_xor_issue_pending(dma_chan); | |
740 | async_tx_ack(tx); | |
741 | msleep(1); | |
742 | ||
07934481 | 743 | if (mv_xor_status(dma_chan, cookie, NULL) != |
b3efb8fc | 744 | DMA_COMPLETE) { |
a3fc74bc TP |
745 | dev_err(dma_chan->device->dev, |
746 | "Self-test copy timed out, disabling\n"); | |
ff7b0479 SB |
747 | err = -ENODEV; |
748 | goto free_resources; | |
749 | } | |
750 | ||
c35064c4 | 751 | dma_sync_single_for_cpu(dma_chan->device->dev, dest_dma, |
d16695a7 EG |
752 | PAGE_SIZE, DMA_FROM_DEVICE); |
753 | if (memcmp(src, dest, PAGE_SIZE)) { | |
a3fc74bc TP |
754 | dev_err(dma_chan->device->dev, |
755 | "Self-test copy failed compare, disabling\n"); | |
ff7b0479 SB |
756 | err = -ENODEV; |
757 | goto free_resources; | |
758 | } | |
759 | ||
760 | free_resources: | |
d16695a7 | 761 | dmaengine_unmap_put(unmap); |
ff7b0479 SB |
762 | mv_xor_free_chan_resources(dma_chan); |
763 | out: | |
764 | kfree(src); | |
765 | kfree(dest); | |
766 | return err; | |
767 | } | |
768 | ||
769 | #define MV_XOR_NUM_SRC_TEST 4 /* must be <= 15 */ | |
463a1f8b | 770 | static int |
275cc0c8 | 771 | mv_xor_xor_self_test(struct mv_xor_chan *mv_chan) |
ff7b0479 SB |
772 | { |
773 | int i, src_idx; | |
774 | struct page *dest; | |
775 | struct page *xor_srcs[MV_XOR_NUM_SRC_TEST]; | |
776 | dma_addr_t dma_srcs[MV_XOR_NUM_SRC_TEST]; | |
777 | dma_addr_t dest_dma; | |
778 | struct dma_async_tx_descriptor *tx; | |
d16695a7 | 779 | struct dmaengine_unmap_data *unmap; |
ff7b0479 SB |
780 | struct dma_chan *dma_chan; |
781 | dma_cookie_t cookie; | |
782 | u8 cmp_byte = 0; | |
783 | u32 cmp_word; | |
784 | int err = 0; | |
d16695a7 | 785 | int src_count = MV_XOR_NUM_SRC_TEST; |
ff7b0479 | 786 | |
d16695a7 | 787 | for (src_idx = 0; src_idx < src_count; src_idx++) { |
ff7b0479 | 788 | xor_srcs[src_idx] = alloc_page(GFP_KERNEL); |
a09b09ae RK |
789 | if (!xor_srcs[src_idx]) { |
790 | while (src_idx--) | |
ff7b0479 | 791 | __free_page(xor_srcs[src_idx]); |
a09b09ae RK |
792 | return -ENOMEM; |
793 | } | |
ff7b0479 SB |
794 | } |
795 | ||
796 | dest = alloc_page(GFP_KERNEL); | |
a09b09ae RK |
797 | if (!dest) { |
798 | while (src_idx--) | |
ff7b0479 | 799 | __free_page(xor_srcs[src_idx]); |
a09b09ae RK |
800 | return -ENOMEM; |
801 | } | |
ff7b0479 SB |
802 | |
803 | /* Fill in src buffers */ | |
d16695a7 | 804 | for (src_idx = 0; src_idx < src_count; src_idx++) { |
ff7b0479 SB |
805 | u8 *ptr = page_address(xor_srcs[src_idx]); |
806 | for (i = 0; i < PAGE_SIZE; i++) | |
807 | ptr[i] = (1 << src_idx); | |
808 | } | |
809 | ||
d16695a7 | 810 | for (src_idx = 0; src_idx < src_count; src_idx++) |
ff7b0479 SB |
811 | cmp_byte ^= (u8) (1 << src_idx); |
812 | ||
813 | cmp_word = (cmp_byte << 24) | (cmp_byte << 16) | | |
814 | (cmp_byte << 8) | cmp_byte; | |
815 | ||
816 | memset(page_address(dest), 0, PAGE_SIZE); | |
817 | ||
275cc0c8 | 818 | dma_chan = &mv_chan->dmachan; |
aa1e6f1a | 819 | if (mv_xor_alloc_chan_resources(dma_chan) < 1) { |
ff7b0479 SB |
820 | err = -ENODEV; |
821 | goto out; | |
822 | } | |
823 | ||
d16695a7 EG |
824 | unmap = dmaengine_get_unmap_data(dma_chan->device->dev, src_count + 1, |
825 | GFP_KERNEL); | |
826 | if (!unmap) { | |
827 | err = -ENOMEM; | |
828 | goto free_resources; | |
829 | } | |
830 | ||
ff7b0479 | 831 | /* test xor */ |
d16695a7 EG |
832 | for (i = 0; i < src_count; i++) { |
833 | unmap->addr[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i], | |
834 | 0, PAGE_SIZE, DMA_TO_DEVICE); | |
835 | dma_srcs[i] = unmap->addr[i]; | |
836 | unmap->to_cnt++; | |
837 | } | |
ff7b0479 | 838 | |
d16695a7 EG |
839 | unmap->addr[src_count] = dma_map_page(dma_chan->device->dev, dest, 0, PAGE_SIZE, |
840 | DMA_FROM_DEVICE); | |
841 | dest_dma = unmap->addr[src_count]; | |
842 | unmap->from_cnt = 1; | |
843 | unmap->len = PAGE_SIZE; | |
ff7b0479 SB |
844 | |
845 | tx = mv_xor_prep_dma_xor(dma_chan, dest_dma, dma_srcs, | |
d16695a7 | 846 | src_count, PAGE_SIZE, 0); |
ff7b0479 SB |
847 | |
848 | cookie = mv_xor_tx_submit(tx); | |
849 | mv_xor_issue_pending(dma_chan); | |
850 | async_tx_ack(tx); | |
851 | msleep(8); | |
852 | ||
07934481 | 853 | if (mv_xor_status(dma_chan, cookie, NULL) != |
b3efb8fc | 854 | DMA_COMPLETE) { |
a3fc74bc TP |
855 | dev_err(dma_chan->device->dev, |
856 | "Self-test xor timed out, disabling\n"); | |
ff7b0479 SB |
857 | err = -ENODEV; |
858 | goto free_resources; | |
859 | } | |
860 | ||
c35064c4 | 861 | dma_sync_single_for_cpu(dma_chan->device->dev, dest_dma, |
ff7b0479 SB |
862 | PAGE_SIZE, DMA_FROM_DEVICE); |
863 | for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) { | |
864 | u32 *ptr = page_address(dest); | |
865 | if (ptr[i] != cmp_word) { | |
a3fc74bc | 866 | dev_err(dma_chan->device->dev, |
1ba151cd JP |
867 | "Self-test xor failed compare, disabling. index %d, data %x, expected %x\n", |
868 | i, ptr[i], cmp_word); | |
ff7b0479 SB |
869 | err = -ENODEV; |
870 | goto free_resources; | |
871 | } | |
872 | } | |
873 | ||
874 | free_resources: | |
d16695a7 | 875 | dmaengine_unmap_put(unmap); |
ff7b0479 SB |
876 | mv_xor_free_chan_resources(dma_chan); |
877 | out: | |
d16695a7 | 878 | src_idx = src_count; |
ff7b0479 SB |
879 | while (src_idx--) |
880 | __free_page(xor_srcs[src_idx]); | |
881 | __free_page(dest); | |
882 | return err; | |
883 | } | |
884 | ||
34c93c86 AL |
885 | /* This driver does not implement any of the optional DMA operations. */ |
886 | static int | |
887 | mv_xor_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, | |
888 | unsigned long arg) | |
889 | { | |
890 | return -ENOSYS; | |
891 | } | |
892 | ||
1ef48a26 | 893 | static int mv_xor_channel_remove(struct mv_xor_chan *mv_chan) |
ff7b0479 | 894 | { |
ff7b0479 | 895 | struct dma_chan *chan, *_chan; |
1ef48a26 | 896 | struct device *dev = mv_chan->dmadev.dev; |
ff7b0479 | 897 | |
1ef48a26 | 898 | dma_async_device_unregister(&mv_chan->dmadev); |
ff7b0479 | 899 | |
b503fa01 | 900 | dma_free_coherent(dev, MV_XOR_POOL_SIZE, |
1ef48a26 | 901 | mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool); |
22843545 LA |
902 | dma_unmap_single(dev, mv_chan->dummy_src_addr, |
903 | MV_XOR_MIN_BYTE_COUNT, DMA_FROM_DEVICE); | |
904 | dma_unmap_single(dev, mv_chan->dummy_dst_addr, | |
905 | MV_XOR_MIN_BYTE_COUNT, DMA_TO_DEVICE); | |
ff7b0479 | 906 | |
1ef48a26 | 907 | list_for_each_entry_safe(chan, _chan, &mv_chan->dmadev.channels, |
a6b4a9d2 | 908 | device_node) { |
ff7b0479 SB |
909 | list_del(&chan->device_node); |
910 | } | |
911 | ||
88eb92cb TP |
912 | free_irq(mv_chan->irq, mv_chan); |
913 | ||
ff7b0479 SB |
914 | return 0; |
915 | } | |
916 | ||
1ef48a26 | 917 | static struct mv_xor_chan * |
297eedba | 918 | mv_xor_channel_add(struct mv_xor_device *xordev, |
a6b4a9d2 | 919 | struct platform_device *pdev, |
b503fa01 | 920 | int idx, dma_cap_mask_t cap_mask, int irq) |
ff7b0479 SB |
921 | { |
922 | int ret = 0; | |
ff7b0479 SB |
923 | struct mv_xor_chan *mv_chan; |
924 | struct dma_device *dma_dev; | |
ff7b0479 | 925 | |
1ef48a26 | 926 | mv_chan = devm_kzalloc(&pdev->dev, sizeof(*mv_chan), GFP_KERNEL); |
a577659f SK |
927 | if (!mv_chan) |
928 | return ERR_PTR(-ENOMEM); | |
ff7b0479 | 929 | |
9aedbdba | 930 | mv_chan->idx = idx; |
88eb92cb | 931 | mv_chan->irq = irq; |
ff7b0479 | 932 | |
1ef48a26 | 933 | dma_dev = &mv_chan->dmadev; |
ff7b0479 | 934 | |
22843545 LA |
935 | /* |
936 | * These source and destination dummy buffers are used to implement | |
937 | * a DMA_INTERRUPT operation as a minimum-sized XOR operation. | |
938 | * Hence, we only need to map the buffers at initialization-time. | |
939 | */ | |
940 | mv_chan->dummy_src_addr = dma_map_single(dma_dev->dev, | |
941 | mv_chan->dummy_src, MV_XOR_MIN_BYTE_COUNT, DMA_FROM_DEVICE); | |
942 | mv_chan->dummy_dst_addr = dma_map_single(dma_dev->dev, | |
943 | mv_chan->dummy_dst, MV_XOR_MIN_BYTE_COUNT, DMA_TO_DEVICE); | |
944 | ||
ff7b0479 SB |
945 | /* allocate coherent memory for hardware descriptors |
946 | * note: writecombine gives slightly better performance, but | |
947 | * requires that we explicitly flush the writes | |
948 | */ | |
1ef48a26 | 949 | mv_chan->dma_desc_pool_virt = |
b503fa01 | 950 | dma_alloc_writecombine(&pdev->dev, MV_XOR_POOL_SIZE, |
1ef48a26 TP |
951 | &mv_chan->dma_desc_pool, GFP_KERNEL); |
952 | if (!mv_chan->dma_desc_pool_virt) | |
a6b4a9d2 | 953 | return ERR_PTR(-ENOMEM); |
ff7b0479 SB |
954 | |
955 | /* discover transaction capabilites from the platform data */ | |
a6b4a9d2 | 956 | dma_dev->cap_mask = cap_mask; |
ff7b0479 SB |
957 | |
958 | INIT_LIST_HEAD(&dma_dev->channels); | |
959 | ||
960 | /* set base routines */ | |
961 | dma_dev->device_alloc_chan_resources = mv_xor_alloc_chan_resources; | |
962 | dma_dev->device_free_chan_resources = mv_xor_free_chan_resources; | |
07934481 | 963 | dma_dev->device_tx_status = mv_xor_status; |
ff7b0479 | 964 | dma_dev->device_issue_pending = mv_xor_issue_pending; |
34c93c86 | 965 | dma_dev->device_control = mv_xor_control; |
ff7b0479 SB |
966 | dma_dev->dev = &pdev->dev; |
967 | ||
968 | /* set prep routines based on capability */ | |
22843545 LA |
969 | if (dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask)) |
970 | dma_dev->device_prep_dma_interrupt = mv_xor_prep_dma_interrupt; | |
ff7b0479 SB |
971 | if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) |
972 | dma_dev->device_prep_dma_memcpy = mv_xor_prep_dma_memcpy; | |
ff7b0479 | 973 | if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) { |
c019894e | 974 | dma_dev->max_xor = 8; |
ff7b0479 SB |
975 | dma_dev->device_prep_dma_xor = mv_xor_prep_dma_xor; |
976 | } | |
977 | ||
297eedba | 978 | mv_chan->mmr_base = xordev->xor_base; |
82a1402e | 979 | mv_chan->mmr_high_base = xordev->xor_high_base; |
ff7b0479 SB |
980 | tasklet_init(&mv_chan->irq_tasklet, mv_xor_tasklet, (unsigned long) |
981 | mv_chan); | |
982 | ||
983 | /* clear errors before enabling interrupts */ | |
984 | mv_xor_device_clear_err_status(mv_chan); | |
985 | ||
2d0a0745 TP |
986 | ret = request_irq(mv_chan->irq, mv_xor_interrupt_handler, |
987 | 0, dev_name(&pdev->dev), mv_chan); | |
ff7b0479 SB |
988 | if (ret) |
989 | goto err_free_dma; | |
990 | ||
991 | mv_chan_unmask_interrupts(mv_chan); | |
992 | ||
3e4f52e2 | 993 | mv_set_mode(mv_chan, DMA_XOR); |
ff7b0479 SB |
994 | |
995 | spin_lock_init(&mv_chan->lock); | |
996 | INIT_LIST_HEAD(&mv_chan->chain); | |
997 | INIT_LIST_HEAD(&mv_chan->completed_slots); | |
998 | INIT_LIST_HEAD(&mv_chan->all_slots); | |
98817b99 TP |
999 | mv_chan->dmachan.device = dma_dev; |
1000 | dma_cookie_init(&mv_chan->dmachan); | |
ff7b0479 | 1001 | |
98817b99 | 1002 | list_add_tail(&mv_chan->dmachan.device_node, &dma_dev->channels); |
ff7b0479 SB |
1003 | |
1004 | if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) { | |
275cc0c8 | 1005 | ret = mv_xor_memcpy_self_test(mv_chan); |
ff7b0479 SB |
1006 | dev_dbg(&pdev->dev, "memcpy self test returned %d\n", ret); |
1007 | if (ret) | |
2d0a0745 | 1008 | goto err_free_irq; |
ff7b0479 SB |
1009 | } |
1010 | ||
1011 | if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) { | |
275cc0c8 | 1012 | ret = mv_xor_xor_self_test(mv_chan); |
ff7b0479 SB |
1013 | dev_dbg(&pdev->dev, "xor self test returned %d\n", ret); |
1014 | if (ret) | |
2d0a0745 | 1015 | goto err_free_irq; |
ff7b0479 SB |
1016 | } |
1017 | ||
48a9db46 | 1018 | dev_info(&pdev->dev, "Marvell XOR: ( %s%s%s)\n", |
1ba151cd | 1019 | dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "", |
1ba151cd JP |
1020 | dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "", |
1021 | dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : ""); | |
ff7b0479 SB |
1022 | |
1023 | dma_async_device_register(dma_dev); | |
1ef48a26 | 1024 | return mv_chan; |
ff7b0479 | 1025 | |
2d0a0745 TP |
1026 | err_free_irq: |
1027 | free_irq(mv_chan->irq, mv_chan); | |
ff7b0479 | 1028 | err_free_dma: |
b503fa01 | 1029 | dma_free_coherent(&pdev->dev, MV_XOR_POOL_SIZE, |
1ef48a26 | 1030 | mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool); |
a6b4a9d2 | 1031 | return ERR_PTR(ret); |
ff7b0479 SB |
1032 | } |
1033 | ||
1034 | static void | |
297eedba | 1035 | mv_xor_conf_mbus_windows(struct mv_xor_device *xordev, |
63a9332b | 1036 | const struct mbus_dram_target_info *dram) |
ff7b0479 | 1037 | { |
82a1402e | 1038 | void __iomem *base = xordev->xor_high_base; |
ff7b0479 SB |
1039 | u32 win_enable = 0; |
1040 | int i; | |
1041 | ||
1042 | for (i = 0; i < 8; i++) { | |
1043 | writel(0, base + WINDOW_BASE(i)); | |
1044 | writel(0, base + WINDOW_SIZE(i)); | |
1045 | if (i < 4) | |
1046 | writel(0, base + WINDOW_REMAP_HIGH(i)); | |
1047 | } | |
1048 | ||
1049 | for (i = 0; i < dram->num_cs; i++) { | |
63a9332b | 1050 | const struct mbus_dram_window *cs = dram->cs + i; |
ff7b0479 SB |
1051 | |
1052 | writel((cs->base & 0xffff0000) | | |
1053 | (cs->mbus_attr << 8) | | |
1054 | dram->mbus_dram_target_id, base + WINDOW_BASE(i)); | |
1055 | writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i)); | |
1056 | ||
1057 | win_enable |= (1 << i); | |
1058 | win_enable |= 3 << (16 + (2 * i)); | |
1059 | } | |
1060 | ||
1061 | writel(win_enable, base + WINDOW_BAR_ENABLE(0)); | |
1062 | writel(win_enable, base + WINDOW_BAR_ENABLE(1)); | |
c4b4b732 TP |
1063 | writel(0, base + WINDOW_OVERRIDE_CTRL(0)); |
1064 | writel(0, base + WINDOW_OVERRIDE_CTRL(1)); | |
ff7b0479 SB |
1065 | } |
1066 | ||
c2714334 | 1067 | static int mv_xor_probe(struct platform_device *pdev) |
ff7b0479 | 1068 | { |
63a9332b | 1069 | const struct mbus_dram_target_info *dram; |
297eedba | 1070 | struct mv_xor_device *xordev; |
d4adcc01 | 1071 | struct mv_xor_platform_data *pdata = dev_get_platdata(&pdev->dev); |
ff7b0479 | 1072 | struct resource *res; |
60d151f3 | 1073 | int i, ret; |
ff7b0479 | 1074 | |
1ba151cd | 1075 | dev_notice(&pdev->dev, "Marvell shared XOR driver\n"); |
ff7b0479 | 1076 | |
297eedba TP |
1077 | xordev = devm_kzalloc(&pdev->dev, sizeof(*xordev), GFP_KERNEL); |
1078 | if (!xordev) | |
ff7b0479 SB |
1079 | return -ENOMEM; |
1080 | ||
1081 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1082 | if (!res) | |
1083 | return -ENODEV; | |
1084 | ||
297eedba TP |
1085 | xordev->xor_base = devm_ioremap(&pdev->dev, res->start, |
1086 | resource_size(res)); | |
1087 | if (!xordev->xor_base) | |
ff7b0479 SB |
1088 | return -EBUSY; |
1089 | ||
1090 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
1091 | if (!res) | |
1092 | return -ENODEV; | |
1093 | ||
297eedba TP |
1094 | xordev->xor_high_base = devm_ioremap(&pdev->dev, res->start, |
1095 | resource_size(res)); | |
1096 | if (!xordev->xor_high_base) | |
ff7b0479 SB |
1097 | return -EBUSY; |
1098 | ||
297eedba | 1099 | platform_set_drvdata(pdev, xordev); |
ff7b0479 SB |
1100 | |
1101 | /* | |
1102 | * (Re-)program MBUS remapping windows if we are asked to. | |
1103 | */ | |
63a9332b AL |
1104 | dram = mv_mbus_dram_info(); |
1105 | if (dram) | |
297eedba | 1106 | mv_xor_conf_mbus_windows(xordev, dram); |
ff7b0479 | 1107 | |
c510182b AL |
1108 | /* Not all platforms can gate the clock, so it is not |
1109 | * an error if the clock does not exists. | |
1110 | */ | |
297eedba TP |
1111 | xordev->clk = clk_get(&pdev->dev, NULL); |
1112 | if (!IS_ERR(xordev->clk)) | |
1113 | clk_prepare_enable(xordev->clk); | |
c510182b | 1114 | |
f7d12ef5 TP |
1115 | if (pdev->dev.of_node) { |
1116 | struct device_node *np; | |
1117 | int i = 0; | |
1118 | ||
1119 | for_each_child_of_node(pdev->dev.of_node, np) { | |
0be8253f | 1120 | struct mv_xor_chan *chan; |
f7d12ef5 TP |
1121 | dma_cap_mask_t cap_mask; |
1122 | int irq; | |
1123 | ||
1124 | dma_cap_zero(cap_mask); | |
1125 | if (of_property_read_bool(np, "dmacap,memcpy")) | |
1126 | dma_cap_set(DMA_MEMCPY, cap_mask); | |
1127 | if (of_property_read_bool(np, "dmacap,xor")) | |
1128 | dma_cap_set(DMA_XOR, cap_mask); | |
f7d12ef5 TP |
1129 | if (of_property_read_bool(np, "dmacap,interrupt")) |
1130 | dma_cap_set(DMA_INTERRUPT, cap_mask); | |
1131 | ||
1132 | irq = irq_of_parse_and_map(np, 0); | |
f8eb9e7d TP |
1133 | if (!irq) { |
1134 | ret = -ENODEV; | |
f7d12ef5 TP |
1135 | goto err_channel_add; |
1136 | } | |
1137 | ||
0be8253f RK |
1138 | chan = mv_xor_channel_add(xordev, pdev, i, |
1139 | cap_mask, irq); | |
1140 | if (IS_ERR(chan)) { | |
1141 | ret = PTR_ERR(chan); | |
f7d12ef5 TP |
1142 | irq_dispose_mapping(irq); |
1143 | goto err_channel_add; | |
1144 | } | |
1145 | ||
0be8253f | 1146 | xordev->channels[i] = chan; |
f7d12ef5 TP |
1147 | i++; |
1148 | } | |
1149 | } else if (pdata && pdata->channels) { | |
60d151f3 | 1150 | for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) { |
e39f6ec1 | 1151 | struct mv_xor_channel_data *cd; |
0be8253f | 1152 | struct mv_xor_chan *chan; |
60d151f3 TP |
1153 | int irq; |
1154 | ||
1155 | cd = &pdata->channels[i]; | |
1156 | if (!cd) { | |
1157 | ret = -ENODEV; | |
1158 | goto err_channel_add; | |
1159 | } | |
1160 | ||
1161 | irq = platform_get_irq(pdev, i); | |
1162 | if (irq < 0) { | |
1163 | ret = irq; | |
1164 | goto err_channel_add; | |
1165 | } | |
1166 | ||
0be8253f RK |
1167 | chan = mv_xor_channel_add(xordev, pdev, i, |
1168 | cd->cap_mask, irq); | |
1169 | if (IS_ERR(chan)) { | |
1170 | ret = PTR_ERR(chan); | |
60d151f3 TP |
1171 | goto err_channel_add; |
1172 | } | |
0be8253f RK |
1173 | |
1174 | xordev->channels[i] = chan; | |
60d151f3 TP |
1175 | } |
1176 | } | |
c510182b | 1177 | |
ff7b0479 | 1178 | return 0; |
60d151f3 TP |
1179 | |
1180 | err_channel_add: | |
1181 | for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) | |
f7d12ef5 | 1182 | if (xordev->channels[i]) { |
ab6e439f | 1183 | mv_xor_channel_remove(xordev->channels[i]); |
f7d12ef5 TP |
1184 | if (pdev->dev.of_node) |
1185 | irq_dispose_mapping(xordev->channels[i]->irq); | |
f7d12ef5 | 1186 | } |
60d151f3 | 1187 | |
dab92064 TP |
1188 | if (!IS_ERR(xordev->clk)) { |
1189 | clk_disable_unprepare(xordev->clk); | |
1190 | clk_put(xordev->clk); | |
1191 | } | |
1192 | ||
60d151f3 | 1193 | return ret; |
ff7b0479 SB |
1194 | } |
1195 | ||
c2714334 | 1196 | static int mv_xor_remove(struct platform_device *pdev) |
ff7b0479 | 1197 | { |
297eedba | 1198 | struct mv_xor_device *xordev = platform_get_drvdata(pdev); |
60d151f3 TP |
1199 | int i; |
1200 | ||
1201 | for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) { | |
297eedba TP |
1202 | if (xordev->channels[i]) |
1203 | mv_xor_channel_remove(xordev->channels[i]); | |
60d151f3 | 1204 | } |
c510182b | 1205 | |
297eedba TP |
1206 | if (!IS_ERR(xordev->clk)) { |
1207 | clk_disable_unprepare(xordev->clk); | |
1208 | clk_put(xordev->clk); | |
c510182b AL |
1209 | } |
1210 | ||
ff7b0479 SB |
1211 | return 0; |
1212 | } | |
1213 | ||
f7d12ef5 | 1214 | #ifdef CONFIG_OF |
c2714334 | 1215 | static struct of_device_id mv_xor_dt_ids[] = { |
f7d12ef5 TP |
1216 | { .compatible = "marvell,orion-xor", }, |
1217 | {}, | |
1218 | }; | |
1219 | MODULE_DEVICE_TABLE(of, mv_xor_dt_ids); | |
1220 | #endif | |
1221 | ||
61971656 TP |
1222 | static struct platform_driver mv_xor_driver = { |
1223 | .probe = mv_xor_probe, | |
c2714334 | 1224 | .remove = mv_xor_remove, |
ff7b0479 | 1225 | .driver = { |
f7d12ef5 TP |
1226 | .owner = THIS_MODULE, |
1227 | .name = MV_XOR_NAME, | |
1228 | .of_match_table = of_match_ptr(mv_xor_dt_ids), | |
ff7b0479 SB |
1229 | }, |
1230 | }; | |
1231 | ||
1232 | ||
1233 | static int __init mv_xor_init(void) | |
1234 | { | |
61971656 | 1235 | return platform_driver_register(&mv_xor_driver); |
ff7b0479 SB |
1236 | } |
1237 | module_init(mv_xor_init); | |
1238 | ||
1239 | /* it's currently unsafe to unload this module */ | |
1240 | #if 0 | |
1241 | static void __exit mv_xor_exit(void) | |
1242 | { | |
1243 | platform_driver_unregister(&mv_xor_driver); | |
ff7b0479 SB |
1244 | return; |
1245 | } | |
1246 | ||
1247 | module_exit(mv_xor_exit); | |
1248 | #endif | |
1249 | ||
1250 | MODULE_AUTHOR("Saeed Bishara <saeed@marvell.com>"); | |
1251 | MODULE_DESCRIPTION("DMA engine driver for Marvell's XOR engine"); | |
1252 | MODULE_LICENSE("GPL"); |