Commit | Line | Data |
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7bedaa55 RK |
1 | /* |
2 | * OMAP DMAengine support | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
fa3ad86a | 8 | #include <linux/delay.h> |
7bedaa55 RK |
9 | #include <linux/dmaengine.h> |
10 | #include <linux/dma-mapping.h> | |
11 | #include <linux/err.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/interrupt.h> | |
14 | #include <linux/list.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/omap-dma.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/slab.h> | |
19 | #include <linux/spinlock.h> | |
8d30662a JH |
20 | #include <linux/of_dma.h> |
21 | #include <linux/of_device.h> | |
7bedaa55 RK |
22 | |
23 | #include "virt-dma.h" | |
7d7e1eba | 24 | |
7bedaa55 RK |
25 | struct omap_dmadev { |
26 | struct dma_device ddev; | |
27 | spinlock_t lock; | |
28 | struct tasklet_struct task; | |
29 | struct list_head pending; | |
596c471b RK |
30 | void __iomem *base; |
31 | const struct omap_dma_reg *reg_map; | |
1b416c4b | 32 | struct omap_system_dma_plat_info *plat; |
6ddeb6d8 RK |
33 | bool legacy; |
34 | spinlock_t irq_lock; | |
35 | uint32_t irq_enable_mask; | |
36 | struct omap_chan *lch_map[32]; | |
7bedaa55 RK |
37 | }; |
38 | ||
39 | struct omap_chan { | |
40 | struct virt_dma_chan vc; | |
41 | struct list_head node; | |
596c471b RK |
42 | void __iomem *channel_base; |
43 | const struct omap_dma_reg *reg_map; | |
aa4c5b96 | 44 | uint32_t ccr; |
7bedaa55 RK |
45 | |
46 | struct dma_slave_config cfg; | |
47 | unsigned dma_sig; | |
3a774ea9 | 48 | bool cyclic; |
2dcdf570 | 49 | bool paused; |
7bedaa55 RK |
50 | |
51 | int dma_ch; | |
52 | struct omap_desc *desc; | |
53 | unsigned sgidx; | |
54 | }; | |
55 | ||
56 | struct omap_sg { | |
57 | dma_addr_t addr; | |
58 | uint32_t en; /* number of elements (24-bit) */ | |
59 | uint32_t fn; /* number of frames (16-bit) */ | |
60 | }; | |
61 | ||
62 | struct omap_desc { | |
63 | struct virt_dma_desc vd; | |
64 | enum dma_transfer_direction dir; | |
65 | dma_addr_t dev_addr; | |
66 | ||
7c836bc7 | 67 | int16_t fi; /* for OMAP_DMA_SYNC_PACKET */ |
9043826d | 68 | uint8_t es; /* CSDP_DATA_TYPE_xxx */ |
3ed4d18f | 69 | uint32_t ccr; /* CCR value */ |
965aeb4d | 70 | uint16_t clnk_ctrl; /* CLNK_CTRL value */ |
fa3ad86a | 71 | uint16_t cicr; /* CICR value */ |
2f0d13bd | 72 | uint32_t csdp; /* CSDP value */ |
7bedaa55 RK |
73 | |
74 | unsigned sglen; | |
75 | struct omap_sg sg[0]; | |
76 | }; | |
77 | ||
9043826d RK |
78 | enum { |
79 | CCR_FS = BIT(5), | |
80 | CCR_READ_PRIORITY = BIT(6), | |
81 | CCR_ENABLE = BIT(7), | |
82 | CCR_AUTO_INIT = BIT(8), /* OMAP1 only */ | |
83 | CCR_REPEAT = BIT(9), /* OMAP1 only */ | |
84 | CCR_OMAP31_DISABLE = BIT(10), /* OMAP1 only */ | |
85 | CCR_SUSPEND_SENSITIVE = BIT(8), /* OMAP2+ only */ | |
86 | CCR_RD_ACTIVE = BIT(9), /* OMAP2+ only */ | |
87 | CCR_WR_ACTIVE = BIT(10), /* OMAP2+ only */ | |
88 | CCR_SRC_AMODE_CONSTANT = 0 << 12, | |
89 | CCR_SRC_AMODE_POSTINC = 1 << 12, | |
90 | CCR_SRC_AMODE_SGLIDX = 2 << 12, | |
91 | CCR_SRC_AMODE_DBLIDX = 3 << 12, | |
92 | CCR_DST_AMODE_CONSTANT = 0 << 14, | |
93 | CCR_DST_AMODE_POSTINC = 1 << 14, | |
94 | CCR_DST_AMODE_SGLIDX = 2 << 14, | |
95 | CCR_DST_AMODE_DBLIDX = 3 << 14, | |
96 | CCR_CONSTANT_FILL = BIT(16), | |
97 | CCR_TRANSPARENT_COPY = BIT(17), | |
98 | CCR_BS = BIT(18), | |
99 | CCR_SUPERVISOR = BIT(22), | |
100 | CCR_PREFETCH = BIT(23), | |
101 | CCR_TRIGGER_SRC = BIT(24), | |
102 | CCR_BUFFERING_DISABLE = BIT(25), | |
103 | CCR_WRITE_PRIORITY = BIT(26), | |
104 | CCR_SYNC_ELEMENT = 0, | |
105 | CCR_SYNC_FRAME = CCR_FS, | |
106 | CCR_SYNC_BLOCK = CCR_BS, | |
107 | CCR_SYNC_PACKET = CCR_BS | CCR_FS, | |
108 | ||
109 | CSDP_DATA_TYPE_8 = 0, | |
110 | CSDP_DATA_TYPE_16 = 1, | |
111 | CSDP_DATA_TYPE_32 = 2, | |
112 | CSDP_SRC_PORT_EMIFF = 0 << 2, /* OMAP1 only */ | |
113 | CSDP_SRC_PORT_EMIFS = 1 << 2, /* OMAP1 only */ | |
114 | CSDP_SRC_PORT_OCP_T1 = 2 << 2, /* OMAP1 only */ | |
115 | CSDP_SRC_PORT_TIPB = 3 << 2, /* OMAP1 only */ | |
116 | CSDP_SRC_PORT_OCP_T2 = 4 << 2, /* OMAP1 only */ | |
117 | CSDP_SRC_PORT_MPUI = 5 << 2, /* OMAP1 only */ | |
118 | CSDP_SRC_PACKED = BIT(6), | |
119 | CSDP_SRC_BURST_1 = 0 << 7, | |
120 | CSDP_SRC_BURST_16 = 1 << 7, | |
121 | CSDP_SRC_BURST_32 = 2 << 7, | |
122 | CSDP_SRC_BURST_64 = 3 << 7, | |
123 | CSDP_DST_PORT_EMIFF = 0 << 9, /* OMAP1 only */ | |
124 | CSDP_DST_PORT_EMIFS = 1 << 9, /* OMAP1 only */ | |
125 | CSDP_DST_PORT_OCP_T1 = 2 << 9, /* OMAP1 only */ | |
126 | CSDP_DST_PORT_TIPB = 3 << 9, /* OMAP1 only */ | |
127 | CSDP_DST_PORT_OCP_T2 = 4 << 9, /* OMAP1 only */ | |
128 | CSDP_DST_PORT_MPUI = 5 << 9, /* OMAP1 only */ | |
129 | CSDP_DST_PACKED = BIT(13), | |
130 | CSDP_DST_BURST_1 = 0 << 14, | |
131 | CSDP_DST_BURST_16 = 1 << 14, | |
132 | CSDP_DST_BURST_32 = 2 << 14, | |
133 | CSDP_DST_BURST_64 = 3 << 14, | |
134 | ||
135 | CICR_TOUT_IE = BIT(0), /* OMAP1 only */ | |
136 | CICR_DROP_IE = BIT(1), | |
137 | CICR_HALF_IE = BIT(2), | |
138 | CICR_FRAME_IE = BIT(3), | |
139 | CICR_LAST_IE = BIT(4), | |
140 | CICR_BLOCK_IE = BIT(5), | |
141 | CICR_PKT_IE = BIT(7), /* OMAP2+ only */ | |
142 | CICR_TRANS_ERR_IE = BIT(8), /* OMAP2+ only */ | |
143 | CICR_SUPERVISOR_ERR_IE = BIT(10), /* OMAP2+ only */ | |
144 | CICR_MISALIGNED_ERR_IE = BIT(11), /* OMAP2+ only */ | |
145 | CICR_DRAIN_IE = BIT(12), /* OMAP2+ only */ | |
146 | CICR_SUPER_BLOCK_IE = BIT(14), /* OMAP2+ only */ | |
147 | ||
148 | CLNK_CTRL_ENABLE_LNK = BIT(15), | |
149 | }; | |
150 | ||
7bedaa55 | 151 | static const unsigned es_bytes[] = { |
9043826d RK |
152 | [CSDP_DATA_TYPE_8] = 1, |
153 | [CSDP_DATA_TYPE_16] = 2, | |
154 | [CSDP_DATA_TYPE_32] = 4, | |
7bedaa55 RK |
155 | }; |
156 | ||
8d30662a JH |
157 | static struct of_dma_filter_info omap_dma_info = { |
158 | .filter_fn = omap_dma_filter_fn, | |
159 | }; | |
160 | ||
7bedaa55 RK |
161 | static inline struct omap_dmadev *to_omap_dma_dev(struct dma_device *d) |
162 | { | |
163 | return container_of(d, struct omap_dmadev, ddev); | |
164 | } | |
165 | ||
166 | static inline struct omap_chan *to_omap_dma_chan(struct dma_chan *c) | |
167 | { | |
168 | return container_of(c, struct omap_chan, vc.chan); | |
169 | } | |
170 | ||
171 | static inline struct omap_desc *to_omap_dma_desc(struct dma_async_tx_descriptor *t) | |
172 | { | |
173 | return container_of(t, struct omap_desc, vd.tx); | |
174 | } | |
175 | ||
176 | static void omap_dma_desc_free(struct virt_dma_desc *vd) | |
177 | { | |
178 | kfree(container_of(vd, struct omap_desc, vd)); | |
179 | } | |
180 | ||
596c471b RK |
181 | static void omap_dma_write(uint32_t val, unsigned type, void __iomem *addr) |
182 | { | |
183 | switch (type) { | |
184 | case OMAP_DMA_REG_16BIT: | |
185 | writew_relaxed(val, addr); | |
186 | break; | |
187 | case OMAP_DMA_REG_2X16BIT: | |
188 | writew_relaxed(val, addr); | |
189 | writew_relaxed(val >> 16, addr + 2); | |
190 | break; | |
191 | case OMAP_DMA_REG_32BIT: | |
192 | writel_relaxed(val, addr); | |
193 | break; | |
194 | default: | |
195 | WARN_ON(1); | |
196 | } | |
197 | } | |
198 | ||
199 | static unsigned omap_dma_read(unsigned type, void __iomem *addr) | |
200 | { | |
201 | unsigned val; | |
202 | ||
203 | switch (type) { | |
204 | case OMAP_DMA_REG_16BIT: | |
205 | val = readw_relaxed(addr); | |
206 | break; | |
207 | case OMAP_DMA_REG_2X16BIT: | |
208 | val = readw_relaxed(addr); | |
209 | val |= readw_relaxed(addr + 2) << 16; | |
210 | break; | |
211 | case OMAP_DMA_REG_32BIT: | |
212 | val = readl_relaxed(addr); | |
213 | break; | |
214 | default: | |
215 | WARN_ON(1); | |
216 | val = 0; | |
217 | } | |
218 | ||
219 | return val; | |
220 | } | |
221 | ||
c5ed98b6 RK |
222 | static void omap_dma_glbl_write(struct omap_dmadev *od, unsigned reg, unsigned val) |
223 | { | |
596c471b RK |
224 | const struct omap_dma_reg *r = od->reg_map + reg; |
225 | ||
226 | WARN_ON(r->stride); | |
227 | ||
228 | omap_dma_write(val, r->type, od->base + r->offset); | |
c5ed98b6 RK |
229 | } |
230 | ||
231 | static unsigned omap_dma_glbl_read(struct omap_dmadev *od, unsigned reg) | |
232 | { | |
596c471b RK |
233 | const struct omap_dma_reg *r = od->reg_map + reg; |
234 | ||
235 | WARN_ON(r->stride); | |
236 | ||
237 | return omap_dma_read(r->type, od->base + r->offset); | |
c5ed98b6 RK |
238 | } |
239 | ||
240 | static void omap_dma_chan_write(struct omap_chan *c, unsigned reg, unsigned val) | |
241 | { | |
596c471b RK |
242 | const struct omap_dma_reg *r = c->reg_map + reg; |
243 | ||
244 | omap_dma_write(val, r->type, c->channel_base + r->offset); | |
c5ed98b6 RK |
245 | } |
246 | ||
247 | static unsigned omap_dma_chan_read(struct omap_chan *c, unsigned reg) | |
248 | { | |
596c471b RK |
249 | const struct omap_dma_reg *r = c->reg_map + reg; |
250 | ||
251 | return omap_dma_read(r->type, c->channel_base + r->offset); | |
c5ed98b6 RK |
252 | } |
253 | ||
470b23f7 RK |
254 | static void omap_dma_clear_csr(struct omap_chan *c) |
255 | { | |
256 | if (dma_omap1()) | |
c5ed98b6 | 257 | omap_dma_chan_read(c, CSR); |
470b23f7 | 258 | else |
c5ed98b6 | 259 | omap_dma_chan_write(c, CSR, ~0); |
470b23f7 RK |
260 | } |
261 | ||
6ddeb6d8 RK |
262 | static unsigned omap_dma_get_csr(struct omap_chan *c) |
263 | { | |
264 | unsigned val = omap_dma_chan_read(c, CSR); | |
265 | ||
266 | if (!dma_omap1()) | |
267 | omap_dma_chan_write(c, CSR, val); | |
268 | ||
269 | return val; | |
270 | } | |
271 | ||
596c471b RK |
272 | static void omap_dma_assign(struct omap_dmadev *od, struct omap_chan *c, |
273 | unsigned lch) | |
274 | { | |
275 | c->channel_base = od->base + od->plat->channel_stride * lch; | |
6ddeb6d8 RK |
276 | |
277 | od->lch_map[lch] = c; | |
596c471b RK |
278 | } |
279 | ||
fa3ad86a RK |
280 | static void omap_dma_start(struct omap_chan *c, struct omap_desc *d) |
281 | { | |
282 | struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device); | |
fa3ad86a RK |
283 | |
284 | if (__dma_omap15xx(od->plat->dma_attr)) | |
c5ed98b6 | 285 | omap_dma_chan_write(c, CPC, 0); |
fa3ad86a | 286 | else |
c5ed98b6 | 287 | omap_dma_chan_write(c, CDAC, 0); |
fa3ad86a | 288 | |
470b23f7 | 289 | omap_dma_clear_csr(c); |
fa3ad86a RK |
290 | |
291 | /* Enable interrupts */ | |
c5ed98b6 | 292 | omap_dma_chan_write(c, CICR, d->cicr); |
fa3ad86a | 293 | |
45da7b04 | 294 | /* Enable channel */ |
c5ed98b6 | 295 | omap_dma_chan_write(c, CCR, d->ccr | CCR_ENABLE); |
fa3ad86a RK |
296 | } |
297 | ||
298 | static void omap_dma_stop(struct omap_chan *c) | |
299 | { | |
300 | struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device); | |
301 | uint32_t val; | |
302 | ||
303 | /* disable irq */ | |
c5ed98b6 | 304 | omap_dma_chan_write(c, CICR, 0); |
fa3ad86a | 305 | |
470b23f7 | 306 | omap_dma_clear_csr(c); |
fa3ad86a | 307 | |
c5ed98b6 | 308 | val = omap_dma_chan_read(c, CCR); |
9043826d | 309 | if (od->plat->errata & DMA_ERRATA_i541 && val & CCR_TRIGGER_SRC) { |
fa3ad86a RK |
310 | uint32_t sysconfig; |
311 | unsigned i; | |
312 | ||
c5ed98b6 | 313 | sysconfig = omap_dma_glbl_read(od, OCP_SYSCONFIG); |
fa3ad86a RK |
314 | val = sysconfig & ~DMA_SYSCONFIG_MIDLEMODE_MASK; |
315 | val |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE); | |
c5ed98b6 | 316 | omap_dma_glbl_write(od, OCP_SYSCONFIG, val); |
fa3ad86a | 317 | |
c5ed98b6 | 318 | val = omap_dma_chan_read(c, CCR); |
9043826d | 319 | val &= ~CCR_ENABLE; |
c5ed98b6 | 320 | omap_dma_chan_write(c, CCR, val); |
fa3ad86a RK |
321 | |
322 | /* Wait for sDMA FIFO to drain */ | |
323 | for (i = 0; ; i++) { | |
c5ed98b6 | 324 | val = omap_dma_chan_read(c, CCR); |
9043826d | 325 | if (!(val & (CCR_RD_ACTIVE | CCR_WR_ACTIVE))) |
fa3ad86a RK |
326 | break; |
327 | ||
328 | if (i > 100) | |
329 | break; | |
330 | ||
331 | udelay(5); | |
332 | } | |
333 | ||
9043826d | 334 | if (val & (CCR_RD_ACTIVE | CCR_WR_ACTIVE)) |
fa3ad86a RK |
335 | dev_err(c->vc.chan.device->dev, |
336 | "DMA drain did not complete on lch %d\n", | |
337 | c->dma_ch); | |
338 | ||
c5ed98b6 | 339 | omap_dma_glbl_write(od, OCP_SYSCONFIG, sysconfig); |
fa3ad86a | 340 | } else { |
9043826d | 341 | val &= ~CCR_ENABLE; |
c5ed98b6 | 342 | omap_dma_chan_write(c, CCR, val); |
fa3ad86a RK |
343 | } |
344 | ||
345 | mb(); | |
346 | ||
347 | if (!__dma_omap15xx(od->plat->dma_attr) && c->cyclic) { | |
c5ed98b6 | 348 | val = omap_dma_chan_read(c, CLNK_CTRL); |
fa3ad86a RK |
349 | |
350 | if (dma_omap1()) | |
351 | val |= 1 << 14; /* set the STOP_LNK bit */ | |
352 | else | |
9043826d | 353 | val &= ~CLNK_CTRL_ENABLE_LNK; |
fa3ad86a | 354 | |
c5ed98b6 | 355 | omap_dma_chan_write(c, CLNK_CTRL, val); |
fa3ad86a RK |
356 | } |
357 | } | |
358 | ||
7bedaa55 RK |
359 | static void omap_dma_start_sg(struct omap_chan *c, struct omap_desc *d, |
360 | unsigned idx) | |
361 | { | |
362 | struct omap_sg *sg = d->sg + idx; | |
893e63e3 | 363 | unsigned cxsa, cxei, cxfi; |
913a2d0c RK |
364 | |
365 | if (d->dir == DMA_DEV_TO_MEM) { | |
893e63e3 RK |
366 | cxsa = CDSA; |
367 | cxei = CDEI; | |
368 | cxfi = CDFI; | |
913a2d0c | 369 | } else { |
893e63e3 RK |
370 | cxsa = CSSA; |
371 | cxei = CSEI; | |
372 | cxfi = CSFI; | |
913a2d0c RK |
373 | } |
374 | ||
c5ed98b6 RK |
375 | omap_dma_chan_write(c, cxsa, sg->addr); |
376 | omap_dma_chan_write(c, cxei, 0); | |
377 | omap_dma_chan_write(c, cxfi, 0); | |
378 | omap_dma_chan_write(c, CEN, sg->en); | |
379 | omap_dma_chan_write(c, CFN, sg->fn); | |
913a2d0c | 380 | |
fa3ad86a | 381 | omap_dma_start(c, d); |
913a2d0c RK |
382 | } |
383 | ||
384 | static void omap_dma_start_desc(struct omap_chan *c) | |
385 | { | |
386 | struct virt_dma_desc *vd = vchan_next_desc(&c->vc); | |
387 | struct omap_desc *d; | |
893e63e3 | 388 | unsigned cxsa, cxei, cxfi; |
b9e97822 | 389 | |
913a2d0c RK |
390 | if (!vd) { |
391 | c->desc = NULL; | |
392 | return; | |
393 | } | |
394 | ||
395 | list_del(&vd->node); | |
396 | ||
397 | c->desc = d = to_omap_dma_desc(&vd->tx); | |
398 | c->sgidx = 0; | |
399 | ||
59871902 RK |
400 | /* |
401 | * This provides the necessary barrier to ensure data held in | |
402 | * DMA coherent memory is visible to the DMA engine prior to | |
403 | * the transfer starting. | |
404 | */ | |
405 | mb(); | |
406 | ||
c5ed98b6 | 407 | omap_dma_chan_write(c, CCR, d->ccr); |
3ed4d18f | 408 | if (dma_omap1()) |
c5ed98b6 | 409 | omap_dma_chan_write(c, CCR2, d->ccr >> 16); |
b9e97822 | 410 | |
3ed4d18f | 411 | if (d->dir == DMA_DEV_TO_MEM) { |
893e63e3 RK |
412 | cxsa = CSSA; |
413 | cxei = CSEI; | |
414 | cxfi = CSFI; | |
b9e97822 | 415 | } else { |
893e63e3 RK |
416 | cxsa = CDSA; |
417 | cxei = CDEI; | |
418 | cxfi = CDFI; | |
b9e97822 RK |
419 | } |
420 | ||
c5ed98b6 RK |
421 | omap_dma_chan_write(c, cxsa, d->dev_addr); |
422 | omap_dma_chan_write(c, cxei, 0); | |
423 | omap_dma_chan_write(c, cxfi, d->fi); | |
424 | omap_dma_chan_write(c, CSDP, d->csdp); | |
425 | omap_dma_chan_write(c, CLNK_CTRL, d->clnk_ctrl); | |
b9e97822 | 426 | |
7bedaa55 RK |
427 | omap_dma_start_sg(c, d, 0); |
428 | } | |
429 | ||
430 | static void omap_dma_callback(int ch, u16 status, void *data) | |
431 | { | |
432 | struct omap_chan *c = data; | |
433 | struct omap_desc *d; | |
434 | unsigned long flags; | |
435 | ||
436 | spin_lock_irqsave(&c->vc.lock, flags); | |
437 | d = c->desc; | |
438 | if (d) { | |
3a774ea9 RK |
439 | if (!c->cyclic) { |
440 | if (++c->sgidx < d->sglen) { | |
441 | omap_dma_start_sg(c, d, c->sgidx); | |
442 | } else { | |
443 | omap_dma_start_desc(c); | |
444 | vchan_cookie_complete(&d->vd); | |
445 | } | |
7bedaa55 | 446 | } else { |
3a774ea9 | 447 | vchan_cyclic_callback(&d->vd); |
7bedaa55 RK |
448 | } |
449 | } | |
450 | spin_unlock_irqrestore(&c->vc.lock, flags); | |
451 | } | |
452 | ||
453 | /* | |
454 | * This callback schedules all pending channels. We could be more | |
455 | * clever here by postponing allocation of the real DMA channels to | |
456 | * this point, and freeing them when our virtual channel becomes idle. | |
457 | * | |
458 | * We would then need to deal with 'all channels in-use' | |
459 | */ | |
460 | static void omap_dma_sched(unsigned long data) | |
461 | { | |
462 | struct omap_dmadev *d = (struct omap_dmadev *)data; | |
463 | LIST_HEAD(head); | |
464 | ||
465 | spin_lock_irq(&d->lock); | |
466 | list_splice_tail_init(&d->pending, &head); | |
467 | spin_unlock_irq(&d->lock); | |
468 | ||
469 | while (!list_empty(&head)) { | |
470 | struct omap_chan *c = list_first_entry(&head, | |
471 | struct omap_chan, node); | |
472 | ||
473 | spin_lock_irq(&c->vc.lock); | |
474 | list_del_init(&c->node); | |
475 | omap_dma_start_desc(c); | |
476 | spin_unlock_irq(&c->vc.lock); | |
477 | } | |
478 | } | |
479 | ||
6ddeb6d8 RK |
480 | static irqreturn_t omap_dma_irq(int irq, void *devid) |
481 | { | |
482 | struct omap_dmadev *od = devid; | |
483 | unsigned status, channel; | |
484 | ||
485 | spin_lock(&od->irq_lock); | |
486 | ||
487 | status = omap_dma_glbl_read(od, IRQSTATUS_L1); | |
488 | status &= od->irq_enable_mask; | |
489 | if (status == 0) { | |
490 | spin_unlock(&od->irq_lock); | |
491 | return IRQ_NONE; | |
492 | } | |
493 | ||
494 | while ((channel = ffs(status)) != 0) { | |
495 | unsigned mask, csr; | |
496 | struct omap_chan *c; | |
497 | ||
498 | channel -= 1; | |
499 | mask = BIT(channel); | |
500 | status &= ~mask; | |
501 | ||
502 | c = od->lch_map[channel]; | |
503 | if (c == NULL) { | |
504 | /* This should never happen */ | |
505 | dev_err(od->ddev.dev, "invalid channel %u\n", channel); | |
506 | continue; | |
507 | } | |
508 | ||
509 | csr = omap_dma_get_csr(c); | |
510 | omap_dma_glbl_write(od, IRQSTATUS_L1, mask); | |
511 | ||
512 | omap_dma_callback(channel, csr, c); | |
513 | } | |
514 | ||
515 | spin_unlock(&od->irq_lock); | |
516 | ||
517 | return IRQ_HANDLED; | |
518 | } | |
519 | ||
7bedaa55 RK |
520 | static int omap_dma_alloc_chan_resources(struct dma_chan *chan) |
521 | { | |
596c471b | 522 | struct omap_dmadev *od = to_omap_dma_dev(chan->device); |
7bedaa55 | 523 | struct omap_chan *c = to_omap_dma_chan(chan); |
596c471b RK |
524 | int ret; |
525 | ||
6ddeb6d8 RK |
526 | if (od->legacy) { |
527 | ret = omap_request_dma(c->dma_sig, "DMA engine", | |
528 | omap_dma_callback, c, &c->dma_ch); | |
529 | } else { | |
530 | ret = omap_request_dma(c->dma_sig, "DMA engine", NULL, NULL, | |
531 | &c->dma_ch); | |
532 | } | |
7bedaa55 | 533 | |
6ddeb6d8 RK |
534 | dev_dbg(od->ddev.dev, "allocating channel %u for %u\n", |
535 | c->dma_ch, c->dma_sig); | |
7bedaa55 | 536 | |
6ddeb6d8 | 537 | if (ret >= 0) { |
596c471b RK |
538 | omap_dma_assign(od, c, c->dma_ch); |
539 | ||
6ddeb6d8 RK |
540 | if (!od->legacy) { |
541 | unsigned val; | |
542 | ||
543 | spin_lock_irq(&od->irq_lock); | |
544 | val = BIT(c->dma_ch); | |
545 | omap_dma_glbl_write(od, IRQSTATUS_L1, val); | |
546 | od->irq_enable_mask |= val; | |
547 | omap_dma_glbl_write(od, IRQENABLE_L1, od->irq_enable_mask); | |
548 | ||
549 | val = omap_dma_glbl_read(od, IRQENABLE_L0); | |
550 | val &= ~BIT(c->dma_ch); | |
551 | omap_dma_glbl_write(od, IRQENABLE_L0, val); | |
552 | spin_unlock_irq(&od->irq_lock); | |
553 | } | |
554 | } | |
555 | ||
aa4c5b96 RK |
556 | if (dma_omap1()) { |
557 | if (__dma_omap16xx(od->plat->dma_attr)) { | |
558 | c->ccr = CCR_OMAP31_DISABLE; | |
559 | /* Duplicate what plat-omap/dma.c does */ | |
560 | c->ccr |= c->dma_ch + 1; | |
561 | } else { | |
562 | c->ccr = c->dma_sig & 0x1f; | |
563 | } | |
564 | } else { | |
565 | c->ccr = c->dma_sig & 0x1f; | |
566 | c->ccr |= (c->dma_sig & ~0x1f) << 14; | |
567 | } | |
568 | if (od->plat->errata & DMA_ERRATA_IFRAME_BUFFERING) | |
569 | c->ccr |= CCR_BUFFERING_DISABLE; | |
570 | ||
596c471b | 571 | return ret; |
7bedaa55 RK |
572 | } |
573 | ||
574 | static void omap_dma_free_chan_resources(struct dma_chan *chan) | |
575 | { | |
6ddeb6d8 | 576 | struct omap_dmadev *od = to_omap_dma_dev(chan->device); |
7bedaa55 RK |
577 | struct omap_chan *c = to_omap_dma_chan(chan); |
578 | ||
6ddeb6d8 RK |
579 | if (!od->legacy) { |
580 | spin_lock_irq(&od->irq_lock); | |
581 | od->irq_enable_mask &= ~BIT(c->dma_ch); | |
582 | omap_dma_glbl_write(od, IRQENABLE_L1, od->irq_enable_mask); | |
583 | spin_unlock_irq(&od->irq_lock); | |
584 | } | |
585 | ||
596c471b | 586 | c->channel_base = NULL; |
6ddeb6d8 | 587 | od->lch_map[c->dma_ch] = NULL; |
7bedaa55 RK |
588 | vchan_free_chan_resources(&c->vc); |
589 | omap_free_dma(c->dma_ch); | |
590 | ||
6ddeb6d8 | 591 | dev_dbg(od->ddev.dev, "freeing channel for %u\n", c->dma_sig); |
7bedaa55 RK |
592 | } |
593 | ||
3850e22f RK |
594 | static size_t omap_dma_sg_size(struct omap_sg *sg) |
595 | { | |
596 | return sg->en * sg->fn; | |
597 | } | |
598 | ||
599 | static size_t omap_dma_desc_size(struct omap_desc *d) | |
600 | { | |
601 | unsigned i; | |
602 | size_t size; | |
603 | ||
604 | for (size = i = 0; i < d->sglen; i++) | |
605 | size += omap_dma_sg_size(&d->sg[i]); | |
606 | ||
607 | return size * es_bytes[d->es]; | |
608 | } | |
609 | ||
610 | static size_t omap_dma_desc_size_pos(struct omap_desc *d, dma_addr_t addr) | |
611 | { | |
612 | unsigned i; | |
613 | size_t size, es_size = es_bytes[d->es]; | |
614 | ||
615 | for (size = i = 0; i < d->sglen; i++) { | |
616 | size_t this_size = omap_dma_sg_size(&d->sg[i]) * es_size; | |
617 | ||
618 | if (size) | |
619 | size += this_size; | |
620 | else if (addr >= d->sg[i].addr && | |
621 | addr < d->sg[i].addr + this_size) | |
622 | size += d->sg[i].addr + this_size - addr; | |
623 | } | |
624 | return size; | |
625 | } | |
626 | ||
b07fd625 RK |
627 | /* |
628 | * OMAP 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is | |
629 | * read before the DMA controller finished disabling the channel. | |
630 | */ | |
631 | static uint32_t omap_dma_chan_read_3_3(struct omap_chan *c, unsigned reg) | |
632 | { | |
633 | struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device); | |
634 | uint32_t val; | |
635 | ||
636 | val = omap_dma_chan_read(c, reg); | |
637 | if (val == 0 && od->plat->errata & DMA_ERRATA_3_3) | |
638 | val = omap_dma_chan_read(c, reg); | |
639 | ||
640 | return val; | |
641 | } | |
642 | ||
3997cab3 RK |
643 | static dma_addr_t omap_dma_get_src_pos(struct omap_chan *c) |
644 | { | |
645 | struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device); | |
b07fd625 | 646 | dma_addr_t addr, cdac; |
3997cab3 | 647 | |
b07fd625 | 648 | if (__dma_omap15xx(od->plat->dma_attr)) { |
c5ed98b6 | 649 | addr = omap_dma_chan_read(c, CPC); |
b07fd625 RK |
650 | } else { |
651 | addr = omap_dma_chan_read_3_3(c, CSAC); | |
652 | cdac = omap_dma_chan_read_3_3(c, CDAC); | |
3997cab3 | 653 | |
3997cab3 RK |
654 | /* |
655 | * CDAC == 0 indicates that the DMA transfer on the channel has | |
656 | * not been started (no data has been transferred so far). | |
657 | * Return the programmed source start address in this case. | |
658 | */ | |
b07fd625 | 659 | if (cdac == 0) |
c5ed98b6 | 660 | addr = omap_dma_chan_read(c, CSSA); |
3997cab3 RK |
661 | } |
662 | ||
663 | if (dma_omap1()) | |
c5ed98b6 | 664 | addr |= omap_dma_chan_read(c, CSSA) & 0xffff0000; |
3997cab3 RK |
665 | |
666 | return addr; | |
667 | } | |
668 | ||
669 | static dma_addr_t omap_dma_get_dst_pos(struct omap_chan *c) | |
670 | { | |
671 | struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device); | |
672 | dma_addr_t addr; | |
673 | ||
b07fd625 | 674 | if (__dma_omap15xx(od->plat->dma_attr)) { |
c5ed98b6 | 675 | addr = omap_dma_chan_read(c, CPC); |
b07fd625 RK |
676 | } else { |
677 | addr = omap_dma_chan_read_3_3(c, CDAC); | |
3997cab3 | 678 | |
3997cab3 | 679 | /* |
b07fd625 RK |
680 | * CDAC == 0 indicates that the DMA transfer on the channel |
681 | * has not been started (no data has been transferred so | |
682 | * far). Return the programmed destination start address in | |
683 | * this case. | |
3997cab3 RK |
684 | */ |
685 | if (addr == 0) | |
c5ed98b6 | 686 | addr = omap_dma_chan_read(c, CDSA); |
3997cab3 RK |
687 | } |
688 | ||
689 | if (dma_omap1()) | |
c5ed98b6 | 690 | addr |= omap_dma_chan_read(c, CDSA) & 0xffff0000; |
3997cab3 RK |
691 | |
692 | return addr; | |
693 | } | |
694 | ||
7bedaa55 RK |
695 | static enum dma_status omap_dma_tx_status(struct dma_chan *chan, |
696 | dma_cookie_t cookie, struct dma_tx_state *txstate) | |
697 | { | |
3850e22f RK |
698 | struct omap_chan *c = to_omap_dma_chan(chan); |
699 | struct virt_dma_desc *vd; | |
700 | enum dma_status ret; | |
701 | unsigned long flags; | |
702 | ||
703 | ret = dma_cookie_status(chan, cookie, txstate); | |
7cce5083 | 704 | if (ret == DMA_COMPLETE || !txstate) |
3850e22f RK |
705 | return ret; |
706 | ||
707 | spin_lock_irqsave(&c->vc.lock, flags); | |
708 | vd = vchan_find_desc(&c->vc, cookie); | |
709 | if (vd) { | |
710 | txstate->residue = omap_dma_desc_size(to_omap_dma_desc(&vd->tx)); | |
711 | } else if (c->desc && c->desc->vd.tx.cookie == cookie) { | |
712 | struct omap_desc *d = c->desc; | |
713 | dma_addr_t pos; | |
714 | ||
715 | if (d->dir == DMA_MEM_TO_DEV) | |
3997cab3 | 716 | pos = omap_dma_get_src_pos(c); |
3850e22f | 717 | else if (d->dir == DMA_DEV_TO_MEM) |
3997cab3 | 718 | pos = omap_dma_get_dst_pos(c); |
3850e22f RK |
719 | else |
720 | pos = 0; | |
721 | ||
722 | txstate->residue = omap_dma_desc_size_pos(d, pos); | |
723 | } else { | |
724 | txstate->residue = 0; | |
725 | } | |
726 | spin_unlock_irqrestore(&c->vc.lock, flags); | |
727 | ||
728 | return ret; | |
7bedaa55 RK |
729 | } |
730 | ||
731 | static void omap_dma_issue_pending(struct dma_chan *chan) | |
732 | { | |
733 | struct omap_chan *c = to_omap_dma_chan(chan); | |
734 | unsigned long flags; | |
735 | ||
736 | spin_lock_irqsave(&c->vc.lock, flags); | |
737 | if (vchan_issue_pending(&c->vc) && !c->desc) { | |
76502469 PU |
738 | /* |
739 | * c->cyclic is used only by audio and in this case the DMA need | |
740 | * to be started without delay. | |
741 | */ | |
742 | if (!c->cyclic) { | |
743 | struct omap_dmadev *d = to_omap_dma_dev(chan->device); | |
744 | spin_lock(&d->lock); | |
745 | if (list_empty(&c->node)) | |
746 | list_add_tail(&c->node, &d->pending); | |
747 | spin_unlock(&d->lock); | |
748 | tasklet_schedule(&d->task); | |
749 | } else { | |
750 | omap_dma_start_desc(c); | |
751 | } | |
7bedaa55 RK |
752 | } |
753 | spin_unlock_irqrestore(&c->vc.lock, flags); | |
754 | } | |
755 | ||
756 | static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg( | |
757 | struct dma_chan *chan, struct scatterlist *sgl, unsigned sglen, | |
758 | enum dma_transfer_direction dir, unsigned long tx_flags, void *context) | |
759 | { | |
49ae0b29 | 760 | struct omap_dmadev *od = to_omap_dma_dev(chan->device); |
7bedaa55 RK |
761 | struct omap_chan *c = to_omap_dma_chan(chan); |
762 | enum dma_slave_buswidth dev_width; | |
763 | struct scatterlist *sgent; | |
764 | struct omap_desc *d; | |
765 | dma_addr_t dev_addr; | |
3ed4d18f | 766 | unsigned i, j = 0, es, en, frame_bytes; |
7bedaa55 RK |
767 | u32 burst; |
768 | ||
769 | if (dir == DMA_DEV_TO_MEM) { | |
770 | dev_addr = c->cfg.src_addr; | |
771 | dev_width = c->cfg.src_addr_width; | |
772 | burst = c->cfg.src_maxburst; | |
7bedaa55 RK |
773 | } else if (dir == DMA_MEM_TO_DEV) { |
774 | dev_addr = c->cfg.dst_addr; | |
775 | dev_width = c->cfg.dst_addr_width; | |
776 | burst = c->cfg.dst_maxburst; | |
7bedaa55 RK |
777 | } else { |
778 | dev_err(chan->device->dev, "%s: bad direction?\n", __func__); | |
779 | return NULL; | |
780 | } | |
781 | ||
782 | /* Bus width translates to the element size (ES) */ | |
783 | switch (dev_width) { | |
784 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
9043826d | 785 | es = CSDP_DATA_TYPE_8; |
7bedaa55 RK |
786 | break; |
787 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
9043826d | 788 | es = CSDP_DATA_TYPE_16; |
7bedaa55 RK |
789 | break; |
790 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
9043826d | 791 | es = CSDP_DATA_TYPE_32; |
7bedaa55 RK |
792 | break; |
793 | default: /* not reached */ | |
794 | return NULL; | |
795 | } | |
796 | ||
797 | /* Now allocate and setup the descriptor. */ | |
798 | d = kzalloc(sizeof(*d) + sglen * sizeof(d->sg[0]), GFP_ATOMIC); | |
799 | if (!d) | |
800 | return NULL; | |
801 | ||
802 | d->dir = dir; | |
803 | d->dev_addr = dev_addr; | |
804 | d->es = es; | |
3ed4d18f | 805 | |
aa4c5b96 | 806 | d->ccr = c->ccr | CCR_SYNC_FRAME; |
3ed4d18f | 807 | if (dir == DMA_DEV_TO_MEM) |
9043826d | 808 | d->ccr |= CCR_DST_AMODE_POSTINC | CCR_SRC_AMODE_CONSTANT; |
3ed4d18f | 809 | else |
9043826d | 810 | d->ccr |= CCR_DST_AMODE_CONSTANT | CCR_SRC_AMODE_POSTINC; |
3ed4d18f | 811 | |
9043826d | 812 | d->cicr = CICR_DROP_IE | CICR_BLOCK_IE; |
2f0d13bd | 813 | d->csdp = es; |
fa3ad86a | 814 | |
2f0d13bd | 815 | if (dma_omap1()) { |
9043826d | 816 | d->cicr |= CICR_TOUT_IE; |
2f0d13bd RK |
817 | |
818 | if (dir == DMA_DEV_TO_MEM) | |
9043826d | 819 | d->csdp |= CSDP_DST_PORT_EMIFF | CSDP_SRC_PORT_TIPB; |
2f0d13bd | 820 | else |
9043826d | 821 | d->csdp |= CSDP_DST_PORT_TIPB | CSDP_SRC_PORT_EMIFF; |
2f0d13bd | 822 | } else { |
3ed4d18f | 823 | if (dir == DMA_DEV_TO_MEM) |
9043826d | 824 | d->ccr |= CCR_TRIGGER_SRC; |
3ed4d18f | 825 | |
9043826d | 826 | d->cicr |= CICR_MISALIGNED_ERR_IE | CICR_TRANS_ERR_IE; |
2f0d13bd | 827 | } |
965aeb4d RK |
828 | if (od->plat->errata & DMA_ERRATA_PARALLEL_CHANNELS) |
829 | d->clnk_ctrl = c->dma_ch; | |
7bedaa55 RK |
830 | |
831 | /* | |
832 | * Build our scatterlist entries: each contains the address, | |
833 | * the number of elements (EN) in each frame, and the number of | |
834 | * frames (FN). Number of bytes for this entry = ES * EN * FN. | |
835 | * | |
836 | * Burst size translates to number of elements with frame sync. | |
837 | * Note: DMA engine defines burst to be the number of dev-width | |
838 | * transfers. | |
839 | */ | |
840 | en = burst; | |
841 | frame_bytes = es_bytes[es] * en; | |
842 | for_each_sg(sgl, sgent, sglen, i) { | |
843 | d->sg[j].addr = sg_dma_address(sgent); | |
844 | d->sg[j].en = en; | |
845 | d->sg[j].fn = sg_dma_len(sgent) / frame_bytes; | |
846 | j++; | |
847 | } | |
848 | ||
849 | d->sglen = j; | |
850 | ||
851 | return vchan_tx_prep(&c->vc, &d->vd, tx_flags); | |
852 | } | |
853 | ||
3a774ea9 RK |
854 | static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic( |
855 | struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, | |
31c1e5a1 | 856 | size_t period_len, enum dma_transfer_direction dir, unsigned long flags) |
3a774ea9 | 857 | { |
fa3ad86a | 858 | struct omap_dmadev *od = to_omap_dma_dev(chan->device); |
3a774ea9 RK |
859 | struct omap_chan *c = to_omap_dma_chan(chan); |
860 | enum dma_slave_buswidth dev_width; | |
861 | struct omap_desc *d; | |
862 | dma_addr_t dev_addr; | |
3ed4d18f | 863 | unsigned es; |
3a774ea9 RK |
864 | u32 burst; |
865 | ||
866 | if (dir == DMA_DEV_TO_MEM) { | |
867 | dev_addr = c->cfg.src_addr; | |
868 | dev_width = c->cfg.src_addr_width; | |
869 | burst = c->cfg.src_maxburst; | |
3a774ea9 RK |
870 | } else if (dir == DMA_MEM_TO_DEV) { |
871 | dev_addr = c->cfg.dst_addr; | |
872 | dev_width = c->cfg.dst_addr_width; | |
873 | burst = c->cfg.dst_maxburst; | |
3a774ea9 RK |
874 | } else { |
875 | dev_err(chan->device->dev, "%s: bad direction?\n", __func__); | |
876 | return NULL; | |
877 | } | |
878 | ||
879 | /* Bus width translates to the element size (ES) */ | |
880 | switch (dev_width) { | |
881 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
9043826d | 882 | es = CSDP_DATA_TYPE_8; |
3a774ea9 RK |
883 | break; |
884 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
9043826d | 885 | es = CSDP_DATA_TYPE_16; |
3a774ea9 RK |
886 | break; |
887 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
9043826d | 888 | es = CSDP_DATA_TYPE_32; |
3a774ea9 RK |
889 | break; |
890 | default: /* not reached */ | |
891 | return NULL; | |
892 | } | |
893 | ||
894 | /* Now allocate and setup the descriptor. */ | |
895 | d = kzalloc(sizeof(*d) + sizeof(d->sg[0]), GFP_ATOMIC); | |
896 | if (!d) | |
897 | return NULL; | |
898 | ||
899 | d->dir = dir; | |
900 | d->dev_addr = dev_addr; | |
901 | d->fi = burst; | |
902 | d->es = es; | |
3a774ea9 RK |
903 | d->sg[0].addr = buf_addr; |
904 | d->sg[0].en = period_len / es_bytes[es]; | |
905 | d->sg[0].fn = buf_len / period_len; | |
906 | d->sglen = 1; | |
3ed4d18f | 907 | |
aa4c5b96 | 908 | d->ccr = c->ccr; |
3ed4d18f | 909 | if (dir == DMA_DEV_TO_MEM) |
9043826d | 910 | d->ccr |= CCR_DST_AMODE_POSTINC | CCR_SRC_AMODE_CONSTANT; |
3ed4d18f | 911 | else |
9043826d | 912 | d->ccr |= CCR_DST_AMODE_CONSTANT | CCR_SRC_AMODE_POSTINC; |
3ed4d18f | 913 | |
9043826d | 914 | d->cicr = CICR_DROP_IE; |
fa3ad86a | 915 | if (flags & DMA_PREP_INTERRUPT) |
9043826d | 916 | d->cicr |= CICR_FRAME_IE; |
fa3ad86a | 917 | |
2f0d13bd RK |
918 | d->csdp = es; |
919 | ||
920 | if (dma_omap1()) { | |
9043826d | 921 | d->cicr |= CICR_TOUT_IE; |
2f0d13bd RK |
922 | |
923 | if (dir == DMA_DEV_TO_MEM) | |
9043826d | 924 | d->csdp |= CSDP_DST_PORT_EMIFF | CSDP_SRC_PORT_MPUI; |
2f0d13bd | 925 | else |
9043826d | 926 | d->csdp |= CSDP_DST_PORT_MPUI | CSDP_SRC_PORT_EMIFF; |
2f0d13bd | 927 | } else { |
3ed4d18f | 928 | if (burst) |
9043826d RK |
929 | d->ccr |= CCR_SYNC_PACKET; |
930 | else | |
931 | d->ccr |= CCR_SYNC_ELEMENT; | |
3ed4d18f RK |
932 | |
933 | if (dir == DMA_DEV_TO_MEM) | |
9043826d | 934 | d->ccr |= CCR_TRIGGER_SRC; |
3ed4d18f | 935 | |
9043826d | 936 | d->cicr |= CICR_MISALIGNED_ERR_IE | CICR_TRANS_ERR_IE; |
3a774ea9 | 937 | |
9043826d | 938 | d->csdp |= CSDP_DST_BURST_64 | CSDP_SRC_BURST_64; |
2f0d13bd RK |
939 | } |
940 | ||
965aeb4d RK |
941 | if (__dma_omap15xx(od->plat->dma_attr)) |
942 | d->ccr |= CCR_AUTO_INIT | CCR_REPEAT; | |
943 | else | |
944 | d->clnk_ctrl = c->dma_ch | CLNK_CTRL_ENABLE_LNK; | |
945 | ||
3ed4d18f | 946 | c->cyclic = true; |
3a774ea9 | 947 | |
2dde5b90 | 948 | return vchan_tx_prep(&c->vc, &d->vd, flags); |
3a774ea9 RK |
949 | } |
950 | ||
78ea4fe7 | 951 | static int omap_dma_slave_config(struct dma_chan *chan, struct dma_slave_config *cfg) |
7bedaa55 | 952 | { |
78ea4fe7 MR |
953 | struct omap_chan *c = to_omap_dma_chan(chan); |
954 | ||
7bedaa55 RK |
955 | if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES || |
956 | cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES) | |
957 | return -EINVAL; | |
958 | ||
959 | memcpy(&c->cfg, cfg, sizeof(c->cfg)); | |
960 | ||
961 | return 0; | |
962 | } | |
963 | ||
78ea4fe7 | 964 | static int omap_dma_terminate_all(struct dma_chan *chan) |
7bedaa55 | 965 | { |
78ea4fe7 | 966 | struct omap_chan *c = to_omap_dma_chan(chan); |
7bedaa55 RK |
967 | struct omap_dmadev *d = to_omap_dma_dev(c->vc.chan.device); |
968 | unsigned long flags; | |
969 | LIST_HEAD(head); | |
970 | ||
971 | spin_lock_irqsave(&c->vc.lock, flags); | |
972 | ||
973 | /* Prevent this channel being scheduled */ | |
974 | spin_lock(&d->lock); | |
975 | list_del_init(&c->node); | |
976 | spin_unlock(&d->lock); | |
977 | ||
978 | /* | |
979 | * Stop DMA activity: we assume the callback will not be called | |
fa3ad86a | 980 | * after omap_dma_stop() returns (even if it does, it will see |
7bedaa55 RK |
981 | * c->desc is NULL and exit.) |
982 | */ | |
983 | if (c->desc) { | |
984 | c->desc = NULL; | |
2dcdf570 PU |
985 | /* Avoid stopping the dma twice */ |
986 | if (!c->paused) | |
fa3ad86a | 987 | omap_dma_stop(c); |
7bedaa55 RK |
988 | } |
989 | ||
3a774ea9 RK |
990 | if (c->cyclic) { |
991 | c->cyclic = false; | |
2dcdf570 | 992 | c->paused = false; |
3a774ea9 RK |
993 | } |
994 | ||
7bedaa55 RK |
995 | vchan_get_all_descriptors(&c->vc, &head); |
996 | spin_unlock_irqrestore(&c->vc.lock, flags); | |
997 | vchan_dma_desc_free_list(&c->vc, &head); | |
998 | ||
999 | return 0; | |
1000 | } | |
1001 | ||
78ea4fe7 | 1002 | static int omap_dma_pause(struct dma_chan *chan) |
7bedaa55 | 1003 | { |
78ea4fe7 MR |
1004 | struct omap_chan *c = to_omap_dma_chan(chan); |
1005 | ||
2dcdf570 PU |
1006 | /* Pause/Resume only allowed with cyclic mode */ |
1007 | if (!c->cyclic) | |
1008 | return -EINVAL; | |
1009 | ||
1010 | if (!c->paused) { | |
fa3ad86a | 1011 | omap_dma_stop(c); |
2dcdf570 PU |
1012 | c->paused = true; |
1013 | } | |
1014 | ||
1015 | return 0; | |
7bedaa55 RK |
1016 | } |
1017 | ||
78ea4fe7 | 1018 | static int omap_dma_resume(struct dma_chan *chan) |
7bedaa55 | 1019 | { |
78ea4fe7 MR |
1020 | struct omap_chan *c = to_omap_dma_chan(chan); |
1021 | ||
2dcdf570 PU |
1022 | /* Pause/Resume only allowed with cyclic mode */ |
1023 | if (!c->cyclic) | |
1024 | return -EINVAL; | |
1025 | ||
1026 | if (c->paused) { | |
b3d09da7 PU |
1027 | mb(); |
1028 | ||
bfb60745 PU |
1029 | /* Restore channel link register */ |
1030 | omap_dma_chan_write(c, CLNK_CTRL, c->desc->clnk_ctrl); | |
1031 | ||
fa3ad86a | 1032 | omap_dma_start(c, c->desc); |
2dcdf570 PU |
1033 | c->paused = false; |
1034 | } | |
1035 | ||
1036 | return 0; | |
7bedaa55 RK |
1037 | } |
1038 | ||
7bedaa55 RK |
1039 | static int omap_dma_chan_init(struct omap_dmadev *od, int dma_sig) |
1040 | { | |
1041 | struct omap_chan *c; | |
1042 | ||
1043 | c = kzalloc(sizeof(*c), GFP_KERNEL); | |
1044 | if (!c) | |
1045 | return -ENOMEM; | |
1046 | ||
596c471b | 1047 | c->reg_map = od->reg_map; |
7bedaa55 RK |
1048 | c->dma_sig = dma_sig; |
1049 | c->vc.desc_free = omap_dma_desc_free; | |
1050 | vchan_init(&c->vc, &od->ddev); | |
1051 | INIT_LIST_HEAD(&c->node); | |
1052 | ||
7bedaa55 RK |
1053 | return 0; |
1054 | } | |
1055 | ||
1056 | static void omap_dma_free(struct omap_dmadev *od) | |
1057 | { | |
1058 | tasklet_kill(&od->task); | |
1059 | while (!list_empty(&od->ddev.channels)) { | |
1060 | struct omap_chan *c = list_first_entry(&od->ddev.channels, | |
1061 | struct omap_chan, vc.chan.device_node); | |
1062 | ||
1063 | list_del(&c->vc.chan.device_node); | |
1064 | tasklet_kill(&c->vc.task); | |
1065 | kfree(c); | |
1066 | } | |
7bedaa55 RK |
1067 | } |
1068 | ||
80b0e0ab PU |
1069 | #define OMAP_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ |
1070 | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ | |
1071 | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)) | |
1072 | ||
7bedaa55 RK |
1073 | static int omap_dma_probe(struct platform_device *pdev) |
1074 | { | |
1075 | struct omap_dmadev *od; | |
596c471b | 1076 | struct resource *res; |
6ddeb6d8 | 1077 | int rc, i, irq; |
7bedaa55 | 1078 | |
104fce73 | 1079 | od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL); |
7bedaa55 RK |
1080 | if (!od) |
1081 | return -ENOMEM; | |
1082 | ||
596c471b RK |
1083 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1084 | od->base = devm_ioremap_resource(&pdev->dev, res); | |
1085 | if (IS_ERR(od->base)) | |
1086 | return PTR_ERR(od->base); | |
1087 | ||
1b416c4b RK |
1088 | od->plat = omap_get_plat_info(); |
1089 | if (!od->plat) | |
1090 | return -EPROBE_DEFER; | |
1091 | ||
596c471b RK |
1092 | od->reg_map = od->plat->reg_map; |
1093 | ||
7bedaa55 | 1094 | dma_cap_set(DMA_SLAVE, od->ddev.cap_mask); |
3a774ea9 | 1095 | dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask); |
7bedaa55 RK |
1096 | od->ddev.device_alloc_chan_resources = omap_dma_alloc_chan_resources; |
1097 | od->ddev.device_free_chan_resources = omap_dma_free_chan_resources; | |
1098 | od->ddev.device_tx_status = omap_dma_tx_status; | |
1099 | od->ddev.device_issue_pending = omap_dma_issue_pending; | |
1100 | od->ddev.device_prep_slave_sg = omap_dma_prep_slave_sg; | |
3a774ea9 | 1101 | od->ddev.device_prep_dma_cyclic = omap_dma_prep_dma_cyclic; |
6c04cd4f | 1102 | od->ddev.device_config = omap_dma_slave_config; |
78ea4fe7 MR |
1103 | od->ddev.device_pause = omap_dma_pause; |
1104 | od->ddev.device_resume = omap_dma_resume; | |
1105 | od->ddev.device_terminate_all = omap_dma_terminate_all; | |
7d15b87d MR |
1106 | od->ddev.src_addr_widths = OMAP_DMA_BUSWIDTHS; |
1107 | od->ddev.dst_addr_widths = OMAP_DMA_BUSWIDTHS; | |
1108 | od->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); | |
1109 | od->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; | |
7bedaa55 RK |
1110 | od->ddev.dev = &pdev->dev; |
1111 | INIT_LIST_HEAD(&od->ddev.channels); | |
1112 | INIT_LIST_HEAD(&od->pending); | |
1113 | spin_lock_init(&od->lock); | |
6ddeb6d8 | 1114 | spin_lock_init(&od->irq_lock); |
7bedaa55 RK |
1115 | |
1116 | tasklet_init(&od->task, omap_dma_sched, (unsigned long)od); | |
1117 | ||
1118 | for (i = 0; i < 127; i++) { | |
1119 | rc = omap_dma_chan_init(od, i); | |
1120 | if (rc) { | |
1121 | omap_dma_free(od); | |
1122 | return rc; | |
1123 | } | |
1124 | } | |
1125 | ||
6ddeb6d8 RK |
1126 | irq = platform_get_irq(pdev, 1); |
1127 | if (irq <= 0) { | |
1128 | dev_info(&pdev->dev, "failed to get L1 IRQ: %d\n", irq); | |
1129 | od->legacy = true; | |
1130 | } else { | |
1131 | /* Disable all interrupts */ | |
1132 | od->irq_enable_mask = 0; | |
1133 | omap_dma_glbl_write(od, IRQENABLE_L1, 0); | |
1134 | ||
1135 | rc = devm_request_irq(&pdev->dev, irq, omap_dma_irq, | |
1136 | IRQF_SHARED, "omap-dma-engine", od); | |
1137 | if (rc) | |
1138 | return rc; | |
1139 | } | |
1140 | ||
7bedaa55 RK |
1141 | rc = dma_async_device_register(&od->ddev); |
1142 | if (rc) { | |
1143 | pr_warn("OMAP-DMA: failed to register slave DMA engine device: %d\n", | |
1144 | rc); | |
1145 | omap_dma_free(od); | |
8d30662a JH |
1146 | return rc; |
1147 | } | |
1148 | ||
1149 | platform_set_drvdata(pdev, od); | |
1150 | ||
1151 | if (pdev->dev.of_node) { | |
1152 | omap_dma_info.dma_cap = od->ddev.cap_mask; | |
1153 | ||
1154 | /* Device-tree DMA controller registration */ | |
1155 | rc = of_dma_controller_register(pdev->dev.of_node, | |
1156 | of_dma_simple_xlate, &omap_dma_info); | |
1157 | if (rc) { | |
1158 | pr_warn("OMAP-DMA: failed to register DMA controller\n"); | |
1159 | dma_async_device_unregister(&od->ddev); | |
1160 | omap_dma_free(od); | |
1161 | } | |
7bedaa55 RK |
1162 | } |
1163 | ||
1164 | dev_info(&pdev->dev, "OMAP DMA engine driver\n"); | |
1165 | ||
1166 | return rc; | |
1167 | } | |
1168 | ||
1169 | static int omap_dma_remove(struct platform_device *pdev) | |
1170 | { | |
1171 | struct omap_dmadev *od = platform_get_drvdata(pdev); | |
1172 | ||
8d30662a JH |
1173 | if (pdev->dev.of_node) |
1174 | of_dma_controller_free(pdev->dev.of_node); | |
1175 | ||
7bedaa55 | 1176 | dma_async_device_unregister(&od->ddev); |
6ddeb6d8 RK |
1177 | |
1178 | if (!od->legacy) { | |
1179 | /* Disable all interrupts */ | |
1180 | omap_dma_glbl_write(od, IRQENABLE_L0, 0); | |
1181 | } | |
1182 | ||
7bedaa55 RK |
1183 | omap_dma_free(od); |
1184 | ||
1185 | return 0; | |
1186 | } | |
1187 | ||
8d30662a JH |
1188 | static const struct of_device_id omap_dma_match[] = { |
1189 | { .compatible = "ti,omap2420-sdma", }, | |
1190 | { .compatible = "ti,omap2430-sdma", }, | |
1191 | { .compatible = "ti,omap3430-sdma", }, | |
1192 | { .compatible = "ti,omap3630-sdma", }, | |
1193 | { .compatible = "ti,omap4430-sdma", }, | |
1194 | {}, | |
1195 | }; | |
1196 | MODULE_DEVICE_TABLE(of, omap_dma_match); | |
1197 | ||
7bedaa55 RK |
1198 | static struct platform_driver omap_dma_driver = { |
1199 | .probe = omap_dma_probe, | |
1200 | .remove = omap_dma_remove, | |
1201 | .driver = { | |
1202 | .name = "omap-dma-engine", | |
8d30662a | 1203 | .of_match_table = of_match_ptr(omap_dma_match), |
7bedaa55 RK |
1204 | }, |
1205 | }; | |
1206 | ||
1207 | bool omap_dma_filter_fn(struct dma_chan *chan, void *param) | |
1208 | { | |
1209 | if (chan->device->dev->driver == &omap_dma_driver.driver) { | |
1210 | struct omap_chan *c = to_omap_dma_chan(chan); | |
1211 | unsigned req = *(unsigned *)param; | |
1212 | ||
1213 | return req == c->dma_sig; | |
1214 | } | |
1215 | return false; | |
1216 | } | |
1217 | EXPORT_SYMBOL_GPL(omap_dma_filter_fn); | |
1218 | ||
7bedaa55 RK |
1219 | static int omap_dma_init(void) |
1220 | { | |
be1f9481 | 1221 | return platform_driver_register(&omap_dma_driver); |
7bedaa55 RK |
1222 | } |
1223 | subsys_initcall(omap_dma_init); | |
1224 | ||
1225 | static void __exit omap_dma_exit(void) | |
1226 | { | |
7bedaa55 RK |
1227 | platform_driver_unregister(&omap_dma_driver); |
1228 | } | |
1229 | module_exit(omap_dma_exit); | |
1230 | ||
1231 | MODULE_AUTHOR("Russell King"); | |
1232 | MODULE_LICENSE("GPL"); |