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b7d861d9 BK |
1 | /* |
2 | * Copyright (c) 2012 Samsung Electronics Co., Ltd. | |
3 | * http://www.samsung.com | |
b3040e40 JB |
4 | * |
5 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. | |
6 | * Jaswinder Singh <jassi.brar@samsung.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | */ | |
13 | ||
b7d861d9 | 14 | #include <linux/kernel.h> |
b3040e40 JB |
15 | #include <linux/io.h> |
16 | #include <linux/init.h> | |
17 | #include <linux/slab.h> | |
18 | #include <linux/module.h> | |
b7d861d9 BK |
19 | #include <linux/string.h> |
20 | #include <linux/delay.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/dma-mapping.h> | |
b3040e40 | 23 | #include <linux/dmaengine.h> |
b3040e40 JB |
24 | #include <linux/amba/bus.h> |
25 | #include <linux/amba/pl330.h> | |
1b9bb715 | 26 | #include <linux/scatterlist.h> |
93ed5544 | 27 | #include <linux/of.h> |
a80258f9 | 28 | #include <linux/of_dma.h> |
bcc7fa95 | 29 | #include <linux/err.h> |
b3040e40 | 30 | |
d2ebfb33 | 31 | #include "dmaengine.h" |
b7d861d9 BK |
32 | #define PL330_MAX_CHAN 8 |
33 | #define PL330_MAX_IRQS 32 | |
34 | #define PL330_MAX_PERI 32 | |
35 | ||
f0564c7e LPC |
36 | enum pl330_cachectrl { |
37 | CCTRL0, /* Noncacheable and nonbufferable */ | |
38 | CCTRL1, /* Bufferable only */ | |
39 | CCTRL2, /* Cacheable, but do not allocate */ | |
40 | CCTRL3, /* Cacheable and bufferable, but do not allocate */ | |
41 | INVALID1, /* AWCACHE = 0x1000 */ | |
42 | INVALID2, | |
43 | CCTRL6, /* Cacheable write-through, allocate on writes only */ | |
44 | CCTRL7, /* Cacheable write-back, allocate on writes only */ | |
b7d861d9 BK |
45 | }; |
46 | ||
47 | enum pl330_byteswap { | |
48 | SWAP_NO, | |
49 | SWAP_2, | |
50 | SWAP_4, | |
51 | SWAP_8, | |
52 | SWAP_16, | |
53 | }; | |
54 | ||
b7d861d9 BK |
55 | /* Register and Bit field Definitions */ |
56 | #define DS 0x0 | |
57 | #define DS_ST_STOP 0x0 | |
58 | #define DS_ST_EXEC 0x1 | |
59 | #define DS_ST_CMISS 0x2 | |
60 | #define DS_ST_UPDTPC 0x3 | |
61 | #define DS_ST_WFE 0x4 | |
62 | #define DS_ST_ATBRR 0x5 | |
63 | #define DS_ST_QBUSY 0x6 | |
64 | #define DS_ST_WFP 0x7 | |
65 | #define DS_ST_KILL 0x8 | |
66 | #define DS_ST_CMPLT 0x9 | |
67 | #define DS_ST_FLTCMP 0xe | |
68 | #define DS_ST_FAULT 0xf | |
69 | ||
70 | #define DPC 0x4 | |
71 | #define INTEN 0x20 | |
72 | #define ES 0x24 | |
73 | #define INTSTATUS 0x28 | |
74 | #define INTCLR 0x2c | |
75 | #define FSM 0x30 | |
76 | #define FSC 0x34 | |
77 | #define FTM 0x38 | |
78 | ||
79 | #define _FTC 0x40 | |
80 | #define FTC(n) (_FTC + (n)*0x4) | |
81 | ||
82 | #define _CS 0x100 | |
83 | #define CS(n) (_CS + (n)*0x8) | |
84 | #define CS_CNS (1 << 21) | |
85 | ||
86 | #define _CPC 0x104 | |
87 | #define CPC(n) (_CPC + (n)*0x8) | |
88 | ||
89 | #define _SA 0x400 | |
90 | #define SA(n) (_SA + (n)*0x20) | |
91 | ||
92 | #define _DA 0x404 | |
93 | #define DA(n) (_DA + (n)*0x20) | |
94 | ||
95 | #define _CC 0x408 | |
96 | #define CC(n) (_CC + (n)*0x20) | |
97 | ||
98 | #define CC_SRCINC (1 << 0) | |
99 | #define CC_DSTINC (1 << 14) | |
100 | #define CC_SRCPRI (1 << 8) | |
101 | #define CC_DSTPRI (1 << 22) | |
102 | #define CC_SRCNS (1 << 9) | |
103 | #define CC_DSTNS (1 << 23) | |
104 | #define CC_SRCIA (1 << 10) | |
105 | #define CC_DSTIA (1 << 24) | |
106 | #define CC_SRCBRSTLEN_SHFT 4 | |
107 | #define CC_DSTBRSTLEN_SHFT 18 | |
108 | #define CC_SRCBRSTSIZE_SHFT 1 | |
109 | #define CC_DSTBRSTSIZE_SHFT 15 | |
110 | #define CC_SRCCCTRL_SHFT 11 | |
111 | #define CC_SRCCCTRL_MASK 0x7 | |
112 | #define CC_DSTCCTRL_SHFT 25 | |
113 | #define CC_DRCCCTRL_MASK 0x7 | |
114 | #define CC_SWAP_SHFT 28 | |
115 | ||
116 | #define _LC0 0x40c | |
117 | #define LC0(n) (_LC0 + (n)*0x20) | |
118 | ||
119 | #define _LC1 0x410 | |
120 | #define LC1(n) (_LC1 + (n)*0x20) | |
121 | ||
122 | #define DBGSTATUS 0xd00 | |
123 | #define DBG_BUSY (1 << 0) | |
124 | ||
125 | #define DBGCMD 0xd04 | |
126 | #define DBGINST0 0xd08 | |
127 | #define DBGINST1 0xd0c | |
128 | ||
129 | #define CR0 0xe00 | |
130 | #define CR1 0xe04 | |
131 | #define CR2 0xe08 | |
132 | #define CR3 0xe0c | |
133 | #define CR4 0xe10 | |
134 | #define CRD 0xe14 | |
135 | ||
136 | #define PERIPH_ID 0xfe0 | |
3ecf51a4 BK |
137 | #define PERIPH_REV_SHIFT 20 |
138 | #define PERIPH_REV_MASK 0xf | |
139 | #define PERIPH_REV_R0P0 0 | |
140 | #define PERIPH_REV_R1P0 1 | |
141 | #define PERIPH_REV_R1P1 2 | |
b7d861d9 BK |
142 | |
143 | #define CR0_PERIPH_REQ_SET (1 << 0) | |
144 | #define CR0_BOOT_EN_SET (1 << 1) | |
145 | #define CR0_BOOT_MAN_NS (1 << 2) | |
146 | #define CR0_NUM_CHANS_SHIFT 4 | |
147 | #define CR0_NUM_CHANS_MASK 0x7 | |
148 | #define CR0_NUM_PERIPH_SHIFT 12 | |
149 | #define CR0_NUM_PERIPH_MASK 0x1f | |
150 | #define CR0_NUM_EVENTS_SHIFT 17 | |
151 | #define CR0_NUM_EVENTS_MASK 0x1f | |
152 | ||
153 | #define CR1_ICACHE_LEN_SHIFT 0 | |
154 | #define CR1_ICACHE_LEN_MASK 0x7 | |
155 | #define CR1_NUM_ICACHELINES_SHIFT 4 | |
156 | #define CR1_NUM_ICACHELINES_MASK 0xf | |
157 | ||
158 | #define CRD_DATA_WIDTH_SHIFT 0 | |
159 | #define CRD_DATA_WIDTH_MASK 0x7 | |
160 | #define CRD_WR_CAP_SHIFT 4 | |
161 | #define CRD_WR_CAP_MASK 0x7 | |
162 | #define CRD_WR_Q_DEP_SHIFT 8 | |
163 | #define CRD_WR_Q_DEP_MASK 0xf | |
164 | #define CRD_RD_CAP_SHIFT 12 | |
165 | #define CRD_RD_CAP_MASK 0x7 | |
166 | #define CRD_RD_Q_DEP_SHIFT 16 | |
167 | #define CRD_RD_Q_DEP_MASK 0xf | |
168 | #define CRD_DATA_BUFF_SHIFT 20 | |
169 | #define CRD_DATA_BUFF_MASK 0x3ff | |
170 | ||
171 | #define PART 0x330 | |
172 | #define DESIGNER 0x41 | |
173 | #define REVISION 0x0 | |
174 | #define INTEG_CFG 0x0 | |
175 | #define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12)) | |
176 | ||
b7d861d9 BK |
177 | #define PL330_STATE_STOPPED (1 << 0) |
178 | #define PL330_STATE_EXECUTING (1 << 1) | |
179 | #define PL330_STATE_WFE (1 << 2) | |
180 | #define PL330_STATE_FAULTING (1 << 3) | |
181 | #define PL330_STATE_COMPLETING (1 << 4) | |
182 | #define PL330_STATE_WFP (1 << 5) | |
183 | #define PL330_STATE_KILLING (1 << 6) | |
184 | #define PL330_STATE_FAULT_COMPLETING (1 << 7) | |
185 | #define PL330_STATE_CACHEMISS (1 << 8) | |
186 | #define PL330_STATE_UPDTPC (1 << 9) | |
187 | #define PL330_STATE_ATBARRIER (1 << 10) | |
188 | #define PL330_STATE_QUEUEBUSY (1 << 11) | |
189 | #define PL330_STATE_INVALID (1 << 15) | |
190 | ||
191 | #define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \ | |
192 | | PL330_STATE_WFE | PL330_STATE_FAULTING) | |
193 | ||
194 | #define CMD_DMAADDH 0x54 | |
195 | #define CMD_DMAEND 0x00 | |
196 | #define CMD_DMAFLUSHP 0x35 | |
197 | #define CMD_DMAGO 0xa0 | |
198 | #define CMD_DMALD 0x04 | |
199 | #define CMD_DMALDP 0x25 | |
200 | #define CMD_DMALP 0x20 | |
201 | #define CMD_DMALPEND 0x28 | |
202 | #define CMD_DMAKILL 0x01 | |
203 | #define CMD_DMAMOV 0xbc | |
204 | #define CMD_DMANOP 0x18 | |
205 | #define CMD_DMARMB 0x12 | |
206 | #define CMD_DMASEV 0x34 | |
207 | #define CMD_DMAST 0x08 | |
208 | #define CMD_DMASTP 0x29 | |
209 | #define CMD_DMASTZ 0x0c | |
210 | #define CMD_DMAWFE 0x36 | |
211 | #define CMD_DMAWFP 0x30 | |
212 | #define CMD_DMAWMB 0x13 | |
213 | ||
214 | #define SZ_DMAADDH 3 | |
215 | #define SZ_DMAEND 1 | |
216 | #define SZ_DMAFLUSHP 2 | |
217 | #define SZ_DMALD 1 | |
218 | #define SZ_DMALDP 2 | |
219 | #define SZ_DMALP 2 | |
220 | #define SZ_DMALPEND 2 | |
221 | #define SZ_DMAKILL 1 | |
222 | #define SZ_DMAMOV 6 | |
223 | #define SZ_DMANOP 1 | |
224 | #define SZ_DMARMB 1 | |
225 | #define SZ_DMASEV 2 | |
226 | #define SZ_DMAST 1 | |
227 | #define SZ_DMASTP 2 | |
228 | #define SZ_DMASTZ 1 | |
229 | #define SZ_DMAWFE 2 | |
230 | #define SZ_DMAWFP 2 | |
231 | #define SZ_DMAWMB 1 | |
232 | #define SZ_DMAGO 6 | |
233 | ||
234 | #define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1) | |
235 | #define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7)) | |
236 | ||
237 | #define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr)) | |
238 | #define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr)) | |
239 | ||
240 | /* | |
241 | * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req | |
242 | * at 1byte/burst for P<->M and M<->M respectively. | |
243 | * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req | |
244 | * should be enough for P<->M and M<->M respectively. | |
245 | */ | |
246 | #define MCODE_BUFF_PER_REQ 256 | |
247 | ||
248 | /* If the _pl330_req is available to the client */ | |
249 | #define IS_FREE(req) (*((u8 *)((req)->mc_cpu)) == CMD_DMAEND) | |
250 | ||
251 | /* Use this _only_ to wait on transient states */ | |
252 | #define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax(); | |
253 | ||
254 | #ifdef PL330_DEBUG_MCGEN | |
255 | static unsigned cmd_line; | |
256 | #define PL330_DBGCMD_DUMP(off, x...) do { \ | |
257 | printk("%x:", cmd_line); \ | |
258 | printk(x); \ | |
259 | cmd_line += off; \ | |
260 | } while (0) | |
261 | #define PL330_DBGMC_START(addr) (cmd_line = addr) | |
262 | #else | |
263 | #define PL330_DBGCMD_DUMP(off, x...) do {} while (0) | |
264 | #define PL330_DBGMC_START(addr) do {} while (0) | |
265 | #endif | |
266 | ||
267 | /* The number of default descriptors */ | |
d2ebfb33 | 268 | |
b3040e40 JB |
269 | #define NR_DEFAULT_DESC 16 |
270 | ||
b7d861d9 BK |
271 | /* Populated by the PL330 core driver for DMA API driver's info */ |
272 | struct pl330_config { | |
273 | u32 periph_id; | |
b7d861d9 BK |
274 | #define DMAC_MODE_NS (1 << 0) |
275 | unsigned int mode; | |
276 | unsigned int data_bus_width:10; /* In number of bits */ | |
277 | unsigned int data_buf_dep:10; | |
278 | unsigned int num_chan:4; | |
279 | unsigned int num_peri:6; | |
280 | u32 peri_ns; | |
281 | unsigned int num_events:6; | |
282 | u32 irq_ns; | |
283 | }; | |
284 | ||
285 | /* Handle to the DMAC provided to the PL330 core */ | |
286 | struct pl330_info { | |
287 | /* Owning device */ | |
288 | struct device *dev; | |
289 | /* Size of MicroCode buffers for each channel. */ | |
290 | unsigned mcbufsz; | |
291 | /* ioremap'ed address of PL330 registers. */ | |
292 | void __iomem *base; | |
b7d861d9 BK |
293 | /* PL330 core data, Client must not touch it. */ |
294 | void *pl330_data; | |
295 | /* Populated by the PL330 core driver during pl330_add */ | |
296 | struct pl330_config pcfg; | |
b7d861d9 BK |
297 | }; |
298 | ||
299 | /** | |
300 | * Request Configuration. | |
301 | * The PL330 core does not modify this and uses the last | |
302 | * working configuration if the request doesn't provide any. | |
303 | * | |
304 | * The Client may want to provide this info only for the | |
305 | * first request and a request with new settings. | |
306 | */ | |
307 | struct pl330_reqcfg { | |
308 | /* Address Incrementing */ | |
309 | unsigned dst_inc:1; | |
310 | unsigned src_inc:1; | |
311 | ||
312 | /* | |
313 | * For now, the SRC & DST protection levels | |
314 | * and burst size/length are assumed same. | |
315 | */ | |
316 | bool nonsecure; | |
317 | bool privileged; | |
318 | bool insnaccess; | |
319 | unsigned brst_len:5; | |
320 | unsigned brst_size:3; /* in power of 2 */ | |
321 | ||
f0564c7e LPC |
322 | enum pl330_cachectrl dcctl; |
323 | enum pl330_cachectrl scctl; | |
b7d861d9 | 324 | enum pl330_byteswap swap; |
3ecf51a4 | 325 | struct pl330_config *pcfg; |
b7d861d9 BK |
326 | }; |
327 | ||
328 | /* | |
329 | * One cycle of DMAC operation. | |
330 | * There may be more than one xfer in a request. | |
331 | */ | |
332 | struct pl330_xfer { | |
333 | u32 src_addr; | |
334 | u32 dst_addr; | |
335 | /* Size to xfer */ | |
336 | u32 bytes; | |
b7d861d9 BK |
337 | }; |
338 | ||
339 | /* The xfer callbacks are made with one of these arguments. */ | |
340 | enum pl330_op_err { | |
341 | /* The all xfers in the request were success. */ | |
342 | PL330_ERR_NONE, | |
343 | /* If req aborted due to global error. */ | |
344 | PL330_ERR_ABORT, | |
345 | /* If req failed due to problem with Channel. */ | |
346 | PL330_ERR_FAIL, | |
347 | }; | |
348 | ||
349 | /* A request defining Scatter-Gather List ending with NULL xfer. */ | |
350 | struct pl330_req { | |
585a9d0b | 351 | enum dma_transfer_direction rqtype; |
b7d861d9 BK |
352 | /* Index of peripheral for the xfer. */ |
353 | unsigned peri:5; | |
b7d861d9 BK |
354 | /* If NULL, req will be done at last set parameters. */ |
355 | struct pl330_reqcfg *cfg; | |
356 | /* Pointer to first xfer in the request. */ | |
357 | struct pl330_xfer *x; | |
fdec53d5 JM |
358 | /* Hook to attach to DMAC's list of reqs with due callback */ |
359 | struct list_head rqd; | |
b7d861d9 BK |
360 | }; |
361 | ||
b7d861d9 BK |
362 | enum pl330_chan_op { |
363 | /* Start the channel */ | |
364 | PL330_OP_START, | |
365 | /* Abort the active xfer */ | |
366 | PL330_OP_ABORT, | |
367 | /* Stop xfer and flush queue */ | |
368 | PL330_OP_FLUSH, | |
369 | }; | |
370 | ||
371 | struct _xfer_spec { | |
372 | u32 ccr; | |
373 | struct pl330_req *r; | |
374 | struct pl330_xfer *x; | |
375 | }; | |
376 | ||
377 | enum dmamov_dst { | |
378 | SAR = 0, | |
379 | CCR, | |
380 | DAR, | |
381 | }; | |
382 | ||
383 | enum pl330_dst { | |
384 | SRC = 0, | |
385 | DST, | |
386 | }; | |
387 | ||
388 | enum pl330_cond { | |
389 | SINGLE, | |
390 | BURST, | |
391 | ALWAYS, | |
392 | }; | |
393 | ||
394 | struct _pl330_req { | |
395 | u32 mc_bus; | |
396 | void *mc_cpu; | |
b7d861d9 | 397 | struct pl330_req *r; |
b7d861d9 BK |
398 | }; |
399 | ||
400 | /* ToBeDone for tasklet */ | |
401 | struct _pl330_tbd { | |
402 | bool reset_dmac; | |
403 | bool reset_mngr; | |
404 | u8 reset_chan; | |
405 | }; | |
406 | ||
407 | /* A DMAC Thread */ | |
408 | struct pl330_thread { | |
409 | u8 id; | |
410 | int ev; | |
411 | /* If the channel is not yet acquired by any client */ | |
412 | bool free; | |
413 | /* Parent DMAC */ | |
414 | struct pl330_dmac *dmac; | |
415 | /* Only two at a time */ | |
416 | struct _pl330_req req[2]; | |
417 | /* Index of the last enqueued request */ | |
418 | unsigned lstenq; | |
419 | /* Index of the last submitted request or -1 if the DMA is stopped */ | |
420 | int req_running; | |
421 | }; | |
422 | ||
423 | enum pl330_dmac_state { | |
424 | UNINIT, | |
425 | INIT, | |
426 | DYING, | |
427 | }; | |
428 | ||
429 | /* A DMAC */ | |
430 | struct pl330_dmac { | |
431 | spinlock_t lock; | |
432 | /* Holds list of reqs with due callbacks */ | |
433 | struct list_head req_done; | |
434 | /* Pointer to platform specific stuff */ | |
435 | struct pl330_info *pinfo; | |
436 | /* Maximum possible events/irqs */ | |
437 | int events[32]; | |
438 | /* BUS address of MicroCode buffer */ | |
fed8c457 | 439 | dma_addr_t mcode_bus; |
b7d861d9 BK |
440 | /* CPU address of MicroCode buffer */ |
441 | void *mcode_cpu; | |
442 | /* List of all Channel threads */ | |
443 | struct pl330_thread *channels; | |
444 | /* Pointer to the MANAGER thread */ | |
445 | struct pl330_thread *manager; | |
446 | /* To handle bad news in interrupt */ | |
447 | struct tasklet_struct tasks; | |
448 | struct _pl330_tbd dmac_tbd; | |
449 | /* State of DMAC operation */ | |
450 | enum pl330_dmac_state state; | |
451 | }; | |
452 | ||
b3040e40 JB |
453 | enum desc_status { |
454 | /* In the DMAC pool */ | |
455 | FREE, | |
456 | /* | |
d73111c6 | 457 | * Allocated to some channel during prep_xxx |
b3040e40 JB |
458 | * Also may be sitting on the work_list. |
459 | */ | |
460 | PREP, | |
461 | /* | |
462 | * Sitting on the work_list and already submitted | |
463 | * to the PL330 core. Not more than two descriptors | |
464 | * of a channel can be BUSY at any time. | |
465 | */ | |
466 | BUSY, | |
467 | /* | |
468 | * Sitting on the channel work_list but xfer done | |
469 | * by PL330 core | |
470 | */ | |
471 | DONE, | |
472 | }; | |
473 | ||
474 | struct dma_pl330_chan { | |
475 | /* Schedule desc completion */ | |
476 | struct tasklet_struct task; | |
477 | ||
478 | /* DMA-Engine Channel */ | |
479 | struct dma_chan chan; | |
480 | ||
04abf5da LPC |
481 | /* List of submitted descriptors */ |
482 | struct list_head submitted_list; | |
483 | /* List of issued descriptors */ | |
b3040e40 | 484 | struct list_head work_list; |
39ff8613 LPC |
485 | /* List of completed descriptors */ |
486 | struct list_head completed_list; | |
b3040e40 JB |
487 | |
488 | /* Pointer to the DMAC that manages this channel, | |
489 | * NULL if the channel is available to be acquired. | |
490 | * As the parent, this DMAC also provides descriptors | |
491 | * to the channel. | |
492 | */ | |
493 | struct dma_pl330_dmac *dmac; | |
494 | ||
495 | /* To protect channel manipulation */ | |
496 | spinlock_t lock; | |
497 | ||
65ad6060 LPC |
498 | /* |
499 | * Hardware channel thread of PL330 DMAC. NULL if the channel is | |
500 | * available. | |
b3040e40 | 501 | */ |
65ad6060 | 502 | struct pl330_thread *thread; |
1b9bb715 BK |
503 | |
504 | /* For D-to-M and M-to-D channels */ | |
505 | int burst_sz; /* the peripheral fifo width */ | |
1d0c1d60 | 506 | int burst_len; /* the number of burst */ |
1b9bb715 | 507 | dma_addr_t fifo_addr; |
42bc9cf4 BK |
508 | |
509 | /* for cyclic capability */ | |
510 | bool cyclic; | |
b3040e40 JB |
511 | }; |
512 | ||
513 | struct dma_pl330_dmac { | |
514 | struct pl330_info pif; | |
515 | ||
516 | /* DMA-Engine Device */ | |
517 | struct dma_device ddma; | |
518 | ||
b714b84e LPC |
519 | /* Holds info about sg limitations */ |
520 | struct device_dma_parameters dma_parms; | |
521 | ||
b3040e40 JB |
522 | /* Pool of descriptors available for the DMAC's channels */ |
523 | struct list_head desc_pool; | |
524 | /* To protect desc_pool manipulation */ | |
525 | spinlock_t pool_lock; | |
526 | ||
527 | /* Peripheral channels connected to this DMAC */ | |
70cbb163 | 528 | unsigned int num_peripherals; |
4e0e6109 | 529 | struct dma_pl330_chan *peripherals; /* keep at end */ |
b3040e40 JB |
530 | }; |
531 | ||
532 | struct dma_pl330_desc { | |
533 | /* To attach to a queue as child */ | |
534 | struct list_head node; | |
535 | ||
536 | /* Descriptor for the DMA Engine API */ | |
537 | struct dma_async_tx_descriptor txd; | |
538 | ||
539 | /* Xfer for PL330 core */ | |
540 | struct pl330_xfer px; | |
541 | ||
542 | struct pl330_reqcfg rqcfg; | |
543 | struct pl330_req req; | |
544 | ||
545 | enum desc_status status; | |
546 | ||
547 | /* The channel which currently holds this desc */ | |
548 | struct dma_pl330_chan *pchan; | |
549 | }; | |
550 | ||
b7d861d9 BK |
551 | static inline bool _queue_empty(struct pl330_thread *thrd) |
552 | { | |
553 | return (IS_FREE(&thrd->req[0]) && IS_FREE(&thrd->req[1])) | |
554 | ? true : false; | |
555 | } | |
556 | ||
557 | static inline bool _queue_full(struct pl330_thread *thrd) | |
558 | { | |
559 | return (IS_FREE(&thrd->req[0]) || IS_FREE(&thrd->req[1])) | |
560 | ? false : true; | |
561 | } | |
562 | ||
563 | static inline bool is_manager(struct pl330_thread *thrd) | |
564 | { | |
565 | struct pl330_dmac *pl330 = thrd->dmac; | |
566 | ||
567 | /* MANAGER is indexed at the end */ | |
568 | if (thrd->id == pl330->pinfo->pcfg.num_chan) | |
569 | return true; | |
570 | else | |
571 | return false; | |
572 | } | |
573 | ||
574 | /* If manager of the thread is in Non-Secure mode */ | |
575 | static inline bool _manager_ns(struct pl330_thread *thrd) | |
576 | { | |
577 | struct pl330_dmac *pl330 = thrd->dmac; | |
578 | ||
579 | return (pl330->pinfo->pcfg.mode & DMAC_MODE_NS) ? true : false; | |
580 | } | |
581 | ||
3ecf51a4 BK |
582 | static inline u32 get_revision(u32 periph_id) |
583 | { | |
584 | return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK; | |
585 | } | |
586 | ||
b7d861d9 BK |
587 | static inline u32 _emit_ADDH(unsigned dry_run, u8 buf[], |
588 | enum pl330_dst da, u16 val) | |
589 | { | |
590 | if (dry_run) | |
591 | return SZ_DMAADDH; | |
592 | ||
593 | buf[0] = CMD_DMAADDH; | |
594 | buf[0] |= (da << 1); | |
595 | *((u16 *)&buf[1]) = val; | |
596 | ||
597 | PL330_DBGCMD_DUMP(SZ_DMAADDH, "\tDMAADDH %s %u\n", | |
598 | da == 1 ? "DA" : "SA", val); | |
599 | ||
600 | return SZ_DMAADDH; | |
601 | } | |
602 | ||
603 | static inline u32 _emit_END(unsigned dry_run, u8 buf[]) | |
604 | { | |
605 | if (dry_run) | |
606 | return SZ_DMAEND; | |
607 | ||
608 | buf[0] = CMD_DMAEND; | |
609 | ||
610 | PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n"); | |
611 | ||
612 | return SZ_DMAEND; | |
613 | } | |
614 | ||
615 | static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri) | |
616 | { | |
617 | if (dry_run) | |
618 | return SZ_DMAFLUSHP; | |
619 | ||
620 | buf[0] = CMD_DMAFLUSHP; | |
621 | ||
622 | peri &= 0x1f; | |
623 | peri <<= 3; | |
624 | buf[1] = peri; | |
625 | ||
626 | PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3); | |
627 | ||
628 | return SZ_DMAFLUSHP; | |
629 | } | |
630 | ||
631 | static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond) | |
632 | { | |
633 | if (dry_run) | |
634 | return SZ_DMALD; | |
635 | ||
636 | buf[0] = CMD_DMALD; | |
637 | ||
638 | if (cond == SINGLE) | |
639 | buf[0] |= (0 << 1) | (1 << 0); | |
640 | else if (cond == BURST) | |
641 | buf[0] |= (1 << 1) | (1 << 0); | |
642 | ||
643 | PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n", | |
644 | cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A')); | |
645 | ||
646 | return SZ_DMALD; | |
647 | } | |
648 | ||
649 | static inline u32 _emit_LDP(unsigned dry_run, u8 buf[], | |
650 | enum pl330_cond cond, u8 peri) | |
651 | { | |
652 | if (dry_run) | |
653 | return SZ_DMALDP; | |
654 | ||
655 | buf[0] = CMD_DMALDP; | |
656 | ||
657 | if (cond == BURST) | |
658 | buf[0] |= (1 << 1); | |
659 | ||
660 | peri &= 0x1f; | |
661 | peri <<= 3; | |
662 | buf[1] = peri; | |
663 | ||
664 | PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n", | |
665 | cond == SINGLE ? 'S' : 'B', peri >> 3); | |
666 | ||
667 | return SZ_DMALDP; | |
668 | } | |
669 | ||
670 | static inline u32 _emit_LP(unsigned dry_run, u8 buf[], | |
671 | unsigned loop, u8 cnt) | |
672 | { | |
673 | if (dry_run) | |
674 | return SZ_DMALP; | |
675 | ||
676 | buf[0] = CMD_DMALP; | |
677 | ||
678 | if (loop) | |
679 | buf[0] |= (1 << 1); | |
680 | ||
681 | cnt--; /* DMAC increments by 1 internally */ | |
682 | buf[1] = cnt; | |
683 | ||
684 | PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt); | |
685 | ||
686 | return SZ_DMALP; | |
687 | } | |
688 | ||
689 | struct _arg_LPEND { | |
690 | enum pl330_cond cond; | |
691 | bool forever; | |
692 | unsigned loop; | |
693 | u8 bjump; | |
694 | }; | |
695 | ||
696 | static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[], | |
697 | const struct _arg_LPEND *arg) | |
698 | { | |
699 | enum pl330_cond cond = arg->cond; | |
700 | bool forever = arg->forever; | |
701 | unsigned loop = arg->loop; | |
702 | u8 bjump = arg->bjump; | |
703 | ||
704 | if (dry_run) | |
705 | return SZ_DMALPEND; | |
706 | ||
707 | buf[0] = CMD_DMALPEND; | |
708 | ||
709 | if (loop) | |
710 | buf[0] |= (1 << 2); | |
711 | ||
712 | if (!forever) | |
713 | buf[0] |= (1 << 4); | |
714 | ||
715 | if (cond == SINGLE) | |
716 | buf[0] |= (0 << 1) | (1 << 0); | |
717 | else if (cond == BURST) | |
718 | buf[0] |= (1 << 1) | (1 << 0); | |
719 | ||
720 | buf[1] = bjump; | |
721 | ||
722 | PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n", | |
723 | forever ? "FE" : "END", | |
724 | cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'), | |
725 | loop ? '1' : '0', | |
726 | bjump); | |
727 | ||
728 | return SZ_DMALPEND; | |
729 | } | |
730 | ||
731 | static inline u32 _emit_KILL(unsigned dry_run, u8 buf[]) | |
732 | { | |
733 | if (dry_run) | |
734 | return SZ_DMAKILL; | |
735 | ||
736 | buf[0] = CMD_DMAKILL; | |
737 | ||
738 | return SZ_DMAKILL; | |
739 | } | |
740 | ||
741 | static inline u32 _emit_MOV(unsigned dry_run, u8 buf[], | |
742 | enum dmamov_dst dst, u32 val) | |
743 | { | |
744 | if (dry_run) | |
745 | return SZ_DMAMOV; | |
746 | ||
747 | buf[0] = CMD_DMAMOV; | |
748 | buf[1] = dst; | |
749 | *((u32 *)&buf[2]) = val; | |
750 | ||
751 | PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n", | |
752 | dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val); | |
753 | ||
754 | return SZ_DMAMOV; | |
755 | } | |
756 | ||
757 | static inline u32 _emit_NOP(unsigned dry_run, u8 buf[]) | |
758 | { | |
759 | if (dry_run) | |
760 | return SZ_DMANOP; | |
761 | ||
762 | buf[0] = CMD_DMANOP; | |
763 | ||
764 | PL330_DBGCMD_DUMP(SZ_DMANOP, "\tDMANOP\n"); | |
765 | ||
766 | return SZ_DMANOP; | |
767 | } | |
768 | ||
769 | static inline u32 _emit_RMB(unsigned dry_run, u8 buf[]) | |
770 | { | |
771 | if (dry_run) | |
772 | return SZ_DMARMB; | |
773 | ||
774 | buf[0] = CMD_DMARMB; | |
775 | ||
776 | PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n"); | |
777 | ||
778 | return SZ_DMARMB; | |
779 | } | |
780 | ||
781 | static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev) | |
782 | { | |
783 | if (dry_run) | |
784 | return SZ_DMASEV; | |
785 | ||
786 | buf[0] = CMD_DMASEV; | |
787 | ||
788 | ev &= 0x1f; | |
789 | ev <<= 3; | |
790 | buf[1] = ev; | |
791 | ||
792 | PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3); | |
793 | ||
794 | return SZ_DMASEV; | |
795 | } | |
796 | ||
797 | static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond) | |
798 | { | |
799 | if (dry_run) | |
800 | return SZ_DMAST; | |
801 | ||
802 | buf[0] = CMD_DMAST; | |
803 | ||
804 | if (cond == SINGLE) | |
805 | buf[0] |= (0 << 1) | (1 << 0); | |
806 | else if (cond == BURST) | |
807 | buf[0] |= (1 << 1) | (1 << 0); | |
808 | ||
809 | PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n", | |
810 | cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A')); | |
811 | ||
812 | return SZ_DMAST; | |
813 | } | |
814 | ||
815 | static inline u32 _emit_STP(unsigned dry_run, u8 buf[], | |
816 | enum pl330_cond cond, u8 peri) | |
817 | { | |
818 | if (dry_run) | |
819 | return SZ_DMASTP; | |
820 | ||
821 | buf[0] = CMD_DMASTP; | |
822 | ||
823 | if (cond == BURST) | |
824 | buf[0] |= (1 << 1); | |
825 | ||
826 | peri &= 0x1f; | |
827 | peri <<= 3; | |
828 | buf[1] = peri; | |
829 | ||
830 | PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n", | |
831 | cond == SINGLE ? 'S' : 'B', peri >> 3); | |
832 | ||
833 | return SZ_DMASTP; | |
834 | } | |
835 | ||
836 | static inline u32 _emit_STZ(unsigned dry_run, u8 buf[]) | |
837 | { | |
838 | if (dry_run) | |
839 | return SZ_DMASTZ; | |
840 | ||
841 | buf[0] = CMD_DMASTZ; | |
842 | ||
843 | PL330_DBGCMD_DUMP(SZ_DMASTZ, "\tDMASTZ\n"); | |
844 | ||
845 | return SZ_DMASTZ; | |
846 | } | |
847 | ||
848 | static inline u32 _emit_WFE(unsigned dry_run, u8 buf[], u8 ev, | |
849 | unsigned invalidate) | |
850 | { | |
851 | if (dry_run) | |
852 | return SZ_DMAWFE; | |
853 | ||
854 | buf[0] = CMD_DMAWFE; | |
855 | ||
856 | ev &= 0x1f; | |
857 | ev <<= 3; | |
858 | buf[1] = ev; | |
859 | ||
860 | if (invalidate) | |
861 | buf[1] |= (1 << 1); | |
862 | ||
863 | PL330_DBGCMD_DUMP(SZ_DMAWFE, "\tDMAWFE %u%s\n", | |
864 | ev >> 3, invalidate ? ", I" : ""); | |
865 | ||
866 | return SZ_DMAWFE; | |
867 | } | |
868 | ||
869 | static inline u32 _emit_WFP(unsigned dry_run, u8 buf[], | |
870 | enum pl330_cond cond, u8 peri) | |
871 | { | |
872 | if (dry_run) | |
873 | return SZ_DMAWFP; | |
874 | ||
875 | buf[0] = CMD_DMAWFP; | |
876 | ||
877 | if (cond == SINGLE) | |
878 | buf[0] |= (0 << 1) | (0 << 0); | |
879 | else if (cond == BURST) | |
880 | buf[0] |= (1 << 1) | (0 << 0); | |
881 | else | |
882 | buf[0] |= (0 << 1) | (1 << 0); | |
883 | ||
884 | peri &= 0x1f; | |
885 | peri <<= 3; | |
886 | buf[1] = peri; | |
887 | ||
888 | PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n", | |
889 | cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3); | |
890 | ||
891 | return SZ_DMAWFP; | |
892 | } | |
893 | ||
894 | static inline u32 _emit_WMB(unsigned dry_run, u8 buf[]) | |
895 | { | |
896 | if (dry_run) | |
897 | return SZ_DMAWMB; | |
898 | ||
899 | buf[0] = CMD_DMAWMB; | |
900 | ||
901 | PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n"); | |
902 | ||
903 | return SZ_DMAWMB; | |
904 | } | |
905 | ||
906 | struct _arg_GO { | |
907 | u8 chan; | |
908 | u32 addr; | |
909 | unsigned ns; | |
910 | }; | |
911 | ||
912 | static inline u32 _emit_GO(unsigned dry_run, u8 buf[], | |
913 | const struct _arg_GO *arg) | |
914 | { | |
915 | u8 chan = arg->chan; | |
916 | u32 addr = arg->addr; | |
917 | unsigned ns = arg->ns; | |
918 | ||
919 | if (dry_run) | |
920 | return SZ_DMAGO; | |
921 | ||
922 | buf[0] = CMD_DMAGO; | |
923 | buf[0] |= (ns << 1); | |
924 | ||
925 | buf[1] = chan & 0x7; | |
926 | ||
927 | *((u32 *)&buf[2]) = addr; | |
928 | ||
929 | return SZ_DMAGO; | |
930 | } | |
931 | ||
932 | #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) | |
933 | ||
934 | /* Returns Time-Out */ | |
935 | static bool _until_dmac_idle(struct pl330_thread *thrd) | |
936 | { | |
937 | void __iomem *regs = thrd->dmac->pinfo->base; | |
938 | unsigned long loops = msecs_to_loops(5); | |
939 | ||
940 | do { | |
941 | /* Until Manager is Idle */ | |
942 | if (!(readl(regs + DBGSTATUS) & DBG_BUSY)) | |
943 | break; | |
944 | ||
945 | cpu_relax(); | |
946 | } while (--loops); | |
947 | ||
948 | if (!loops) | |
949 | return true; | |
950 | ||
951 | return false; | |
952 | } | |
953 | ||
954 | static inline void _execute_DBGINSN(struct pl330_thread *thrd, | |
955 | u8 insn[], bool as_manager) | |
956 | { | |
957 | void __iomem *regs = thrd->dmac->pinfo->base; | |
958 | u32 val; | |
959 | ||
960 | val = (insn[0] << 16) | (insn[1] << 24); | |
961 | if (!as_manager) { | |
962 | val |= (1 << 0); | |
963 | val |= (thrd->id << 8); /* Channel Number */ | |
964 | } | |
965 | writel(val, regs + DBGINST0); | |
966 | ||
967 | val = *((u32 *)&insn[2]); | |
968 | writel(val, regs + DBGINST1); | |
969 | ||
970 | /* If timed out due to halted state-machine */ | |
971 | if (_until_dmac_idle(thrd)) { | |
972 | dev_err(thrd->dmac->pinfo->dev, "DMAC halted!\n"); | |
973 | return; | |
974 | } | |
975 | ||
976 | /* Get going */ | |
977 | writel(0, regs + DBGCMD); | |
978 | } | |
979 | ||
980 | /* | |
981 | * Mark a _pl330_req as free. | |
982 | * We do it by writing DMAEND as the first instruction | |
983 | * because no valid request is going to have DMAEND as | |
984 | * its first instruction to execute. | |
985 | */ | |
986 | static void mark_free(struct pl330_thread *thrd, int idx) | |
987 | { | |
988 | struct _pl330_req *req = &thrd->req[idx]; | |
989 | ||
990 | _emit_END(0, req->mc_cpu); | |
b7d861d9 BK |
991 | |
992 | thrd->req_running = -1; | |
993 | } | |
994 | ||
995 | static inline u32 _state(struct pl330_thread *thrd) | |
996 | { | |
997 | void __iomem *regs = thrd->dmac->pinfo->base; | |
998 | u32 val; | |
999 | ||
1000 | if (is_manager(thrd)) | |
1001 | val = readl(regs + DS) & 0xf; | |
1002 | else | |
1003 | val = readl(regs + CS(thrd->id)) & 0xf; | |
1004 | ||
1005 | switch (val) { | |
1006 | case DS_ST_STOP: | |
1007 | return PL330_STATE_STOPPED; | |
1008 | case DS_ST_EXEC: | |
1009 | return PL330_STATE_EXECUTING; | |
1010 | case DS_ST_CMISS: | |
1011 | return PL330_STATE_CACHEMISS; | |
1012 | case DS_ST_UPDTPC: | |
1013 | return PL330_STATE_UPDTPC; | |
1014 | case DS_ST_WFE: | |
1015 | return PL330_STATE_WFE; | |
1016 | case DS_ST_FAULT: | |
1017 | return PL330_STATE_FAULTING; | |
1018 | case DS_ST_ATBRR: | |
1019 | if (is_manager(thrd)) | |
1020 | return PL330_STATE_INVALID; | |
1021 | else | |
1022 | return PL330_STATE_ATBARRIER; | |
1023 | case DS_ST_QBUSY: | |
1024 | if (is_manager(thrd)) | |
1025 | return PL330_STATE_INVALID; | |
1026 | else | |
1027 | return PL330_STATE_QUEUEBUSY; | |
1028 | case DS_ST_WFP: | |
1029 | if (is_manager(thrd)) | |
1030 | return PL330_STATE_INVALID; | |
1031 | else | |
1032 | return PL330_STATE_WFP; | |
1033 | case DS_ST_KILL: | |
1034 | if (is_manager(thrd)) | |
1035 | return PL330_STATE_INVALID; | |
1036 | else | |
1037 | return PL330_STATE_KILLING; | |
1038 | case DS_ST_CMPLT: | |
1039 | if (is_manager(thrd)) | |
1040 | return PL330_STATE_INVALID; | |
1041 | else | |
1042 | return PL330_STATE_COMPLETING; | |
1043 | case DS_ST_FLTCMP: | |
1044 | if (is_manager(thrd)) | |
1045 | return PL330_STATE_INVALID; | |
1046 | else | |
1047 | return PL330_STATE_FAULT_COMPLETING; | |
1048 | default: | |
1049 | return PL330_STATE_INVALID; | |
1050 | } | |
1051 | } | |
1052 | ||
1053 | static void _stop(struct pl330_thread *thrd) | |
1054 | { | |
1055 | void __iomem *regs = thrd->dmac->pinfo->base; | |
1056 | u8 insn[6] = {0, 0, 0, 0, 0, 0}; | |
1057 | ||
1058 | if (_state(thrd) == PL330_STATE_FAULT_COMPLETING) | |
1059 | UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING); | |
1060 | ||
1061 | /* Return if nothing needs to be done */ | |
1062 | if (_state(thrd) == PL330_STATE_COMPLETING | |
1063 | || _state(thrd) == PL330_STATE_KILLING | |
1064 | || _state(thrd) == PL330_STATE_STOPPED) | |
1065 | return; | |
1066 | ||
1067 | _emit_KILL(0, insn); | |
1068 | ||
1069 | /* Stop generating interrupts for SEV */ | |
1070 | writel(readl(regs + INTEN) & ~(1 << thrd->ev), regs + INTEN); | |
1071 | ||
1072 | _execute_DBGINSN(thrd, insn, is_manager(thrd)); | |
1073 | } | |
1074 | ||
1075 | /* Start doing req 'idx' of thread 'thrd' */ | |
1076 | static bool _trigger(struct pl330_thread *thrd) | |
1077 | { | |
1078 | void __iomem *regs = thrd->dmac->pinfo->base; | |
1079 | struct _pl330_req *req; | |
1080 | struct pl330_req *r; | |
1081 | struct _arg_GO go; | |
1082 | unsigned ns; | |
1083 | u8 insn[6] = {0, 0, 0, 0, 0, 0}; | |
1084 | int idx; | |
1085 | ||
1086 | /* Return if already ACTIVE */ | |
1087 | if (_state(thrd) != PL330_STATE_STOPPED) | |
1088 | return true; | |
1089 | ||
1090 | idx = 1 - thrd->lstenq; | |
1091 | if (!IS_FREE(&thrd->req[idx])) | |
1092 | req = &thrd->req[idx]; | |
1093 | else { | |
1094 | idx = thrd->lstenq; | |
1095 | if (!IS_FREE(&thrd->req[idx])) | |
1096 | req = &thrd->req[idx]; | |
1097 | else | |
1098 | req = NULL; | |
1099 | } | |
1100 | ||
1101 | /* Return if no request */ | |
1102 | if (!req || !req->r) | |
1103 | return true; | |
1104 | ||
1105 | r = req->r; | |
1106 | ||
1107 | if (r->cfg) | |
1108 | ns = r->cfg->nonsecure ? 1 : 0; | |
1109 | else if (readl(regs + CS(thrd->id)) & CS_CNS) | |
1110 | ns = 1; | |
1111 | else | |
1112 | ns = 0; | |
1113 | ||
1114 | /* See 'Abort Sources' point-4 at Page 2-25 */ | |
1115 | if (_manager_ns(thrd) && !ns) | |
1116 | dev_info(thrd->dmac->pinfo->dev, "%s:%d Recipe for ABORT!\n", | |
1117 | __func__, __LINE__); | |
1118 | ||
1119 | go.chan = thrd->id; | |
1120 | go.addr = req->mc_bus; | |
1121 | go.ns = ns; | |
1122 | _emit_GO(0, insn, &go); | |
1123 | ||
1124 | /* Set to generate interrupts for SEV */ | |
1125 | writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN); | |
1126 | ||
1127 | /* Only manager can execute GO */ | |
1128 | _execute_DBGINSN(thrd, insn, true); | |
1129 | ||
1130 | thrd->req_running = idx; | |
1131 | ||
1132 | return true; | |
1133 | } | |
1134 | ||
1135 | static bool _start(struct pl330_thread *thrd) | |
1136 | { | |
1137 | switch (_state(thrd)) { | |
1138 | case PL330_STATE_FAULT_COMPLETING: | |
1139 | UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING); | |
1140 | ||
1141 | if (_state(thrd) == PL330_STATE_KILLING) | |
1142 | UNTIL(thrd, PL330_STATE_STOPPED) | |
1143 | ||
1144 | case PL330_STATE_FAULTING: | |
1145 | _stop(thrd); | |
1146 | ||
1147 | case PL330_STATE_KILLING: | |
1148 | case PL330_STATE_COMPLETING: | |
1149 | UNTIL(thrd, PL330_STATE_STOPPED) | |
1150 | ||
1151 | case PL330_STATE_STOPPED: | |
1152 | return _trigger(thrd); | |
1153 | ||
1154 | case PL330_STATE_WFP: | |
1155 | case PL330_STATE_QUEUEBUSY: | |
1156 | case PL330_STATE_ATBARRIER: | |
1157 | case PL330_STATE_UPDTPC: | |
1158 | case PL330_STATE_CACHEMISS: | |
1159 | case PL330_STATE_EXECUTING: | |
1160 | return true; | |
1161 | ||
1162 | case PL330_STATE_WFE: /* For RESUME, nothing yet */ | |
1163 | default: | |
1164 | return false; | |
1165 | } | |
1166 | } | |
1167 | ||
1168 | static inline int _ldst_memtomem(unsigned dry_run, u8 buf[], | |
1169 | const struct _xfer_spec *pxs, int cyc) | |
1170 | { | |
1171 | int off = 0; | |
3ecf51a4 | 1172 | struct pl330_config *pcfg = pxs->r->cfg->pcfg; |
b7d861d9 | 1173 | |
3ecf51a4 BK |
1174 | /* check lock-up free version */ |
1175 | if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) { | |
1176 | while (cyc--) { | |
1177 | off += _emit_LD(dry_run, &buf[off], ALWAYS); | |
1178 | off += _emit_ST(dry_run, &buf[off], ALWAYS); | |
1179 | } | |
1180 | } else { | |
1181 | while (cyc--) { | |
1182 | off += _emit_LD(dry_run, &buf[off], ALWAYS); | |
1183 | off += _emit_RMB(dry_run, &buf[off]); | |
1184 | off += _emit_ST(dry_run, &buf[off], ALWAYS); | |
1185 | off += _emit_WMB(dry_run, &buf[off]); | |
1186 | } | |
b7d861d9 BK |
1187 | } |
1188 | ||
1189 | return off; | |
1190 | } | |
1191 | ||
1192 | static inline int _ldst_devtomem(unsigned dry_run, u8 buf[], | |
1193 | const struct _xfer_spec *pxs, int cyc) | |
1194 | { | |
1195 | int off = 0; | |
1196 | ||
1197 | while (cyc--) { | |
1198 | off += _emit_WFP(dry_run, &buf[off], SINGLE, pxs->r->peri); | |
1199 | off += _emit_LDP(dry_run, &buf[off], SINGLE, pxs->r->peri); | |
1200 | off += _emit_ST(dry_run, &buf[off], ALWAYS); | |
1201 | off += _emit_FLUSHP(dry_run, &buf[off], pxs->r->peri); | |
1202 | } | |
1203 | ||
1204 | return off; | |
1205 | } | |
1206 | ||
1207 | static inline int _ldst_memtodev(unsigned dry_run, u8 buf[], | |
1208 | const struct _xfer_spec *pxs, int cyc) | |
1209 | { | |
1210 | int off = 0; | |
1211 | ||
1212 | while (cyc--) { | |
1213 | off += _emit_WFP(dry_run, &buf[off], SINGLE, pxs->r->peri); | |
1214 | off += _emit_LD(dry_run, &buf[off], ALWAYS); | |
1215 | off += _emit_STP(dry_run, &buf[off], SINGLE, pxs->r->peri); | |
1216 | off += _emit_FLUSHP(dry_run, &buf[off], pxs->r->peri); | |
1217 | } | |
1218 | ||
1219 | return off; | |
1220 | } | |
1221 | ||
1222 | static int _bursts(unsigned dry_run, u8 buf[], | |
1223 | const struct _xfer_spec *pxs, int cyc) | |
1224 | { | |
1225 | int off = 0; | |
1226 | ||
1227 | switch (pxs->r->rqtype) { | |
585a9d0b | 1228 | case DMA_MEM_TO_DEV: |
b7d861d9 BK |
1229 | off += _ldst_memtodev(dry_run, &buf[off], pxs, cyc); |
1230 | break; | |
585a9d0b | 1231 | case DMA_DEV_TO_MEM: |
b7d861d9 BK |
1232 | off += _ldst_devtomem(dry_run, &buf[off], pxs, cyc); |
1233 | break; | |
585a9d0b | 1234 | case DMA_MEM_TO_MEM: |
b7d861d9 BK |
1235 | off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc); |
1236 | break; | |
1237 | default: | |
1238 | off += 0x40000000; /* Scare off the Client */ | |
1239 | break; | |
1240 | } | |
1241 | ||
1242 | return off; | |
1243 | } | |
1244 | ||
1245 | /* Returns bytes consumed and updates bursts */ | |
1246 | static inline int _loop(unsigned dry_run, u8 buf[], | |
1247 | unsigned long *bursts, const struct _xfer_spec *pxs) | |
1248 | { | |
1249 | int cyc, cycmax, szlp, szlpend, szbrst, off; | |
1250 | unsigned lcnt0, lcnt1, ljmp0, ljmp1; | |
1251 | struct _arg_LPEND lpend; | |
1252 | ||
1253 | /* Max iterations possible in DMALP is 256 */ | |
1254 | if (*bursts >= 256*256) { | |
1255 | lcnt1 = 256; | |
1256 | lcnt0 = 256; | |
1257 | cyc = *bursts / lcnt1 / lcnt0; | |
1258 | } else if (*bursts > 256) { | |
1259 | lcnt1 = 256; | |
1260 | lcnt0 = *bursts / lcnt1; | |
1261 | cyc = 1; | |
1262 | } else { | |
1263 | lcnt1 = *bursts; | |
1264 | lcnt0 = 0; | |
1265 | cyc = 1; | |
1266 | } | |
1267 | ||
1268 | szlp = _emit_LP(1, buf, 0, 0); | |
1269 | szbrst = _bursts(1, buf, pxs, 1); | |
1270 | ||
1271 | lpend.cond = ALWAYS; | |
1272 | lpend.forever = false; | |
1273 | lpend.loop = 0; | |
1274 | lpend.bjump = 0; | |
1275 | szlpend = _emit_LPEND(1, buf, &lpend); | |
1276 | ||
1277 | if (lcnt0) { | |
1278 | szlp *= 2; | |
1279 | szlpend *= 2; | |
1280 | } | |
1281 | ||
1282 | /* | |
1283 | * Max bursts that we can unroll due to limit on the | |
1284 | * size of backward jump that can be encoded in DMALPEND | |
1285 | * which is 8-bits and hence 255 | |
1286 | */ | |
1287 | cycmax = (255 - (szlp + szlpend)) / szbrst; | |
1288 | ||
1289 | cyc = (cycmax < cyc) ? cycmax : cyc; | |
1290 | ||
1291 | off = 0; | |
1292 | ||
1293 | if (lcnt0) { | |
1294 | off += _emit_LP(dry_run, &buf[off], 0, lcnt0); | |
1295 | ljmp0 = off; | |
1296 | } | |
1297 | ||
1298 | off += _emit_LP(dry_run, &buf[off], 1, lcnt1); | |
1299 | ljmp1 = off; | |
1300 | ||
1301 | off += _bursts(dry_run, &buf[off], pxs, cyc); | |
1302 | ||
1303 | lpend.cond = ALWAYS; | |
1304 | lpend.forever = false; | |
1305 | lpend.loop = 1; | |
1306 | lpend.bjump = off - ljmp1; | |
1307 | off += _emit_LPEND(dry_run, &buf[off], &lpend); | |
1308 | ||
1309 | if (lcnt0) { | |
1310 | lpend.cond = ALWAYS; | |
1311 | lpend.forever = false; | |
1312 | lpend.loop = 0; | |
1313 | lpend.bjump = off - ljmp0; | |
1314 | off += _emit_LPEND(dry_run, &buf[off], &lpend); | |
1315 | } | |
1316 | ||
1317 | *bursts = lcnt1 * cyc; | |
1318 | if (lcnt0) | |
1319 | *bursts *= lcnt0; | |
1320 | ||
1321 | return off; | |
1322 | } | |
1323 | ||
1324 | static inline int _setup_loops(unsigned dry_run, u8 buf[], | |
1325 | const struct _xfer_spec *pxs) | |
1326 | { | |
1327 | struct pl330_xfer *x = pxs->x; | |
1328 | u32 ccr = pxs->ccr; | |
1329 | unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr); | |
1330 | int off = 0; | |
1331 | ||
1332 | while (bursts) { | |
1333 | c = bursts; | |
1334 | off += _loop(dry_run, &buf[off], &c, pxs); | |
1335 | bursts -= c; | |
1336 | } | |
1337 | ||
1338 | return off; | |
1339 | } | |
1340 | ||
1341 | static inline int _setup_xfer(unsigned dry_run, u8 buf[], | |
1342 | const struct _xfer_spec *pxs) | |
1343 | { | |
1344 | struct pl330_xfer *x = pxs->x; | |
1345 | int off = 0; | |
1346 | ||
1347 | /* DMAMOV SAR, x->src_addr */ | |
1348 | off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr); | |
1349 | /* DMAMOV DAR, x->dst_addr */ | |
1350 | off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr); | |
1351 | ||
1352 | /* Setup Loop(s) */ | |
1353 | off += _setup_loops(dry_run, &buf[off], pxs); | |
1354 | ||
1355 | return off; | |
1356 | } | |
1357 | ||
1358 | /* | |
1359 | * A req is a sequence of one or more xfer units. | |
1360 | * Returns the number of bytes taken to setup the MC for the req. | |
1361 | */ | |
1362 | static int _setup_req(unsigned dry_run, struct pl330_thread *thrd, | |
1363 | unsigned index, struct _xfer_spec *pxs) | |
1364 | { | |
1365 | struct _pl330_req *req = &thrd->req[index]; | |
1366 | struct pl330_xfer *x; | |
1367 | u8 *buf = req->mc_cpu; | |
1368 | int off = 0; | |
1369 | ||
1370 | PL330_DBGMC_START(req->mc_bus); | |
1371 | ||
1372 | /* DMAMOV CCR, ccr */ | |
1373 | off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr); | |
1374 | ||
1375 | x = pxs->r->x; | |
d5cef121 LPC |
1376 | /* Error if xfer length is not aligned at burst size */ |
1377 | if (x->bytes % (BRST_SIZE(pxs->ccr) * BRST_LEN(pxs->ccr))) | |
1378 | return -EINVAL; | |
b7d861d9 | 1379 | |
d5cef121 LPC |
1380 | pxs->x = x; |
1381 | off += _setup_xfer(dry_run, &buf[off], pxs); | |
b7d861d9 BK |
1382 | |
1383 | /* DMASEV peripheral/event */ | |
1384 | off += _emit_SEV(dry_run, &buf[off], thrd->ev); | |
1385 | /* DMAEND */ | |
1386 | off += _emit_END(dry_run, &buf[off]); | |
1387 | ||
1388 | return off; | |
1389 | } | |
1390 | ||
1391 | static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc) | |
1392 | { | |
1393 | u32 ccr = 0; | |
1394 | ||
1395 | if (rqc->src_inc) | |
1396 | ccr |= CC_SRCINC; | |
1397 | ||
1398 | if (rqc->dst_inc) | |
1399 | ccr |= CC_DSTINC; | |
1400 | ||
1401 | /* We set same protection levels for Src and DST for now */ | |
1402 | if (rqc->privileged) | |
1403 | ccr |= CC_SRCPRI | CC_DSTPRI; | |
1404 | if (rqc->nonsecure) | |
1405 | ccr |= CC_SRCNS | CC_DSTNS; | |
1406 | if (rqc->insnaccess) | |
1407 | ccr |= CC_SRCIA | CC_DSTIA; | |
1408 | ||
1409 | ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT); | |
1410 | ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT); | |
1411 | ||
1412 | ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT); | |
1413 | ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT); | |
1414 | ||
1415 | ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT); | |
1416 | ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT); | |
1417 | ||
1418 | ccr |= (rqc->swap << CC_SWAP_SHFT); | |
1419 | ||
1420 | return ccr; | |
1421 | } | |
1422 | ||
b7d861d9 BK |
1423 | /* |
1424 | * Submit a list of xfers after which the client wants notification. | |
1425 | * Client is not notified after each xfer unit, just once after all | |
1426 | * xfer units are done or some error occurs. | |
1427 | */ | |
65ad6060 | 1428 | static int pl330_submit_req(struct pl330_thread *thrd, struct pl330_req *r) |
b7d861d9 | 1429 | { |
b7d861d9 BK |
1430 | struct pl330_dmac *pl330; |
1431 | struct pl330_info *pi; | |
1432 | struct _xfer_spec xs; | |
1433 | unsigned long flags; | |
1434 | void __iomem *regs; | |
1435 | unsigned idx; | |
1436 | u32 ccr; | |
1437 | int ret = 0; | |
1438 | ||
1439 | /* No Req or Unacquired Channel or DMAC */ | |
1440 | if (!r || !thrd || thrd->free) | |
1441 | return -EINVAL; | |
1442 | ||
1443 | pl330 = thrd->dmac; | |
1444 | pi = pl330->pinfo; | |
1445 | regs = pi->base; | |
1446 | ||
1447 | if (pl330->state == DYING | |
1448 | || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) { | |
1449 | dev_info(thrd->dmac->pinfo->dev, "%s:%d\n", | |
1450 | __func__, __LINE__); | |
1451 | return -EAGAIN; | |
1452 | } | |
1453 | ||
1454 | /* If request for non-existing peripheral */ | |
585a9d0b | 1455 | if (r->rqtype != DMA_MEM_TO_MEM && r->peri >= pi->pcfg.num_peri) { |
b7d861d9 BK |
1456 | dev_info(thrd->dmac->pinfo->dev, |
1457 | "%s:%d Invalid peripheral(%u)!\n", | |
1458 | __func__, __LINE__, r->peri); | |
1459 | return -EINVAL; | |
1460 | } | |
1461 | ||
1462 | spin_lock_irqsave(&pl330->lock, flags); | |
1463 | ||
1464 | if (_queue_full(thrd)) { | |
1465 | ret = -EAGAIN; | |
1466 | goto xfer_exit; | |
1467 | } | |
1468 | ||
b7d861d9 BK |
1469 | |
1470 | /* Use last settings, if not provided */ | |
2e2c682b SK |
1471 | if (r->cfg) { |
1472 | /* Prefer Secure Channel */ | |
1473 | if (!_manager_ns(thrd)) | |
1474 | r->cfg->nonsecure = 0; | |
1475 | else | |
1476 | r->cfg->nonsecure = 1; | |
1477 | ||
b7d861d9 | 1478 | ccr = _prepare_ccr(r->cfg); |
2e2c682b | 1479 | } else { |
b7d861d9 | 1480 | ccr = readl(regs + CC(thrd->id)); |
2e2c682b | 1481 | } |
b7d861d9 | 1482 | |
b7d861d9 BK |
1483 | idx = IS_FREE(&thrd->req[0]) ? 0 : 1; |
1484 | ||
1485 | xs.ccr = ccr; | |
1486 | xs.r = r; | |
1487 | ||
1488 | /* First dry run to check if req is acceptable */ | |
1489 | ret = _setup_req(1, thrd, idx, &xs); | |
1490 | if (ret < 0) | |
1491 | goto xfer_exit; | |
1492 | ||
1493 | if (ret > pi->mcbufsz / 2) { | |
1494 | dev_info(thrd->dmac->pinfo->dev, | |
1495 | "%s:%d Trying increasing mcbufsz\n", | |
1496 | __func__, __LINE__); | |
1497 | ret = -ENOMEM; | |
1498 | goto xfer_exit; | |
1499 | } | |
1500 | ||
1501 | /* Hook the request */ | |
1502 | thrd->lstenq = idx; | |
b7d861d9 | 1503 | thrd->req[idx].r = r; |
be025329 | 1504 | _setup_req(0, thrd, idx, &xs); |
b7d861d9 BK |
1505 | |
1506 | ret = 0; | |
1507 | ||
1508 | xfer_exit: | |
1509 | spin_unlock_irqrestore(&pl330->lock, flags); | |
1510 | ||
1511 | return ret; | |
1512 | } | |
1513 | ||
6079d38c LPC |
1514 | static void dma_pl330_rqcb(struct pl330_req *req, enum pl330_op_err err) |
1515 | { | |
1516 | struct dma_pl330_desc *desc = container_of(req, struct dma_pl330_desc, req); | |
1517 | struct dma_pl330_chan *pch = desc->pchan; | |
1518 | unsigned long flags; | |
1519 | ||
1520 | /* If desc aborted */ | |
1521 | if (!pch) | |
1522 | return; | |
1523 | ||
1524 | spin_lock_irqsave(&pch->lock, flags); | |
1525 | ||
1526 | desc->status = DONE; | |
1527 | ||
1528 | spin_unlock_irqrestore(&pch->lock, flags); | |
1529 | ||
1530 | tasklet_schedule(&pch->task); | |
1531 | } | |
1532 | ||
b7d861d9 BK |
1533 | static void pl330_dotask(unsigned long data) |
1534 | { | |
1535 | struct pl330_dmac *pl330 = (struct pl330_dmac *) data; | |
1536 | struct pl330_info *pi = pl330->pinfo; | |
1537 | unsigned long flags; | |
1538 | int i; | |
1539 | ||
1540 | spin_lock_irqsave(&pl330->lock, flags); | |
1541 | ||
1542 | /* The DMAC itself gone nuts */ | |
1543 | if (pl330->dmac_tbd.reset_dmac) { | |
1544 | pl330->state = DYING; | |
1545 | /* Reset the manager too */ | |
1546 | pl330->dmac_tbd.reset_mngr = true; | |
1547 | /* Clear the reset flag */ | |
1548 | pl330->dmac_tbd.reset_dmac = false; | |
1549 | } | |
1550 | ||
1551 | if (pl330->dmac_tbd.reset_mngr) { | |
1552 | _stop(pl330->manager); | |
1553 | /* Reset all channels */ | |
1554 | pl330->dmac_tbd.reset_chan = (1 << pi->pcfg.num_chan) - 1; | |
1555 | /* Clear the reset flag */ | |
1556 | pl330->dmac_tbd.reset_mngr = false; | |
1557 | } | |
1558 | ||
1559 | for (i = 0; i < pi->pcfg.num_chan; i++) { | |
1560 | ||
1561 | if (pl330->dmac_tbd.reset_chan & (1 << i)) { | |
1562 | struct pl330_thread *thrd = &pl330->channels[i]; | |
1563 | void __iomem *regs = pi->base; | |
1564 | enum pl330_op_err err; | |
1565 | ||
1566 | _stop(thrd); | |
1567 | ||
1568 | if (readl(regs + FSC) & (1 << thrd->id)) | |
1569 | err = PL330_ERR_FAIL; | |
1570 | else | |
1571 | err = PL330_ERR_ABORT; | |
1572 | ||
1573 | spin_unlock_irqrestore(&pl330->lock, flags); | |
6079d38c LPC |
1574 | dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].r, err); |
1575 | dma_pl330_rqcb(thrd->req[thrd->lstenq].r, err); | |
b7d861d9 BK |
1576 | spin_lock_irqsave(&pl330->lock, flags); |
1577 | ||
1578 | thrd->req[0].r = NULL; | |
1579 | thrd->req[1].r = NULL; | |
1580 | mark_free(thrd, 0); | |
1581 | mark_free(thrd, 1); | |
1582 | ||
1583 | /* Clear the reset flag */ | |
1584 | pl330->dmac_tbd.reset_chan &= ~(1 << i); | |
1585 | } | |
1586 | } | |
1587 | ||
1588 | spin_unlock_irqrestore(&pl330->lock, flags); | |
1589 | ||
1590 | return; | |
1591 | } | |
1592 | ||
1593 | /* Returns 1 if state was updated, 0 otherwise */ | |
1594 | static int pl330_update(const struct pl330_info *pi) | |
1595 | { | |
fdec53d5 | 1596 | struct pl330_req *rqdone, *tmp; |
b7d861d9 BK |
1597 | struct pl330_dmac *pl330; |
1598 | unsigned long flags; | |
1599 | void __iomem *regs; | |
1600 | u32 val; | |
1601 | int id, ev, ret = 0; | |
1602 | ||
1603 | if (!pi || !pi->pl330_data) | |
1604 | return 0; | |
1605 | ||
1606 | regs = pi->base; | |
1607 | pl330 = pi->pl330_data; | |
1608 | ||
1609 | spin_lock_irqsave(&pl330->lock, flags); | |
1610 | ||
1611 | val = readl(regs + FSM) & 0x1; | |
1612 | if (val) | |
1613 | pl330->dmac_tbd.reset_mngr = true; | |
1614 | else | |
1615 | pl330->dmac_tbd.reset_mngr = false; | |
1616 | ||
1617 | val = readl(regs + FSC) & ((1 << pi->pcfg.num_chan) - 1); | |
1618 | pl330->dmac_tbd.reset_chan |= val; | |
1619 | if (val) { | |
1620 | int i = 0; | |
1621 | while (i < pi->pcfg.num_chan) { | |
1622 | if (val & (1 << i)) { | |
1623 | dev_info(pi->dev, | |
1624 | "Reset Channel-%d\t CS-%x FTC-%x\n", | |
1625 | i, readl(regs + CS(i)), | |
1626 | readl(regs + FTC(i))); | |
1627 | _stop(&pl330->channels[i]); | |
1628 | } | |
1629 | i++; | |
1630 | } | |
1631 | } | |
1632 | ||
1633 | /* Check which event happened i.e, thread notified */ | |
1634 | val = readl(regs + ES); | |
1635 | if (pi->pcfg.num_events < 32 | |
1636 | && val & ~((1 << pi->pcfg.num_events) - 1)) { | |
1637 | pl330->dmac_tbd.reset_dmac = true; | |
1638 | dev_err(pi->dev, "%s:%d Unexpected!\n", __func__, __LINE__); | |
1639 | ret = 1; | |
1640 | goto updt_exit; | |
1641 | } | |
1642 | ||
1643 | for (ev = 0; ev < pi->pcfg.num_events; ev++) { | |
1644 | if (val & (1 << ev)) { /* Event occurred */ | |
1645 | struct pl330_thread *thrd; | |
1646 | u32 inten = readl(regs + INTEN); | |
1647 | int active; | |
1648 | ||
1649 | /* Clear the event */ | |
1650 | if (inten & (1 << ev)) | |
1651 | writel(1 << ev, regs + INTCLR); | |
1652 | ||
1653 | ret = 1; | |
1654 | ||
1655 | id = pl330->events[ev]; | |
1656 | ||
1657 | thrd = &pl330->channels[id]; | |
1658 | ||
1659 | active = thrd->req_running; | |
1660 | if (active == -1) /* Aborted */ | |
1661 | continue; | |
1662 | ||
fdec53d5 JM |
1663 | /* Detach the req */ |
1664 | rqdone = thrd->req[active].r; | |
1665 | thrd->req[active].r = NULL; | |
1666 | ||
b7d861d9 BK |
1667 | mark_free(thrd, active); |
1668 | ||
1669 | /* Get going again ASAP */ | |
1670 | _start(thrd); | |
1671 | ||
1672 | /* For now, just make a list of callbacks to be done */ | |
1673 | list_add_tail(&rqdone->rqd, &pl330->req_done); | |
1674 | } | |
1675 | } | |
1676 | ||
1677 | /* Now that we are in no hurry, do the callbacks */ | |
fdec53d5 JM |
1678 | list_for_each_entry_safe(rqdone, tmp, &pl330->req_done, rqd) { |
1679 | list_del(&rqdone->rqd); | |
b7d861d9 BK |
1680 | |
1681 | spin_unlock_irqrestore(&pl330->lock, flags); | |
6079d38c | 1682 | dma_pl330_rqcb(rqdone, PL330_ERR_NONE); |
b7d861d9 BK |
1683 | spin_lock_irqsave(&pl330->lock, flags); |
1684 | } | |
1685 | ||
1686 | updt_exit: | |
1687 | spin_unlock_irqrestore(&pl330->lock, flags); | |
1688 | ||
1689 | if (pl330->dmac_tbd.reset_dmac | |
1690 | || pl330->dmac_tbd.reset_mngr | |
1691 | || pl330->dmac_tbd.reset_chan) { | |
1692 | ret = 1; | |
1693 | tasklet_schedule(&pl330->tasks); | |
1694 | } | |
1695 | ||
1696 | return ret; | |
1697 | } | |
1698 | ||
65ad6060 | 1699 | static int pl330_chan_ctrl(struct pl330_thread *thrd, enum pl330_chan_op op) |
b7d861d9 | 1700 | { |
b7d861d9 BK |
1701 | struct pl330_dmac *pl330; |
1702 | unsigned long flags; | |
ef08e782 | 1703 | int ret = 0, active; |
b7d861d9 BK |
1704 | |
1705 | if (!thrd || thrd->free || thrd->dmac->state == DYING) | |
1706 | return -EINVAL; | |
1707 | ||
1708 | pl330 = thrd->dmac; | |
ef08e782 | 1709 | active = thrd->req_running; |
b7d861d9 BK |
1710 | |
1711 | spin_lock_irqsave(&pl330->lock, flags); | |
1712 | ||
1713 | switch (op) { | |
1714 | case PL330_OP_FLUSH: | |
1715 | /* Make sure the channel is stopped */ | |
1716 | _stop(thrd); | |
1717 | ||
1718 | thrd->req[0].r = NULL; | |
1719 | thrd->req[1].r = NULL; | |
1720 | mark_free(thrd, 0); | |
1721 | mark_free(thrd, 1); | |
1722 | break; | |
1723 | ||
1724 | case PL330_OP_ABORT: | |
1725 | /* Make sure the channel is stopped */ | |
1726 | _stop(thrd); | |
1727 | ||
1728 | /* ABORT is only for the active req */ | |
1729 | if (active == -1) | |
1730 | break; | |
1731 | ||
1732 | thrd->req[active].r = NULL; | |
1733 | mark_free(thrd, active); | |
1734 | ||
1735 | /* Start the next */ | |
1736 | case PL330_OP_START: | |
1737 | if ((active == -1) && !_start(thrd)) | |
1738 | ret = -EIO; | |
1739 | break; | |
1740 | ||
1741 | default: | |
1742 | ret = -EINVAL; | |
1743 | } | |
1744 | ||
1745 | spin_unlock_irqrestore(&pl330->lock, flags); | |
1746 | return ret; | |
1747 | } | |
1748 | ||
b7d861d9 BK |
1749 | /* Reserve an event */ |
1750 | static inline int _alloc_event(struct pl330_thread *thrd) | |
1751 | { | |
1752 | struct pl330_dmac *pl330 = thrd->dmac; | |
1753 | struct pl330_info *pi = pl330->pinfo; | |
1754 | int ev; | |
1755 | ||
1756 | for (ev = 0; ev < pi->pcfg.num_events; ev++) | |
1757 | if (pl330->events[ev] == -1) { | |
1758 | pl330->events[ev] = thrd->id; | |
1759 | return ev; | |
1760 | } | |
1761 | ||
1762 | return -1; | |
1763 | } | |
1764 | ||
1765 | static bool _chan_ns(const struct pl330_info *pi, int i) | |
1766 | { | |
1767 | return pi->pcfg.irq_ns & (1 << i); | |
1768 | } | |
1769 | ||
1770 | /* Upon success, returns IdentityToken for the | |
1771 | * allocated channel, NULL otherwise. | |
1772 | */ | |
65ad6060 | 1773 | static struct pl330_thread *pl330_request_channel(const struct pl330_info *pi) |
b7d861d9 BK |
1774 | { |
1775 | struct pl330_thread *thrd = NULL; | |
1776 | struct pl330_dmac *pl330; | |
1777 | unsigned long flags; | |
1778 | int chans, i; | |
1779 | ||
1780 | if (!pi || !pi->pl330_data) | |
1781 | return NULL; | |
b3040e40 | 1782 | |
b7d861d9 BK |
1783 | pl330 = pi->pl330_data; |
1784 | ||
1785 | if (pl330->state == DYING) | |
1786 | return NULL; | |
1787 | ||
1788 | chans = pi->pcfg.num_chan; | |
1789 | ||
1790 | spin_lock_irqsave(&pl330->lock, flags); | |
1791 | ||
1792 | for (i = 0; i < chans; i++) { | |
1793 | thrd = &pl330->channels[i]; | |
1794 | if ((thrd->free) && (!_manager_ns(thrd) || | |
1795 | _chan_ns(pi, i))) { | |
1796 | thrd->ev = _alloc_event(thrd); | |
1797 | if (thrd->ev >= 0) { | |
1798 | thrd->free = false; | |
1799 | thrd->lstenq = 1; | |
1800 | thrd->req[0].r = NULL; | |
1801 | mark_free(thrd, 0); | |
1802 | thrd->req[1].r = NULL; | |
1803 | mark_free(thrd, 1); | |
1804 | break; | |
1805 | } | |
1806 | } | |
1807 | thrd = NULL; | |
1808 | } | |
1809 | ||
1810 | spin_unlock_irqrestore(&pl330->lock, flags); | |
1811 | ||
1812 | return thrd; | |
1813 | } | |
1814 | ||
1815 | /* Release an event */ | |
1816 | static inline void _free_event(struct pl330_thread *thrd, int ev) | |
1817 | { | |
1818 | struct pl330_dmac *pl330 = thrd->dmac; | |
1819 | struct pl330_info *pi = pl330->pinfo; | |
1820 | ||
1821 | /* If the event is valid and was held by the thread */ | |
1822 | if (ev >= 0 && ev < pi->pcfg.num_events | |
1823 | && pl330->events[ev] == thrd->id) | |
1824 | pl330->events[ev] = -1; | |
1825 | } | |
1826 | ||
65ad6060 | 1827 | static void pl330_release_channel(struct pl330_thread *thrd) |
b7d861d9 | 1828 | { |
b7d861d9 BK |
1829 | struct pl330_dmac *pl330; |
1830 | unsigned long flags; | |
1831 | ||
1832 | if (!thrd || thrd->free) | |
1833 | return; | |
1834 | ||
1835 | _stop(thrd); | |
1836 | ||
6079d38c LPC |
1837 | dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].r, PL330_ERR_ABORT); |
1838 | dma_pl330_rqcb(thrd->req[thrd->lstenq].r, PL330_ERR_ABORT); | |
b7d861d9 BK |
1839 | |
1840 | pl330 = thrd->dmac; | |
1841 | ||
1842 | spin_lock_irqsave(&pl330->lock, flags); | |
1843 | _free_event(thrd, thrd->ev); | |
1844 | thrd->free = true; | |
1845 | spin_unlock_irqrestore(&pl330->lock, flags); | |
1846 | } | |
1847 | ||
1848 | /* Initialize the structure for PL330 configuration, that can be used | |
1849 | * by the client driver the make best use of the DMAC | |
1850 | */ | |
1851 | static void read_dmac_config(struct pl330_info *pi) | |
1852 | { | |
1853 | void __iomem *regs = pi->base; | |
1854 | u32 val; | |
1855 | ||
1856 | val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT; | |
1857 | val &= CRD_DATA_WIDTH_MASK; | |
1858 | pi->pcfg.data_bus_width = 8 * (1 << val); | |
1859 | ||
1860 | val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT; | |
1861 | val &= CRD_DATA_BUFF_MASK; | |
1862 | pi->pcfg.data_buf_dep = val + 1; | |
1863 | ||
1864 | val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT; | |
1865 | val &= CR0_NUM_CHANS_MASK; | |
1866 | val += 1; | |
1867 | pi->pcfg.num_chan = val; | |
1868 | ||
1869 | val = readl(regs + CR0); | |
1870 | if (val & CR0_PERIPH_REQ_SET) { | |
1871 | val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK; | |
1872 | val += 1; | |
1873 | pi->pcfg.num_peri = val; | |
1874 | pi->pcfg.peri_ns = readl(regs + CR4); | |
1875 | } else { | |
1876 | pi->pcfg.num_peri = 0; | |
1877 | } | |
1878 | ||
1879 | val = readl(regs + CR0); | |
1880 | if (val & CR0_BOOT_MAN_NS) | |
1881 | pi->pcfg.mode |= DMAC_MODE_NS; | |
1882 | else | |
1883 | pi->pcfg.mode &= ~DMAC_MODE_NS; | |
1884 | ||
1885 | val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT; | |
1886 | val &= CR0_NUM_EVENTS_MASK; | |
1887 | val += 1; | |
1888 | pi->pcfg.num_events = val; | |
1889 | ||
1890 | pi->pcfg.irq_ns = readl(regs + CR3); | |
b7d861d9 BK |
1891 | } |
1892 | ||
1893 | static inline void _reset_thread(struct pl330_thread *thrd) | |
1894 | { | |
1895 | struct pl330_dmac *pl330 = thrd->dmac; | |
1896 | struct pl330_info *pi = pl330->pinfo; | |
1897 | ||
1898 | thrd->req[0].mc_cpu = pl330->mcode_cpu | |
1899 | + (thrd->id * pi->mcbufsz); | |
1900 | thrd->req[0].mc_bus = pl330->mcode_bus | |
1901 | + (thrd->id * pi->mcbufsz); | |
1902 | thrd->req[0].r = NULL; | |
1903 | mark_free(thrd, 0); | |
1904 | ||
1905 | thrd->req[1].mc_cpu = thrd->req[0].mc_cpu | |
1906 | + pi->mcbufsz / 2; | |
1907 | thrd->req[1].mc_bus = thrd->req[0].mc_bus | |
1908 | + pi->mcbufsz / 2; | |
1909 | thrd->req[1].r = NULL; | |
1910 | mark_free(thrd, 1); | |
1911 | } | |
1912 | ||
1913 | static int dmac_alloc_threads(struct pl330_dmac *pl330) | |
1914 | { | |
1915 | struct pl330_info *pi = pl330->pinfo; | |
1916 | int chans = pi->pcfg.num_chan; | |
1917 | struct pl330_thread *thrd; | |
1918 | int i; | |
1919 | ||
1920 | /* Allocate 1 Manager and 'chans' Channel threads */ | |
1921 | pl330->channels = kzalloc((1 + chans) * sizeof(*thrd), | |
1922 | GFP_KERNEL); | |
1923 | if (!pl330->channels) | |
1924 | return -ENOMEM; | |
1925 | ||
1926 | /* Init Channel threads */ | |
1927 | for (i = 0; i < chans; i++) { | |
1928 | thrd = &pl330->channels[i]; | |
1929 | thrd->id = i; | |
1930 | thrd->dmac = pl330; | |
1931 | _reset_thread(thrd); | |
1932 | thrd->free = true; | |
1933 | } | |
1934 | ||
1935 | /* MANAGER is indexed at the end */ | |
1936 | thrd = &pl330->channels[chans]; | |
1937 | thrd->id = chans; | |
1938 | thrd->dmac = pl330; | |
1939 | thrd->free = false; | |
1940 | pl330->manager = thrd; | |
1941 | ||
1942 | return 0; | |
1943 | } | |
1944 | ||
1945 | static int dmac_alloc_resources(struct pl330_dmac *pl330) | |
1946 | { | |
1947 | struct pl330_info *pi = pl330->pinfo; | |
1948 | int chans = pi->pcfg.num_chan; | |
1949 | int ret; | |
b3040e40 | 1950 | |
b3040e40 | 1951 | /* |
b7d861d9 BK |
1952 | * Alloc MicroCode buffer for 'chans' Channel threads. |
1953 | * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN) | |
b3040e40 | 1954 | */ |
b7d861d9 BK |
1955 | pl330->mcode_cpu = dma_alloc_coherent(pi->dev, |
1956 | chans * pi->mcbufsz, | |
1957 | &pl330->mcode_bus, GFP_KERNEL); | |
1958 | if (!pl330->mcode_cpu) { | |
1959 | dev_err(pi->dev, "%s:%d Can't allocate memory!\n", | |
1960 | __func__, __LINE__); | |
1961 | return -ENOMEM; | |
1962 | } | |
1963 | ||
1964 | ret = dmac_alloc_threads(pl330); | |
1965 | if (ret) { | |
1966 | dev_err(pi->dev, "%s:%d Can't to create channels for DMAC!\n", | |
1967 | __func__, __LINE__); | |
1968 | dma_free_coherent(pi->dev, | |
1969 | chans * pi->mcbufsz, | |
1970 | pl330->mcode_cpu, pl330->mcode_bus); | |
1971 | return ret; | |
1972 | } | |
1973 | ||
1974 | return 0; | |
1975 | } | |
1976 | ||
1977 | static int pl330_add(struct pl330_info *pi) | |
1978 | { | |
1979 | struct pl330_dmac *pl330; | |
1980 | void __iomem *regs; | |
1981 | int i, ret; | |
1982 | ||
1983 | if (!pi || !pi->dev) | |
1984 | return -EINVAL; | |
1985 | ||
1986 | /* If already added */ | |
1987 | if (pi->pl330_data) | |
1988 | return -EINVAL; | |
1989 | ||
b7d861d9 | 1990 | regs = pi->base; |
b3040e40 | 1991 | |
b7d861d9 | 1992 | /* Check if we can handle this DMAC */ |
09677176 WD |
1993 | if ((pi->pcfg.periph_id & 0xfffff) != PERIPH_ID_VAL) { |
1994 | dev_err(pi->dev, "PERIPH_ID 0x%x !\n", pi->pcfg.periph_id); | |
b7d861d9 BK |
1995 | return -EINVAL; |
1996 | } | |
b3040e40 | 1997 | |
b7d861d9 BK |
1998 | /* Read the configuration of the DMAC */ |
1999 | read_dmac_config(pi); | |
b3040e40 | 2000 | |
b7d861d9 BK |
2001 | if (pi->pcfg.num_events == 0) { |
2002 | dev_err(pi->dev, "%s:%d Can't work without events!\n", | |
2003 | __func__, __LINE__); | |
2004 | return -EINVAL; | |
2005 | } | |
b3040e40 | 2006 | |
b7d861d9 BK |
2007 | pl330 = kzalloc(sizeof(*pl330), GFP_KERNEL); |
2008 | if (!pl330) { | |
2009 | dev_err(pi->dev, "%s:%d Can't allocate memory!\n", | |
2010 | __func__, __LINE__); | |
2011 | return -ENOMEM; | |
2012 | } | |
b3040e40 | 2013 | |
b7d861d9 BK |
2014 | /* Assign the info structure and private data */ |
2015 | pl330->pinfo = pi; | |
2016 | pi->pl330_data = pl330; | |
b3040e40 | 2017 | |
b7d861d9 | 2018 | spin_lock_init(&pl330->lock); |
1b9bb715 | 2019 | |
b7d861d9 | 2020 | INIT_LIST_HEAD(&pl330->req_done); |
42bc9cf4 | 2021 | |
b7d861d9 BK |
2022 | /* Use default MC buffer size if not provided */ |
2023 | if (!pi->mcbufsz) | |
2024 | pi->mcbufsz = MCODE_BUFF_PER_REQ * 2; | |
b3040e40 | 2025 | |
b7d861d9 BK |
2026 | /* Mark all events as free */ |
2027 | for (i = 0; i < pi->pcfg.num_events; i++) | |
2028 | pl330->events[i] = -1; | |
b3040e40 | 2029 | |
b7d861d9 BK |
2030 | /* Allocate resources needed by the DMAC */ |
2031 | ret = dmac_alloc_resources(pl330); | |
2032 | if (ret) { | |
2033 | dev_err(pi->dev, "Unable to create channels for DMAC\n"); | |
2034 | kfree(pl330); | |
2035 | return ret; | |
2036 | } | |
b3040e40 | 2037 | |
b7d861d9 | 2038 | tasklet_init(&pl330->tasks, pl330_dotask, (unsigned long) pl330); |
b3040e40 | 2039 | |
b7d861d9 | 2040 | pl330->state = INIT; |
a2f5203f | 2041 | |
b7d861d9 BK |
2042 | return 0; |
2043 | } | |
b3040e40 | 2044 | |
b7d861d9 BK |
2045 | static int dmac_free_threads(struct pl330_dmac *pl330) |
2046 | { | |
2047 | struct pl330_info *pi = pl330->pinfo; | |
2048 | int chans = pi->pcfg.num_chan; | |
2049 | struct pl330_thread *thrd; | |
2050 | int i; | |
b3040e40 | 2051 | |
b7d861d9 BK |
2052 | /* Release Channel threads */ |
2053 | for (i = 0; i < chans; i++) { | |
2054 | thrd = &pl330->channels[i]; | |
65ad6060 | 2055 | pl330_release_channel(thrd); |
b7d861d9 | 2056 | } |
b3040e40 | 2057 | |
b7d861d9 BK |
2058 | /* Free memory */ |
2059 | kfree(pl330->channels); | |
b3040e40 | 2060 | |
b7d861d9 BK |
2061 | return 0; |
2062 | } | |
b3040e40 | 2063 | |
b7d861d9 BK |
2064 | static void dmac_free_resources(struct pl330_dmac *pl330) |
2065 | { | |
2066 | struct pl330_info *pi = pl330->pinfo; | |
2067 | int chans = pi->pcfg.num_chan; | |
b3040e40 | 2068 | |
b7d861d9 BK |
2069 | dmac_free_threads(pl330); |
2070 | ||
2071 | dma_free_coherent(pi->dev, chans * pi->mcbufsz, | |
2072 | pl330->mcode_cpu, pl330->mcode_bus); | |
2073 | } | |
2074 | ||
2075 | static void pl330_del(struct pl330_info *pi) | |
2076 | { | |
2077 | struct pl330_dmac *pl330; | |
2078 | ||
2079 | if (!pi || !pi->pl330_data) | |
2080 | return; | |
2081 | ||
2082 | pl330 = pi->pl330_data; | |
2083 | ||
2084 | pl330->state = UNINIT; | |
2085 | ||
2086 | tasklet_kill(&pl330->tasks); | |
2087 | ||
2088 | /* Free DMAC resources */ | |
2089 | dmac_free_resources(pl330); | |
2090 | ||
2091 | kfree(pl330); | |
2092 | pi->pl330_data = NULL; | |
2093 | } | |
b3040e40 | 2094 | |
3e2ec13a TA |
2095 | /* forward declaration */ |
2096 | static struct amba_driver pl330_driver; | |
2097 | ||
b3040e40 JB |
2098 | static inline struct dma_pl330_chan * |
2099 | to_pchan(struct dma_chan *ch) | |
2100 | { | |
2101 | if (!ch) | |
2102 | return NULL; | |
2103 | ||
2104 | return container_of(ch, struct dma_pl330_chan, chan); | |
2105 | } | |
2106 | ||
2107 | static inline struct dma_pl330_desc * | |
2108 | to_desc(struct dma_async_tx_descriptor *tx) | |
2109 | { | |
2110 | return container_of(tx, struct dma_pl330_desc, txd); | |
2111 | } | |
2112 | ||
b3040e40 JB |
2113 | static inline void fill_queue(struct dma_pl330_chan *pch) |
2114 | { | |
2115 | struct dma_pl330_desc *desc; | |
2116 | int ret; | |
2117 | ||
2118 | list_for_each_entry(desc, &pch->work_list, node) { | |
2119 | ||
2120 | /* If already submitted */ | |
2121 | if (desc->status == BUSY) | |
30fb980b | 2122 | continue; |
b3040e40 | 2123 | |
65ad6060 | 2124 | ret = pl330_submit_req(pch->thread, &desc->req); |
b3040e40 JB |
2125 | if (!ret) { |
2126 | desc->status = BUSY; | |
b3040e40 JB |
2127 | } else if (ret == -EAGAIN) { |
2128 | /* QFull or DMAC Dying */ | |
2129 | break; | |
2130 | } else { | |
2131 | /* Unacceptable request */ | |
2132 | desc->status = DONE; | |
2133 | dev_err(pch->dmac->pif.dev, "%s:%d Bad Desc(%d)\n", | |
2134 | __func__, __LINE__, desc->txd.cookie); | |
2135 | tasklet_schedule(&pch->task); | |
2136 | } | |
2137 | } | |
2138 | } | |
2139 | ||
2140 | static void pl330_tasklet(unsigned long data) | |
2141 | { | |
2142 | struct dma_pl330_chan *pch = (struct dma_pl330_chan *)data; | |
2143 | struct dma_pl330_desc *desc, *_dt; | |
2144 | unsigned long flags; | |
b3040e40 JB |
2145 | |
2146 | spin_lock_irqsave(&pch->lock, flags); | |
2147 | ||
2148 | /* Pick up ripe tomatoes */ | |
2149 | list_for_each_entry_safe(desc, _dt, &pch->work_list, node) | |
2150 | if (desc->status == DONE) { | |
30c1dc0f | 2151 | if (!pch->cyclic) |
eab21585 | 2152 | dma_cookie_complete(&desc->txd); |
39ff8613 | 2153 | list_move_tail(&desc->node, &pch->completed_list); |
b3040e40 JB |
2154 | } |
2155 | ||
2156 | /* Try to submit a req imm. next to the last completed cookie */ | |
2157 | fill_queue(pch); | |
2158 | ||
2159 | /* Make sure the PL330 Channel thread is active */ | |
65ad6060 | 2160 | pl330_chan_ctrl(pch->thread, PL330_OP_START); |
b3040e40 | 2161 | |
39ff8613 LPC |
2162 | while (!list_empty(&pch->completed_list)) { |
2163 | dma_async_tx_callback callback; | |
2164 | void *callback_param; | |
b3040e40 | 2165 | |
39ff8613 LPC |
2166 | desc = list_first_entry(&pch->completed_list, |
2167 | struct dma_pl330_desc, node); | |
2168 | ||
2169 | callback = desc->txd.callback; | |
2170 | callback_param = desc->txd.callback_param; | |
2171 | ||
2172 | if (pch->cyclic) { | |
2173 | desc->status = PREP; | |
2174 | list_move_tail(&desc->node, &pch->work_list); | |
2175 | } else { | |
2176 | desc->status = FREE; | |
2177 | list_move_tail(&desc->node, &pch->dmac->desc_pool); | |
2178 | } | |
2179 | ||
d38a8c62 DW |
2180 | dma_descriptor_unmap(&desc->txd); |
2181 | ||
39ff8613 LPC |
2182 | if (callback) { |
2183 | spin_unlock_irqrestore(&pch->lock, flags); | |
2184 | callback(callback_param); | |
2185 | spin_lock_irqsave(&pch->lock, flags); | |
2186 | } | |
2187 | } | |
2188 | spin_unlock_irqrestore(&pch->lock, flags); | |
b3040e40 JB |
2189 | } |
2190 | ||
3e2ec13a TA |
2191 | bool pl330_filter(struct dma_chan *chan, void *param) |
2192 | { | |
cd072515 | 2193 | u8 *peri_id; |
3e2ec13a TA |
2194 | |
2195 | if (chan->device->dev->driver != &pl330_driver.drv) | |
2196 | return false; | |
2197 | ||
cd072515 | 2198 | peri_id = chan->private; |
2f986ec6 | 2199 | return *peri_id == (unsigned long)param; |
3e2ec13a TA |
2200 | } |
2201 | EXPORT_SYMBOL(pl330_filter); | |
2202 | ||
a80258f9 PV |
2203 | static struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec, |
2204 | struct of_dma *ofdma) | |
2205 | { | |
2206 | int count = dma_spec->args_count; | |
2207 | struct dma_pl330_dmac *pdmac = ofdma->of_dma_data; | |
70cbb163 | 2208 | unsigned int chan_id; |
a80258f9 PV |
2209 | |
2210 | if (count != 1) | |
2211 | return NULL; | |
2212 | ||
70cbb163 LPC |
2213 | chan_id = dma_spec->args[0]; |
2214 | if (chan_id >= pdmac->num_peripherals) | |
2215 | return NULL; | |
a80258f9 | 2216 | |
70cbb163 | 2217 | return dma_get_slave_channel(&pdmac->peripherals[chan_id].chan); |
a80258f9 PV |
2218 | } |
2219 | ||
b3040e40 JB |
2220 | static int pl330_alloc_chan_resources(struct dma_chan *chan) |
2221 | { | |
2222 | struct dma_pl330_chan *pch = to_pchan(chan); | |
2223 | struct dma_pl330_dmac *pdmac = pch->dmac; | |
2224 | unsigned long flags; | |
2225 | ||
2226 | spin_lock_irqsave(&pch->lock, flags); | |
2227 | ||
d3ee98cd | 2228 | dma_cookie_init(chan); |
42bc9cf4 | 2229 | pch->cyclic = false; |
b3040e40 | 2230 | |
65ad6060 LPC |
2231 | pch->thread = pl330_request_channel(&pdmac->pif); |
2232 | if (!pch->thread) { | |
b3040e40 | 2233 | spin_unlock_irqrestore(&pch->lock, flags); |
02747885 | 2234 | return -ENOMEM; |
b3040e40 JB |
2235 | } |
2236 | ||
2237 | tasklet_init(&pch->task, pl330_tasklet, (unsigned long) pch); | |
2238 | ||
2239 | spin_unlock_irqrestore(&pch->lock, flags); | |
2240 | ||
2241 | return 1; | |
2242 | } | |
2243 | ||
2244 | static int pl330_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, unsigned long arg) | |
2245 | { | |
2246 | struct dma_pl330_chan *pch = to_pchan(chan); | |
39ff8613 | 2247 | struct dma_pl330_desc *desc; |
b3040e40 | 2248 | unsigned long flags; |
1d0c1d60 BK |
2249 | struct dma_pl330_dmac *pdmac = pch->dmac; |
2250 | struct dma_slave_config *slave_config; | |
ae43b886 | 2251 | LIST_HEAD(list); |
b3040e40 | 2252 | |
1d0c1d60 BK |
2253 | switch (cmd) { |
2254 | case DMA_TERMINATE_ALL: | |
2255 | spin_lock_irqsave(&pch->lock, flags); | |
b3040e40 | 2256 | |
1d0c1d60 | 2257 | /* FLUSH the PL330 Channel thread */ |
65ad6060 | 2258 | pl330_chan_ctrl(pch->thread, PL330_OP_FLUSH); |
b3040e40 | 2259 | |
1d0c1d60 | 2260 | /* Mark all desc done */ |
04abf5da LPC |
2261 | list_for_each_entry(desc, &pch->submitted_list, node) { |
2262 | desc->status = FREE; | |
2263 | dma_cookie_complete(&desc->txd); | |
2264 | } | |
2265 | ||
39ff8613 LPC |
2266 | list_for_each_entry(desc, &pch->work_list , node) { |
2267 | desc->status = FREE; | |
2268 | dma_cookie_complete(&desc->txd); | |
2269 | } | |
2270 | ||
2271 | list_for_each_entry(desc, &pch->completed_list , node) { | |
2272 | desc->status = FREE; | |
2273 | dma_cookie_complete(&desc->txd); | |
ae43b886 | 2274 | } |
b3040e40 | 2275 | |
04abf5da | 2276 | list_splice_tail_init(&pch->submitted_list, &pdmac->desc_pool); |
39ff8613 LPC |
2277 | list_splice_tail_init(&pch->work_list, &pdmac->desc_pool); |
2278 | list_splice_tail_init(&pch->completed_list, &pdmac->desc_pool); | |
1d0c1d60 | 2279 | spin_unlock_irqrestore(&pch->lock, flags); |
1d0c1d60 BK |
2280 | break; |
2281 | case DMA_SLAVE_CONFIG: | |
2282 | slave_config = (struct dma_slave_config *)arg; | |
2283 | ||
db8196df | 2284 | if (slave_config->direction == DMA_MEM_TO_DEV) { |
1d0c1d60 BK |
2285 | if (slave_config->dst_addr) |
2286 | pch->fifo_addr = slave_config->dst_addr; | |
2287 | if (slave_config->dst_addr_width) | |
2288 | pch->burst_sz = __ffs(slave_config->dst_addr_width); | |
2289 | if (slave_config->dst_maxburst) | |
2290 | pch->burst_len = slave_config->dst_maxburst; | |
db8196df | 2291 | } else if (slave_config->direction == DMA_DEV_TO_MEM) { |
1d0c1d60 BK |
2292 | if (slave_config->src_addr) |
2293 | pch->fifo_addr = slave_config->src_addr; | |
2294 | if (slave_config->src_addr_width) | |
2295 | pch->burst_sz = __ffs(slave_config->src_addr_width); | |
2296 | if (slave_config->src_maxburst) | |
2297 | pch->burst_len = slave_config->src_maxburst; | |
2298 | } | |
2299 | break; | |
2300 | default: | |
2301 | dev_err(pch->dmac->pif.dev, "Not supported command.\n"); | |
2302 | return -ENXIO; | |
2303 | } | |
b3040e40 JB |
2304 | |
2305 | return 0; | |
2306 | } | |
2307 | ||
2308 | static void pl330_free_chan_resources(struct dma_chan *chan) | |
2309 | { | |
2310 | struct dma_pl330_chan *pch = to_pchan(chan); | |
2311 | unsigned long flags; | |
2312 | ||
b3040e40 JB |
2313 | tasklet_kill(&pch->task); |
2314 | ||
da331ba8 BZ |
2315 | spin_lock_irqsave(&pch->lock, flags); |
2316 | ||
65ad6060 LPC |
2317 | pl330_release_channel(pch->thread); |
2318 | pch->thread = NULL; | |
b3040e40 | 2319 | |
42bc9cf4 BK |
2320 | if (pch->cyclic) |
2321 | list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool); | |
2322 | ||
b3040e40 JB |
2323 | spin_unlock_irqrestore(&pch->lock, flags); |
2324 | } | |
2325 | ||
2326 | static enum dma_status | |
2327 | pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie, | |
2328 | struct dma_tx_state *txstate) | |
2329 | { | |
96a2af41 | 2330 | return dma_cookie_status(chan, cookie, txstate); |
b3040e40 JB |
2331 | } |
2332 | ||
2333 | static void pl330_issue_pending(struct dma_chan *chan) | |
2334 | { | |
04abf5da LPC |
2335 | struct dma_pl330_chan *pch = to_pchan(chan); |
2336 | unsigned long flags; | |
2337 | ||
2338 | spin_lock_irqsave(&pch->lock, flags); | |
2339 | list_splice_tail_init(&pch->submitted_list, &pch->work_list); | |
2340 | spin_unlock_irqrestore(&pch->lock, flags); | |
2341 | ||
2342 | pl330_tasklet((unsigned long)pch); | |
b3040e40 JB |
2343 | } |
2344 | ||
2345 | /* | |
2346 | * We returned the last one of the circular list of descriptor(s) | |
2347 | * from prep_xxx, so the argument to submit corresponds to the last | |
2348 | * descriptor of the list. | |
2349 | */ | |
2350 | static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx) | |
2351 | { | |
2352 | struct dma_pl330_desc *desc, *last = to_desc(tx); | |
2353 | struct dma_pl330_chan *pch = to_pchan(tx->chan); | |
2354 | dma_cookie_t cookie; | |
2355 | unsigned long flags; | |
2356 | ||
2357 | spin_lock_irqsave(&pch->lock, flags); | |
2358 | ||
2359 | /* Assign cookies to all nodes */ | |
b3040e40 JB |
2360 | while (!list_empty(&last->node)) { |
2361 | desc = list_entry(last->node.next, struct dma_pl330_desc, node); | |
fc514460 LPC |
2362 | if (pch->cyclic) { |
2363 | desc->txd.callback = last->txd.callback; | |
2364 | desc->txd.callback_param = last->txd.callback_param; | |
2365 | } | |
b3040e40 | 2366 | |
884485e1 | 2367 | dma_cookie_assign(&desc->txd); |
b3040e40 | 2368 | |
04abf5da | 2369 | list_move_tail(&desc->node, &pch->submitted_list); |
b3040e40 JB |
2370 | } |
2371 | ||
884485e1 | 2372 | cookie = dma_cookie_assign(&last->txd); |
04abf5da | 2373 | list_add_tail(&last->node, &pch->submitted_list); |
b3040e40 JB |
2374 | spin_unlock_irqrestore(&pch->lock, flags); |
2375 | ||
2376 | return cookie; | |
2377 | } | |
2378 | ||
2379 | static inline void _init_desc(struct dma_pl330_desc *desc) | |
2380 | { | |
b3040e40 | 2381 | desc->req.x = &desc->px; |
b3040e40 | 2382 | desc->rqcfg.swap = SWAP_NO; |
f0564c7e LPC |
2383 | desc->rqcfg.scctl = CCTRL0; |
2384 | desc->rqcfg.dcctl = CCTRL0; | |
b3040e40 | 2385 | desc->req.cfg = &desc->rqcfg; |
b3040e40 JB |
2386 | desc->txd.tx_submit = pl330_tx_submit; |
2387 | ||
2388 | INIT_LIST_HEAD(&desc->node); | |
2389 | } | |
2390 | ||
2391 | /* Returns the number of descriptors added to the DMAC pool */ | |
5a67ac57 | 2392 | static int add_desc(struct dma_pl330_dmac *pdmac, gfp_t flg, int count) |
b3040e40 JB |
2393 | { |
2394 | struct dma_pl330_desc *desc; | |
2395 | unsigned long flags; | |
2396 | int i; | |
2397 | ||
2398 | if (!pdmac) | |
2399 | return 0; | |
2400 | ||
0baf8f6a | 2401 | desc = kcalloc(count, sizeof(*desc), flg); |
b3040e40 JB |
2402 | if (!desc) |
2403 | return 0; | |
2404 | ||
2405 | spin_lock_irqsave(&pdmac->pool_lock, flags); | |
2406 | ||
2407 | for (i = 0; i < count; i++) { | |
2408 | _init_desc(&desc[i]); | |
2409 | list_add_tail(&desc[i].node, &pdmac->desc_pool); | |
2410 | } | |
2411 | ||
2412 | spin_unlock_irqrestore(&pdmac->pool_lock, flags); | |
2413 | ||
2414 | return count; | |
2415 | } | |
2416 | ||
2417 | static struct dma_pl330_desc * | |
2418 | pluck_desc(struct dma_pl330_dmac *pdmac) | |
2419 | { | |
2420 | struct dma_pl330_desc *desc = NULL; | |
2421 | unsigned long flags; | |
2422 | ||
2423 | if (!pdmac) | |
2424 | return NULL; | |
2425 | ||
2426 | spin_lock_irqsave(&pdmac->pool_lock, flags); | |
2427 | ||
2428 | if (!list_empty(&pdmac->desc_pool)) { | |
2429 | desc = list_entry(pdmac->desc_pool.next, | |
2430 | struct dma_pl330_desc, node); | |
2431 | ||
2432 | list_del_init(&desc->node); | |
2433 | ||
2434 | desc->status = PREP; | |
2435 | desc->txd.callback = NULL; | |
2436 | } | |
2437 | ||
2438 | spin_unlock_irqrestore(&pdmac->pool_lock, flags); | |
2439 | ||
2440 | return desc; | |
2441 | } | |
2442 | ||
2443 | static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch) | |
2444 | { | |
2445 | struct dma_pl330_dmac *pdmac = pch->dmac; | |
cd072515 | 2446 | u8 *peri_id = pch->chan.private; |
b3040e40 JB |
2447 | struct dma_pl330_desc *desc; |
2448 | ||
2449 | /* Pluck one desc from the pool of DMAC */ | |
2450 | desc = pluck_desc(pdmac); | |
2451 | ||
2452 | /* If the DMAC pool is empty, alloc new */ | |
2453 | if (!desc) { | |
2454 | if (!add_desc(pdmac, GFP_ATOMIC, 1)) | |
2455 | return NULL; | |
2456 | ||
2457 | /* Try again */ | |
2458 | desc = pluck_desc(pdmac); | |
2459 | if (!desc) { | |
2460 | dev_err(pch->dmac->pif.dev, | |
2461 | "%s:%d ALERT!\n", __func__, __LINE__); | |
2462 | return NULL; | |
2463 | } | |
2464 | } | |
2465 | ||
2466 | /* Initialize the descriptor */ | |
2467 | desc->pchan = pch; | |
2468 | desc->txd.cookie = 0; | |
2469 | async_tx_ack(&desc->txd); | |
2470 | ||
cd072515 | 2471 | desc->req.peri = peri_id ? pch->chan.chan_id : 0; |
3ecf51a4 | 2472 | desc->rqcfg.pcfg = &pch->dmac->pif.pcfg; |
b3040e40 JB |
2473 | |
2474 | dma_async_tx_descriptor_init(&desc->txd, &pch->chan); | |
2475 | ||
2476 | return desc; | |
2477 | } | |
2478 | ||
2479 | static inline void fill_px(struct pl330_xfer *px, | |
2480 | dma_addr_t dst, dma_addr_t src, size_t len) | |
2481 | { | |
b3040e40 JB |
2482 | px->bytes = len; |
2483 | px->dst_addr = dst; | |
2484 | px->src_addr = src; | |
2485 | } | |
2486 | ||
2487 | static struct dma_pl330_desc * | |
2488 | __pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst, | |
2489 | dma_addr_t src, size_t len) | |
2490 | { | |
2491 | struct dma_pl330_desc *desc = pl330_get_desc(pch); | |
2492 | ||
2493 | if (!desc) { | |
2494 | dev_err(pch->dmac->pif.dev, "%s:%d Unable to fetch desc\n", | |
2495 | __func__, __LINE__); | |
2496 | return NULL; | |
2497 | } | |
2498 | ||
2499 | /* | |
2500 | * Ideally we should lookout for reqs bigger than | |
2501 | * those that can be programmed with 256 bytes of | |
2502 | * MC buffer, but considering a req size is seldom | |
2503 | * going to be word-unaligned and more than 200MB, | |
2504 | * we take it easy. | |
2505 | * Also, should the limit is reached we'd rather | |
2506 | * have the platform increase MC buffer size than | |
2507 | * complicating this API driver. | |
2508 | */ | |
2509 | fill_px(&desc->px, dst, src, len); | |
2510 | ||
2511 | return desc; | |
2512 | } | |
2513 | ||
2514 | /* Call after fixing burst size */ | |
2515 | static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len) | |
2516 | { | |
2517 | struct dma_pl330_chan *pch = desc->pchan; | |
2518 | struct pl330_info *pi = &pch->dmac->pif; | |
2519 | int burst_len; | |
2520 | ||
2521 | burst_len = pi->pcfg.data_bus_width / 8; | |
2522 | burst_len *= pi->pcfg.data_buf_dep; | |
2523 | burst_len >>= desc->rqcfg.brst_size; | |
2524 | ||
2525 | /* src/dst_burst_len can't be more than 16 */ | |
2526 | if (burst_len > 16) | |
2527 | burst_len = 16; | |
2528 | ||
2529 | while (burst_len > 1) { | |
2530 | if (!(len % (burst_len << desc->rqcfg.brst_size))) | |
2531 | break; | |
2532 | burst_len--; | |
2533 | } | |
2534 | ||
2535 | return burst_len; | |
2536 | } | |
2537 | ||
42bc9cf4 BK |
2538 | static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic( |
2539 | struct dma_chan *chan, dma_addr_t dma_addr, size_t len, | |
185ecb5f | 2540 | size_t period_len, enum dma_transfer_direction direction, |
ec8b5e48 | 2541 | unsigned long flags, void *context) |
42bc9cf4 | 2542 | { |
fc514460 | 2543 | struct dma_pl330_desc *desc = NULL, *first = NULL; |
42bc9cf4 | 2544 | struct dma_pl330_chan *pch = to_pchan(chan); |
fc514460 LPC |
2545 | struct dma_pl330_dmac *pdmac = pch->dmac; |
2546 | unsigned int i; | |
42bc9cf4 BK |
2547 | dma_addr_t dst; |
2548 | dma_addr_t src; | |
2549 | ||
fc514460 | 2550 | if (len % period_len != 0) |
42bc9cf4 | 2551 | return NULL; |
42bc9cf4 | 2552 | |
fc514460 | 2553 | if (!is_slave_direction(direction)) { |
42bc9cf4 BK |
2554 | dev_err(pch->dmac->pif.dev, "%s:%d Invalid dma direction\n", |
2555 | __func__, __LINE__); | |
2556 | return NULL; | |
2557 | } | |
2558 | ||
fc514460 LPC |
2559 | for (i = 0; i < len / period_len; i++) { |
2560 | desc = pl330_get_desc(pch); | |
2561 | if (!desc) { | |
2562 | dev_err(pch->dmac->pif.dev, "%s:%d Unable to fetch desc\n", | |
2563 | __func__, __LINE__); | |
42bc9cf4 | 2564 | |
fc514460 LPC |
2565 | if (!first) |
2566 | return NULL; | |
2567 | ||
2568 | spin_lock_irqsave(&pdmac->pool_lock, flags); | |
2569 | ||
2570 | while (!list_empty(&first->node)) { | |
2571 | desc = list_entry(first->node.next, | |
2572 | struct dma_pl330_desc, node); | |
2573 | list_move_tail(&desc->node, &pdmac->desc_pool); | |
2574 | } | |
2575 | ||
2576 | list_move_tail(&first->node, &pdmac->desc_pool); | |
2577 | ||
2578 | spin_unlock_irqrestore(&pdmac->pool_lock, flags); | |
42bc9cf4 | 2579 | |
fc514460 LPC |
2580 | return NULL; |
2581 | } | |
2582 | ||
2583 | switch (direction) { | |
2584 | case DMA_MEM_TO_DEV: | |
2585 | desc->rqcfg.src_inc = 1; | |
2586 | desc->rqcfg.dst_inc = 0; | |
fc514460 LPC |
2587 | src = dma_addr; |
2588 | dst = pch->fifo_addr; | |
2589 | break; | |
2590 | case DMA_DEV_TO_MEM: | |
2591 | desc->rqcfg.src_inc = 0; | |
2592 | desc->rqcfg.dst_inc = 1; | |
fc514460 LPC |
2593 | src = pch->fifo_addr; |
2594 | dst = dma_addr; | |
2595 | break; | |
2596 | default: | |
2597 | break; | |
2598 | } | |
2599 | ||
585a9d0b | 2600 | desc->req.rqtype = direction; |
fc514460 LPC |
2601 | desc->rqcfg.brst_size = pch->burst_sz; |
2602 | desc->rqcfg.brst_len = 1; | |
2603 | fill_px(&desc->px, dst, src, period_len); | |
2604 | ||
2605 | if (!first) | |
2606 | first = desc; | |
2607 | else | |
2608 | list_add_tail(&desc->node, &first->node); | |
2609 | ||
2610 | dma_addr += period_len; | |
2611 | } | |
2612 | ||
2613 | if (!desc) | |
2614 | return NULL; | |
2615 | ||
2616 | pch->cyclic = true; | |
2617 | desc->txd.flags = flags; | |
42bc9cf4 BK |
2618 | |
2619 | return &desc->txd; | |
2620 | } | |
2621 | ||
b3040e40 JB |
2622 | static struct dma_async_tx_descriptor * |
2623 | pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst, | |
2624 | dma_addr_t src, size_t len, unsigned long flags) | |
2625 | { | |
2626 | struct dma_pl330_desc *desc; | |
2627 | struct dma_pl330_chan *pch = to_pchan(chan); | |
b3040e40 JB |
2628 | struct pl330_info *pi; |
2629 | int burst; | |
2630 | ||
4e0e6109 | 2631 | if (unlikely(!pch || !len)) |
b3040e40 JB |
2632 | return NULL; |
2633 | ||
b3040e40 JB |
2634 | pi = &pch->dmac->pif; |
2635 | ||
2636 | desc = __pl330_prep_dma_memcpy(pch, dst, src, len); | |
2637 | if (!desc) | |
2638 | return NULL; | |
2639 | ||
2640 | desc->rqcfg.src_inc = 1; | |
2641 | desc->rqcfg.dst_inc = 1; | |
585a9d0b | 2642 | desc->req.rqtype = DMA_MEM_TO_MEM; |
b3040e40 JB |
2643 | |
2644 | /* Select max possible burst size */ | |
2645 | burst = pi->pcfg.data_bus_width / 8; | |
2646 | ||
2647 | while (burst > 1) { | |
2648 | if (!(len % burst)) | |
2649 | break; | |
2650 | burst /= 2; | |
2651 | } | |
2652 | ||
2653 | desc->rqcfg.brst_size = 0; | |
2654 | while (burst != (1 << desc->rqcfg.brst_size)) | |
2655 | desc->rqcfg.brst_size++; | |
2656 | ||
2657 | desc->rqcfg.brst_len = get_burst_len(desc, len); | |
2658 | ||
2659 | desc->txd.flags = flags; | |
2660 | ||
2661 | return &desc->txd; | |
2662 | } | |
2663 | ||
52a9d179 CP |
2664 | static void __pl330_giveback_desc(struct dma_pl330_dmac *pdmac, |
2665 | struct dma_pl330_desc *first) | |
2666 | { | |
2667 | unsigned long flags; | |
2668 | struct dma_pl330_desc *desc; | |
2669 | ||
2670 | if (!first) | |
2671 | return; | |
2672 | ||
2673 | spin_lock_irqsave(&pdmac->pool_lock, flags); | |
2674 | ||
2675 | while (!list_empty(&first->node)) { | |
2676 | desc = list_entry(first->node.next, | |
2677 | struct dma_pl330_desc, node); | |
2678 | list_move_tail(&desc->node, &pdmac->desc_pool); | |
2679 | } | |
2680 | ||
2681 | list_move_tail(&first->node, &pdmac->desc_pool); | |
2682 | ||
2683 | spin_unlock_irqrestore(&pdmac->pool_lock, flags); | |
2684 | } | |
2685 | ||
b3040e40 JB |
2686 | static struct dma_async_tx_descriptor * |
2687 | pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 2688 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 2689 | unsigned long flg, void *context) |
b3040e40 JB |
2690 | { |
2691 | struct dma_pl330_desc *first, *desc = NULL; | |
2692 | struct dma_pl330_chan *pch = to_pchan(chan); | |
b3040e40 | 2693 | struct scatterlist *sg; |
1b9bb715 | 2694 | int i; |
b3040e40 JB |
2695 | dma_addr_t addr; |
2696 | ||
cd072515 | 2697 | if (unlikely(!pch || !sgl || !sg_len)) |
b3040e40 JB |
2698 | return NULL; |
2699 | ||
1b9bb715 | 2700 | addr = pch->fifo_addr; |
b3040e40 JB |
2701 | |
2702 | first = NULL; | |
2703 | ||
2704 | for_each_sg(sgl, sg, sg_len, i) { | |
2705 | ||
2706 | desc = pl330_get_desc(pch); | |
2707 | if (!desc) { | |
2708 | struct dma_pl330_dmac *pdmac = pch->dmac; | |
2709 | ||
2710 | dev_err(pch->dmac->pif.dev, | |
2711 | "%s:%d Unable to fetch desc\n", | |
2712 | __func__, __LINE__); | |
52a9d179 | 2713 | __pl330_giveback_desc(pdmac, first); |
b3040e40 JB |
2714 | |
2715 | return NULL; | |
2716 | } | |
2717 | ||
2718 | if (!first) | |
2719 | first = desc; | |
2720 | else | |
2721 | list_add_tail(&desc->node, &first->node); | |
2722 | ||
db8196df | 2723 | if (direction == DMA_MEM_TO_DEV) { |
b3040e40 JB |
2724 | desc->rqcfg.src_inc = 1; |
2725 | desc->rqcfg.dst_inc = 0; | |
2726 | fill_px(&desc->px, | |
2727 | addr, sg_dma_address(sg), sg_dma_len(sg)); | |
2728 | } else { | |
2729 | desc->rqcfg.src_inc = 0; | |
2730 | desc->rqcfg.dst_inc = 1; | |
2731 | fill_px(&desc->px, | |
2732 | sg_dma_address(sg), addr, sg_dma_len(sg)); | |
2733 | } | |
2734 | ||
1b9bb715 | 2735 | desc->rqcfg.brst_size = pch->burst_sz; |
b3040e40 | 2736 | desc->rqcfg.brst_len = 1; |
585a9d0b | 2737 | desc->req.rqtype = direction; |
b3040e40 JB |
2738 | } |
2739 | ||
2740 | /* Return the last desc in the chain */ | |
2741 | desc->txd.flags = flg; | |
2742 | return &desc->txd; | |
2743 | } | |
2744 | ||
2745 | static irqreturn_t pl330_irq_handler(int irq, void *data) | |
2746 | { | |
2747 | if (pl330_update(data)) | |
2748 | return IRQ_HANDLED; | |
2749 | else | |
2750 | return IRQ_NONE; | |
2751 | } | |
2752 | ||
ca38ff13 LPC |
2753 | #define PL330_DMA_BUSWIDTHS \ |
2754 | BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \ | |
2755 | BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ | |
2756 | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ | |
2757 | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \ | |
2758 | BIT(DMA_SLAVE_BUSWIDTH_8_BYTES) | |
2759 | ||
2760 | static int pl330_dma_device_slave_caps(struct dma_chan *dchan, | |
2761 | struct dma_slave_caps *caps) | |
2762 | { | |
2763 | caps->src_addr_widths = PL330_DMA_BUSWIDTHS; | |
2764 | caps->dstn_addr_widths = PL330_DMA_BUSWIDTHS; | |
2765 | caps->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); | |
2766 | caps->cmd_pause = false; | |
2767 | caps->cmd_terminate = true; | |
bfb9bb42 | 2768 | caps->residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR; |
ca38ff13 | 2769 | |
ca38ff13 LPC |
2770 | return 0; |
2771 | } | |
2772 | ||
463a1f8b | 2773 | static int |
aa25afad | 2774 | pl330_probe(struct amba_device *adev, const struct amba_id *id) |
b3040e40 JB |
2775 | { |
2776 | struct dma_pl330_platdata *pdat; | |
2777 | struct dma_pl330_dmac *pdmac; | |
0b94c577 | 2778 | struct dma_pl330_chan *pch, *_p; |
b3040e40 JB |
2779 | struct pl330_info *pi; |
2780 | struct dma_device *pd; | |
2781 | struct resource *res; | |
2782 | int i, ret, irq; | |
4e0e6109 | 2783 | int num_chan; |
b3040e40 | 2784 | |
d4adcc01 | 2785 | pdat = dev_get_platdata(&adev->dev); |
b3040e40 | 2786 | |
64113016 RK |
2787 | ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32)); |
2788 | if (ret) | |
2789 | return ret; | |
2790 | ||
b3040e40 | 2791 | /* Allocate a new DMAC and its Channels */ |
e4d43c17 | 2792 | pdmac = devm_kzalloc(&adev->dev, sizeof(*pdmac), GFP_KERNEL); |
b3040e40 JB |
2793 | if (!pdmac) { |
2794 | dev_err(&adev->dev, "unable to allocate mem\n"); | |
2795 | return -ENOMEM; | |
2796 | } | |
2797 | ||
2798 | pi = &pdmac->pif; | |
2799 | pi->dev = &adev->dev; | |
2800 | pi->pl330_data = NULL; | |
4e0e6109 | 2801 | pi->mcbufsz = pdat ? pdat->mcbuf_sz : 0; |
b3040e40 JB |
2802 | |
2803 | res = &adev->res; | |
bcc7fa95 SK |
2804 | pi->base = devm_ioremap_resource(&adev->dev, res); |
2805 | if (IS_ERR(pi->base)) | |
2806 | return PTR_ERR(pi->base); | |
b3040e40 | 2807 | |
a2f5203f BK |
2808 | amba_set_drvdata(adev, pdmac); |
2809 | ||
02808b42 | 2810 | for (i = 0; i < AMBA_NR_IRQS; i++) { |
e98b3caf MS |
2811 | irq = adev->irq[i]; |
2812 | if (irq) { | |
2813 | ret = devm_request_irq(&adev->dev, irq, | |
2814 | pl330_irq_handler, 0, | |
2815 | dev_name(&adev->dev), pi); | |
2816 | if (ret) | |
2817 | return ret; | |
2818 | } else { | |
2819 | break; | |
2820 | } | |
2821 | } | |
b3040e40 | 2822 | |
09677176 | 2823 | pi->pcfg.periph_id = adev->periphid; |
b3040e40 JB |
2824 | ret = pl330_add(pi); |
2825 | if (ret) | |
173e838c | 2826 | return ret; |
b3040e40 JB |
2827 | |
2828 | INIT_LIST_HEAD(&pdmac->desc_pool); | |
2829 | spin_lock_init(&pdmac->pool_lock); | |
2830 | ||
2831 | /* Create a descriptor pool of default size */ | |
2832 | if (!add_desc(pdmac, GFP_KERNEL, NR_DEFAULT_DESC)) | |
2833 | dev_warn(&adev->dev, "unable to allocate desc\n"); | |
2834 | ||
2835 | pd = &pdmac->ddma; | |
2836 | INIT_LIST_HEAD(&pd->channels); | |
2837 | ||
2838 | /* Initialize channel parameters */ | |
c8473828 OJ |
2839 | if (pdat) |
2840 | num_chan = max_t(int, pdat->nr_valid_peri, pi->pcfg.num_chan); | |
2841 | else | |
2842 | num_chan = max_t(int, pi->pcfg.num_peri, pi->pcfg.num_chan); | |
2843 | ||
70cbb163 LPC |
2844 | pdmac->num_peripherals = num_chan; |
2845 | ||
4e0e6109 | 2846 | pdmac->peripherals = kzalloc(num_chan * sizeof(*pch), GFP_KERNEL); |
61c6e753 SK |
2847 | if (!pdmac->peripherals) { |
2848 | ret = -ENOMEM; | |
2849 | dev_err(&adev->dev, "unable to allocate pdmac->peripherals\n"); | |
e4d43c17 | 2850 | goto probe_err2; |
61c6e753 | 2851 | } |
b3040e40 | 2852 | |
4e0e6109 RH |
2853 | for (i = 0; i < num_chan; i++) { |
2854 | pch = &pdmac->peripherals[i]; | |
93ed5544 TA |
2855 | if (!adev->dev.of_node) |
2856 | pch->chan.private = pdat ? &pdat->peri_id[i] : NULL; | |
2857 | else | |
2858 | pch->chan.private = adev->dev.of_node; | |
b3040e40 | 2859 | |
04abf5da | 2860 | INIT_LIST_HEAD(&pch->submitted_list); |
b3040e40 | 2861 | INIT_LIST_HEAD(&pch->work_list); |
39ff8613 | 2862 | INIT_LIST_HEAD(&pch->completed_list); |
b3040e40 | 2863 | spin_lock_init(&pch->lock); |
65ad6060 | 2864 | pch->thread = NULL; |
b3040e40 | 2865 | pch->chan.device = pd; |
b3040e40 JB |
2866 | pch->dmac = pdmac; |
2867 | ||
2868 | /* Add the channel to the DMAC list */ | |
b3040e40 JB |
2869 | list_add_tail(&pch->chan.device_node, &pd->channels); |
2870 | } | |
2871 | ||
2872 | pd->dev = &adev->dev; | |
93ed5544 | 2873 | if (pdat) { |
cd072515 | 2874 | pd->cap_mask = pdat->cap_mask; |
93ed5544 | 2875 | } else { |
cd072515 | 2876 | dma_cap_set(DMA_MEMCPY, pd->cap_mask); |
93ed5544 TA |
2877 | if (pi->pcfg.num_peri) { |
2878 | dma_cap_set(DMA_SLAVE, pd->cap_mask); | |
2879 | dma_cap_set(DMA_CYCLIC, pd->cap_mask); | |
5557a419 | 2880 | dma_cap_set(DMA_PRIVATE, pd->cap_mask); |
93ed5544 TA |
2881 | } |
2882 | } | |
b3040e40 JB |
2883 | |
2884 | pd->device_alloc_chan_resources = pl330_alloc_chan_resources; | |
2885 | pd->device_free_chan_resources = pl330_free_chan_resources; | |
2886 | pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy; | |
42bc9cf4 | 2887 | pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic; |
b3040e40 JB |
2888 | pd->device_tx_status = pl330_tx_status; |
2889 | pd->device_prep_slave_sg = pl330_prep_slave_sg; | |
2890 | pd->device_control = pl330_control; | |
2891 | pd->device_issue_pending = pl330_issue_pending; | |
ca38ff13 | 2892 | pd->device_slave_caps = pl330_dma_device_slave_caps; |
b3040e40 JB |
2893 | |
2894 | ret = dma_async_device_register(pd); | |
2895 | if (ret) { | |
2896 | dev_err(&adev->dev, "unable to register DMAC\n"); | |
0b94c577 PV |
2897 | goto probe_err3; |
2898 | } | |
2899 | ||
2900 | if (adev->dev.of_node) { | |
2901 | ret = of_dma_controller_register(adev->dev.of_node, | |
2902 | of_dma_pl330_xlate, pdmac); | |
2903 | if (ret) { | |
2904 | dev_err(&adev->dev, | |
2905 | "unable to register DMA to the generic DT DMA helpers\n"); | |
2906 | } | |
b3040e40 | 2907 | } |
b714b84e LPC |
2908 | |
2909 | adev->dev.dma_parms = &pdmac->dma_parms; | |
2910 | ||
dbaf6d85 VK |
2911 | /* |
2912 | * This is the limit for transfers with a buswidth of 1, larger | |
2913 | * buswidths will have larger limits. | |
2914 | */ | |
2915 | ret = dma_set_max_seg_size(&adev->dev, 1900800); | |
2916 | if (ret) | |
2917 | dev_err(&adev->dev, "unable to set the seg size\n"); | |
2918 | ||
b3040e40 | 2919 | |
b3040e40 JB |
2920 | dev_info(&adev->dev, |
2921 | "Loaded driver for PL330 DMAC-%d\n", adev->periphid); | |
2922 | dev_info(&adev->dev, | |
2923 | "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n", | |
2924 | pi->pcfg.data_buf_dep, | |
2925 | pi->pcfg.data_bus_width / 8, pi->pcfg.num_chan, | |
2926 | pi->pcfg.num_peri, pi->pcfg.num_events); | |
2927 | ||
2928 | return 0; | |
0b94c577 | 2929 | probe_err3: |
0b94c577 PV |
2930 | /* Idle the DMAC */ |
2931 | list_for_each_entry_safe(pch, _p, &pdmac->ddma.channels, | |
2932 | chan.device_node) { | |
2933 | ||
2934 | /* Remove the channel */ | |
2935 | list_del(&pch->chan.device_node); | |
2936 | ||
2937 | /* Flush the channel */ | |
2938 | pl330_control(&pch->chan, DMA_TERMINATE_ALL, 0); | |
2939 | pl330_free_chan_resources(&pch->chan); | |
2940 | } | |
b3040e40 | 2941 | probe_err2: |
e4d43c17 | 2942 | pl330_del(pi); |
b3040e40 JB |
2943 | |
2944 | return ret; | |
2945 | } | |
2946 | ||
4bf27b8b | 2947 | static int pl330_remove(struct amba_device *adev) |
b3040e40 JB |
2948 | { |
2949 | struct dma_pl330_dmac *pdmac = amba_get_drvdata(adev); | |
2950 | struct dma_pl330_chan *pch, *_p; | |
2951 | struct pl330_info *pi; | |
b3040e40 JB |
2952 | |
2953 | if (!pdmac) | |
2954 | return 0; | |
2955 | ||
0b94c577 PV |
2956 | if (adev->dev.of_node) |
2957 | of_dma_controller_free(adev->dev.of_node); | |
421da89a | 2958 | |
0b94c577 | 2959 | dma_async_device_unregister(&pdmac->ddma); |
b3040e40 JB |
2960 | |
2961 | /* Idle the DMAC */ | |
2962 | list_for_each_entry_safe(pch, _p, &pdmac->ddma.channels, | |
2963 | chan.device_node) { | |
2964 | ||
2965 | /* Remove the channel */ | |
2966 | list_del(&pch->chan.device_node); | |
2967 | ||
2968 | /* Flush the channel */ | |
2969 | pl330_control(&pch->chan, DMA_TERMINATE_ALL, 0); | |
2970 | pl330_free_chan_resources(&pch->chan); | |
2971 | } | |
2972 | ||
2973 | pi = &pdmac->pif; | |
2974 | ||
2975 | pl330_del(pi); | |
2976 | ||
b3040e40 JB |
2977 | return 0; |
2978 | } | |
2979 | ||
2980 | static struct amba_id pl330_ids[] = { | |
2981 | { | |
2982 | .id = 0x00041330, | |
2983 | .mask = 0x000fffff, | |
2984 | }, | |
2985 | { 0, 0 }, | |
2986 | }; | |
2987 | ||
e8fa516a DM |
2988 | MODULE_DEVICE_TABLE(amba, pl330_ids); |
2989 | ||
b3040e40 JB |
2990 | static struct amba_driver pl330_driver = { |
2991 | .drv = { | |
2992 | .owner = THIS_MODULE, | |
2993 | .name = "dma-pl330", | |
2994 | }, | |
2995 | .id_table = pl330_ids, | |
2996 | .probe = pl330_probe, | |
2997 | .remove = pl330_remove, | |
2998 | }; | |
2999 | ||
9e5ed094 | 3000 | module_amba_driver(pl330_driver); |
b3040e40 JB |
3001 | |
3002 | MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>"); | |
3003 | MODULE_DESCRIPTION("API Driver for PL330 DMAC"); | |
3004 | MODULE_LICENSE("GPL"); |