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b3040e40 JB |
1 | /* linux/drivers/dma/pl330.c |
2 | * | |
3 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. | |
4 | * Jaswinder Singh <jassi.brar@samsung.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | */ | |
11 | ||
12 | #include <linux/io.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/slab.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/dmaengine.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/amba/bus.h> | |
19 | #include <linux/amba/pl330.h> | |
a2f5203f | 20 | #include <linux/pm_runtime.h> |
1b9bb715 | 21 | #include <linux/scatterlist.h> |
93ed5544 | 22 | #include <linux/of.h> |
b3040e40 | 23 | |
d2ebfb33 RKAL |
24 | #include "dmaengine.h" |
25 | ||
b3040e40 JB |
26 | #define NR_DEFAULT_DESC 16 |
27 | ||
28 | enum desc_status { | |
29 | /* In the DMAC pool */ | |
30 | FREE, | |
31 | /* | |
32 | * Allocted to some channel during prep_xxx | |
33 | * Also may be sitting on the work_list. | |
34 | */ | |
35 | PREP, | |
36 | /* | |
37 | * Sitting on the work_list and already submitted | |
38 | * to the PL330 core. Not more than two descriptors | |
39 | * of a channel can be BUSY at any time. | |
40 | */ | |
41 | BUSY, | |
42 | /* | |
43 | * Sitting on the channel work_list but xfer done | |
44 | * by PL330 core | |
45 | */ | |
46 | DONE, | |
47 | }; | |
48 | ||
49 | struct dma_pl330_chan { | |
50 | /* Schedule desc completion */ | |
51 | struct tasklet_struct task; | |
52 | ||
53 | /* DMA-Engine Channel */ | |
54 | struct dma_chan chan; | |
55 | ||
b3040e40 JB |
56 | /* List of to be xfered descriptors */ |
57 | struct list_head work_list; | |
58 | ||
59 | /* Pointer to the DMAC that manages this channel, | |
60 | * NULL if the channel is available to be acquired. | |
61 | * As the parent, this DMAC also provides descriptors | |
62 | * to the channel. | |
63 | */ | |
64 | struct dma_pl330_dmac *dmac; | |
65 | ||
66 | /* To protect channel manipulation */ | |
67 | spinlock_t lock; | |
68 | ||
69 | /* Token of a hardware channel thread of PL330 DMAC | |
70 | * NULL if the channel is available to be acquired. | |
71 | */ | |
72 | void *pl330_chid; | |
1b9bb715 BK |
73 | |
74 | /* For D-to-M and M-to-D channels */ | |
75 | int burst_sz; /* the peripheral fifo width */ | |
1d0c1d60 | 76 | int burst_len; /* the number of burst */ |
1b9bb715 | 77 | dma_addr_t fifo_addr; |
42bc9cf4 BK |
78 | |
79 | /* for cyclic capability */ | |
80 | bool cyclic; | |
b3040e40 JB |
81 | }; |
82 | ||
83 | struct dma_pl330_dmac { | |
84 | struct pl330_info pif; | |
85 | ||
86 | /* DMA-Engine Device */ | |
87 | struct dma_device ddma; | |
88 | ||
89 | /* Pool of descriptors available for the DMAC's channels */ | |
90 | struct list_head desc_pool; | |
91 | /* To protect desc_pool manipulation */ | |
92 | spinlock_t pool_lock; | |
93 | ||
94 | /* Peripheral channels connected to this DMAC */ | |
4e0e6109 | 95 | struct dma_pl330_chan *peripherals; /* keep at end */ |
a2f5203f BK |
96 | |
97 | struct clk *clk; | |
b3040e40 JB |
98 | }; |
99 | ||
100 | struct dma_pl330_desc { | |
101 | /* To attach to a queue as child */ | |
102 | struct list_head node; | |
103 | ||
104 | /* Descriptor for the DMA Engine API */ | |
105 | struct dma_async_tx_descriptor txd; | |
106 | ||
107 | /* Xfer for PL330 core */ | |
108 | struct pl330_xfer px; | |
109 | ||
110 | struct pl330_reqcfg rqcfg; | |
111 | struct pl330_req req; | |
112 | ||
113 | enum desc_status status; | |
114 | ||
115 | /* The channel which currently holds this desc */ | |
116 | struct dma_pl330_chan *pchan; | |
117 | }; | |
118 | ||
3e2ec13a TA |
119 | /* forward declaration */ |
120 | static struct amba_driver pl330_driver; | |
121 | ||
b3040e40 JB |
122 | static inline struct dma_pl330_chan * |
123 | to_pchan(struct dma_chan *ch) | |
124 | { | |
125 | if (!ch) | |
126 | return NULL; | |
127 | ||
128 | return container_of(ch, struct dma_pl330_chan, chan); | |
129 | } | |
130 | ||
131 | static inline struct dma_pl330_desc * | |
132 | to_desc(struct dma_async_tx_descriptor *tx) | |
133 | { | |
134 | return container_of(tx, struct dma_pl330_desc, txd); | |
135 | } | |
136 | ||
137 | static inline void free_desc_list(struct list_head *list) | |
138 | { | |
139 | struct dma_pl330_dmac *pdmac; | |
140 | struct dma_pl330_desc *desc; | |
141 | struct dma_pl330_chan *pch; | |
142 | unsigned long flags; | |
143 | ||
144 | if (list_empty(list)) | |
145 | return; | |
146 | ||
147 | /* Finish off the work list */ | |
148 | list_for_each_entry(desc, list, node) { | |
149 | dma_async_tx_callback callback; | |
150 | void *param; | |
151 | ||
152 | /* All desc in a list belong to same channel */ | |
153 | pch = desc->pchan; | |
154 | callback = desc->txd.callback; | |
155 | param = desc->txd.callback_param; | |
156 | ||
157 | if (callback) | |
158 | callback(param); | |
159 | ||
160 | desc->pchan = NULL; | |
161 | } | |
162 | ||
163 | pdmac = pch->dmac; | |
164 | ||
165 | spin_lock_irqsave(&pdmac->pool_lock, flags); | |
166 | list_splice_tail_init(list, &pdmac->desc_pool); | |
167 | spin_unlock_irqrestore(&pdmac->pool_lock, flags); | |
168 | } | |
169 | ||
42bc9cf4 BK |
170 | static inline void handle_cyclic_desc_list(struct list_head *list) |
171 | { | |
172 | struct dma_pl330_desc *desc; | |
173 | struct dma_pl330_chan *pch; | |
174 | unsigned long flags; | |
175 | ||
176 | if (list_empty(list)) | |
177 | return; | |
178 | ||
179 | list_for_each_entry(desc, list, node) { | |
180 | dma_async_tx_callback callback; | |
181 | ||
182 | /* Change status to reload it */ | |
183 | desc->status = PREP; | |
184 | pch = desc->pchan; | |
185 | callback = desc->txd.callback; | |
186 | if (callback) | |
187 | callback(desc->txd.callback_param); | |
188 | } | |
189 | ||
190 | spin_lock_irqsave(&pch->lock, flags); | |
191 | list_splice_tail_init(list, &pch->work_list); | |
192 | spin_unlock_irqrestore(&pch->lock, flags); | |
193 | } | |
194 | ||
b3040e40 JB |
195 | static inline void fill_queue(struct dma_pl330_chan *pch) |
196 | { | |
197 | struct dma_pl330_desc *desc; | |
198 | int ret; | |
199 | ||
200 | list_for_each_entry(desc, &pch->work_list, node) { | |
201 | ||
202 | /* If already submitted */ | |
203 | if (desc->status == BUSY) | |
204 | break; | |
205 | ||
206 | ret = pl330_submit_req(pch->pl330_chid, | |
207 | &desc->req); | |
208 | if (!ret) { | |
209 | desc->status = BUSY; | |
210 | break; | |
211 | } else if (ret == -EAGAIN) { | |
212 | /* QFull or DMAC Dying */ | |
213 | break; | |
214 | } else { | |
215 | /* Unacceptable request */ | |
216 | desc->status = DONE; | |
217 | dev_err(pch->dmac->pif.dev, "%s:%d Bad Desc(%d)\n", | |
218 | __func__, __LINE__, desc->txd.cookie); | |
219 | tasklet_schedule(&pch->task); | |
220 | } | |
221 | } | |
222 | } | |
223 | ||
224 | static void pl330_tasklet(unsigned long data) | |
225 | { | |
226 | struct dma_pl330_chan *pch = (struct dma_pl330_chan *)data; | |
227 | struct dma_pl330_desc *desc, *_dt; | |
228 | unsigned long flags; | |
229 | LIST_HEAD(list); | |
230 | ||
231 | spin_lock_irqsave(&pch->lock, flags); | |
232 | ||
233 | /* Pick up ripe tomatoes */ | |
234 | list_for_each_entry_safe(desc, _dt, &pch->work_list, node) | |
235 | if (desc->status == DONE) { | |
f7fbce07 | 236 | dma_cookie_complete(&desc->txd); |
b3040e40 JB |
237 | list_move_tail(&desc->node, &list); |
238 | } | |
239 | ||
240 | /* Try to submit a req imm. next to the last completed cookie */ | |
241 | fill_queue(pch); | |
242 | ||
243 | /* Make sure the PL330 Channel thread is active */ | |
244 | pl330_chan_ctrl(pch->pl330_chid, PL330_OP_START); | |
245 | ||
246 | spin_unlock_irqrestore(&pch->lock, flags); | |
247 | ||
42bc9cf4 BK |
248 | if (pch->cyclic) |
249 | handle_cyclic_desc_list(&list); | |
250 | else | |
251 | free_desc_list(&list); | |
b3040e40 JB |
252 | } |
253 | ||
254 | static void dma_pl330_rqcb(void *token, enum pl330_op_err err) | |
255 | { | |
256 | struct dma_pl330_desc *desc = token; | |
257 | struct dma_pl330_chan *pch = desc->pchan; | |
258 | unsigned long flags; | |
259 | ||
260 | /* If desc aborted */ | |
261 | if (!pch) | |
262 | return; | |
263 | ||
264 | spin_lock_irqsave(&pch->lock, flags); | |
265 | ||
266 | desc->status = DONE; | |
267 | ||
268 | spin_unlock_irqrestore(&pch->lock, flags); | |
269 | ||
270 | tasklet_schedule(&pch->task); | |
271 | } | |
272 | ||
3e2ec13a TA |
273 | bool pl330_filter(struct dma_chan *chan, void *param) |
274 | { | |
cd072515 | 275 | u8 *peri_id; |
3e2ec13a TA |
276 | |
277 | if (chan->device->dev->driver != &pl330_driver.drv) | |
278 | return false; | |
279 | ||
93ed5544 TA |
280 | #ifdef CONFIG_OF |
281 | if (chan->device->dev->of_node) { | |
282 | const __be32 *prop_value; | |
283 | phandle phandle; | |
284 | struct device_node *node; | |
285 | ||
286 | prop_value = ((struct property *)param)->value; | |
287 | phandle = be32_to_cpup(prop_value++); | |
288 | node = of_find_node_by_phandle(phandle); | |
289 | return ((chan->private == node) && | |
290 | (chan->chan_id == be32_to_cpup(prop_value))); | |
291 | } | |
292 | #endif | |
293 | ||
cd072515 TA |
294 | peri_id = chan->private; |
295 | return *peri_id == (unsigned)param; | |
3e2ec13a TA |
296 | } |
297 | EXPORT_SYMBOL(pl330_filter); | |
298 | ||
b3040e40 JB |
299 | static int pl330_alloc_chan_resources(struct dma_chan *chan) |
300 | { | |
301 | struct dma_pl330_chan *pch = to_pchan(chan); | |
302 | struct dma_pl330_dmac *pdmac = pch->dmac; | |
303 | unsigned long flags; | |
304 | ||
305 | spin_lock_irqsave(&pch->lock, flags); | |
306 | ||
4d4e58de | 307 | chan->completed_cookie = chan->cookie = 1; |
42bc9cf4 | 308 | pch->cyclic = false; |
b3040e40 JB |
309 | |
310 | pch->pl330_chid = pl330_request_channel(&pdmac->pif); | |
311 | if (!pch->pl330_chid) { | |
312 | spin_unlock_irqrestore(&pch->lock, flags); | |
313 | return 0; | |
314 | } | |
315 | ||
316 | tasklet_init(&pch->task, pl330_tasklet, (unsigned long) pch); | |
317 | ||
318 | spin_unlock_irqrestore(&pch->lock, flags); | |
319 | ||
320 | return 1; | |
321 | } | |
322 | ||
323 | static int pl330_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, unsigned long arg) | |
324 | { | |
325 | struct dma_pl330_chan *pch = to_pchan(chan); | |
ae43b886 | 326 | struct dma_pl330_desc *desc, *_dt; |
b3040e40 | 327 | unsigned long flags; |
1d0c1d60 BK |
328 | struct dma_pl330_dmac *pdmac = pch->dmac; |
329 | struct dma_slave_config *slave_config; | |
ae43b886 | 330 | LIST_HEAD(list); |
b3040e40 | 331 | |
1d0c1d60 BK |
332 | switch (cmd) { |
333 | case DMA_TERMINATE_ALL: | |
334 | spin_lock_irqsave(&pch->lock, flags); | |
b3040e40 | 335 | |
1d0c1d60 BK |
336 | /* FLUSH the PL330 Channel thread */ |
337 | pl330_chan_ctrl(pch->pl330_chid, PL330_OP_FLUSH); | |
b3040e40 | 338 | |
1d0c1d60 | 339 | /* Mark all desc done */ |
ae43b886 | 340 | list_for_each_entry_safe(desc, _dt, &pch->work_list , node) { |
1d0c1d60 | 341 | desc->status = DONE; |
ae43b886 BK |
342 | pch->completed = desc->txd.cookie; |
343 | list_move_tail(&desc->node, &list); | |
344 | } | |
b3040e40 | 345 | |
ae43b886 | 346 | list_splice_tail_init(&list, &pdmac->desc_pool); |
1d0c1d60 | 347 | spin_unlock_irqrestore(&pch->lock, flags); |
1d0c1d60 BK |
348 | break; |
349 | case DMA_SLAVE_CONFIG: | |
350 | slave_config = (struct dma_slave_config *)arg; | |
351 | ||
db8196df | 352 | if (slave_config->direction == DMA_MEM_TO_DEV) { |
1d0c1d60 BK |
353 | if (slave_config->dst_addr) |
354 | pch->fifo_addr = slave_config->dst_addr; | |
355 | if (slave_config->dst_addr_width) | |
356 | pch->burst_sz = __ffs(slave_config->dst_addr_width); | |
357 | if (slave_config->dst_maxburst) | |
358 | pch->burst_len = slave_config->dst_maxburst; | |
db8196df | 359 | } else if (slave_config->direction == DMA_DEV_TO_MEM) { |
1d0c1d60 BK |
360 | if (slave_config->src_addr) |
361 | pch->fifo_addr = slave_config->src_addr; | |
362 | if (slave_config->src_addr_width) | |
363 | pch->burst_sz = __ffs(slave_config->src_addr_width); | |
364 | if (slave_config->src_maxburst) | |
365 | pch->burst_len = slave_config->src_maxburst; | |
366 | } | |
367 | break; | |
368 | default: | |
369 | dev_err(pch->dmac->pif.dev, "Not supported command.\n"); | |
370 | return -ENXIO; | |
371 | } | |
b3040e40 JB |
372 | |
373 | return 0; | |
374 | } | |
375 | ||
376 | static void pl330_free_chan_resources(struct dma_chan *chan) | |
377 | { | |
378 | struct dma_pl330_chan *pch = to_pchan(chan); | |
379 | unsigned long flags; | |
380 | ||
381 | spin_lock_irqsave(&pch->lock, flags); | |
382 | ||
383 | tasklet_kill(&pch->task); | |
384 | ||
385 | pl330_release_channel(pch->pl330_chid); | |
386 | pch->pl330_chid = NULL; | |
387 | ||
42bc9cf4 BK |
388 | if (pch->cyclic) |
389 | list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool); | |
390 | ||
b3040e40 JB |
391 | spin_unlock_irqrestore(&pch->lock, flags); |
392 | } | |
393 | ||
394 | static enum dma_status | |
395 | pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie, | |
396 | struct dma_tx_state *txstate) | |
397 | { | |
96a2af41 | 398 | return dma_cookie_status(chan, cookie, txstate); |
b3040e40 JB |
399 | } |
400 | ||
401 | static void pl330_issue_pending(struct dma_chan *chan) | |
402 | { | |
403 | pl330_tasklet((unsigned long) to_pchan(chan)); | |
404 | } | |
405 | ||
406 | /* | |
407 | * We returned the last one of the circular list of descriptor(s) | |
408 | * from prep_xxx, so the argument to submit corresponds to the last | |
409 | * descriptor of the list. | |
410 | */ | |
411 | static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx) | |
412 | { | |
413 | struct dma_pl330_desc *desc, *last = to_desc(tx); | |
414 | struct dma_pl330_chan *pch = to_pchan(tx->chan); | |
415 | dma_cookie_t cookie; | |
416 | unsigned long flags; | |
417 | ||
418 | spin_lock_irqsave(&pch->lock, flags); | |
419 | ||
420 | /* Assign cookies to all nodes */ | |
b3040e40 JB |
421 | while (!list_empty(&last->node)) { |
422 | desc = list_entry(last->node.next, struct dma_pl330_desc, node); | |
423 | ||
884485e1 | 424 | dma_cookie_assign(&desc->txd); |
b3040e40 JB |
425 | |
426 | list_move_tail(&desc->node, &pch->work_list); | |
427 | } | |
428 | ||
884485e1 | 429 | cookie = dma_cookie_assign(&last->txd); |
b3040e40 | 430 | list_add_tail(&last->node, &pch->work_list); |
b3040e40 JB |
431 | spin_unlock_irqrestore(&pch->lock, flags); |
432 | ||
433 | return cookie; | |
434 | } | |
435 | ||
436 | static inline void _init_desc(struct dma_pl330_desc *desc) | |
437 | { | |
438 | desc->pchan = NULL; | |
439 | desc->req.x = &desc->px; | |
440 | desc->req.token = desc; | |
441 | desc->rqcfg.swap = SWAP_NO; | |
442 | desc->rqcfg.privileged = 0; | |
443 | desc->rqcfg.insnaccess = 0; | |
444 | desc->rqcfg.scctl = SCCTRL0; | |
445 | desc->rqcfg.dcctl = DCCTRL0; | |
446 | desc->req.cfg = &desc->rqcfg; | |
447 | desc->req.xfer_cb = dma_pl330_rqcb; | |
448 | desc->txd.tx_submit = pl330_tx_submit; | |
449 | ||
450 | INIT_LIST_HEAD(&desc->node); | |
451 | } | |
452 | ||
453 | /* Returns the number of descriptors added to the DMAC pool */ | |
454 | int add_desc(struct dma_pl330_dmac *pdmac, gfp_t flg, int count) | |
455 | { | |
456 | struct dma_pl330_desc *desc; | |
457 | unsigned long flags; | |
458 | int i; | |
459 | ||
460 | if (!pdmac) | |
461 | return 0; | |
462 | ||
463 | desc = kmalloc(count * sizeof(*desc), flg); | |
464 | if (!desc) | |
465 | return 0; | |
466 | ||
467 | spin_lock_irqsave(&pdmac->pool_lock, flags); | |
468 | ||
469 | for (i = 0; i < count; i++) { | |
470 | _init_desc(&desc[i]); | |
471 | list_add_tail(&desc[i].node, &pdmac->desc_pool); | |
472 | } | |
473 | ||
474 | spin_unlock_irqrestore(&pdmac->pool_lock, flags); | |
475 | ||
476 | return count; | |
477 | } | |
478 | ||
479 | static struct dma_pl330_desc * | |
480 | pluck_desc(struct dma_pl330_dmac *pdmac) | |
481 | { | |
482 | struct dma_pl330_desc *desc = NULL; | |
483 | unsigned long flags; | |
484 | ||
485 | if (!pdmac) | |
486 | return NULL; | |
487 | ||
488 | spin_lock_irqsave(&pdmac->pool_lock, flags); | |
489 | ||
490 | if (!list_empty(&pdmac->desc_pool)) { | |
491 | desc = list_entry(pdmac->desc_pool.next, | |
492 | struct dma_pl330_desc, node); | |
493 | ||
494 | list_del_init(&desc->node); | |
495 | ||
496 | desc->status = PREP; | |
497 | desc->txd.callback = NULL; | |
498 | } | |
499 | ||
500 | spin_unlock_irqrestore(&pdmac->pool_lock, flags); | |
501 | ||
502 | return desc; | |
503 | } | |
504 | ||
505 | static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch) | |
506 | { | |
507 | struct dma_pl330_dmac *pdmac = pch->dmac; | |
cd072515 | 508 | u8 *peri_id = pch->chan.private; |
b3040e40 JB |
509 | struct dma_pl330_desc *desc; |
510 | ||
511 | /* Pluck one desc from the pool of DMAC */ | |
512 | desc = pluck_desc(pdmac); | |
513 | ||
514 | /* If the DMAC pool is empty, alloc new */ | |
515 | if (!desc) { | |
516 | if (!add_desc(pdmac, GFP_ATOMIC, 1)) | |
517 | return NULL; | |
518 | ||
519 | /* Try again */ | |
520 | desc = pluck_desc(pdmac); | |
521 | if (!desc) { | |
522 | dev_err(pch->dmac->pif.dev, | |
523 | "%s:%d ALERT!\n", __func__, __LINE__); | |
524 | return NULL; | |
525 | } | |
526 | } | |
527 | ||
528 | /* Initialize the descriptor */ | |
529 | desc->pchan = pch; | |
530 | desc->txd.cookie = 0; | |
531 | async_tx_ack(&desc->txd); | |
532 | ||
cd072515 | 533 | desc->req.peri = peri_id ? pch->chan.chan_id : 0; |
b3040e40 JB |
534 | |
535 | dma_async_tx_descriptor_init(&desc->txd, &pch->chan); | |
536 | ||
537 | return desc; | |
538 | } | |
539 | ||
540 | static inline void fill_px(struct pl330_xfer *px, | |
541 | dma_addr_t dst, dma_addr_t src, size_t len) | |
542 | { | |
543 | px->next = NULL; | |
544 | px->bytes = len; | |
545 | px->dst_addr = dst; | |
546 | px->src_addr = src; | |
547 | } | |
548 | ||
549 | static struct dma_pl330_desc * | |
550 | __pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst, | |
551 | dma_addr_t src, size_t len) | |
552 | { | |
553 | struct dma_pl330_desc *desc = pl330_get_desc(pch); | |
554 | ||
555 | if (!desc) { | |
556 | dev_err(pch->dmac->pif.dev, "%s:%d Unable to fetch desc\n", | |
557 | __func__, __LINE__); | |
558 | return NULL; | |
559 | } | |
560 | ||
561 | /* | |
562 | * Ideally we should lookout for reqs bigger than | |
563 | * those that can be programmed with 256 bytes of | |
564 | * MC buffer, but considering a req size is seldom | |
565 | * going to be word-unaligned and more than 200MB, | |
566 | * we take it easy. | |
567 | * Also, should the limit is reached we'd rather | |
568 | * have the platform increase MC buffer size than | |
569 | * complicating this API driver. | |
570 | */ | |
571 | fill_px(&desc->px, dst, src, len); | |
572 | ||
573 | return desc; | |
574 | } | |
575 | ||
576 | /* Call after fixing burst size */ | |
577 | static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len) | |
578 | { | |
579 | struct dma_pl330_chan *pch = desc->pchan; | |
580 | struct pl330_info *pi = &pch->dmac->pif; | |
581 | int burst_len; | |
582 | ||
583 | burst_len = pi->pcfg.data_bus_width / 8; | |
584 | burst_len *= pi->pcfg.data_buf_dep; | |
585 | burst_len >>= desc->rqcfg.brst_size; | |
586 | ||
587 | /* src/dst_burst_len can't be more than 16 */ | |
588 | if (burst_len > 16) | |
589 | burst_len = 16; | |
590 | ||
591 | while (burst_len > 1) { | |
592 | if (!(len % (burst_len << desc->rqcfg.brst_size))) | |
593 | break; | |
594 | burst_len--; | |
595 | } | |
596 | ||
597 | return burst_len; | |
598 | } | |
599 | ||
42bc9cf4 BK |
600 | static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic( |
601 | struct dma_chan *chan, dma_addr_t dma_addr, size_t len, | |
db8196df | 602 | size_t period_len, enum dma_transfer_direction direction) |
42bc9cf4 BK |
603 | { |
604 | struct dma_pl330_desc *desc; | |
605 | struct dma_pl330_chan *pch = to_pchan(chan); | |
606 | dma_addr_t dst; | |
607 | dma_addr_t src; | |
608 | ||
609 | desc = pl330_get_desc(pch); | |
610 | if (!desc) { | |
611 | dev_err(pch->dmac->pif.dev, "%s:%d Unable to fetch desc\n", | |
612 | __func__, __LINE__); | |
613 | return NULL; | |
614 | } | |
615 | ||
616 | switch (direction) { | |
db8196df | 617 | case DMA_MEM_TO_DEV: |
42bc9cf4 BK |
618 | desc->rqcfg.src_inc = 1; |
619 | desc->rqcfg.dst_inc = 0; | |
cd072515 | 620 | desc->req.rqtype = MEMTODEV; |
42bc9cf4 BK |
621 | src = dma_addr; |
622 | dst = pch->fifo_addr; | |
623 | break; | |
db8196df | 624 | case DMA_DEV_TO_MEM: |
42bc9cf4 BK |
625 | desc->rqcfg.src_inc = 0; |
626 | desc->rqcfg.dst_inc = 1; | |
cd072515 | 627 | desc->req.rqtype = DEVTOMEM; |
42bc9cf4 BK |
628 | src = pch->fifo_addr; |
629 | dst = dma_addr; | |
630 | break; | |
631 | default: | |
632 | dev_err(pch->dmac->pif.dev, "%s:%d Invalid dma direction\n", | |
633 | __func__, __LINE__); | |
634 | return NULL; | |
635 | } | |
636 | ||
637 | desc->rqcfg.brst_size = pch->burst_sz; | |
638 | desc->rqcfg.brst_len = 1; | |
639 | ||
640 | pch->cyclic = true; | |
641 | ||
642 | fill_px(&desc->px, dst, src, period_len); | |
643 | ||
644 | return &desc->txd; | |
645 | } | |
646 | ||
b3040e40 JB |
647 | static struct dma_async_tx_descriptor * |
648 | pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst, | |
649 | dma_addr_t src, size_t len, unsigned long flags) | |
650 | { | |
651 | struct dma_pl330_desc *desc; | |
652 | struct dma_pl330_chan *pch = to_pchan(chan); | |
b3040e40 JB |
653 | struct pl330_info *pi; |
654 | int burst; | |
655 | ||
4e0e6109 | 656 | if (unlikely(!pch || !len)) |
b3040e40 JB |
657 | return NULL; |
658 | ||
b3040e40 JB |
659 | pi = &pch->dmac->pif; |
660 | ||
661 | desc = __pl330_prep_dma_memcpy(pch, dst, src, len); | |
662 | if (!desc) | |
663 | return NULL; | |
664 | ||
665 | desc->rqcfg.src_inc = 1; | |
666 | desc->rqcfg.dst_inc = 1; | |
cd072515 | 667 | desc->req.rqtype = MEMTOMEM; |
b3040e40 JB |
668 | |
669 | /* Select max possible burst size */ | |
670 | burst = pi->pcfg.data_bus_width / 8; | |
671 | ||
672 | while (burst > 1) { | |
673 | if (!(len % burst)) | |
674 | break; | |
675 | burst /= 2; | |
676 | } | |
677 | ||
678 | desc->rqcfg.brst_size = 0; | |
679 | while (burst != (1 << desc->rqcfg.brst_size)) | |
680 | desc->rqcfg.brst_size++; | |
681 | ||
682 | desc->rqcfg.brst_len = get_burst_len(desc, len); | |
683 | ||
684 | desc->txd.flags = flags; | |
685 | ||
686 | return &desc->txd; | |
687 | } | |
688 | ||
689 | static struct dma_async_tx_descriptor * | |
690 | pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 691 | unsigned int sg_len, enum dma_transfer_direction direction, |
b3040e40 JB |
692 | unsigned long flg) |
693 | { | |
694 | struct dma_pl330_desc *first, *desc = NULL; | |
695 | struct dma_pl330_chan *pch = to_pchan(chan); | |
b3040e40 JB |
696 | struct scatterlist *sg; |
697 | unsigned long flags; | |
1b9bb715 | 698 | int i; |
b3040e40 JB |
699 | dma_addr_t addr; |
700 | ||
cd072515 | 701 | if (unlikely(!pch || !sgl || !sg_len)) |
b3040e40 JB |
702 | return NULL; |
703 | ||
1b9bb715 | 704 | addr = pch->fifo_addr; |
b3040e40 JB |
705 | |
706 | first = NULL; | |
707 | ||
708 | for_each_sg(sgl, sg, sg_len, i) { | |
709 | ||
710 | desc = pl330_get_desc(pch); | |
711 | if (!desc) { | |
712 | struct dma_pl330_dmac *pdmac = pch->dmac; | |
713 | ||
714 | dev_err(pch->dmac->pif.dev, | |
715 | "%s:%d Unable to fetch desc\n", | |
716 | __func__, __LINE__); | |
717 | if (!first) | |
718 | return NULL; | |
719 | ||
720 | spin_lock_irqsave(&pdmac->pool_lock, flags); | |
721 | ||
722 | while (!list_empty(&first->node)) { | |
723 | desc = list_entry(first->node.next, | |
724 | struct dma_pl330_desc, node); | |
725 | list_move_tail(&desc->node, &pdmac->desc_pool); | |
726 | } | |
727 | ||
728 | list_move_tail(&first->node, &pdmac->desc_pool); | |
729 | ||
730 | spin_unlock_irqrestore(&pdmac->pool_lock, flags); | |
731 | ||
732 | return NULL; | |
733 | } | |
734 | ||
735 | if (!first) | |
736 | first = desc; | |
737 | else | |
738 | list_add_tail(&desc->node, &first->node); | |
739 | ||
db8196df | 740 | if (direction == DMA_MEM_TO_DEV) { |
b3040e40 JB |
741 | desc->rqcfg.src_inc = 1; |
742 | desc->rqcfg.dst_inc = 0; | |
cd072515 | 743 | desc->req.rqtype = MEMTODEV; |
b3040e40 JB |
744 | fill_px(&desc->px, |
745 | addr, sg_dma_address(sg), sg_dma_len(sg)); | |
746 | } else { | |
747 | desc->rqcfg.src_inc = 0; | |
748 | desc->rqcfg.dst_inc = 1; | |
cd072515 | 749 | desc->req.rqtype = DEVTOMEM; |
b3040e40 JB |
750 | fill_px(&desc->px, |
751 | sg_dma_address(sg), addr, sg_dma_len(sg)); | |
752 | } | |
753 | ||
1b9bb715 | 754 | desc->rqcfg.brst_size = pch->burst_sz; |
b3040e40 JB |
755 | desc->rqcfg.brst_len = 1; |
756 | } | |
757 | ||
758 | /* Return the last desc in the chain */ | |
759 | desc->txd.flags = flg; | |
760 | return &desc->txd; | |
761 | } | |
762 | ||
763 | static irqreturn_t pl330_irq_handler(int irq, void *data) | |
764 | { | |
765 | if (pl330_update(data)) | |
766 | return IRQ_HANDLED; | |
767 | else | |
768 | return IRQ_NONE; | |
769 | } | |
770 | ||
771 | static int __devinit | |
aa25afad | 772 | pl330_probe(struct amba_device *adev, const struct amba_id *id) |
b3040e40 JB |
773 | { |
774 | struct dma_pl330_platdata *pdat; | |
775 | struct dma_pl330_dmac *pdmac; | |
776 | struct dma_pl330_chan *pch; | |
777 | struct pl330_info *pi; | |
778 | struct dma_device *pd; | |
779 | struct resource *res; | |
780 | int i, ret, irq; | |
4e0e6109 | 781 | int num_chan; |
b3040e40 JB |
782 | |
783 | pdat = adev->dev.platform_data; | |
784 | ||
b3040e40 | 785 | /* Allocate a new DMAC and its Channels */ |
4e0e6109 | 786 | pdmac = kzalloc(sizeof(*pdmac), GFP_KERNEL); |
b3040e40 JB |
787 | if (!pdmac) { |
788 | dev_err(&adev->dev, "unable to allocate mem\n"); | |
789 | return -ENOMEM; | |
790 | } | |
791 | ||
792 | pi = &pdmac->pif; | |
793 | pi->dev = &adev->dev; | |
794 | pi->pl330_data = NULL; | |
4e0e6109 | 795 | pi->mcbufsz = pdat ? pdat->mcbuf_sz : 0; |
b3040e40 JB |
796 | |
797 | res = &adev->res; | |
798 | request_mem_region(res->start, resource_size(res), "dma-pl330"); | |
799 | ||
800 | pi->base = ioremap(res->start, resource_size(res)); | |
801 | if (!pi->base) { | |
802 | ret = -ENXIO; | |
803 | goto probe_err1; | |
804 | } | |
805 | ||
a2f5203f BK |
806 | pdmac->clk = clk_get(&adev->dev, "dma"); |
807 | if (IS_ERR(pdmac->clk)) { | |
808 | dev_err(&adev->dev, "Cannot get operation clock.\n"); | |
809 | ret = -EINVAL; | |
7bec78e0 | 810 | goto probe_err2; |
a2f5203f BK |
811 | } |
812 | ||
813 | amba_set_drvdata(adev, pdmac); | |
814 | ||
3506c0d5 | 815 | #ifndef CONFIG_PM_RUNTIME |
a2f5203f BK |
816 | /* enable dma clk */ |
817 | clk_enable(pdmac->clk); | |
818 | #endif | |
819 | ||
b3040e40 JB |
820 | irq = adev->irq[0]; |
821 | ret = request_irq(irq, pl330_irq_handler, 0, | |
822 | dev_name(&adev->dev), pi); | |
823 | if (ret) | |
7bec78e0 | 824 | goto probe_err3; |
b3040e40 JB |
825 | |
826 | ret = pl330_add(pi); | |
827 | if (ret) | |
7bec78e0 | 828 | goto probe_err4; |
b3040e40 JB |
829 | |
830 | INIT_LIST_HEAD(&pdmac->desc_pool); | |
831 | spin_lock_init(&pdmac->pool_lock); | |
832 | ||
833 | /* Create a descriptor pool of default size */ | |
834 | if (!add_desc(pdmac, GFP_KERNEL, NR_DEFAULT_DESC)) | |
835 | dev_warn(&adev->dev, "unable to allocate desc\n"); | |
836 | ||
837 | pd = &pdmac->ddma; | |
838 | INIT_LIST_HEAD(&pd->channels); | |
839 | ||
840 | /* Initialize channel parameters */ | |
93ed5544 TA |
841 | num_chan = max(pdat ? pdat->nr_valid_peri : (u8)pi->pcfg.num_peri, |
842 | (u8)pi->pcfg.num_chan); | |
4e0e6109 | 843 | pdmac->peripherals = kzalloc(num_chan * sizeof(*pch), GFP_KERNEL); |
b3040e40 | 844 | |
4e0e6109 RH |
845 | for (i = 0; i < num_chan; i++) { |
846 | pch = &pdmac->peripherals[i]; | |
93ed5544 TA |
847 | if (!adev->dev.of_node) |
848 | pch->chan.private = pdat ? &pdat->peri_id[i] : NULL; | |
849 | else | |
850 | pch->chan.private = adev->dev.of_node; | |
b3040e40 JB |
851 | |
852 | INIT_LIST_HEAD(&pch->work_list); | |
853 | spin_lock_init(&pch->lock); | |
854 | pch->pl330_chid = NULL; | |
b3040e40 | 855 | pch->chan.device = pd; |
b3040e40 JB |
856 | pch->dmac = pdmac; |
857 | ||
858 | /* Add the channel to the DMAC list */ | |
b3040e40 JB |
859 | list_add_tail(&pch->chan.device_node, &pd->channels); |
860 | } | |
861 | ||
862 | pd->dev = &adev->dev; | |
93ed5544 | 863 | if (pdat) { |
cd072515 | 864 | pd->cap_mask = pdat->cap_mask; |
93ed5544 | 865 | } else { |
cd072515 | 866 | dma_cap_set(DMA_MEMCPY, pd->cap_mask); |
93ed5544 TA |
867 | if (pi->pcfg.num_peri) { |
868 | dma_cap_set(DMA_SLAVE, pd->cap_mask); | |
869 | dma_cap_set(DMA_CYCLIC, pd->cap_mask); | |
870 | } | |
871 | } | |
b3040e40 JB |
872 | |
873 | pd->device_alloc_chan_resources = pl330_alloc_chan_resources; | |
874 | pd->device_free_chan_resources = pl330_free_chan_resources; | |
875 | pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy; | |
42bc9cf4 | 876 | pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic; |
b3040e40 JB |
877 | pd->device_tx_status = pl330_tx_status; |
878 | pd->device_prep_slave_sg = pl330_prep_slave_sg; | |
879 | pd->device_control = pl330_control; | |
880 | pd->device_issue_pending = pl330_issue_pending; | |
881 | ||
882 | ret = dma_async_device_register(pd); | |
883 | if (ret) { | |
884 | dev_err(&adev->dev, "unable to register DMAC\n"); | |
7bec78e0 | 885 | goto probe_err5; |
b3040e40 JB |
886 | } |
887 | ||
b3040e40 JB |
888 | dev_info(&adev->dev, |
889 | "Loaded driver for PL330 DMAC-%d\n", adev->periphid); | |
890 | dev_info(&adev->dev, | |
891 | "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n", | |
892 | pi->pcfg.data_buf_dep, | |
893 | pi->pcfg.data_bus_width / 8, pi->pcfg.num_chan, | |
894 | pi->pcfg.num_peri, pi->pcfg.num_events); | |
895 | ||
896 | return 0; | |
897 | ||
7bec78e0 | 898 | probe_err5: |
b3040e40 | 899 | pl330_del(pi); |
7bec78e0 | 900 | probe_err4: |
b3040e40 | 901 | free_irq(irq, pi); |
7bec78e0 JL |
902 | probe_err3: |
903 | #ifndef CONFIG_PM_RUNTIME | |
904 | clk_disable(pdmac->clk); | |
905 | #endif | |
906 | clk_put(pdmac->clk); | |
b3040e40 JB |
907 | probe_err2: |
908 | iounmap(pi->base); | |
909 | probe_err1: | |
910 | release_mem_region(res->start, resource_size(res)); | |
911 | kfree(pdmac); | |
912 | ||
913 | return ret; | |
914 | } | |
915 | ||
916 | static int __devexit pl330_remove(struct amba_device *adev) | |
917 | { | |
918 | struct dma_pl330_dmac *pdmac = amba_get_drvdata(adev); | |
919 | struct dma_pl330_chan *pch, *_p; | |
920 | struct pl330_info *pi; | |
921 | struct resource *res; | |
922 | int irq; | |
923 | ||
924 | if (!pdmac) | |
925 | return 0; | |
926 | ||
927 | amba_set_drvdata(adev, NULL); | |
928 | ||
929 | /* Idle the DMAC */ | |
930 | list_for_each_entry_safe(pch, _p, &pdmac->ddma.channels, | |
931 | chan.device_node) { | |
932 | ||
933 | /* Remove the channel */ | |
934 | list_del(&pch->chan.device_node); | |
935 | ||
936 | /* Flush the channel */ | |
937 | pl330_control(&pch->chan, DMA_TERMINATE_ALL, 0); | |
938 | pl330_free_chan_resources(&pch->chan); | |
939 | } | |
940 | ||
941 | pi = &pdmac->pif; | |
942 | ||
943 | pl330_del(pi); | |
944 | ||
945 | irq = adev->irq[0]; | |
946 | free_irq(irq, pi); | |
947 | ||
948 | iounmap(pi->base); | |
949 | ||
950 | res = &adev->res; | |
951 | release_mem_region(res->start, resource_size(res)); | |
952 | ||
3506c0d5 | 953 | #ifndef CONFIG_PM_RUNTIME |
a2f5203f BK |
954 | clk_disable(pdmac->clk); |
955 | #endif | |
956 | ||
b3040e40 JB |
957 | kfree(pdmac); |
958 | ||
959 | return 0; | |
960 | } | |
961 | ||
962 | static struct amba_id pl330_ids[] = { | |
963 | { | |
964 | .id = 0x00041330, | |
965 | .mask = 0x000fffff, | |
966 | }, | |
967 | { 0, 0 }, | |
968 | }; | |
969 | ||
e8fa516a DM |
970 | MODULE_DEVICE_TABLE(amba, pl330_ids); |
971 | ||
a2f5203f BK |
972 | #ifdef CONFIG_PM_RUNTIME |
973 | static int pl330_runtime_suspend(struct device *dev) | |
974 | { | |
975 | struct dma_pl330_dmac *pdmac = dev_get_drvdata(dev); | |
976 | ||
977 | if (!pdmac) { | |
978 | dev_err(dev, "failed to get dmac\n"); | |
979 | return -ENODEV; | |
980 | } | |
981 | ||
982 | clk_disable(pdmac->clk); | |
983 | ||
984 | return 0; | |
985 | } | |
986 | ||
987 | static int pl330_runtime_resume(struct device *dev) | |
988 | { | |
989 | struct dma_pl330_dmac *pdmac = dev_get_drvdata(dev); | |
990 | ||
991 | if (!pdmac) { | |
992 | dev_err(dev, "failed to get dmac\n"); | |
993 | return -ENODEV; | |
994 | } | |
995 | ||
996 | clk_enable(pdmac->clk); | |
997 | ||
998 | return 0; | |
999 | } | |
1000 | #else | |
1001 | #define pl330_runtime_suspend NULL | |
1002 | #define pl330_runtime_resume NULL | |
1003 | #endif /* CONFIG_PM_RUNTIME */ | |
1004 | ||
1005 | static const struct dev_pm_ops pl330_pm_ops = { | |
1006 | .runtime_suspend = pl330_runtime_suspend, | |
1007 | .runtime_resume = pl330_runtime_resume, | |
1008 | }; | |
1009 | ||
b3040e40 JB |
1010 | static struct amba_driver pl330_driver = { |
1011 | .drv = { | |
1012 | .owner = THIS_MODULE, | |
1013 | .name = "dma-pl330", | |
a2f5203f | 1014 | .pm = &pl330_pm_ops, |
b3040e40 JB |
1015 | }, |
1016 | .id_table = pl330_ids, | |
1017 | .probe = pl330_probe, | |
1018 | .remove = pl330_remove, | |
1019 | }; | |
1020 | ||
1021 | static int __init pl330_init(void) | |
1022 | { | |
1023 | return amba_driver_register(&pl330_driver); | |
1024 | } | |
1025 | module_init(pl330_init); | |
1026 | ||
1027 | static void __exit pl330_exit(void) | |
1028 | { | |
1029 | amba_driver_unregister(&pl330_driver); | |
1030 | return; | |
1031 | } | |
1032 | module_exit(pl330_exit); | |
1033 | ||
1034 | MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>"); | |
1035 | MODULE_DESCRIPTION("API Driver for PL330 DMAC"); | |
1036 | MODULE_LICENSE("GPL"); |