Commit | Line | Data |
---|---|---|
d8902adc NI |
1 | /* |
2 | * Renesas SuperH DMA Engine support | |
3 | * | |
4 | * base is drivers/dma/flsdma.c | |
5 | * | |
6 | * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> | |
7 | * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved. | |
8 | * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved. | |
9 | * | |
10 | * This is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * - DMA of SuperH does not have Hardware DMA chain mode. | |
16 | * - MAX DMA size is 16MB. | |
17 | * | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/module.h> | |
5a0e3ad6 | 22 | #include <linux/slab.h> |
d8902adc NI |
23 | #include <linux/interrupt.h> |
24 | #include <linux/dmaengine.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/dma-mapping.h> | |
d8902adc | 27 | #include <linux/platform_device.h> |
20f2a3b5 | 28 | #include <linux/pm_runtime.h> |
b2623a61 | 29 | #include <linux/sh_dma.h> |
03aa18f5 PM |
30 | #include <linux/notifier.h> |
31 | #include <linux/kdebug.h> | |
32 | #include <linux/spinlock.h> | |
33 | #include <linux/rculist.h> | |
d8902adc NI |
34 | #include "shdma.h" |
35 | ||
36 | /* DMA descriptor control */ | |
3542a113 GL |
37 | enum sh_dmae_desc_status { |
38 | DESC_IDLE, | |
39 | DESC_PREPARED, | |
40 | DESC_SUBMITTED, | |
41 | DESC_COMPLETED, /* completed, have to call callback */ | |
42 | DESC_WAITING, /* callback called, waiting for ack / re-submit */ | |
43 | }; | |
d8902adc NI |
44 | |
45 | #define NR_DESCS_PER_CHANNEL 32 | |
8b1935e6 GL |
46 | /* Default MEMCPY transfer size = 2^2 = 4 bytes */ |
47 | #define LOG2_DEFAULT_XFER_SIZE 2 | |
d8902adc | 48 | |
03aa18f5 PM |
49 | /* |
50 | * Used for write-side mutual exclusion for the global device list, | |
51 | * read-side synchronization by way of RCU. | |
52 | */ | |
53 | static DEFINE_SPINLOCK(sh_dmae_lock); | |
54 | static LIST_HEAD(sh_dmae_devices); | |
55 | ||
cfefe997 | 56 | /* A bitmask with bits enough for enum sh_dmae_slave_chan_id */ |
02ca5083 | 57 | static unsigned long sh_dmae_slave_used[BITS_TO_LONGS(SH_DMA_SLAVE_NUMBER)]; |
cfefe997 | 58 | |
3542a113 GL |
59 | static void sh_dmae_chan_ld_cleanup(struct sh_dmae_chan *sh_chan, bool all); |
60 | ||
d8902adc NI |
61 | static void sh_dmae_writel(struct sh_dmae_chan *sh_dc, u32 data, u32 reg) |
62 | { | |
027811b9 | 63 | __raw_writel(data, sh_dc->base + reg / sizeof(u32)); |
d8902adc NI |
64 | } |
65 | ||
66 | static u32 sh_dmae_readl(struct sh_dmae_chan *sh_dc, u32 reg) | |
67 | { | |
027811b9 GL |
68 | return __raw_readl(sh_dc->base + reg / sizeof(u32)); |
69 | } | |
70 | ||
71 | static u16 dmaor_read(struct sh_dmae_device *shdev) | |
72 | { | |
73 | return __raw_readw(shdev->chan_reg + DMAOR / sizeof(u32)); | |
74 | } | |
75 | ||
76 | static void dmaor_write(struct sh_dmae_device *shdev, u16 data) | |
77 | { | |
78 | __raw_writew(data, shdev->chan_reg + DMAOR / sizeof(u32)); | |
d8902adc NI |
79 | } |
80 | ||
d8902adc NI |
81 | /* |
82 | * Reset DMA controller | |
83 | * | |
84 | * SH7780 has two DMAOR register | |
85 | */ | |
027811b9 | 86 | static void sh_dmae_ctl_stop(struct sh_dmae_device *shdev) |
d8902adc | 87 | { |
027811b9 | 88 | unsigned short dmaor = dmaor_read(shdev); |
d8902adc | 89 | |
027811b9 | 90 | dmaor_write(shdev, dmaor & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME)); |
d8902adc NI |
91 | } |
92 | ||
027811b9 | 93 | static int sh_dmae_rst(struct sh_dmae_device *shdev) |
d8902adc NI |
94 | { |
95 | unsigned short dmaor; | |
96 | ||
027811b9 | 97 | sh_dmae_ctl_stop(shdev); |
8b1935e6 | 98 | dmaor = dmaor_read(shdev) | shdev->pdata->dmaor_init; |
d8902adc | 99 | |
027811b9 GL |
100 | dmaor_write(shdev, dmaor); |
101 | if (dmaor_read(shdev) & (DMAOR_AE | DMAOR_NMIF)) { | |
47a4dc26 | 102 | pr_warning("dma-sh: Can't initialize DMAOR.\n"); |
d8902adc NI |
103 | return -EINVAL; |
104 | } | |
105 | return 0; | |
106 | } | |
107 | ||
fc461857 | 108 | static bool dmae_is_busy(struct sh_dmae_chan *sh_chan) |
d8902adc NI |
109 | { |
110 | u32 chcr = sh_dmae_readl(sh_chan, CHCR); | |
fc461857 GL |
111 | |
112 | if ((chcr & (CHCR_DE | CHCR_TE)) == CHCR_DE) | |
113 | return true; /* working */ | |
114 | ||
115 | return false; /* waiting */ | |
d8902adc NI |
116 | } |
117 | ||
8b1935e6 | 118 | static unsigned int calc_xmit_shift(struct sh_dmae_chan *sh_chan, u32 chcr) |
d8902adc | 119 | { |
8b1935e6 GL |
120 | struct sh_dmae_device *shdev = container_of(sh_chan->common.device, |
121 | struct sh_dmae_device, common); | |
122 | struct sh_dmae_pdata *pdata = shdev->pdata; | |
123 | int cnt = ((chcr & pdata->ts_low_mask) >> pdata->ts_low_shift) | | |
124 | ((chcr & pdata->ts_high_mask) >> pdata->ts_high_shift); | |
125 | ||
126 | if (cnt >= pdata->ts_shift_num) | |
127 | cnt = 0; | |
623b4ac4 | 128 | |
8b1935e6 GL |
129 | return pdata->ts_shift[cnt]; |
130 | } | |
131 | ||
132 | static u32 log2size_to_chcr(struct sh_dmae_chan *sh_chan, int l2size) | |
133 | { | |
134 | struct sh_dmae_device *shdev = container_of(sh_chan->common.device, | |
135 | struct sh_dmae_device, common); | |
136 | struct sh_dmae_pdata *pdata = shdev->pdata; | |
137 | int i; | |
138 | ||
139 | for (i = 0; i < pdata->ts_shift_num; i++) | |
140 | if (pdata->ts_shift[i] == l2size) | |
141 | break; | |
142 | ||
143 | if (i == pdata->ts_shift_num) | |
144 | i = 0; | |
145 | ||
146 | return ((i << pdata->ts_low_shift) & pdata->ts_low_mask) | | |
147 | ((i << pdata->ts_high_shift) & pdata->ts_high_mask); | |
d8902adc NI |
148 | } |
149 | ||
3542a113 | 150 | static void dmae_set_reg(struct sh_dmae_chan *sh_chan, struct sh_dmae_regs *hw) |
d8902adc | 151 | { |
3542a113 GL |
152 | sh_dmae_writel(sh_chan, hw->sar, SAR); |
153 | sh_dmae_writel(sh_chan, hw->dar, DAR); | |
cfefe997 | 154 | sh_dmae_writel(sh_chan, hw->tcr >> sh_chan->xmit_shift, TCR); |
d8902adc NI |
155 | } |
156 | ||
157 | static void dmae_start(struct sh_dmae_chan *sh_chan) | |
158 | { | |
159 | u32 chcr = sh_dmae_readl(sh_chan, CHCR); | |
160 | ||
86d61b33 | 161 | chcr |= CHCR_DE | CHCR_IE; |
cfefe997 | 162 | sh_dmae_writel(sh_chan, chcr & ~CHCR_TE, CHCR); |
d8902adc NI |
163 | } |
164 | ||
165 | static void dmae_halt(struct sh_dmae_chan *sh_chan) | |
166 | { | |
167 | u32 chcr = sh_dmae_readl(sh_chan, CHCR); | |
168 | ||
169 | chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE); | |
170 | sh_dmae_writel(sh_chan, chcr, CHCR); | |
171 | } | |
172 | ||
cfefe997 GL |
173 | static void dmae_init(struct sh_dmae_chan *sh_chan) |
174 | { | |
8b1935e6 GL |
175 | /* |
176 | * Default configuration for dual address memory-memory transfer. | |
177 | * 0x400 represents auto-request. | |
178 | */ | |
179 | u32 chcr = DM_INC | SM_INC | 0x400 | log2size_to_chcr(sh_chan, | |
180 | LOG2_DEFAULT_XFER_SIZE); | |
181 | sh_chan->xmit_shift = calc_xmit_shift(sh_chan, chcr); | |
cfefe997 GL |
182 | sh_dmae_writel(sh_chan, chcr, CHCR); |
183 | } | |
184 | ||
d8902adc NI |
185 | static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val) |
186 | { | |
d8902adc | 187 | /* When DMA was working, can not set data to CHCR */ |
fc461857 GL |
188 | if (dmae_is_busy(sh_chan)) |
189 | return -EBUSY; | |
d8902adc | 190 | |
8b1935e6 | 191 | sh_chan->xmit_shift = calc_xmit_shift(sh_chan, val); |
d8902adc | 192 | sh_dmae_writel(sh_chan, val, CHCR); |
cfefe997 | 193 | |
d8902adc NI |
194 | return 0; |
195 | } | |
196 | ||
d8902adc NI |
197 | static int dmae_set_dmars(struct sh_dmae_chan *sh_chan, u16 val) |
198 | { | |
027811b9 GL |
199 | struct sh_dmae_device *shdev = container_of(sh_chan->common.device, |
200 | struct sh_dmae_device, common); | |
201 | struct sh_dmae_pdata *pdata = shdev->pdata; | |
5bac942d | 202 | const struct sh_dmae_channel *chan_pdata = &pdata->channel[sh_chan->id]; |
027811b9 GL |
203 | u16 __iomem *addr = shdev->dmars + chan_pdata->dmars / sizeof(u16); |
204 | int shift = chan_pdata->dmars_bit; | |
fc461857 GL |
205 | |
206 | if (dmae_is_busy(sh_chan)) | |
207 | return -EBUSY; | |
d8902adc | 208 | |
027811b9 GL |
209 | __raw_writew((__raw_readw(addr) & (0xff00 >> shift)) | (val << shift), |
210 | addr); | |
d8902adc NI |
211 | |
212 | return 0; | |
213 | } | |
214 | ||
215 | static dma_cookie_t sh_dmae_tx_submit(struct dma_async_tx_descriptor *tx) | |
216 | { | |
3542a113 | 217 | struct sh_desc *desc = tx_to_sh_desc(tx), *chunk, *last = desc, *c; |
d8902adc | 218 | struct sh_dmae_chan *sh_chan = to_sh_chan(tx->chan); |
3542a113 | 219 | dma_async_tx_callback callback = tx->callback; |
d8902adc NI |
220 | dma_cookie_t cookie; |
221 | ||
222 | spin_lock_bh(&sh_chan->desc_lock); | |
223 | ||
224 | cookie = sh_chan->common.cookie; | |
225 | cookie++; | |
226 | if (cookie < 0) | |
227 | cookie = 1; | |
228 | ||
3542a113 GL |
229 | sh_chan->common.cookie = cookie; |
230 | tx->cookie = cookie; | |
231 | ||
232 | /* Mark all chunks of this descriptor as submitted, move to the queue */ | |
233 | list_for_each_entry_safe(chunk, c, desc->node.prev, node) { | |
234 | /* | |
235 | * All chunks are on the global ld_free, so, we have to find | |
236 | * the end of the chain ourselves | |
237 | */ | |
238 | if (chunk != desc && (chunk->mark == DESC_IDLE || | |
239 | chunk->async_tx.cookie > 0 || | |
240 | chunk->async_tx.cookie == -EBUSY || | |
241 | &chunk->node == &sh_chan->ld_free)) | |
242 | break; | |
243 | chunk->mark = DESC_SUBMITTED; | |
244 | /* Callback goes to the last chunk */ | |
245 | chunk->async_tx.callback = NULL; | |
246 | chunk->cookie = cookie; | |
247 | list_move_tail(&chunk->node, &sh_chan->ld_queue); | |
248 | last = chunk; | |
249 | } | |
d8902adc | 250 | |
3542a113 GL |
251 | last->async_tx.callback = callback; |
252 | last->async_tx.callback_param = tx->callback_param; | |
253 | ||
254 | dev_dbg(sh_chan->dev, "submit #%d@%p on %d: %x[%d] -> %x\n", | |
255 | tx->cookie, &last->async_tx, sh_chan->id, | |
256 | desc->hw.sar, desc->hw.tcr, desc->hw.dar); | |
d8902adc NI |
257 | |
258 | spin_unlock_bh(&sh_chan->desc_lock); | |
259 | ||
260 | return cookie; | |
261 | } | |
262 | ||
3542a113 | 263 | /* Called with desc_lock held */ |
d8902adc NI |
264 | static struct sh_desc *sh_dmae_get_desc(struct sh_dmae_chan *sh_chan) |
265 | { | |
3542a113 | 266 | struct sh_desc *desc; |
d8902adc | 267 | |
3542a113 GL |
268 | list_for_each_entry(desc, &sh_chan->ld_free, node) |
269 | if (desc->mark != DESC_PREPARED) { | |
270 | BUG_ON(desc->mark != DESC_IDLE); | |
d8902adc | 271 | list_del(&desc->node); |
3542a113 | 272 | return desc; |
d8902adc | 273 | } |
d8902adc | 274 | |
3542a113 | 275 | return NULL; |
d8902adc NI |
276 | } |
277 | ||
5bac942d | 278 | static const struct sh_dmae_slave_config *sh_dmae_find_slave( |
4bab9d42 | 279 | struct sh_dmae_chan *sh_chan, struct sh_dmae_slave *param) |
cfefe997 GL |
280 | { |
281 | struct dma_device *dma_dev = sh_chan->common.device; | |
282 | struct sh_dmae_device *shdev = container_of(dma_dev, | |
283 | struct sh_dmae_device, common); | |
027811b9 | 284 | struct sh_dmae_pdata *pdata = shdev->pdata; |
cfefe997 GL |
285 | int i; |
286 | ||
02ca5083 | 287 | if (param->slave_id >= SH_DMA_SLAVE_NUMBER) |
cfefe997 GL |
288 | return NULL; |
289 | ||
027811b9 | 290 | for (i = 0; i < pdata->slave_num; i++) |
4bab9d42 | 291 | if (pdata->slave[i].slave_id == param->slave_id) |
027811b9 | 292 | return pdata->slave + i; |
cfefe997 GL |
293 | |
294 | return NULL; | |
295 | } | |
296 | ||
d8902adc NI |
297 | static int sh_dmae_alloc_chan_resources(struct dma_chan *chan) |
298 | { | |
299 | struct sh_dmae_chan *sh_chan = to_sh_chan(chan); | |
300 | struct sh_desc *desc; | |
cfefe997 | 301 | struct sh_dmae_slave *param = chan->private; |
83515bc7 | 302 | int ret; |
cfefe997 | 303 | |
20f2a3b5 GL |
304 | pm_runtime_get_sync(sh_chan->dev); |
305 | ||
cfefe997 GL |
306 | /* |
307 | * This relies on the guarantee from dmaengine that alloc_chan_resources | |
308 | * never runs concurrently with itself or free_chan_resources. | |
309 | */ | |
310 | if (param) { | |
5bac942d | 311 | const struct sh_dmae_slave_config *cfg; |
cfefe997 | 312 | |
4bab9d42 | 313 | cfg = sh_dmae_find_slave(sh_chan, param); |
83515bc7 GL |
314 | if (!cfg) { |
315 | ret = -EINVAL; | |
316 | goto efindslave; | |
317 | } | |
cfefe997 | 318 | |
83515bc7 GL |
319 | if (test_and_set_bit(param->slave_id, sh_dmae_slave_used)) { |
320 | ret = -EBUSY; | |
321 | goto etestused; | |
322 | } | |
cfefe997 GL |
323 | |
324 | param->config = cfg; | |
325 | ||
326 | dmae_set_dmars(sh_chan, cfg->mid_rid); | |
327 | dmae_set_chcr(sh_chan, cfg->chcr); | |
8b1935e6 GL |
328 | } else if ((sh_dmae_readl(sh_chan, CHCR) & 0xf00) != 0x400) { |
329 | dmae_init(sh_chan); | |
cfefe997 | 330 | } |
d8902adc NI |
331 | |
332 | spin_lock_bh(&sh_chan->desc_lock); | |
333 | while (sh_chan->descs_allocated < NR_DESCS_PER_CHANNEL) { | |
334 | spin_unlock_bh(&sh_chan->desc_lock); | |
335 | desc = kzalloc(sizeof(struct sh_desc), GFP_KERNEL); | |
336 | if (!desc) { | |
337 | spin_lock_bh(&sh_chan->desc_lock); | |
338 | break; | |
339 | } | |
340 | dma_async_tx_descriptor_init(&desc->async_tx, | |
341 | &sh_chan->common); | |
342 | desc->async_tx.tx_submit = sh_dmae_tx_submit; | |
3542a113 | 343 | desc->mark = DESC_IDLE; |
d8902adc NI |
344 | |
345 | spin_lock_bh(&sh_chan->desc_lock); | |
3542a113 | 346 | list_add(&desc->node, &sh_chan->ld_free); |
d8902adc NI |
347 | sh_chan->descs_allocated++; |
348 | } | |
349 | spin_unlock_bh(&sh_chan->desc_lock); | |
350 | ||
83515bc7 GL |
351 | if (!sh_chan->descs_allocated) { |
352 | ret = -ENOMEM; | |
353 | goto edescalloc; | |
354 | } | |
20f2a3b5 | 355 | |
d8902adc | 356 | return sh_chan->descs_allocated; |
83515bc7 GL |
357 | |
358 | edescalloc: | |
359 | if (param) | |
360 | clear_bit(param->slave_id, sh_dmae_slave_used); | |
361 | etestused: | |
362 | efindslave: | |
363 | pm_runtime_put(sh_chan->dev); | |
364 | return ret; | |
d8902adc NI |
365 | } |
366 | ||
367 | /* | |
368 | * sh_dma_free_chan_resources - Free all resources of the channel. | |
369 | */ | |
370 | static void sh_dmae_free_chan_resources(struct dma_chan *chan) | |
371 | { | |
372 | struct sh_dmae_chan *sh_chan = to_sh_chan(chan); | |
373 | struct sh_desc *desc, *_desc; | |
374 | LIST_HEAD(list); | |
20f2a3b5 | 375 | int descs = sh_chan->descs_allocated; |
d8902adc | 376 | |
cfefe997 GL |
377 | dmae_halt(sh_chan); |
378 | ||
3542a113 GL |
379 | /* Prepared and not submitted descriptors can still be on the queue */ |
380 | if (!list_empty(&sh_chan->ld_queue)) | |
381 | sh_dmae_chan_ld_cleanup(sh_chan, true); | |
382 | ||
cfefe997 GL |
383 | if (chan->private) { |
384 | /* The caller is holding dma_list_mutex */ | |
385 | struct sh_dmae_slave *param = chan->private; | |
386 | clear_bit(param->slave_id, sh_dmae_slave_used); | |
387 | } | |
388 | ||
d8902adc NI |
389 | spin_lock_bh(&sh_chan->desc_lock); |
390 | ||
391 | list_splice_init(&sh_chan->ld_free, &list); | |
392 | sh_chan->descs_allocated = 0; | |
393 | ||
394 | spin_unlock_bh(&sh_chan->desc_lock); | |
395 | ||
20f2a3b5 GL |
396 | if (descs > 0) |
397 | pm_runtime_put(sh_chan->dev); | |
398 | ||
d8902adc NI |
399 | list_for_each_entry_safe(desc, _desc, &list, node) |
400 | kfree(desc); | |
401 | } | |
402 | ||
cfefe997 | 403 | /** |
fc461857 GL |
404 | * sh_dmae_add_desc - get, set up and return one transfer descriptor |
405 | * @sh_chan: DMA channel | |
406 | * @flags: DMA transfer flags | |
407 | * @dest: destination DMA address, incremented when direction equals | |
408 | * DMA_FROM_DEVICE or DMA_BIDIRECTIONAL | |
409 | * @src: source DMA address, incremented when direction equals | |
410 | * DMA_TO_DEVICE or DMA_BIDIRECTIONAL | |
411 | * @len: DMA transfer length | |
412 | * @first: if NULL, set to the current descriptor and cookie set to -EBUSY | |
413 | * @direction: needed for slave DMA to decide which address to keep constant, | |
414 | * equals DMA_BIDIRECTIONAL for MEMCPY | |
415 | * Returns 0 or an error | |
416 | * Locks: called with desc_lock held | |
417 | */ | |
418 | static struct sh_desc *sh_dmae_add_desc(struct sh_dmae_chan *sh_chan, | |
419 | unsigned long flags, dma_addr_t *dest, dma_addr_t *src, size_t *len, | |
420 | struct sh_desc **first, enum dma_data_direction direction) | |
d8902adc | 421 | { |
fc461857 | 422 | struct sh_desc *new; |
d8902adc NI |
423 | size_t copy_size; |
424 | ||
fc461857 | 425 | if (!*len) |
d8902adc NI |
426 | return NULL; |
427 | ||
fc461857 GL |
428 | /* Allocate the link descriptor from the free list */ |
429 | new = sh_dmae_get_desc(sh_chan); | |
430 | if (!new) { | |
431 | dev_err(sh_chan->dev, "No free link descriptor available\n"); | |
d8902adc | 432 | return NULL; |
fc461857 | 433 | } |
d8902adc | 434 | |
fc461857 GL |
435 | copy_size = min(*len, (size_t)SH_DMA_TCR_MAX + 1); |
436 | ||
437 | new->hw.sar = *src; | |
438 | new->hw.dar = *dest; | |
439 | new->hw.tcr = copy_size; | |
440 | ||
441 | if (!*first) { | |
442 | /* First desc */ | |
443 | new->async_tx.cookie = -EBUSY; | |
444 | *first = new; | |
445 | } else { | |
446 | /* Other desc - invisible to the user */ | |
447 | new->async_tx.cookie = -EINVAL; | |
448 | } | |
449 | ||
cfefe997 GL |
450 | dev_dbg(sh_chan->dev, |
451 | "chaining (%u/%u)@%x -> %x with %p, cookie %d, shift %d\n", | |
fc461857 | 452 | copy_size, *len, *src, *dest, &new->async_tx, |
cfefe997 | 453 | new->async_tx.cookie, sh_chan->xmit_shift); |
fc461857 GL |
454 | |
455 | new->mark = DESC_PREPARED; | |
456 | new->async_tx.flags = flags; | |
cfefe997 | 457 | new->direction = direction; |
fc461857 GL |
458 | |
459 | *len -= copy_size; | |
460 | if (direction == DMA_BIDIRECTIONAL || direction == DMA_TO_DEVICE) | |
461 | *src += copy_size; | |
462 | if (direction == DMA_BIDIRECTIONAL || direction == DMA_FROM_DEVICE) | |
463 | *dest += copy_size; | |
464 | ||
465 | return new; | |
466 | } | |
467 | ||
468 | /* | |
469 | * sh_dmae_prep_sg - prepare transfer descriptors from an SG list | |
470 | * | |
471 | * Common routine for public (MEMCPY) and slave DMA. The MEMCPY case is also | |
472 | * converted to scatter-gather to guarantee consistent locking and a correct | |
473 | * list manipulation. For slave DMA direction carries the usual meaning, and, | |
474 | * logically, the SG list is RAM and the addr variable contains slave address, | |
475 | * e.g., the FIFO I/O register. For MEMCPY direction equals DMA_BIDIRECTIONAL | |
476 | * and the SG list contains only one element and points at the source buffer. | |
477 | */ | |
478 | static struct dma_async_tx_descriptor *sh_dmae_prep_sg(struct sh_dmae_chan *sh_chan, | |
479 | struct scatterlist *sgl, unsigned int sg_len, dma_addr_t *addr, | |
480 | enum dma_data_direction direction, unsigned long flags) | |
481 | { | |
482 | struct scatterlist *sg; | |
483 | struct sh_desc *first = NULL, *new = NULL /* compiler... */; | |
484 | LIST_HEAD(tx_list); | |
485 | int chunks = 0; | |
486 | int i; | |
487 | ||
488 | if (!sg_len) | |
489 | return NULL; | |
490 | ||
491 | for_each_sg(sgl, sg, sg_len, i) | |
492 | chunks += (sg_dma_len(sg) + SH_DMA_TCR_MAX) / | |
493 | (SH_DMA_TCR_MAX + 1); | |
d8902adc | 494 | |
3542a113 GL |
495 | /* Have to lock the whole loop to protect against concurrent release */ |
496 | spin_lock_bh(&sh_chan->desc_lock); | |
497 | ||
498 | /* | |
499 | * Chaining: | |
500 | * first descriptor is what user is dealing with in all API calls, its | |
501 | * cookie is at first set to -EBUSY, at tx-submit to a positive | |
502 | * number | |
503 | * if more than one chunk is needed further chunks have cookie = -EINVAL | |
504 | * the last chunk, if not equal to the first, has cookie = -ENOSPC | |
505 | * all chunks are linked onto the tx_list head with their .node heads | |
506 | * only during this function, then they are immediately spliced | |
507 | * back onto the free list in form of a chain | |
508 | */ | |
fc461857 GL |
509 | for_each_sg(sgl, sg, sg_len, i) { |
510 | dma_addr_t sg_addr = sg_dma_address(sg); | |
511 | size_t len = sg_dma_len(sg); | |
512 | ||
513 | if (!len) | |
514 | goto err_get_desc; | |
515 | ||
516 | do { | |
517 | dev_dbg(sh_chan->dev, "Add SG #%d@%p[%d], dma %llx\n", | |
518 | i, sg, len, (unsigned long long)sg_addr); | |
519 | ||
520 | if (direction == DMA_FROM_DEVICE) | |
521 | new = sh_dmae_add_desc(sh_chan, flags, | |
522 | &sg_addr, addr, &len, &first, | |
523 | direction); | |
524 | else | |
525 | new = sh_dmae_add_desc(sh_chan, flags, | |
526 | addr, &sg_addr, &len, &first, | |
527 | direction); | |
528 | if (!new) | |
529 | goto err_get_desc; | |
530 | ||
531 | new->chunks = chunks--; | |
532 | list_add_tail(&new->node, &tx_list); | |
533 | } while (len); | |
534 | } | |
d8902adc | 535 | |
3542a113 GL |
536 | if (new != first) |
537 | new->async_tx.cookie = -ENOSPC; | |
d8902adc | 538 | |
3542a113 GL |
539 | /* Put them back on the free list, so, they don't get lost */ |
540 | list_splice_tail(&tx_list, &sh_chan->ld_free); | |
d8902adc | 541 | |
3542a113 | 542 | spin_unlock_bh(&sh_chan->desc_lock); |
d8902adc | 543 | |
3542a113 | 544 | return &first->async_tx; |
fc461857 GL |
545 | |
546 | err_get_desc: | |
547 | list_for_each_entry(new, &tx_list, node) | |
548 | new->mark = DESC_IDLE; | |
549 | list_splice(&tx_list, &sh_chan->ld_free); | |
550 | ||
551 | spin_unlock_bh(&sh_chan->desc_lock); | |
552 | ||
553 | return NULL; | |
554 | } | |
555 | ||
556 | static struct dma_async_tx_descriptor *sh_dmae_prep_memcpy( | |
557 | struct dma_chan *chan, dma_addr_t dma_dest, dma_addr_t dma_src, | |
558 | size_t len, unsigned long flags) | |
559 | { | |
560 | struct sh_dmae_chan *sh_chan; | |
561 | struct scatterlist sg; | |
562 | ||
563 | if (!chan || !len) | |
564 | return NULL; | |
565 | ||
cfefe997 GL |
566 | chan->private = NULL; |
567 | ||
fc461857 GL |
568 | sh_chan = to_sh_chan(chan); |
569 | ||
570 | sg_init_table(&sg, 1); | |
571 | sg_set_page(&sg, pfn_to_page(PFN_DOWN(dma_src)), len, | |
572 | offset_in_page(dma_src)); | |
573 | sg_dma_address(&sg) = dma_src; | |
574 | sg_dma_len(&sg) = len; | |
575 | ||
576 | return sh_dmae_prep_sg(sh_chan, &sg, 1, &dma_dest, DMA_BIDIRECTIONAL, | |
577 | flags); | |
d8902adc NI |
578 | } |
579 | ||
cfefe997 GL |
580 | static struct dma_async_tx_descriptor *sh_dmae_prep_slave_sg( |
581 | struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, | |
582 | enum dma_data_direction direction, unsigned long flags) | |
583 | { | |
584 | struct sh_dmae_slave *param; | |
585 | struct sh_dmae_chan *sh_chan; | |
5bac942d | 586 | dma_addr_t slave_addr; |
cfefe997 GL |
587 | |
588 | if (!chan) | |
589 | return NULL; | |
590 | ||
591 | sh_chan = to_sh_chan(chan); | |
592 | param = chan->private; | |
593 | ||
594 | /* Someone calling slave DMA on a public channel? */ | |
595 | if (!param || !sg_len) { | |
596 | dev_warn(sh_chan->dev, "%s: bad parameter: %p, %d, %d\n", | |
597 | __func__, param, sg_len, param ? param->slave_id : -1); | |
598 | return NULL; | |
599 | } | |
600 | ||
9f9ff20d DC |
601 | slave_addr = param->config->addr; |
602 | ||
cfefe997 GL |
603 | /* |
604 | * if (param != NULL), this is a successfully requested slave channel, | |
605 | * therefore param->config != NULL too. | |
606 | */ | |
5bac942d | 607 | return sh_dmae_prep_sg(sh_chan, sgl, sg_len, &slave_addr, |
cfefe997 GL |
608 | direction, flags); |
609 | } | |
610 | ||
05827630 LW |
611 | static int sh_dmae_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
612 | unsigned long arg) | |
cfefe997 GL |
613 | { |
614 | struct sh_dmae_chan *sh_chan = to_sh_chan(chan); | |
615 | ||
c3635c78 LW |
616 | /* Only supports DMA_TERMINATE_ALL */ |
617 | if (cmd != DMA_TERMINATE_ALL) | |
618 | return -ENXIO; | |
619 | ||
cfefe997 | 620 | if (!chan) |
c3635c78 | 621 | return -EINVAL; |
cfefe997 | 622 | |
c014906a GL |
623 | dmae_halt(sh_chan); |
624 | ||
625 | spin_lock_bh(&sh_chan->desc_lock); | |
626 | if (!list_empty(&sh_chan->ld_queue)) { | |
627 | /* Record partial transfer */ | |
628 | struct sh_desc *desc = list_entry(sh_chan->ld_queue.next, | |
629 | struct sh_desc, node); | |
630 | desc->partial = (desc->hw.tcr - sh_dmae_readl(sh_chan, TCR)) << | |
631 | sh_chan->xmit_shift; | |
632 | ||
633 | } | |
634 | spin_unlock_bh(&sh_chan->desc_lock); | |
635 | ||
cfefe997 | 636 | sh_dmae_chan_ld_cleanup(sh_chan, true); |
c3635c78 LW |
637 | |
638 | return 0; | |
cfefe997 GL |
639 | } |
640 | ||
3542a113 | 641 | static dma_async_tx_callback __ld_cleanup(struct sh_dmae_chan *sh_chan, bool all) |
d8902adc NI |
642 | { |
643 | struct sh_desc *desc, *_desc; | |
3542a113 GL |
644 | /* Is the "exposed" head of a chain acked? */ |
645 | bool head_acked = false; | |
646 | dma_cookie_t cookie = 0; | |
647 | dma_async_tx_callback callback = NULL; | |
648 | void *param = NULL; | |
d8902adc NI |
649 | |
650 | spin_lock_bh(&sh_chan->desc_lock); | |
651 | list_for_each_entry_safe(desc, _desc, &sh_chan->ld_queue, node) { | |
3542a113 GL |
652 | struct dma_async_tx_descriptor *tx = &desc->async_tx; |
653 | ||
654 | BUG_ON(tx->cookie > 0 && tx->cookie != desc->cookie); | |
655 | BUG_ON(desc->mark != DESC_SUBMITTED && | |
656 | desc->mark != DESC_COMPLETED && | |
657 | desc->mark != DESC_WAITING); | |
658 | ||
659 | /* | |
660 | * queue is ordered, and we use this loop to (1) clean up all | |
661 | * completed descriptors, and to (2) update descriptor flags of | |
662 | * any chunks in a (partially) completed chain | |
663 | */ | |
664 | if (!all && desc->mark == DESC_SUBMITTED && | |
665 | desc->cookie != cookie) | |
d8902adc NI |
666 | break; |
667 | ||
3542a113 GL |
668 | if (tx->cookie > 0) |
669 | cookie = tx->cookie; | |
d8902adc | 670 | |
3542a113 | 671 | if (desc->mark == DESC_COMPLETED && desc->chunks == 1) { |
cfefe997 GL |
672 | if (sh_chan->completed_cookie != desc->cookie - 1) |
673 | dev_dbg(sh_chan->dev, | |
674 | "Completing cookie %d, expected %d\n", | |
675 | desc->cookie, | |
676 | sh_chan->completed_cookie + 1); | |
3542a113 GL |
677 | sh_chan->completed_cookie = desc->cookie; |
678 | } | |
d8902adc | 679 | |
3542a113 GL |
680 | /* Call callback on the last chunk */ |
681 | if (desc->mark == DESC_COMPLETED && tx->callback) { | |
682 | desc->mark = DESC_WAITING; | |
683 | callback = tx->callback; | |
684 | param = tx->callback_param; | |
685 | dev_dbg(sh_chan->dev, "descriptor #%d@%p on %d callback\n", | |
686 | tx->cookie, tx, sh_chan->id); | |
687 | BUG_ON(desc->chunks != 1); | |
688 | break; | |
689 | } | |
d8902adc | 690 | |
3542a113 GL |
691 | if (tx->cookie > 0 || tx->cookie == -EBUSY) { |
692 | if (desc->mark == DESC_COMPLETED) { | |
693 | BUG_ON(tx->cookie < 0); | |
694 | desc->mark = DESC_WAITING; | |
695 | } | |
696 | head_acked = async_tx_test_ack(tx); | |
697 | } else { | |
698 | switch (desc->mark) { | |
699 | case DESC_COMPLETED: | |
700 | desc->mark = DESC_WAITING; | |
701 | /* Fall through */ | |
702 | case DESC_WAITING: | |
703 | if (head_acked) | |
704 | async_tx_ack(&desc->async_tx); | |
705 | } | |
706 | } | |
707 | ||
708 | dev_dbg(sh_chan->dev, "descriptor %p #%d completed.\n", | |
709 | tx, tx->cookie); | |
710 | ||
711 | if (((desc->mark == DESC_COMPLETED || | |
712 | desc->mark == DESC_WAITING) && | |
713 | async_tx_test_ack(&desc->async_tx)) || all) { | |
714 | /* Remove from ld_queue list */ | |
715 | desc->mark = DESC_IDLE; | |
716 | list_move(&desc->node, &sh_chan->ld_free); | |
d8902adc NI |
717 | } |
718 | } | |
719 | spin_unlock_bh(&sh_chan->desc_lock); | |
3542a113 GL |
720 | |
721 | if (callback) | |
722 | callback(param); | |
723 | ||
724 | return callback; | |
725 | } | |
726 | ||
727 | /* | |
728 | * sh_chan_ld_cleanup - Clean up link descriptors | |
729 | * | |
730 | * This function cleans up the ld_queue of DMA channel. | |
731 | */ | |
732 | static void sh_dmae_chan_ld_cleanup(struct sh_dmae_chan *sh_chan, bool all) | |
733 | { | |
734 | while (__ld_cleanup(sh_chan, all)) | |
735 | ; | |
9255f1de GL |
736 | |
737 | if (all) | |
738 | /* Terminating - forgive uncompleted cookies */ | |
739 | sh_chan->completed_cookie = sh_chan->common.cookie; | |
d8902adc NI |
740 | } |
741 | ||
742 | static void sh_chan_xfer_ld_queue(struct sh_dmae_chan *sh_chan) | |
743 | { | |
47a4dc26 | 744 | struct sh_desc *desc; |
d8902adc | 745 | |
3542a113 | 746 | spin_lock_bh(&sh_chan->desc_lock); |
d8902adc | 747 | /* DMA work check */ |
3542a113 GL |
748 | if (dmae_is_busy(sh_chan)) { |
749 | spin_unlock_bh(&sh_chan->desc_lock); | |
d8902adc | 750 | return; |
3542a113 | 751 | } |
d8902adc | 752 | |
cfefe997 | 753 | /* Find the first not transferred desciptor */ |
47a4dc26 GL |
754 | list_for_each_entry(desc, &sh_chan->ld_queue, node) |
755 | if (desc->mark == DESC_SUBMITTED) { | |
c014906a GL |
756 | dev_dbg(sh_chan->dev, "Queue #%d to %d: %u@%x -> %x\n", |
757 | desc->async_tx.cookie, sh_chan->id, | |
758 | desc->hw.tcr, desc->hw.sar, desc->hw.dar); | |
3542a113 | 759 | /* Get the ld start address from ld_queue */ |
47a4dc26 | 760 | dmae_set_reg(sh_chan, &desc->hw); |
3542a113 GL |
761 | dmae_start(sh_chan); |
762 | break; | |
763 | } | |
764 | ||
765 | spin_unlock_bh(&sh_chan->desc_lock); | |
d8902adc NI |
766 | } |
767 | ||
768 | static void sh_dmae_memcpy_issue_pending(struct dma_chan *chan) | |
769 | { | |
770 | struct sh_dmae_chan *sh_chan = to_sh_chan(chan); | |
771 | sh_chan_xfer_ld_queue(sh_chan); | |
772 | } | |
773 | ||
07934481 | 774 | static enum dma_status sh_dmae_tx_status(struct dma_chan *chan, |
d8902adc | 775 | dma_cookie_t cookie, |
07934481 | 776 | struct dma_tx_state *txstate) |
d8902adc NI |
777 | { |
778 | struct sh_dmae_chan *sh_chan = to_sh_chan(chan); | |
779 | dma_cookie_t last_used; | |
780 | dma_cookie_t last_complete; | |
47a4dc26 | 781 | enum dma_status status; |
d8902adc | 782 | |
3542a113 | 783 | sh_dmae_chan_ld_cleanup(sh_chan, false); |
d8902adc NI |
784 | |
785 | last_used = chan->cookie; | |
786 | last_complete = sh_chan->completed_cookie; | |
3542a113 | 787 | BUG_ON(last_complete < 0); |
bca34692 | 788 | dma_set_tx_state(txstate, last_complete, last_used, 0); |
d8902adc | 789 | |
47a4dc26 GL |
790 | spin_lock_bh(&sh_chan->desc_lock); |
791 | ||
792 | status = dma_async_is_complete(cookie, last_complete, last_used); | |
793 | ||
794 | /* | |
795 | * If we don't find cookie on the queue, it has been aborted and we have | |
796 | * to report error | |
797 | */ | |
798 | if (status != DMA_SUCCESS) { | |
799 | struct sh_desc *desc; | |
800 | status = DMA_ERROR; | |
801 | list_for_each_entry(desc, &sh_chan->ld_queue, node) | |
802 | if (desc->cookie == cookie) { | |
803 | status = DMA_IN_PROGRESS; | |
804 | break; | |
805 | } | |
806 | } | |
807 | ||
808 | spin_unlock_bh(&sh_chan->desc_lock); | |
809 | ||
810 | return status; | |
d8902adc NI |
811 | } |
812 | ||
813 | static irqreturn_t sh_dmae_interrupt(int irq, void *data) | |
814 | { | |
815 | irqreturn_t ret = IRQ_NONE; | |
816 | struct sh_dmae_chan *sh_chan = (struct sh_dmae_chan *)data; | |
817 | u32 chcr = sh_dmae_readl(sh_chan, CHCR); | |
818 | ||
819 | if (chcr & CHCR_TE) { | |
820 | /* DMA stop */ | |
821 | dmae_halt(sh_chan); | |
822 | ||
823 | ret = IRQ_HANDLED; | |
824 | tasklet_schedule(&sh_chan->tasklet); | |
825 | } | |
826 | ||
827 | return ret; | |
828 | } | |
829 | ||
03aa18f5 | 830 | static unsigned int sh_dmae_reset(struct sh_dmae_device *shdev) |
d8902adc | 831 | { |
03aa18f5 | 832 | unsigned int handled = 0; |
47a4dc26 | 833 | int i; |
d8902adc | 834 | |
47a4dc26 | 835 | /* halt the dma controller */ |
027811b9 | 836 | sh_dmae_ctl_stop(shdev); |
47a4dc26 GL |
837 | |
838 | /* We cannot detect, which channel caused the error, have to reset all */ | |
8b1935e6 | 839 | for (i = 0; i < SH_DMAC_MAX_CHANNELS; i++) { |
47a4dc26 | 840 | struct sh_dmae_chan *sh_chan = shdev->chan[i]; |
03aa18f5 PM |
841 | struct sh_desc *desc; |
842 | ||
843 | if (!sh_chan) | |
844 | continue; | |
845 | ||
846 | /* Stop the channel */ | |
847 | dmae_halt(sh_chan); | |
848 | ||
849 | /* Complete all */ | |
850 | list_for_each_entry(desc, &sh_chan->ld_queue, node) { | |
851 | struct dma_async_tx_descriptor *tx = &desc->async_tx; | |
852 | desc->mark = DESC_IDLE; | |
853 | if (tx->callback) | |
854 | tx->callback(tx->callback_param); | |
d8902adc | 855 | } |
03aa18f5 PM |
856 | |
857 | list_splice_init(&sh_chan->ld_queue, &sh_chan->ld_free); | |
858 | handled++; | |
d8902adc | 859 | } |
03aa18f5 | 860 | |
027811b9 | 861 | sh_dmae_rst(shdev); |
47a4dc26 | 862 | |
03aa18f5 PM |
863 | return !!handled; |
864 | } | |
865 | ||
866 | static irqreturn_t sh_dmae_err(int irq, void *data) | |
867 | { | |
868 | return IRQ_RETVAL(sh_dmae_reset(data)); | |
d8902adc | 869 | } |
d8902adc NI |
870 | |
871 | static void dmae_do_tasklet(unsigned long data) | |
872 | { | |
873 | struct sh_dmae_chan *sh_chan = (struct sh_dmae_chan *)data; | |
3542a113 | 874 | struct sh_desc *desc; |
d8902adc | 875 | u32 sar_buf = sh_dmae_readl(sh_chan, SAR); |
cfefe997 | 876 | u32 dar_buf = sh_dmae_readl(sh_chan, DAR); |
86d61b33 | 877 | |
3542a113 GL |
878 | spin_lock(&sh_chan->desc_lock); |
879 | list_for_each_entry(desc, &sh_chan->ld_queue, node) { | |
cfefe997 GL |
880 | if (desc->mark == DESC_SUBMITTED && |
881 | ((desc->direction == DMA_FROM_DEVICE && | |
882 | (desc->hw.dar + desc->hw.tcr) == dar_buf) || | |
883 | (desc->hw.sar + desc->hw.tcr) == sar_buf)) { | |
3542a113 GL |
884 | dev_dbg(sh_chan->dev, "done #%d@%p dst %u\n", |
885 | desc->async_tx.cookie, &desc->async_tx, | |
886 | desc->hw.dar); | |
887 | desc->mark = DESC_COMPLETED; | |
d8902adc NI |
888 | break; |
889 | } | |
890 | } | |
3542a113 | 891 | spin_unlock(&sh_chan->desc_lock); |
d8902adc | 892 | |
d8902adc NI |
893 | /* Next desc */ |
894 | sh_chan_xfer_ld_queue(sh_chan); | |
3542a113 | 895 | sh_dmae_chan_ld_cleanup(sh_chan, false); |
d8902adc NI |
896 | } |
897 | ||
03aa18f5 PM |
898 | static bool sh_dmae_nmi_notify(struct sh_dmae_device *shdev) |
899 | { | |
900 | unsigned int handled; | |
901 | ||
902 | /* Fast path out if NMIF is not asserted for this controller */ | |
903 | if ((dmaor_read(shdev) & DMAOR_NMIF) == 0) | |
904 | return false; | |
905 | ||
906 | handled = sh_dmae_reset(shdev); | |
907 | if (handled) | |
908 | return true; | |
909 | ||
910 | return false; | |
911 | } | |
912 | ||
913 | static int sh_dmae_nmi_handler(struct notifier_block *self, | |
914 | unsigned long cmd, void *data) | |
915 | { | |
916 | struct sh_dmae_device *shdev; | |
917 | int ret = NOTIFY_DONE; | |
918 | bool triggered; | |
919 | ||
920 | /* | |
921 | * Only concern ourselves with NMI events. | |
922 | * | |
923 | * Normally we would check the die chain value, but as this needs | |
924 | * to be architecture independent, check for NMI context instead. | |
925 | */ | |
926 | if (!in_nmi()) | |
927 | return NOTIFY_DONE; | |
928 | ||
929 | rcu_read_lock(); | |
930 | list_for_each_entry_rcu(shdev, &sh_dmae_devices, node) { | |
931 | /* | |
932 | * Only stop if one of the controllers has NMIF asserted, | |
933 | * we do not want to interfere with regular address error | |
934 | * handling or NMI events that don't concern the DMACs. | |
935 | */ | |
936 | triggered = sh_dmae_nmi_notify(shdev); | |
937 | if (triggered == true) | |
938 | ret = NOTIFY_OK; | |
939 | } | |
940 | rcu_read_unlock(); | |
941 | ||
942 | return ret; | |
943 | } | |
944 | ||
945 | static struct notifier_block sh_dmae_nmi_notifier __read_mostly = { | |
946 | .notifier_call = sh_dmae_nmi_handler, | |
947 | ||
948 | /* Run before NMI debug handler and KGDB */ | |
949 | .priority = 1, | |
950 | }; | |
951 | ||
027811b9 GL |
952 | static int __devinit sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id, |
953 | int irq, unsigned long flags) | |
d8902adc NI |
954 | { |
955 | int err; | |
5bac942d | 956 | const struct sh_dmae_channel *chan_pdata = &shdev->pdata->channel[id]; |
027811b9 | 957 | struct platform_device *pdev = to_platform_device(shdev->common.dev); |
d8902adc NI |
958 | struct sh_dmae_chan *new_sh_chan; |
959 | ||
960 | /* alloc channel */ | |
961 | new_sh_chan = kzalloc(sizeof(struct sh_dmae_chan), GFP_KERNEL); | |
962 | if (!new_sh_chan) { | |
86d61b33 GL |
963 | dev_err(shdev->common.dev, |
964 | "No free memory for allocating dma channels!\n"); | |
d8902adc NI |
965 | return -ENOMEM; |
966 | } | |
967 | ||
8b1935e6 GL |
968 | /* copy struct dma_device */ |
969 | new_sh_chan->common.device = &shdev->common; | |
970 | ||
d8902adc NI |
971 | new_sh_chan->dev = shdev->common.dev; |
972 | new_sh_chan->id = id; | |
027811b9 GL |
973 | new_sh_chan->irq = irq; |
974 | new_sh_chan->base = shdev->chan_reg + chan_pdata->offset / sizeof(u32); | |
d8902adc NI |
975 | |
976 | /* Init DMA tasklet */ | |
977 | tasklet_init(&new_sh_chan->tasklet, dmae_do_tasklet, | |
978 | (unsigned long)new_sh_chan); | |
979 | ||
980 | /* Init the channel */ | |
981 | dmae_init(new_sh_chan); | |
982 | ||
983 | spin_lock_init(&new_sh_chan->desc_lock); | |
984 | ||
985 | /* Init descripter manage list */ | |
986 | INIT_LIST_HEAD(&new_sh_chan->ld_queue); | |
987 | INIT_LIST_HEAD(&new_sh_chan->ld_free); | |
988 | ||
d8902adc NI |
989 | /* Add the channel to DMA device channel list */ |
990 | list_add_tail(&new_sh_chan->common.device_node, | |
991 | &shdev->common.channels); | |
992 | shdev->common.chancnt++; | |
993 | ||
027811b9 GL |
994 | if (pdev->id >= 0) |
995 | snprintf(new_sh_chan->dev_id, sizeof(new_sh_chan->dev_id), | |
996 | "sh-dmae%d.%d", pdev->id, new_sh_chan->id); | |
997 | else | |
998 | snprintf(new_sh_chan->dev_id, sizeof(new_sh_chan->dev_id), | |
999 | "sh-dma%d", new_sh_chan->id); | |
d8902adc NI |
1000 | |
1001 | /* set up channel irq */ | |
027811b9 | 1002 | err = request_irq(irq, &sh_dmae_interrupt, flags, |
86d61b33 | 1003 | new_sh_chan->dev_id, new_sh_chan); |
d8902adc NI |
1004 | if (err) { |
1005 | dev_err(shdev->common.dev, "DMA channel %d request_irq error " | |
1006 | "with return %d\n", id, err); | |
1007 | goto err_no_irq; | |
1008 | } | |
1009 | ||
d8902adc NI |
1010 | shdev->chan[id] = new_sh_chan; |
1011 | return 0; | |
1012 | ||
1013 | err_no_irq: | |
1014 | /* remove from dmaengine device node */ | |
1015 | list_del(&new_sh_chan->common.device_node); | |
1016 | kfree(new_sh_chan); | |
1017 | return err; | |
1018 | } | |
1019 | ||
1020 | static void sh_dmae_chan_remove(struct sh_dmae_device *shdev) | |
1021 | { | |
1022 | int i; | |
1023 | ||
1024 | for (i = shdev->common.chancnt - 1 ; i >= 0 ; i--) { | |
1025 | if (shdev->chan[i]) { | |
027811b9 GL |
1026 | struct sh_dmae_chan *sh_chan = shdev->chan[i]; |
1027 | ||
1028 | free_irq(sh_chan->irq, sh_chan); | |
d8902adc | 1029 | |
027811b9 GL |
1030 | list_del(&sh_chan->common.device_node); |
1031 | kfree(sh_chan); | |
d8902adc NI |
1032 | shdev->chan[i] = NULL; |
1033 | } | |
1034 | } | |
1035 | shdev->common.chancnt = 0; | |
1036 | } | |
1037 | ||
1038 | static int __init sh_dmae_probe(struct platform_device *pdev) | |
1039 | { | |
027811b9 GL |
1040 | struct sh_dmae_pdata *pdata = pdev->dev.platform_data; |
1041 | unsigned long irqflags = IRQF_DISABLED, | |
8b1935e6 | 1042 | chan_flag[SH_DMAC_MAX_CHANNELS] = {}; |
03aa18f5 | 1043 | unsigned long flags; |
8b1935e6 | 1044 | int errirq, chan_irq[SH_DMAC_MAX_CHANNELS]; |
027811b9 | 1045 | int err, i, irq_cnt = 0, irqres = 0; |
d8902adc | 1046 | struct sh_dmae_device *shdev; |
027811b9 | 1047 | struct resource *chan, *dmars, *errirq_res, *chanirq_res; |
d8902adc | 1048 | |
56adf7e8 | 1049 | /* get platform data */ |
027811b9 | 1050 | if (!pdata || !pdata->channel_num) |
56adf7e8 DW |
1051 | return -ENODEV; |
1052 | ||
027811b9 GL |
1053 | chan = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1054 | /* DMARS area is optional, if absent, this controller cannot do slave DMA */ | |
1055 | dmars = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
1056 | /* | |
1057 | * IRQ resources: | |
1058 | * 1. there always must be at least one IRQ IO-resource. On SH4 it is | |
1059 | * the error IRQ, in which case it is the only IRQ in this resource: | |
1060 | * start == end. If it is the only IRQ resource, all channels also | |
1061 | * use the same IRQ. | |
1062 | * 2. DMA channel IRQ resources can be specified one per resource or in | |
1063 | * ranges (start != end) | |
1064 | * 3. iff all events (channels and, optionally, error) on this | |
1065 | * controller use the same IRQ, only one IRQ resource can be | |
1066 | * specified, otherwise there must be one IRQ per channel, even if | |
1067 | * some of them are equal | |
1068 | * 4. if all IRQs on this controller are equal or if some specific IRQs | |
1069 | * specify IORESOURCE_IRQ_SHAREABLE in their resources, they will be | |
1070 | * requested with the IRQF_SHARED flag | |
1071 | */ | |
1072 | errirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
1073 | if (!chan || !errirq_res) | |
1074 | return -ENODEV; | |
1075 | ||
1076 | if (!request_mem_region(chan->start, resource_size(chan), pdev->name)) { | |
1077 | dev_err(&pdev->dev, "DMAC register region already claimed\n"); | |
1078 | return -EBUSY; | |
1079 | } | |
1080 | ||
1081 | if (dmars && !request_mem_region(dmars->start, resource_size(dmars), pdev->name)) { | |
1082 | dev_err(&pdev->dev, "DMAC DMARS region already claimed\n"); | |
1083 | err = -EBUSY; | |
1084 | goto ermrdmars; | |
1085 | } | |
1086 | ||
1087 | err = -ENOMEM; | |
d8902adc NI |
1088 | shdev = kzalloc(sizeof(struct sh_dmae_device), GFP_KERNEL); |
1089 | if (!shdev) { | |
027811b9 GL |
1090 | dev_err(&pdev->dev, "Not enough memory\n"); |
1091 | goto ealloc; | |
1092 | } | |
1093 | ||
1094 | shdev->chan_reg = ioremap(chan->start, resource_size(chan)); | |
1095 | if (!shdev->chan_reg) | |
1096 | goto emapchan; | |
1097 | if (dmars) { | |
1098 | shdev->dmars = ioremap(dmars->start, resource_size(dmars)); | |
1099 | if (!shdev->dmars) | |
1100 | goto emapdmars; | |
d8902adc NI |
1101 | } |
1102 | ||
d8902adc | 1103 | /* platform data */ |
027811b9 | 1104 | shdev->pdata = pdata; |
d8902adc | 1105 | |
20f2a3b5 GL |
1106 | pm_runtime_enable(&pdev->dev); |
1107 | pm_runtime_get_sync(&pdev->dev); | |
1108 | ||
03aa18f5 PM |
1109 | spin_lock_irqsave(&sh_dmae_lock, flags); |
1110 | list_add_tail_rcu(&shdev->node, &sh_dmae_devices); | |
1111 | spin_unlock_irqrestore(&sh_dmae_lock, flags); | |
1112 | ||
d8902adc | 1113 | /* reset dma controller */ |
027811b9 | 1114 | err = sh_dmae_rst(shdev); |
d8902adc NI |
1115 | if (err) |
1116 | goto rst_err; | |
1117 | ||
d8902adc NI |
1118 | INIT_LIST_HEAD(&shdev->common.channels); |
1119 | ||
1120 | dma_cap_set(DMA_MEMCPY, shdev->common.cap_mask); | |
027811b9 GL |
1121 | if (dmars) |
1122 | dma_cap_set(DMA_SLAVE, shdev->common.cap_mask); | |
cfefe997 | 1123 | |
d8902adc NI |
1124 | shdev->common.device_alloc_chan_resources |
1125 | = sh_dmae_alloc_chan_resources; | |
1126 | shdev->common.device_free_chan_resources = sh_dmae_free_chan_resources; | |
1127 | shdev->common.device_prep_dma_memcpy = sh_dmae_prep_memcpy; | |
07934481 | 1128 | shdev->common.device_tx_status = sh_dmae_tx_status; |
d8902adc | 1129 | shdev->common.device_issue_pending = sh_dmae_memcpy_issue_pending; |
cfefe997 GL |
1130 | |
1131 | /* Compulsory for DMA_SLAVE fields */ | |
1132 | shdev->common.device_prep_slave_sg = sh_dmae_prep_slave_sg; | |
c3635c78 | 1133 | shdev->common.device_control = sh_dmae_control; |
cfefe997 | 1134 | |
d8902adc | 1135 | shdev->common.dev = &pdev->dev; |
ddb4f0f0 | 1136 | /* Default transfer size of 32 bytes requires 32-byte alignment */ |
8b1935e6 | 1137 | shdev->common.copy_align = LOG2_DEFAULT_XFER_SIZE; |
d8902adc | 1138 | |
927a7c9c | 1139 | #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE) |
027811b9 GL |
1140 | chanirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 1); |
1141 | ||
1142 | if (!chanirq_res) | |
1143 | chanirq_res = errirq_res; | |
1144 | else | |
1145 | irqres++; | |
1146 | ||
1147 | if (chanirq_res == errirq_res || | |
1148 | (errirq_res->flags & IORESOURCE_BITS) == IORESOURCE_IRQ_SHAREABLE) | |
d8902adc | 1149 | irqflags = IRQF_SHARED; |
027811b9 GL |
1150 | |
1151 | errirq = errirq_res->start; | |
1152 | ||
1153 | err = request_irq(errirq, sh_dmae_err, irqflags, | |
1154 | "DMAC Address Error", shdev); | |
1155 | if (err) { | |
1156 | dev_err(&pdev->dev, | |
1157 | "DMA failed requesting irq #%d, error %d\n", | |
1158 | errirq, err); | |
1159 | goto eirq_err; | |
d8902adc NI |
1160 | } |
1161 | ||
027811b9 GL |
1162 | #else |
1163 | chanirq_res = errirq_res; | |
927a7c9c | 1164 | #endif /* CONFIG_CPU_SH4 || CONFIG_ARCH_SHMOBILE */ |
027811b9 GL |
1165 | |
1166 | if (chanirq_res->start == chanirq_res->end && | |
1167 | !platform_get_resource(pdev, IORESOURCE_IRQ, 1)) { | |
1168 | /* Special case - all multiplexed */ | |
1169 | for (; irq_cnt < pdata->channel_num; irq_cnt++) { | |
1170 | chan_irq[irq_cnt] = chanirq_res->start; | |
1171 | chan_flag[irq_cnt] = IRQF_SHARED; | |
d8902adc | 1172 | } |
027811b9 GL |
1173 | } else { |
1174 | do { | |
1175 | for (i = chanirq_res->start; i <= chanirq_res->end; i++) { | |
1176 | if ((errirq_res->flags & IORESOURCE_BITS) == | |
1177 | IORESOURCE_IRQ_SHAREABLE) | |
1178 | chan_flag[irq_cnt] = IRQF_SHARED; | |
1179 | else | |
1180 | chan_flag[irq_cnt] = IRQF_DISABLED; | |
1181 | dev_dbg(&pdev->dev, | |
1182 | "Found IRQ %d for channel %d\n", | |
1183 | i, irq_cnt); | |
1184 | chan_irq[irq_cnt++] = i; | |
1185 | } | |
1186 | chanirq_res = platform_get_resource(pdev, | |
1187 | IORESOURCE_IRQ, ++irqres); | |
1188 | } while (irq_cnt < pdata->channel_num && chanirq_res); | |
d8902adc | 1189 | } |
027811b9 GL |
1190 | |
1191 | if (irq_cnt < pdata->channel_num) | |
1192 | goto eirqres; | |
d8902adc NI |
1193 | |
1194 | /* Create DMA Channel */ | |
027811b9 GL |
1195 | for (i = 0; i < pdata->channel_num; i++) { |
1196 | err = sh_dmae_chan_probe(shdev, i, chan_irq[i], chan_flag[i]); | |
d8902adc NI |
1197 | if (err) |
1198 | goto chan_probe_err; | |
1199 | } | |
1200 | ||
20f2a3b5 GL |
1201 | pm_runtime_put(&pdev->dev); |
1202 | ||
d8902adc NI |
1203 | platform_set_drvdata(pdev, shdev); |
1204 | dma_async_device_register(&shdev->common); | |
1205 | ||
1206 | return err; | |
1207 | ||
1208 | chan_probe_err: | |
1209 | sh_dmae_chan_remove(shdev); | |
027811b9 | 1210 | eirqres: |
927a7c9c | 1211 | #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE) |
027811b9 | 1212 | free_irq(errirq, shdev); |
d8902adc | 1213 | eirq_err: |
027811b9 | 1214 | #endif |
d8902adc | 1215 | rst_err: |
03aa18f5 PM |
1216 | spin_lock_irqsave(&sh_dmae_lock, flags); |
1217 | list_del_rcu(&shdev->node); | |
1218 | spin_unlock_irqrestore(&sh_dmae_lock, flags); | |
1219 | ||
20f2a3b5 | 1220 | pm_runtime_put(&pdev->dev); |
027811b9 GL |
1221 | if (dmars) |
1222 | iounmap(shdev->dmars); | |
1223 | emapdmars: | |
1224 | iounmap(shdev->chan_reg); | |
1225 | emapchan: | |
d8902adc | 1226 | kfree(shdev); |
027811b9 GL |
1227 | ealloc: |
1228 | if (dmars) | |
1229 | release_mem_region(dmars->start, resource_size(dmars)); | |
1230 | ermrdmars: | |
1231 | release_mem_region(chan->start, resource_size(chan)); | |
d8902adc | 1232 | |
d8902adc NI |
1233 | return err; |
1234 | } | |
1235 | ||
1236 | static int __exit sh_dmae_remove(struct platform_device *pdev) | |
1237 | { | |
1238 | struct sh_dmae_device *shdev = platform_get_drvdata(pdev); | |
027811b9 | 1239 | struct resource *res; |
03aa18f5 | 1240 | unsigned long flags; |
027811b9 | 1241 | int errirq = platform_get_irq(pdev, 0); |
d8902adc NI |
1242 | |
1243 | dma_async_device_unregister(&shdev->common); | |
1244 | ||
027811b9 GL |
1245 | if (errirq > 0) |
1246 | free_irq(errirq, shdev); | |
d8902adc | 1247 | |
03aa18f5 PM |
1248 | spin_lock_irqsave(&sh_dmae_lock, flags); |
1249 | list_del_rcu(&shdev->node); | |
1250 | spin_unlock_irqrestore(&sh_dmae_lock, flags); | |
1251 | ||
d8902adc NI |
1252 | /* channel data remove */ |
1253 | sh_dmae_chan_remove(shdev); | |
1254 | ||
20f2a3b5 GL |
1255 | pm_runtime_disable(&pdev->dev); |
1256 | ||
027811b9 GL |
1257 | if (shdev->dmars) |
1258 | iounmap(shdev->dmars); | |
1259 | iounmap(shdev->chan_reg); | |
1260 | ||
d8902adc NI |
1261 | kfree(shdev); |
1262 | ||
027811b9 GL |
1263 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1264 | if (res) | |
1265 | release_mem_region(res->start, resource_size(res)); | |
1266 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
1267 | if (res) | |
1268 | release_mem_region(res->start, resource_size(res)); | |
1269 | ||
d8902adc NI |
1270 | return 0; |
1271 | } | |
1272 | ||
1273 | static void sh_dmae_shutdown(struct platform_device *pdev) | |
1274 | { | |
1275 | struct sh_dmae_device *shdev = platform_get_drvdata(pdev); | |
027811b9 | 1276 | sh_dmae_ctl_stop(shdev); |
d8902adc NI |
1277 | } |
1278 | ||
1279 | static struct platform_driver sh_dmae_driver = { | |
1280 | .remove = __exit_p(sh_dmae_remove), | |
1281 | .shutdown = sh_dmae_shutdown, | |
1282 | .driver = { | |
7a5c106a | 1283 | .owner = THIS_MODULE, |
d8902adc NI |
1284 | .name = "sh-dma-engine", |
1285 | }, | |
1286 | }; | |
1287 | ||
1288 | static int __init sh_dmae_init(void) | |
1289 | { | |
661382fe GL |
1290 | /* Wire up NMI handling */ |
1291 | int err = register_die_notifier(&sh_dmae_nmi_notifier); | |
1292 | if (err) | |
1293 | return err; | |
1294 | ||
d8902adc NI |
1295 | return platform_driver_probe(&sh_dmae_driver, sh_dmae_probe); |
1296 | } | |
1297 | module_init(sh_dmae_init); | |
1298 | ||
1299 | static void __exit sh_dmae_exit(void) | |
1300 | { | |
1301 | platform_driver_unregister(&sh_dmae_driver); | |
661382fe GL |
1302 | |
1303 | unregister_die_notifier(&sh_dmae_nmi_notifier); | |
d8902adc NI |
1304 | } |
1305 | module_exit(sh_dmae_exit); | |
1306 | ||
1307 | MODULE_AUTHOR("Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>"); | |
1308 | MODULE_DESCRIPTION("Renesas SH DMA Engine driver"); | |
1309 | MODULE_LICENSE("GPL"); | |
e5843341 | 1310 | MODULE_ALIAS("platform:sh-dma-engine"); |