Commit | Line | Data |
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8d318a50 | 1 | /* |
d49278e3 PF |
2 | * Copyright (C) Ericsson AB 2007-2008 |
3 | * Copyright (C) ST-Ericsson SA 2008-2010 | |
661385f9 | 4 | * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson |
767a9675 | 5 | * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson |
8d318a50 | 6 | * License terms: GNU General Public License (GPL) version 2 |
8d318a50 LW |
7 | */ |
8 | ||
b7f080cf | 9 | #include <linux/dma-mapping.h> |
8d318a50 LW |
10 | #include <linux/kernel.h> |
11 | #include <linux/slab.h> | |
f492b210 | 12 | #include <linux/export.h> |
8d318a50 LW |
13 | #include <linux/dmaengine.h> |
14 | #include <linux/platform_device.h> | |
15 | #include <linux/clk.h> | |
16 | #include <linux/delay.h> | |
7fb3e75e N |
17 | #include <linux/pm.h> |
18 | #include <linux/pm_runtime.h> | |
698e4732 | 19 | #include <linux/err.h> |
f4b89764 | 20 | #include <linux/amba/bus.h> |
8d318a50 LW |
21 | |
22 | #include <plat/ste_dma40.h> | |
23 | ||
24 | #include "ste_dma40_ll.h" | |
25 | ||
26 | #define D40_NAME "dma40" | |
27 | ||
28 | #define D40_PHY_CHAN -1 | |
29 | ||
30 | /* For masking out/in 2 bit channel positions */ | |
31 | #define D40_CHAN_POS(chan) (2 * (chan / 2)) | |
32 | #define D40_CHAN_POS_MASK(chan) (0x3 << D40_CHAN_POS(chan)) | |
33 | ||
34 | /* Maximum iterations taken before giving up suspending a channel */ | |
35 | #define D40_SUSPEND_MAX_IT 500 | |
36 | ||
7fb3e75e N |
37 | /* Milliseconds */ |
38 | #define DMA40_AUTOSUSPEND_DELAY 100 | |
39 | ||
508849ad LW |
40 | /* Hardware requirement on LCLA alignment */ |
41 | #define LCLA_ALIGNMENT 0x40000 | |
698e4732 JA |
42 | |
43 | /* Max number of links per event group */ | |
44 | #define D40_LCLA_LINK_PER_EVENT_GRP 128 | |
45 | #define D40_LCLA_END D40_LCLA_LINK_PER_EVENT_GRP | |
46 | ||
508849ad LW |
47 | /* Attempts before giving up to trying to get pages that are aligned */ |
48 | #define MAX_LCLA_ALLOC_ATTEMPTS 256 | |
49 | ||
50 | /* Bit markings for allocation map */ | |
8d318a50 LW |
51 | #define D40_ALLOC_FREE (1 << 31) |
52 | #define D40_ALLOC_PHY (1 << 30) | |
53 | #define D40_ALLOC_LOG_FREE 0 | |
54 | ||
8d318a50 LW |
55 | /** |
56 | * enum 40_command - The different commands and/or statuses. | |
57 | * | |
58 | * @D40_DMA_STOP: DMA channel command STOP or status STOPPED, | |
59 | * @D40_DMA_RUN: The DMA channel is RUNNING of the command RUN. | |
60 | * @D40_DMA_SUSPEND_REQ: Request the DMA to SUSPEND as soon as possible. | |
61 | * @D40_DMA_SUSPENDED: The DMA channel is SUSPENDED. | |
62 | */ | |
63 | enum d40_command { | |
64 | D40_DMA_STOP = 0, | |
65 | D40_DMA_RUN = 1, | |
66 | D40_DMA_SUSPEND_REQ = 2, | |
67 | D40_DMA_SUSPENDED = 3 | |
68 | }; | |
69 | ||
7fb3e75e N |
70 | /* |
71 | * These are the registers that has to be saved and later restored | |
72 | * when the DMA hw is powered off. | |
73 | * TODO: Add save/restore of D40_DREG_GCC on dma40 v3 or later, if that works. | |
74 | */ | |
75 | static u32 d40_backup_regs[] = { | |
76 | D40_DREG_LCPA, | |
77 | D40_DREG_LCLA, | |
78 | D40_DREG_PRMSE, | |
79 | D40_DREG_PRMSO, | |
80 | D40_DREG_PRMOE, | |
81 | D40_DREG_PRMOO, | |
82 | }; | |
83 | ||
84 | #define BACKUP_REGS_SZ ARRAY_SIZE(d40_backup_regs) | |
85 | ||
86 | /* TODO: Check if all these registers have to be saved/restored on dma40 v3 */ | |
87 | static u32 d40_backup_regs_v3[] = { | |
88 | D40_DREG_PSEG1, | |
89 | D40_DREG_PSEG2, | |
90 | D40_DREG_PSEG3, | |
91 | D40_DREG_PSEG4, | |
92 | D40_DREG_PCEG1, | |
93 | D40_DREG_PCEG2, | |
94 | D40_DREG_PCEG3, | |
95 | D40_DREG_PCEG4, | |
96 | D40_DREG_RSEG1, | |
97 | D40_DREG_RSEG2, | |
98 | D40_DREG_RSEG3, | |
99 | D40_DREG_RSEG4, | |
100 | D40_DREG_RCEG1, | |
101 | D40_DREG_RCEG2, | |
102 | D40_DREG_RCEG3, | |
103 | D40_DREG_RCEG4, | |
104 | }; | |
105 | ||
106 | #define BACKUP_REGS_SZ_V3 ARRAY_SIZE(d40_backup_regs_v3) | |
107 | ||
108 | static u32 d40_backup_regs_chan[] = { | |
109 | D40_CHAN_REG_SSCFG, | |
110 | D40_CHAN_REG_SSELT, | |
111 | D40_CHAN_REG_SSPTR, | |
112 | D40_CHAN_REG_SSLNK, | |
113 | D40_CHAN_REG_SDCFG, | |
114 | D40_CHAN_REG_SDELT, | |
115 | D40_CHAN_REG_SDPTR, | |
116 | D40_CHAN_REG_SDLNK, | |
117 | }; | |
118 | ||
8d318a50 LW |
119 | /** |
120 | * struct d40_lli_pool - Structure for keeping LLIs in memory | |
121 | * | |
122 | * @base: Pointer to memory area when the pre_alloc_lli's are not large | |
123 | * enough, IE bigger than the most common case, 1 dst and 1 src. NULL if | |
124 | * pre_alloc_lli is used. | |
b00f938c | 125 | * @dma_addr: DMA address, if mapped |
8d318a50 LW |
126 | * @size: The size in bytes of the memory at base or the size of pre_alloc_lli. |
127 | * @pre_alloc_lli: Pre allocated area for the most common case of transfers, | |
128 | * one buffer to one buffer. | |
129 | */ | |
130 | struct d40_lli_pool { | |
131 | void *base; | |
508849ad | 132 | int size; |
b00f938c | 133 | dma_addr_t dma_addr; |
8d318a50 | 134 | /* Space for dst and src, plus an extra for padding */ |
508849ad | 135 | u8 pre_alloc_lli[3 * sizeof(struct d40_phy_lli)]; |
8d318a50 LW |
136 | }; |
137 | ||
138 | /** | |
139 | * struct d40_desc - A descriptor is one DMA job. | |
140 | * | |
141 | * @lli_phy: LLI settings for physical channel. Both src and dst= | |
142 | * points into the lli_pool, to base if lli_len > 1 or to pre_alloc_lli if | |
143 | * lli_len equals one. | |
144 | * @lli_log: Same as above but for logical channels. | |
145 | * @lli_pool: The pool with two entries pre-allocated. | |
941b77a3 | 146 | * @lli_len: Number of llis of current descriptor. |
25985edc | 147 | * @lli_current: Number of transferred llis. |
698e4732 | 148 | * @lcla_alloc: Number of LCLA entries allocated. |
8d318a50 LW |
149 | * @txd: DMA engine struct. Used for among other things for communication |
150 | * during a transfer. | |
151 | * @node: List entry. | |
8d318a50 | 152 | * @is_in_client_list: true if the client owns this descriptor. |
7fb3e75e | 153 | * @cyclic: true if this is a cyclic job |
8d318a50 LW |
154 | * |
155 | * This descriptor is used for both logical and physical transfers. | |
156 | */ | |
8d318a50 LW |
157 | struct d40_desc { |
158 | /* LLI physical */ | |
159 | struct d40_phy_lli_bidir lli_phy; | |
160 | /* LLI logical */ | |
161 | struct d40_log_lli_bidir lli_log; | |
162 | ||
163 | struct d40_lli_pool lli_pool; | |
941b77a3 | 164 | int lli_len; |
698e4732 JA |
165 | int lli_current; |
166 | int lcla_alloc; | |
8d318a50 LW |
167 | |
168 | struct dma_async_tx_descriptor txd; | |
169 | struct list_head node; | |
170 | ||
8d318a50 | 171 | bool is_in_client_list; |
0c842b55 | 172 | bool cyclic; |
8d318a50 LW |
173 | }; |
174 | ||
175 | /** | |
176 | * struct d40_lcla_pool - LCLA pool settings and data. | |
177 | * | |
508849ad LW |
178 | * @base: The virtual address of LCLA. 18 bit aligned. |
179 | * @base_unaligned: The orignal kmalloc pointer, if kmalloc is used. | |
180 | * This pointer is only there for clean-up on error. | |
181 | * @pages: The number of pages needed for all physical channels. | |
182 | * Only used later for clean-up on error | |
8d318a50 | 183 | * @lock: Lock to protect the content in this struct. |
698e4732 | 184 | * @alloc_map: big map over which LCLA entry is own by which job. |
8d318a50 LW |
185 | */ |
186 | struct d40_lcla_pool { | |
187 | void *base; | |
026cbc42 | 188 | dma_addr_t dma_addr; |
508849ad LW |
189 | void *base_unaligned; |
190 | int pages; | |
8d318a50 | 191 | spinlock_t lock; |
698e4732 | 192 | struct d40_desc **alloc_map; |
8d318a50 LW |
193 | }; |
194 | ||
195 | /** | |
196 | * struct d40_phy_res - struct for handling eventlines mapped to physical | |
197 | * channels. | |
198 | * | |
199 | * @lock: A lock protection this entity. | |
7fb3e75e | 200 | * @reserved: True if used by secure world or otherwise. |
8d318a50 LW |
201 | * @num: The physical channel number of this entity. |
202 | * @allocated_src: Bit mapped to show which src event line's are mapped to | |
203 | * this physical channel. Can also be free or physically allocated. | |
204 | * @allocated_dst: Same as for src but is dst. | |
205 | * allocated_dst and allocated_src uses the D40_ALLOC* defines as well as | |
767a9675 | 206 | * event line number. |
8d318a50 LW |
207 | */ |
208 | struct d40_phy_res { | |
209 | spinlock_t lock; | |
7fb3e75e | 210 | bool reserved; |
8d318a50 LW |
211 | int num; |
212 | u32 allocated_src; | |
213 | u32 allocated_dst; | |
214 | }; | |
215 | ||
216 | struct d40_base; | |
217 | ||
218 | /** | |
219 | * struct d40_chan - Struct that describes a channel. | |
220 | * | |
221 | * @lock: A spinlock to protect this struct. | |
222 | * @log_num: The logical number, if any of this channel. | |
8d318a50 LW |
223 | * @pending_tx: The number of pending transfers. Used between interrupt handler |
224 | * and tasklet. | |
225 | * @busy: Set to true when transfer is ongoing on this channel. | |
2a614340 JA |
226 | * @phy_chan: Pointer to physical channel which this instance runs on. If this |
227 | * point is NULL, then the channel is not allocated. | |
8d318a50 LW |
228 | * @chan: DMA engine handle. |
229 | * @tasklet: Tasklet that gets scheduled from interrupt context to complete a | |
230 | * transfer and call client callback. | |
231 | * @client: Cliented owned descriptor list. | |
da063d26 | 232 | * @pending_queue: Submitted jobs, to be issued by issue_pending() |
8d318a50 LW |
233 | * @active: Active descriptor. |
234 | * @queue: Queued jobs. | |
82babbb3 | 235 | * @prepare_queue: Prepared jobs. |
8d318a50 | 236 | * @dma_cfg: The client configuration of this dma channel. |
ce2ca125 | 237 | * @configured: whether the dma_cfg configuration is valid |
8d318a50 LW |
238 | * @base: Pointer to the device instance struct. |
239 | * @src_def_cfg: Default cfg register setting for src. | |
240 | * @dst_def_cfg: Default cfg register setting for dst. | |
241 | * @log_def: Default logical channel settings. | |
8d318a50 | 242 | * @lcpa: Pointer to dst and src lcpa settings. |
ae752bf4 | 243 | * @runtime_addr: runtime configured address. |
244 | * @runtime_direction: runtime configured direction. | |
8d318a50 LW |
245 | * |
246 | * This struct can either "be" a logical or a physical channel. | |
247 | */ | |
248 | struct d40_chan { | |
249 | spinlock_t lock; | |
250 | int log_num; | |
8d318a50 LW |
251 | int pending_tx; |
252 | bool busy; | |
253 | struct d40_phy_res *phy_chan; | |
254 | struct dma_chan chan; | |
255 | struct tasklet_struct tasklet; | |
256 | struct list_head client; | |
a8f3067b | 257 | struct list_head pending_queue; |
8d318a50 LW |
258 | struct list_head active; |
259 | struct list_head queue; | |
82babbb3 | 260 | struct list_head prepare_queue; |
8d318a50 | 261 | struct stedma40_chan_cfg dma_cfg; |
ce2ca125 | 262 | bool configured; |
8d318a50 LW |
263 | struct d40_base *base; |
264 | /* Default register configurations */ | |
265 | u32 src_def_cfg; | |
266 | u32 dst_def_cfg; | |
267 | struct d40_def_lcsp log_def; | |
8d318a50 | 268 | struct d40_log_lli_full *lcpa; |
95e1400f LW |
269 | /* Runtime reconfiguration */ |
270 | dma_addr_t runtime_addr; | |
db8196df | 271 | enum dma_transfer_direction runtime_direction; |
8d318a50 LW |
272 | }; |
273 | ||
274 | /** | |
275 | * struct d40_base - The big global struct, one for each probe'd instance. | |
276 | * | |
277 | * @interrupt_lock: Lock used to make sure one interrupt is handle a time. | |
278 | * @execmd_lock: Lock for execute command usage since several channels share | |
279 | * the same physical register. | |
280 | * @dev: The device structure. | |
281 | * @virtbase: The virtual base address of the DMA's register. | |
f4185592 | 282 | * @rev: silicon revision detected. |
8d318a50 LW |
283 | * @clk: Pointer to the DMA clock structure. |
284 | * @phy_start: Physical memory start of the DMA registers. | |
285 | * @phy_size: Size of the DMA register map. | |
286 | * @irq: The IRQ number. | |
287 | * @num_phy_chans: The number of physical channels. Read from HW. This | |
288 | * is the number of available channels for this driver, not counting "Secure | |
289 | * mode" allocated physical channels. | |
290 | * @num_log_chans: The number of logical channels. Calculated from | |
291 | * num_phy_chans. | |
292 | * @dma_both: dma_device channels that can do both memcpy and slave transfers. | |
293 | * @dma_slave: dma_device channels that can do only do slave transfers. | |
294 | * @dma_memcpy: dma_device channels that can do only do memcpy transfers. | |
7fb3e75e | 295 | * @phy_chans: Room for all possible physical channels in system. |
8d318a50 LW |
296 | * @log_chans: Room for all possible logical channels in system. |
297 | * @lookup_log_chans: Used to map interrupt number to logical channel. Points | |
298 | * to log_chans entries. | |
299 | * @lookup_phy_chans: Used to map interrupt number to physical channel. Points | |
300 | * to phy_chans entries. | |
301 | * @plat_data: Pointer to provided platform_data which is the driver | |
302 | * configuration. | |
28c7a19d | 303 | * @lcpa_regulator: Pointer to hold the regulator for the esram bank for lcla. |
8d318a50 LW |
304 | * @phy_res: Vector containing all physical channels. |
305 | * @lcla_pool: lcla pool settings and data. | |
306 | * @lcpa_base: The virtual mapped address of LCPA. | |
307 | * @phy_lcpa: The physical address of the LCPA. | |
308 | * @lcpa_size: The size of the LCPA area. | |
c675b1b4 | 309 | * @desc_slab: cache for descriptors. |
7fb3e75e N |
310 | * @reg_val_backup: Here the values of some hardware registers are stored |
311 | * before the DMA is powered off. They are restored when the power is back on. | |
312 | * @reg_val_backup_v3: Backup of registers that only exits on dma40 v3 and | |
313 | * later. | |
314 | * @reg_val_backup_chan: Backup data for standard channel parameter registers. | |
315 | * @gcc_pwr_off_mask: Mask to maintain the channels that can be turned off. | |
316 | * @initialized: true if the dma has been initialized | |
8d318a50 LW |
317 | */ |
318 | struct d40_base { | |
319 | spinlock_t interrupt_lock; | |
320 | spinlock_t execmd_lock; | |
321 | struct device *dev; | |
322 | void __iomem *virtbase; | |
f4185592 | 323 | u8 rev:4; |
8d318a50 LW |
324 | struct clk *clk; |
325 | phys_addr_t phy_start; | |
326 | resource_size_t phy_size; | |
327 | int irq; | |
328 | int num_phy_chans; | |
329 | int num_log_chans; | |
330 | struct dma_device dma_both; | |
331 | struct dma_device dma_slave; | |
332 | struct dma_device dma_memcpy; | |
333 | struct d40_chan *phy_chans; | |
334 | struct d40_chan *log_chans; | |
335 | struct d40_chan **lookup_log_chans; | |
336 | struct d40_chan **lookup_phy_chans; | |
337 | struct stedma40_platform_data *plat_data; | |
28c7a19d | 338 | struct regulator *lcpa_regulator; |
8d318a50 LW |
339 | /* Physical half channels */ |
340 | struct d40_phy_res *phy_res; | |
341 | struct d40_lcla_pool lcla_pool; | |
342 | void *lcpa_base; | |
343 | dma_addr_t phy_lcpa; | |
344 | resource_size_t lcpa_size; | |
c675b1b4 | 345 | struct kmem_cache *desc_slab; |
7fb3e75e N |
346 | u32 reg_val_backup[BACKUP_REGS_SZ]; |
347 | u32 reg_val_backup_v3[BACKUP_REGS_SZ_V3]; | |
348 | u32 *reg_val_backup_chan; | |
349 | u16 gcc_pwr_off_mask; | |
350 | bool initialized; | |
8d318a50 LW |
351 | }; |
352 | ||
353 | /** | |
354 | * struct d40_interrupt_lookup - lookup table for interrupt handler | |
355 | * | |
356 | * @src: Interrupt mask register. | |
357 | * @clr: Interrupt clear register. | |
358 | * @is_error: true if this is an error interrupt. | |
359 | * @offset: start delta in the lookup_log_chans in d40_base. If equals to | |
360 | * D40_PHY_CHAN, the lookup_phy_chans shall be used instead. | |
361 | */ | |
362 | struct d40_interrupt_lookup { | |
363 | u32 src; | |
364 | u32 clr; | |
365 | bool is_error; | |
366 | int offset; | |
367 | }; | |
368 | ||
369 | /** | |
370 | * struct d40_reg_val - simple lookup struct | |
371 | * | |
372 | * @reg: The register. | |
373 | * @val: The value that belongs to the register in reg. | |
374 | */ | |
375 | struct d40_reg_val { | |
376 | unsigned int reg; | |
377 | unsigned int val; | |
378 | }; | |
379 | ||
262d2915 RV |
380 | static struct device *chan2dev(struct d40_chan *d40c) |
381 | { | |
382 | return &d40c->chan.dev->device; | |
383 | } | |
384 | ||
724a8577 RV |
385 | static bool chan_is_physical(struct d40_chan *chan) |
386 | { | |
387 | return chan->log_num == D40_PHY_CHAN; | |
388 | } | |
389 | ||
390 | static bool chan_is_logical(struct d40_chan *chan) | |
391 | { | |
392 | return !chan_is_physical(chan); | |
393 | } | |
394 | ||
8ca84687 RV |
395 | static void __iomem *chan_base(struct d40_chan *chan) |
396 | { | |
397 | return chan->base->virtbase + D40_DREG_PCBASE + | |
398 | chan->phy_chan->num * D40_DREG_PCDELTA; | |
399 | } | |
400 | ||
6db5a8ba RV |
401 | #define d40_err(dev, format, arg...) \ |
402 | dev_err(dev, "[%s] " format, __func__, ## arg) | |
403 | ||
404 | #define chan_err(d40c, format, arg...) \ | |
405 | d40_err(chan2dev(d40c), format, ## arg) | |
406 | ||
b00f938c | 407 | static int d40_pool_lli_alloc(struct d40_chan *d40c, struct d40_desc *d40d, |
dbd88788 | 408 | int lli_len) |
8d318a50 | 409 | { |
dbd88788 | 410 | bool is_log = chan_is_logical(d40c); |
8d318a50 LW |
411 | u32 align; |
412 | void *base; | |
413 | ||
414 | if (is_log) | |
415 | align = sizeof(struct d40_log_lli); | |
416 | else | |
417 | align = sizeof(struct d40_phy_lli); | |
418 | ||
419 | if (lli_len == 1) { | |
420 | base = d40d->lli_pool.pre_alloc_lli; | |
421 | d40d->lli_pool.size = sizeof(d40d->lli_pool.pre_alloc_lli); | |
422 | d40d->lli_pool.base = NULL; | |
423 | } else { | |
594ece4d | 424 | d40d->lli_pool.size = lli_len * 2 * align; |
8d318a50 LW |
425 | |
426 | base = kmalloc(d40d->lli_pool.size + align, GFP_NOWAIT); | |
427 | d40d->lli_pool.base = base; | |
428 | ||
429 | if (d40d->lli_pool.base == NULL) | |
430 | return -ENOMEM; | |
431 | } | |
432 | ||
433 | if (is_log) { | |
d924abad | 434 | d40d->lli_log.src = PTR_ALIGN(base, align); |
594ece4d | 435 | d40d->lli_log.dst = d40d->lli_log.src + lli_len; |
b00f938c RV |
436 | |
437 | d40d->lli_pool.dma_addr = 0; | |
8d318a50 | 438 | } else { |
d924abad | 439 | d40d->lli_phy.src = PTR_ALIGN(base, align); |
594ece4d | 440 | d40d->lli_phy.dst = d40d->lli_phy.src + lli_len; |
b00f938c RV |
441 | |
442 | d40d->lli_pool.dma_addr = dma_map_single(d40c->base->dev, | |
443 | d40d->lli_phy.src, | |
444 | d40d->lli_pool.size, | |
445 | DMA_TO_DEVICE); | |
446 | ||
447 | if (dma_mapping_error(d40c->base->dev, | |
448 | d40d->lli_pool.dma_addr)) { | |
449 | kfree(d40d->lli_pool.base); | |
450 | d40d->lli_pool.base = NULL; | |
451 | d40d->lli_pool.dma_addr = 0; | |
452 | return -ENOMEM; | |
453 | } | |
8d318a50 LW |
454 | } |
455 | ||
456 | return 0; | |
457 | } | |
458 | ||
b00f938c | 459 | static void d40_pool_lli_free(struct d40_chan *d40c, struct d40_desc *d40d) |
8d318a50 | 460 | { |
b00f938c RV |
461 | if (d40d->lli_pool.dma_addr) |
462 | dma_unmap_single(d40c->base->dev, d40d->lli_pool.dma_addr, | |
463 | d40d->lli_pool.size, DMA_TO_DEVICE); | |
464 | ||
8d318a50 LW |
465 | kfree(d40d->lli_pool.base); |
466 | d40d->lli_pool.base = NULL; | |
467 | d40d->lli_pool.size = 0; | |
468 | d40d->lli_log.src = NULL; | |
469 | d40d->lli_log.dst = NULL; | |
470 | d40d->lli_phy.src = NULL; | |
471 | d40d->lli_phy.dst = NULL; | |
8d318a50 LW |
472 | } |
473 | ||
698e4732 JA |
474 | static int d40_lcla_alloc_one(struct d40_chan *d40c, |
475 | struct d40_desc *d40d) | |
476 | { | |
477 | unsigned long flags; | |
478 | int i; | |
479 | int ret = -EINVAL; | |
480 | int p; | |
481 | ||
482 | spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags); | |
483 | ||
484 | p = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP; | |
485 | ||
486 | /* | |
487 | * Allocate both src and dst at the same time, therefore the half | |
488 | * start on 1 since 0 can't be used since zero is used as end marker. | |
489 | */ | |
490 | for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) { | |
491 | if (!d40c->base->lcla_pool.alloc_map[p + i]) { | |
492 | d40c->base->lcla_pool.alloc_map[p + i] = d40d; | |
493 | d40d->lcla_alloc++; | |
494 | ret = i; | |
495 | break; | |
496 | } | |
497 | } | |
498 | ||
499 | spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags); | |
500 | ||
501 | return ret; | |
502 | } | |
503 | ||
504 | static int d40_lcla_free_all(struct d40_chan *d40c, | |
505 | struct d40_desc *d40d) | |
506 | { | |
507 | unsigned long flags; | |
508 | int i; | |
509 | int ret = -EINVAL; | |
510 | ||
724a8577 | 511 | if (chan_is_physical(d40c)) |
698e4732 JA |
512 | return 0; |
513 | ||
514 | spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags); | |
515 | ||
516 | for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) { | |
517 | if (d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num * | |
518 | D40_LCLA_LINK_PER_EVENT_GRP + i] == d40d) { | |
519 | d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num * | |
520 | D40_LCLA_LINK_PER_EVENT_GRP + i] = NULL; | |
521 | d40d->lcla_alloc--; | |
522 | if (d40d->lcla_alloc == 0) { | |
523 | ret = 0; | |
524 | break; | |
525 | } | |
526 | } | |
527 | } | |
528 | ||
529 | spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags); | |
530 | ||
531 | return ret; | |
532 | ||
533 | } | |
534 | ||
8d318a50 LW |
535 | static void d40_desc_remove(struct d40_desc *d40d) |
536 | { | |
537 | list_del(&d40d->node); | |
538 | } | |
539 | ||
540 | static struct d40_desc *d40_desc_get(struct d40_chan *d40c) | |
541 | { | |
a2c15fa4 | 542 | struct d40_desc *desc = NULL; |
8d318a50 LW |
543 | |
544 | if (!list_empty(&d40c->client)) { | |
a2c15fa4 RV |
545 | struct d40_desc *d; |
546 | struct d40_desc *_d; | |
547 | ||
7fb3e75e | 548 | list_for_each_entry_safe(d, _d, &d40c->client, node) { |
8d318a50 | 549 | if (async_tx_test_ack(&d->txd)) { |
8d318a50 | 550 | d40_desc_remove(d); |
a2c15fa4 RV |
551 | desc = d; |
552 | memset(desc, 0, sizeof(*desc)); | |
c675b1b4 | 553 | break; |
8d318a50 | 554 | } |
7fb3e75e | 555 | } |
8d318a50 | 556 | } |
a2c15fa4 RV |
557 | |
558 | if (!desc) | |
559 | desc = kmem_cache_zalloc(d40c->base->desc_slab, GFP_NOWAIT); | |
560 | ||
561 | if (desc) | |
562 | INIT_LIST_HEAD(&desc->node); | |
563 | ||
564 | return desc; | |
8d318a50 LW |
565 | } |
566 | ||
567 | static void d40_desc_free(struct d40_chan *d40c, struct d40_desc *d40d) | |
568 | { | |
698e4732 | 569 | |
b00f938c | 570 | d40_pool_lli_free(d40c, d40d); |
698e4732 | 571 | d40_lcla_free_all(d40c, d40d); |
c675b1b4 | 572 | kmem_cache_free(d40c->base->desc_slab, d40d); |
8d318a50 LW |
573 | } |
574 | ||
575 | static void d40_desc_submit(struct d40_chan *d40c, struct d40_desc *desc) | |
576 | { | |
577 | list_add_tail(&desc->node, &d40c->active); | |
578 | } | |
579 | ||
1c4b0927 RV |
580 | static void d40_phy_lli_load(struct d40_chan *chan, struct d40_desc *desc) |
581 | { | |
582 | struct d40_phy_lli *lli_dst = desc->lli_phy.dst; | |
583 | struct d40_phy_lli *lli_src = desc->lli_phy.src; | |
584 | void __iomem *base = chan_base(chan); | |
585 | ||
586 | writel(lli_src->reg_cfg, base + D40_CHAN_REG_SSCFG); | |
587 | writel(lli_src->reg_elt, base + D40_CHAN_REG_SSELT); | |
588 | writel(lli_src->reg_ptr, base + D40_CHAN_REG_SSPTR); | |
589 | writel(lli_src->reg_lnk, base + D40_CHAN_REG_SSLNK); | |
590 | ||
591 | writel(lli_dst->reg_cfg, base + D40_CHAN_REG_SDCFG); | |
592 | writel(lli_dst->reg_elt, base + D40_CHAN_REG_SDELT); | |
593 | writel(lli_dst->reg_ptr, base + D40_CHAN_REG_SDPTR); | |
594 | writel(lli_dst->reg_lnk, base + D40_CHAN_REG_SDLNK); | |
595 | } | |
596 | ||
e65889c7 | 597 | static void d40_log_lli_to_lcxa(struct d40_chan *chan, struct d40_desc *desc) |
698e4732 | 598 | { |
e65889c7 RV |
599 | struct d40_lcla_pool *pool = &chan->base->lcla_pool; |
600 | struct d40_log_lli_bidir *lli = &desc->lli_log; | |
601 | int lli_current = desc->lli_current; | |
602 | int lli_len = desc->lli_len; | |
0c842b55 | 603 | bool cyclic = desc->cyclic; |
e65889c7 | 604 | int curr_lcla = -EINVAL; |
0c842b55 | 605 | int first_lcla = 0; |
28c7a19d | 606 | bool use_esram_lcla = chan->base->plat_data->use_esram_lcla; |
0c842b55 | 607 | bool linkback; |
e65889c7 | 608 | |
0c842b55 RV |
609 | /* |
610 | * We may have partially running cyclic transfers, in case we did't get | |
611 | * enough LCLA entries. | |
612 | */ | |
613 | linkback = cyclic && lli_current == 0; | |
614 | ||
615 | /* | |
616 | * For linkback, we need one LCLA even with only one link, because we | |
617 | * can't link back to the one in LCPA space | |
618 | */ | |
619 | if (linkback || (lli_len - lli_current > 1)) { | |
e65889c7 | 620 | curr_lcla = d40_lcla_alloc_one(chan, desc); |
0c842b55 RV |
621 | first_lcla = curr_lcla; |
622 | } | |
623 | ||
624 | /* | |
625 | * For linkback, we normally load the LCPA in the loop since we need to | |
626 | * link it to the second LCLA and not the first. However, if we | |
627 | * couldn't even get a first LCLA, then we have to run in LCPA and | |
628 | * reload manually. | |
629 | */ | |
630 | if (!linkback || curr_lcla == -EINVAL) { | |
631 | unsigned int flags = 0; | |
e65889c7 | 632 | |
0c842b55 RV |
633 | if (curr_lcla == -EINVAL) |
634 | flags |= LLI_TERM_INT; | |
e65889c7 | 635 | |
0c842b55 RV |
636 | d40_log_lli_lcpa_write(chan->lcpa, |
637 | &lli->dst[lli_current], | |
638 | &lli->src[lli_current], | |
639 | curr_lcla, | |
640 | flags); | |
641 | lli_current++; | |
642 | } | |
6045f0bb RV |
643 | |
644 | if (curr_lcla < 0) | |
645 | goto out; | |
646 | ||
e65889c7 RV |
647 | for (; lli_current < lli_len; lli_current++) { |
648 | unsigned int lcla_offset = chan->phy_chan->num * 1024 + | |
649 | 8 * curr_lcla * 2; | |
650 | struct d40_log_lli *lcla = pool->base + lcla_offset; | |
0c842b55 | 651 | unsigned int flags = 0; |
e65889c7 RV |
652 | int next_lcla; |
653 | ||
654 | if (lli_current + 1 < lli_len) | |
655 | next_lcla = d40_lcla_alloc_one(chan, desc); | |
656 | else | |
0c842b55 RV |
657 | next_lcla = linkback ? first_lcla : -EINVAL; |
658 | ||
659 | if (cyclic || next_lcla == -EINVAL) | |
660 | flags |= LLI_TERM_INT; | |
e65889c7 | 661 | |
0c842b55 RV |
662 | if (linkback && curr_lcla == first_lcla) { |
663 | /* First link goes in both LCPA and LCLA */ | |
664 | d40_log_lli_lcpa_write(chan->lcpa, | |
665 | &lli->dst[lli_current], | |
666 | &lli->src[lli_current], | |
667 | next_lcla, flags); | |
668 | } | |
669 | ||
670 | /* | |
671 | * One unused LCLA in the cyclic case if the very first | |
672 | * next_lcla fails... | |
673 | */ | |
e65889c7 RV |
674 | d40_log_lli_lcla_write(lcla, |
675 | &lli->dst[lli_current], | |
676 | &lli->src[lli_current], | |
0c842b55 | 677 | next_lcla, flags); |
e65889c7 | 678 | |
28c7a19d N |
679 | /* |
680 | * Cache maintenance is not needed if lcla is | |
681 | * mapped in esram | |
682 | */ | |
683 | if (!use_esram_lcla) { | |
684 | dma_sync_single_range_for_device(chan->base->dev, | |
685 | pool->dma_addr, lcla_offset, | |
686 | 2 * sizeof(struct d40_log_lli), | |
687 | DMA_TO_DEVICE); | |
688 | } | |
e65889c7 RV |
689 | curr_lcla = next_lcla; |
690 | ||
0c842b55 | 691 | if (curr_lcla == -EINVAL || curr_lcla == first_lcla) { |
e65889c7 RV |
692 | lli_current++; |
693 | break; | |
694 | } | |
695 | } | |
696 | ||
6045f0bb | 697 | out: |
e65889c7 RV |
698 | desc->lli_current = lli_current; |
699 | } | |
698e4732 | 700 | |
e65889c7 RV |
701 | static void d40_desc_load(struct d40_chan *d40c, struct d40_desc *d40d) |
702 | { | |
724a8577 | 703 | if (chan_is_physical(d40c)) { |
1c4b0927 | 704 | d40_phy_lli_load(d40c, d40d); |
698e4732 | 705 | d40d->lli_current = d40d->lli_len; |
e65889c7 RV |
706 | } else |
707 | d40_log_lli_to_lcxa(d40c, d40d); | |
698e4732 JA |
708 | } |
709 | ||
8d318a50 LW |
710 | static struct d40_desc *d40_first_active_get(struct d40_chan *d40c) |
711 | { | |
712 | struct d40_desc *d; | |
713 | ||
714 | if (list_empty(&d40c->active)) | |
715 | return NULL; | |
716 | ||
717 | d = list_first_entry(&d40c->active, | |
718 | struct d40_desc, | |
719 | node); | |
720 | return d; | |
721 | } | |
722 | ||
7404368c | 723 | /* remove desc from current queue and add it to the pending_queue */ |
8d318a50 LW |
724 | static void d40_desc_queue(struct d40_chan *d40c, struct d40_desc *desc) |
725 | { | |
7404368c PF |
726 | d40_desc_remove(desc); |
727 | desc->is_in_client_list = false; | |
a8f3067b PF |
728 | list_add_tail(&desc->node, &d40c->pending_queue); |
729 | } | |
730 | ||
731 | static struct d40_desc *d40_first_pending(struct d40_chan *d40c) | |
732 | { | |
733 | struct d40_desc *d; | |
734 | ||
735 | if (list_empty(&d40c->pending_queue)) | |
736 | return NULL; | |
737 | ||
738 | d = list_first_entry(&d40c->pending_queue, | |
739 | struct d40_desc, | |
740 | node); | |
741 | return d; | |
8d318a50 LW |
742 | } |
743 | ||
744 | static struct d40_desc *d40_first_queued(struct d40_chan *d40c) | |
745 | { | |
746 | struct d40_desc *d; | |
747 | ||
748 | if (list_empty(&d40c->queue)) | |
749 | return NULL; | |
750 | ||
751 | d = list_first_entry(&d40c->queue, | |
752 | struct d40_desc, | |
753 | node); | |
754 | return d; | |
755 | } | |
756 | ||
d49278e3 PF |
757 | static int d40_psize_2_burst_size(bool is_log, int psize) |
758 | { | |
759 | if (is_log) { | |
760 | if (psize == STEDMA40_PSIZE_LOG_1) | |
761 | return 1; | |
762 | } else { | |
763 | if (psize == STEDMA40_PSIZE_PHY_1) | |
764 | return 1; | |
765 | } | |
766 | ||
767 | return 2 << psize; | |
768 | } | |
769 | ||
770 | /* | |
771 | * The dma only supports transmitting packages up to | |
772 | * STEDMA40_MAX_SEG_SIZE << data_width. Calculate the total number of | |
773 | * dma elements required to send the entire sg list | |
774 | */ | |
775 | static int d40_size_2_dmalen(int size, u32 data_width1, u32 data_width2) | |
776 | { | |
777 | int dmalen; | |
778 | u32 max_w = max(data_width1, data_width2); | |
779 | u32 min_w = min(data_width1, data_width2); | |
780 | u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE << min_w, 1 << max_w); | |
781 | ||
782 | if (seg_max > STEDMA40_MAX_SEG_SIZE) | |
783 | seg_max -= (1 << max_w); | |
784 | ||
785 | if (!IS_ALIGNED(size, 1 << max_w)) | |
786 | return -EINVAL; | |
787 | ||
788 | if (size <= seg_max) | |
789 | dmalen = 1; | |
790 | else { | |
791 | dmalen = size / seg_max; | |
792 | if (dmalen * seg_max < size) | |
793 | dmalen++; | |
794 | } | |
795 | return dmalen; | |
796 | } | |
797 | ||
798 | static int d40_sg_2_dmalen(struct scatterlist *sgl, int sg_len, | |
799 | u32 data_width1, u32 data_width2) | |
800 | { | |
801 | struct scatterlist *sg; | |
802 | int i; | |
803 | int len = 0; | |
804 | int ret; | |
805 | ||
806 | for_each_sg(sgl, sg, sg_len, i) { | |
807 | ret = d40_size_2_dmalen(sg_dma_len(sg), | |
808 | data_width1, data_width2); | |
809 | if (ret < 0) | |
810 | return ret; | |
811 | len += ret; | |
812 | } | |
813 | return len; | |
814 | } | |
8d318a50 | 815 | |
7fb3e75e N |
816 | |
817 | #ifdef CONFIG_PM | |
818 | static void dma40_backup(void __iomem *baseaddr, u32 *backup, | |
819 | u32 *regaddr, int num, bool save) | |
820 | { | |
821 | int i; | |
822 | ||
823 | for (i = 0; i < num; i++) { | |
824 | void __iomem *addr = baseaddr + regaddr[i]; | |
825 | ||
826 | if (save) | |
827 | backup[i] = readl_relaxed(addr); | |
828 | else | |
829 | writel_relaxed(backup[i], addr); | |
830 | } | |
831 | } | |
832 | ||
833 | static void d40_save_restore_registers(struct d40_base *base, bool save) | |
834 | { | |
835 | int i; | |
836 | ||
837 | /* Save/Restore channel specific registers */ | |
838 | for (i = 0; i < base->num_phy_chans; i++) { | |
839 | void __iomem *addr; | |
840 | int idx; | |
841 | ||
842 | if (base->phy_res[i].reserved) | |
843 | continue; | |
844 | ||
845 | addr = base->virtbase + D40_DREG_PCBASE + i * D40_DREG_PCDELTA; | |
846 | idx = i * ARRAY_SIZE(d40_backup_regs_chan); | |
847 | ||
848 | dma40_backup(addr, &base->reg_val_backup_chan[idx], | |
849 | d40_backup_regs_chan, | |
850 | ARRAY_SIZE(d40_backup_regs_chan), | |
851 | save); | |
852 | } | |
853 | ||
854 | /* Save/Restore global registers */ | |
855 | dma40_backup(base->virtbase, base->reg_val_backup, | |
856 | d40_backup_regs, ARRAY_SIZE(d40_backup_regs), | |
857 | save); | |
858 | ||
859 | /* Save/Restore registers only existing on dma40 v3 and later */ | |
860 | if (base->rev >= 3) | |
861 | dma40_backup(base->virtbase, base->reg_val_backup_v3, | |
862 | d40_backup_regs_v3, | |
863 | ARRAY_SIZE(d40_backup_regs_v3), | |
864 | save); | |
865 | } | |
866 | #else | |
867 | static void d40_save_restore_registers(struct d40_base *base, bool save) | |
868 | { | |
869 | } | |
870 | #endif | |
8d318a50 LW |
871 | |
872 | static int d40_channel_execute_command(struct d40_chan *d40c, | |
873 | enum d40_command command) | |
874 | { | |
767a9675 JA |
875 | u32 status; |
876 | int i; | |
8d318a50 LW |
877 | void __iomem *active_reg; |
878 | int ret = 0; | |
879 | unsigned long flags; | |
1d392a7b | 880 | u32 wmask; |
8d318a50 LW |
881 | |
882 | spin_lock_irqsave(&d40c->base->execmd_lock, flags); | |
883 | ||
884 | if (d40c->phy_chan->num % 2 == 0) | |
885 | active_reg = d40c->base->virtbase + D40_DREG_ACTIVE; | |
886 | else | |
887 | active_reg = d40c->base->virtbase + D40_DREG_ACTIVO; | |
888 | ||
889 | if (command == D40_DMA_SUSPEND_REQ) { | |
890 | status = (readl(active_reg) & | |
891 | D40_CHAN_POS_MASK(d40c->phy_chan->num)) >> | |
892 | D40_CHAN_POS(d40c->phy_chan->num); | |
893 | ||
894 | if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP) | |
895 | goto done; | |
896 | } | |
897 | ||
1d392a7b JA |
898 | wmask = 0xffffffff & ~(D40_CHAN_POS_MASK(d40c->phy_chan->num)); |
899 | writel(wmask | (command << D40_CHAN_POS(d40c->phy_chan->num)), | |
900 | active_reg); | |
8d318a50 LW |
901 | |
902 | if (command == D40_DMA_SUSPEND_REQ) { | |
903 | ||
904 | for (i = 0 ; i < D40_SUSPEND_MAX_IT; i++) { | |
905 | status = (readl(active_reg) & | |
906 | D40_CHAN_POS_MASK(d40c->phy_chan->num)) >> | |
907 | D40_CHAN_POS(d40c->phy_chan->num); | |
908 | ||
909 | cpu_relax(); | |
910 | /* | |
911 | * Reduce the number of bus accesses while | |
912 | * waiting for the DMA to suspend. | |
913 | */ | |
914 | udelay(3); | |
915 | ||
916 | if (status == D40_DMA_STOP || | |
917 | status == D40_DMA_SUSPENDED) | |
918 | break; | |
919 | } | |
920 | ||
921 | if (i == D40_SUSPEND_MAX_IT) { | |
6db5a8ba RV |
922 | chan_err(d40c, |
923 | "unable to suspend the chl %d (log: %d) status %x\n", | |
924 | d40c->phy_chan->num, d40c->log_num, | |
8d318a50 LW |
925 | status); |
926 | dump_stack(); | |
927 | ret = -EBUSY; | |
928 | } | |
929 | ||
930 | } | |
931 | done: | |
932 | spin_unlock_irqrestore(&d40c->base->execmd_lock, flags); | |
933 | return ret; | |
934 | } | |
935 | ||
936 | static void d40_term_all(struct d40_chan *d40c) | |
937 | { | |
938 | struct d40_desc *d40d; | |
7404368c | 939 | struct d40_desc *_d; |
8d318a50 LW |
940 | |
941 | /* Release active descriptors */ | |
942 | while ((d40d = d40_first_active_get(d40c))) { | |
943 | d40_desc_remove(d40d); | |
8d318a50 LW |
944 | d40_desc_free(d40c, d40d); |
945 | } | |
946 | ||
947 | /* Release queued descriptors waiting for transfer */ | |
948 | while ((d40d = d40_first_queued(d40c))) { | |
949 | d40_desc_remove(d40d); | |
8d318a50 LW |
950 | d40_desc_free(d40c, d40d); |
951 | } | |
952 | ||
a8f3067b PF |
953 | /* Release pending descriptors */ |
954 | while ((d40d = d40_first_pending(d40c))) { | |
955 | d40_desc_remove(d40d); | |
956 | d40_desc_free(d40c, d40d); | |
957 | } | |
8d318a50 | 958 | |
7404368c PF |
959 | /* Release client owned descriptors */ |
960 | if (!list_empty(&d40c->client)) | |
961 | list_for_each_entry_safe(d40d, _d, &d40c->client, node) { | |
962 | d40_desc_remove(d40d); | |
963 | d40_desc_free(d40c, d40d); | |
964 | } | |
965 | ||
82babbb3 PF |
966 | /* Release descriptors in prepare queue */ |
967 | if (!list_empty(&d40c->prepare_queue)) | |
968 | list_for_each_entry_safe(d40d, _d, | |
969 | &d40c->prepare_queue, node) { | |
970 | d40_desc_remove(d40d); | |
971 | d40_desc_free(d40c, d40d); | |
972 | } | |
7404368c | 973 | |
8d318a50 LW |
974 | d40c->pending_tx = 0; |
975 | d40c->busy = false; | |
976 | } | |
977 | ||
262d2915 RV |
978 | static void __d40_config_set_event(struct d40_chan *d40c, bool enable, |
979 | u32 event, int reg) | |
980 | { | |
8ca84687 | 981 | void __iomem *addr = chan_base(d40c) + reg; |
262d2915 RV |
982 | int tries; |
983 | ||
984 | if (!enable) { | |
985 | writel((D40_DEACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event)) | |
986 | | ~D40_EVENTLINE_MASK(event), addr); | |
987 | return; | |
988 | } | |
989 | ||
990 | /* | |
991 | * The hardware sometimes doesn't register the enable when src and dst | |
992 | * event lines are active on the same logical channel. Retry to ensure | |
993 | * it does. Usually only one retry is sufficient. | |
994 | */ | |
995 | tries = 100; | |
996 | while (--tries) { | |
997 | writel((D40_ACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event)) | |
998 | | ~D40_EVENTLINE_MASK(event), addr); | |
999 | ||
1000 | if (readl(addr) & D40_EVENTLINE_MASK(event)) | |
1001 | break; | |
1002 | } | |
1003 | ||
1004 | if (tries != 99) | |
1005 | dev_dbg(chan2dev(d40c), | |
1006 | "[%s] workaround enable S%cLNK (%d tries)\n", | |
1007 | __func__, reg == D40_CHAN_REG_SSLNK ? 'S' : 'D', | |
1008 | 100 - tries); | |
1009 | ||
1010 | WARN_ON(!tries); | |
1011 | } | |
1012 | ||
8d318a50 LW |
1013 | static void d40_config_set_event(struct d40_chan *d40c, bool do_enable) |
1014 | { | |
8d318a50 LW |
1015 | unsigned long flags; |
1016 | ||
8d318a50 LW |
1017 | spin_lock_irqsave(&d40c->phy_chan->lock, flags); |
1018 | ||
1019 | /* Enable event line connected to device (or memcpy) */ | |
1020 | if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) || | |
1021 | (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) { | |
1022 | u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type); | |
1023 | ||
262d2915 RV |
1024 | __d40_config_set_event(d40c, do_enable, event, |
1025 | D40_CHAN_REG_SSLNK); | |
8d318a50 | 1026 | } |
262d2915 | 1027 | |
8d318a50 LW |
1028 | if (d40c->dma_cfg.dir != STEDMA40_PERIPH_TO_MEM) { |
1029 | u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type); | |
1030 | ||
262d2915 RV |
1031 | __d40_config_set_event(d40c, do_enable, event, |
1032 | D40_CHAN_REG_SDLNK); | |
8d318a50 LW |
1033 | } |
1034 | ||
1035 | spin_unlock_irqrestore(&d40c->phy_chan->lock, flags); | |
1036 | } | |
1037 | ||
a5ebca47 | 1038 | static u32 d40_chan_has_events(struct d40_chan *d40c) |
8d318a50 | 1039 | { |
8ca84687 | 1040 | void __iomem *chanbase = chan_base(d40c); |
be8cb7df | 1041 | u32 val; |
8d318a50 | 1042 | |
8ca84687 RV |
1043 | val = readl(chanbase + D40_CHAN_REG_SSLNK); |
1044 | val |= readl(chanbase + D40_CHAN_REG_SDLNK); | |
be8cb7df | 1045 | |
a5ebca47 | 1046 | return val; |
8d318a50 LW |
1047 | } |
1048 | ||
20a5b6d0 RV |
1049 | static u32 d40_get_prmo(struct d40_chan *d40c) |
1050 | { | |
1051 | static const unsigned int phy_map[] = { | |
1052 | [STEDMA40_PCHAN_BASIC_MODE] | |
1053 | = D40_DREG_PRMO_PCHAN_BASIC, | |
1054 | [STEDMA40_PCHAN_MODULO_MODE] | |
1055 | = D40_DREG_PRMO_PCHAN_MODULO, | |
1056 | [STEDMA40_PCHAN_DOUBLE_DST_MODE] | |
1057 | = D40_DREG_PRMO_PCHAN_DOUBLE_DST, | |
1058 | }; | |
1059 | static const unsigned int log_map[] = { | |
1060 | [STEDMA40_LCHAN_SRC_PHY_DST_LOG] | |
1061 | = D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG, | |
1062 | [STEDMA40_LCHAN_SRC_LOG_DST_PHY] | |
1063 | = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY, | |
1064 | [STEDMA40_LCHAN_SRC_LOG_DST_LOG] | |
1065 | = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG, | |
1066 | }; | |
1067 | ||
724a8577 | 1068 | if (chan_is_physical(d40c)) |
20a5b6d0 RV |
1069 | return phy_map[d40c->dma_cfg.mode_opt]; |
1070 | else | |
1071 | return log_map[d40c->dma_cfg.mode_opt]; | |
1072 | } | |
1073 | ||
b55912c6 | 1074 | static void d40_config_write(struct d40_chan *d40c) |
8d318a50 LW |
1075 | { |
1076 | u32 addr_base; | |
1077 | u32 var; | |
8d318a50 LW |
1078 | |
1079 | /* Odd addresses are even addresses + 4 */ | |
1080 | addr_base = (d40c->phy_chan->num % 2) * 4; | |
1081 | /* Setup channel mode to logical or physical */ | |
724a8577 | 1082 | var = ((u32)(chan_is_logical(d40c)) + 1) << |
8d318a50 LW |
1083 | D40_CHAN_POS(d40c->phy_chan->num); |
1084 | writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base); | |
1085 | ||
1086 | /* Setup operational mode option register */ | |
20a5b6d0 | 1087 | var = d40_get_prmo(d40c) << D40_CHAN_POS(d40c->phy_chan->num); |
8d318a50 LW |
1088 | |
1089 | writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base); | |
1090 | ||
724a8577 | 1091 | if (chan_is_logical(d40c)) { |
8ca84687 RV |
1092 | int lidx = (d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS) |
1093 | & D40_SREG_ELEM_LOG_LIDX_MASK; | |
1094 | void __iomem *chanbase = chan_base(d40c); | |
1095 | ||
8d318a50 | 1096 | /* Set default config for CFG reg */ |
8ca84687 RV |
1097 | writel(d40c->src_def_cfg, chanbase + D40_CHAN_REG_SSCFG); |
1098 | writel(d40c->dst_def_cfg, chanbase + D40_CHAN_REG_SDCFG); | |
8d318a50 | 1099 | |
b55912c6 | 1100 | /* Set LIDX for lcla */ |
8ca84687 RV |
1101 | writel(lidx, chanbase + D40_CHAN_REG_SSELT); |
1102 | writel(lidx, chanbase + D40_CHAN_REG_SDELT); | |
e9f3a49c RV |
1103 | |
1104 | /* Clear LNK which will be used by d40_chan_has_events() */ | |
1105 | writel(0, chanbase + D40_CHAN_REG_SSLNK); | |
1106 | writel(0, chanbase + D40_CHAN_REG_SDLNK); | |
8d318a50 | 1107 | } |
8d318a50 LW |
1108 | } |
1109 | ||
aa182ae2 JA |
1110 | static u32 d40_residue(struct d40_chan *d40c) |
1111 | { | |
1112 | u32 num_elt; | |
1113 | ||
724a8577 | 1114 | if (chan_is_logical(d40c)) |
aa182ae2 JA |
1115 | num_elt = (readl(&d40c->lcpa->lcsp2) & D40_MEM_LCSP2_ECNT_MASK) |
1116 | >> D40_MEM_LCSP2_ECNT_POS; | |
8ca84687 RV |
1117 | else { |
1118 | u32 val = readl(chan_base(d40c) + D40_CHAN_REG_SDELT); | |
1119 | num_elt = (val & D40_SREG_ELEM_PHY_ECNT_MASK) | |
1120 | >> D40_SREG_ELEM_PHY_ECNT_POS; | |
1121 | } | |
1122 | ||
aa182ae2 JA |
1123 | return num_elt * (1 << d40c->dma_cfg.dst_info.data_width); |
1124 | } | |
1125 | ||
1126 | static bool d40_tx_is_linked(struct d40_chan *d40c) | |
1127 | { | |
1128 | bool is_link; | |
1129 | ||
724a8577 | 1130 | if (chan_is_logical(d40c)) |
aa182ae2 JA |
1131 | is_link = readl(&d40c->lcpa->lcsp3) & D40_MEM_LCSP3_DLOS_MASK; |
1132 | else | |
8ca84687 RV |
1133 | is_link = readl(chan_base(d40c) + D40_CHAN_REG_SDLNK) |
1134 | & D40_SREG_LNK_PHYS_LNK_MASK; | |
1135 | ||
aa182ae2 JA |
1136 | return is_link; |
1137 | } | |
1138 | ||
86eb5fb6 | 1139 | static int d40_pause(struct d40_chan *d40c) |
aa182ae2 | 1140 | { |
aa182ae2 JA |
1141 | int res = 0; |
1142 | unsigned long flags; | |
1143 | ||
3ac012af JA |
1144 | if (!d40c->busy) |
1145 | return 0; | |
1146 | ||
7fb3e75e | 1147 | pm_runtime_get_sync(d40c->base->dev); |
aa182ae2 JA |
1148 | spin_lock_irqsave(&d40c->lock, flags); |
1149 | ||
1150 | res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ); | |
1151 | if (res == 0) { | |
724a8577 | 1152 | if (chan_is_logical(d40c)) { |
aa182ae2 JA |
1153 | d40_config_set_event(d40c, false); |
1154 | /* Resume the other logical channels if any */ | |
1155 | if (d40_chan_has_events(d40c)) | |
1156 | res = d40_channel_execute_command(d40c, | |
1157 | D40_DMA_RUN); | |
1158 | } | |
1159 | } | |
7fb3e75e N |
1160 | pm_runtime_mark_last_busy(d40c->base->dev); |
1161 | pm_runtime_put_autosuspend(d40c->base->dev); | |
aa182ae2 JA |
1162 | spin_unlock_irqrestore(&d40c->lock, flags); |
1163 | return res; | |
1164 | } | |
1165 | ||
86eb5fb6 | 1166 | static int d40_resume(struct d40_chan *d40c) |
aa182ae2 | 1167 | { |
aa182ae2 JA |
1168 | int res = 0; |
1169 | unsigned long flags; | |
1170 | ||
3ac012af JA |
1171 | if (!d40c->busy) |
1172 | return 0; | |
1173 | ||
aa182ae2 | 1174 | spin_lock_irqsave(&d40c->lock, flags); |
7fb3e75e | 1175 | pm_runtime_get_sync(d40c->base->dev); |
aa182ae2 | 1176 | if (d40c->base->rev == 0) |
724a8577 | 1177 | if (chan_is_logical(d40c)) { |
aa182ae2 JA |
1178 | res = d40_channel_execute_command(d40c, |
1179 | D40_DMA_SUSPEND_REQ); | |
1180 | goto no_suspend; | |
1181 | } | |
1182 | ||
1183 | /* If bytes left to transfer or linked tx resume job */ | |
1184 | if (d40_residue(d40c) || d40_tx_is_linked(d40c)) { | |
1185 | ||
724a8577 | 1186 | if (chan_is_logical(d40c)) |
aa182ae2 JA |
1187 | d40_config_set_event(d40c, true); |
1188 | ||
1189 | res = d40_channel_execute_command(d40c, D40_DMA_RUN); | |
1190 | } | |
1191 | ||
1192 | no_suspend: | |
7fb3e75e N |
1193 | pm_runtime_mark_last_busy(d40c->base->dev); |
1194 | pm_runtime_put_autosuspend(d40c->base->dev); | |
aa182ae2 JA |
1195 | spin_unlock_irqrestore(&d40c->lock, flags); |
1196 | return res; | |
1197 | } | |
1198 | ||
86eb5fb6 RV |
1199 | static int d40_terminate_all(struct d40_chan *chan) |
1200 | { | |
1201 | unsigned long flags; | |
1202 | int ret = 0; | |
1203 | ||
1204 | ret = d40_pause(chan); | |
1205 | if (!ret && chan_is_physical(chan)) | |
1206 | ret = d40_channel_execute_command(chan, D40_DMA_STOP); | |
1207 | ||
1208 | spin_lock_irqsave(&chan->lock, flags); | |
1209 | d40_term_all(chan); | |
1210 | spin_unlock_irqrestore(&chan->lock, flags); | |
1211 | ||
1212 | return ret; | |
1213 | } | |
1214 | ||
8d318a50 LW |
1215 | static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx) |
1216 | { | |
1217 | struct d40_chan *d40c = container_of(tx->chan, | |
1218 | struct d40_chan, | |
1219 | chan); | |
1220 | struct d40_desc *d40d = container_of(tx, struct d40_desc, txd); | |
1221 | unsigned long flags; | |
1222 | ||
1223 | spin_lock_irqsave(&d40c->lock, flags); | |
1224 | ||
aa182ae2 JA |
1225 | d40c->chan.cookie++; |
1226 | ||
1227 | if (d40c->chan.cookie < 0) | |
1228 | d40c->chan.cookie = 1; | |
1229 | ||
1230 | d40d->txd.cookie = d40c->chan.cookie; | |
1231 | ||
8d318a50 LW |
1232 | d40_desc_queue(d40c, d40d); |
1233 | ||
1234 | spin_unlock_irqrestore(&d40c->lock, flags); | |
1235 | ||
1236 | return tx->cookie; | |
1237 | } | |
1238 | ||
1239 | static int d40_start(struct d40_chan *d40c) | |
1240 | { | |
f4185592 LW |
1241 | if (d40c->base->rev == 0) { |
1242 | int err; | |
1243 | ||
724a8577 | 1244 | if (chan_is_logical(d40c)) { |
f4185592 LW |
1245 | err = d40_channel_execute_command(d40c, |
1246 | D40_DMA_SUSPEND_REQ); | |
1247 | if (err) | |
1248 | return err; | |
1249 | } | |
1250 | } | |
1251 | ||
724a8577 | 1252 | if (chan_is_logical(d40c)) |
8d318a50 | 1253 | d40_config_set_event(d40c, true); |
8d318a50 | 1254 | |
0c32269d | 1255 | return d40_channel_execute_command(d40c, D40_DMA_RUN); |
8d318a50 LW |
1256 | } |
1257 | ||
1258 | static struct d40_desc *d40_queue_start(struct d40_chan *d40c) | |
1259 | { | |
1260 | struct d40_desc *d40d; | |
1261 | int err; | |
1262 | ||
1263 | /* Start queued jobs, if any */ | |
1264 | d40d = d40_first_queued(d40c); | |
1265 | ||
1266 | if (d40d != NULL) { | |
7fb3e75e N |
1267 | if (!d40c->busy) |
1268 | d40c->busy = true; | |
1269 | ||
1270 | pm_runtime_get_sync(d40c->base->dev); | |
8d318a50 LW |
1271 | |
1272 | /* Remove from queue */ | |
1273 | d40_desc_remove(d40d); | |
1274 | ||
1275 | /* Add to active queue */ | |
1276 | d40_desc_submit(d40c, d40d); | |
1277 | ||
7d83a854 RV |
1278 | /* Initiate DMA job */ |
1279 | d40_desc_load(d40c, d40d); | |
8d318a50 | 1280 | |
7d83a854 RV |
1281 | /* Start dma job */ |
1282 | err = d40_start(d40c); | |
8d318a50 | 1283 | |
7d83a854 RV |
1284 | if (err) |
1285 | return NULL; | |
8d318a50 LW |
1286 | } |
1287 | ||
1288 | return d40d; | |
1289 | } | |
1290 | ||
1291 | /* called from interrupt context */ | |
1292 | static void dma_tc_handle(struct d40_chan *d40c) | |
1293 | { | |
1294 | struct d40_desc *d40d; | |
1295 | ||
8d318a50 LW |
1296 | /* Get first active entry from list */ |
1297 | d40d = d40_first_active_get(d40c); | |
1298 | ||
1299 | if (d40d == NULL) | |
1300 | return; | |
1301 | ||
0c842b55 RV |
1302 | if (d40d->cyclic) { |
1303 | /* | |
1304 | * If this was a paritially loaded list, we need to reloaded | |
1305 | * it, and only when the list is completed. We need to check | |
1306 | * for done because the interrupt will hit for every link, and | |
1307 | * not just the last one. | |
1308 | */ | |
1309 | if (d40d->lli_current < d40d->lli_len | |
1310 | && !d40_tx_is_linked(d40c) | |
1311 | && !d40_residue(d40c)) { | |
1312 | d40_lcla_free_all(d40c, d40d); | |
1313 | d40_desc_load(d40c, d40d); | |
1314 | (void) d40_start(d40c); | |
8d318a50 | 1315 | |
0c842b55 RV |
1316 | if (d40d->lli_current == d40d->lli_len) |
1317 | d40d->lli_current = 0; | |
1318 | } | |
1319 | } else { | |
1320 | d40_lcla_free_all(d40c, d40d); | |
8d318a50 | 1321 | |
0c842b55 RV |
1322 | if (d40d->lli_current < d40d->lli_len) { |
1323 | d40_desc_load(d40c, d40d); | |
1324 | /* Start dma job */ | |
1325 | (void) d40_start(d40c); | |
1326 | return; | |
1327 | } | |
1328 | ||
1329 | if (d40_queue_start(d40c) == NULL) | |
1330 | d40c->busy = false; | |
7fb3e75e N |
1331 | pm_runtime_mark_last_busy(d40c->base->dev); |
1332 | pm_runtime_put_autosuspend(d40c->base->dev); | |
0c842b55 | 1333 | } |
8d318a50 LW |
1334 | |
1335 | d40c->pending_tx++; | |
1336 | tasklet_schedule(&d40c->tasklet); | |
1337 | ||
1338 | } | |
1339 | ||
1340 | static void dma_tasklet(unsigned long data) | |
1341 | { | |
1342 | struct d40_chan *d40c = (struct d40_chan *) data; | |
767a9675 | 1343 | struct d40_desc *d40d; |
8d318a50 LW |
1344 | unsigned long flags; |
1345 | dma_async_tx_callback callback; | |
1346 | void *callback_param; | |
1347 | ||
1348 | spin_lock_irqsave(&d40c->lock, flags); | |
1349 | ||
1350 | /* Get first active entry from list */ | |
767a9675 | 1351 | d40d = d40_first_active_get(d40c); |
767a9675 | 1352 | if (d40d == NULL) |
8d318a50 LW |
1353 | goto err; |
1354 | ||
0c842b55 | 1355 | if (!d40d->cyclic) |
4d4e58de | 1356 | d40c->chan.completed_cookie = d40d->txd.cookie; |
8d318a50 LW |
1357 | |
1358 | /* | |
1359 | * If terminating a channel pending_tx is set to zero. | |
1360 | * This prevents any finished active jobs to return to the client. | |
1361 | */ | |
1362 | if (d40c->pending_tx == 0) { | |
1363 | spin_unlock_irqrestore(&d40c->lock, flags); | |
1364 | return; | |
1365 | } | |
1366 | ||
1367 | /* Callback to client */ | |
767a9675 JA |
1368 | callback = d40d->txd.callback; |
1369 | callback_param = d40d->txd.callback_param; | |
1370 | ||
0c842b55 RV |
1371 | if (!d40d->cyclic) { |
1372 | if (async_tx_test_ack(&d40d->txd)) { | |
767a9675 | 1373 | d40_desc_remove(d40d); |
0c842b55 RV |
1374 | d40_desc_free(d40c, d40d); |
1375 | } else { | |
1376 | if (!d40d->is_in_client_list) { | |
1377 | d40_desc_remove(d40d); | |
1378 | d40_lcla_free_all(d40c, d40d); | |
1379 | list_add_tail(&d40d->node, &d40c->client); | |
1380 | d40d->is_in_client_list = true; | |
1381 | } | |
8d318a50 LW |
1382 | } |
1383 | } | |
1384 | ||
1385 | d40c->pending_tx--; | |
1386 | ||
1387 | if (d40c->pending_tx) | |
1388 | tasklet_schedule(&d40c->tasklet); | |
1389 | ||
1390 | spin_unlock_irqrestore(&d40c->lock, flags); | |
1391 | ||
767a9675 | 1392 | if (callback && (d40d->txd.flags & DMA_PREP_INTERRUPT)) |
8d318a50 LW |
1393 | callback(callback_param); |
1394 | ||
1395 | return; | |
1396 | ||
1397 | err: | |
25985edc | 1398 | /* Rescue manoeuvre if receiving double interrupts */ |
8d318a50 LW |
1399 | if (d40c->pending_tx > 0) |
1400 | d40c->pending_tx--; | |
1401 | spin_unlock_irqrestore(&d40c->lock, flags); | |
1402 | } | |
1403 | ||
1404 | static irqreturn_t d40_handle_interrupt(int irq, void *data) | |
1405 | { | |
1406 | static const struct d40_interrupt_lookup il[] = { | |
1407 | {D40_DREG_LCTIS0, D40_DREG_LCICR0, false, 0}, | |
1408 | {D40_DREG_LCTIS1, D40_DREG_LCICR1, false, 32}, | |
1409 | {D40_DREG_LCTIS2, D40_DREG_LCICR2, false, 64}, | |
1410 | {D40_DREG_LCTIS3, D40_DREG_LCICR3, false, 96}, | |
1411 | {D40_DREG_LCEIS0, D40_DREG_LCICR0, true, 0}, | |
1412 | {D40_DREG_LCEIS1, D40_DREG_LCICR1, true, 32}, | |
1413 | {D40_DREG_LCEIS2, D40_DREG_LCICR2, true, 64}, | |
1414 | {D40_DREG_LCEIS3, D40_DREG_LCICR3, true, 96}, | |
1415 | {D40_DREG_PCTIS, D40_DREG_PCICR, false, D40_PHY_CHAN}, | |
1416 | {D40_DREG_PCEIS, D40_DREG_PCICR, true, D40_PHY_CHAN}, | |
1417 | }; | |
1418 | ||
1419 | int i; | |
1420 | u32 regs[ARRAY_SIZE(il)]; | |
8d318a50 LW |
1421 | u32 idx; |
1422 | u32 row; | |
1423 | long chan = -1; | |
1424 | struct d40_chan *d40c; | |
1425 | unsigned long flags; | |
1426 | struct d40_base *base = data; | |
1427 | ||
1428 | spin_lock_irqsave(&base->interrupt_lock, flags); | |
1429 | ||
1430 | /* Read interrupt status of both logical and physical channels */ | |
1431 | for (i = 0; i < ARRAY_SIZE(il); i++) | |
1432 | regs[i] = readl(base->virtbase + il[i].src); | |
1433 | ||
1434 | for (;;) { | |
1435 | ||
1436 | chan = find_next_bit((unsigned long *)regs, | |
1437 | BITS_PER_LONG * ARRAY_SIZE(il), chan + 1); | |
1438 | ||
1439 | /* No more set bits found? */ | |
1440 | if (chan == BITS_PER_LONG * ARRAY_SIZE(il)) | |
1441 | break; | |
1442 | ||
1443 | row = chan / BITS_PER_LONG; | |
1444 | idx = chan & (BITS_PER_LONG - 1); | |
1445 | ||
1446 | /* ACK interrupt */ | |
1b00348d | 1447 | writel(1 << idx, base->virtbase + il[row].clr); |
8d318a50 LW |
1448 | |
1449 | if (il[row].offset == D40_PHY_CHAN) | |
1450 | d40c = base->lookup_phy_chans[idx]; | |
1451 | else | |
1452 | d40c = base->lookup_log_chans[il[row].offset + idx]; | |
1453 | spin_lock(&d40c->lock); | |
1454 | ||
1455 | if (!il[row].is_error) | |
1456 | dma_tc_handle(d40c); | |
1457 | else | |
6db5a8ba RV |
1458 | d40_err(base->dev, "IRQ chan: %ld offset %d idx %d\n", |
1459 | chan, il[row].offset, idx); | |
8d318a50 LW |
1460 | |
1461 | spin_unlock(&d40c->lock); | |
1462 | } | |
1463 | ||
1464 | spin_unlock_irqrestore(&base->interrupt_lock, flags); | |
1465 | ||
1466 | return IRQ_HANDLED; | |
1467 | } | |
1468 | ||
8d318a50 LW |
1469 | static int d40_validate_conf(struct d40_chan *d40c, |
1470 | struct stedma40_chan_cfg *conf) | |
1471 | { | |
1472 | int res = 0; | |
1473 | u32 dst_event_group = D40_TYPE_TO_GROUP(conf->dst_dev_type); | |
1474 | u32 src_event_group = D40_TYPE_TO_GROUP(conf->src_dev_type); | |
38bdbf02 | 1475 | bool is_log = conf->mode == STEDMA40_MODE_LOGICAL; |
8d318a50 | 1476 | |
0747c7ba | 1477 | if (!conf->dir) { |
6db5a8ba | 1478 | chan_err(d40c, "Invalid direction.\n"); |
0747c7ba LW |
1479 | res = -EINVAL; |
1480 | } | |
1481 | ||
1482 | if (conf->dst_dev_type != STEDMA40_DEV_DST_MEMORY && | |
1483 | d40c->base->plat_data->dev_tx[conf->dst_dev_type] == 0 && | |
1484 | d40c->runtime_addr == 0) { | |
1485 | ||
6db5a8ba RV |
1486 | chan_err(d40c, "Invalid TX channel address (%d)\n", |
1487 | conf->dst_dev_type); | |
0747c7ba LW |
1488 | res = -EINVAL; |
1489 | } | |
1490 | ||
1491 | if (conf->src_dev_type != STEDMA40_DEV_SRC_MEMORY && | |
1492 | d40c->base->plat_data->dev_rx[conf->src_dev_type] == 0 && | |
1493 | d40c->runtime_addr == 0) { | |
6db5a8ba RV |
1494 | chan_err(d40c, "Invalid RX channel address (%d)\n", |
1495 | conf->src_dev_type); | |
0747c7ba LW |
1496 | res = -EINVAL; |
1497 | } | |
1498 | ||
1499 | if (conf->dir == STEDMA40_MEM_TO_PERIPH && | |
8d318a50 | 1500 | dst_event_group == STEDMA40_DEV_DST_MEMORY) { |
6db5a8ba | 1501 | chan_err(d40c, "Invalid dst\n"); |
8d318a50 LW |
1502 | res = -EINVAL; |
1503 | } | |
1504 | ||
0747c7ba | 1505 | if (conf->dir == STEDMA40_PERIPH_TO_MEM && |
8d318a50 | 1506 | src_event_group == STEDMA40_DEV_SRC_MEMORY) { |
6db5a8ba | 1507 | chan_err(d40c, "Invalid src\n"); |
8d318a50 LW |
1508 | res = -EINVAL; |
1509 | } | |
1510 | ||
1511 | if (src_event_group == STEDMA40_DEV_SRC_MEMORY && | |
1512 | dst_event_group == STEDMA40_DEV_DST_MEMORY && is_log) { | |
6db5a8ba | 1513 | chan_err(d40c, "No event line\n"); |
8d318a50 LW |
1514 | res = -EINVAL; |
1515 | } | |
1516 | ||
1517 | if (conf->dir == STEDMA40_PERIPH_TO_PERIPH && | |
1518 | (src_event_group != dst_event_group)) { | |
6db5a8ba | 1519 | chan_err(d40c, "Invalid event group\n"); |
8d318a50 LW |
1520 | res = -EINVAL; |
1521 | } | |
1522 | ||
1523 | if (conf->dir == STEDMA40_PERIPH_TO_PERIPH) { | |
1524 | /* | |
1525 | * DMAC HW supports it. Will be added to this driver, | |
1526 | * in case any dma client requires it. | |
1527 | */ | |
6db5a8ba | 1528 | chan_err(d40c, "periph to periph not supported\n"); |
8d318a50 LW |
1529 | res = -EINVAL; |
1530 | } | |
1531 | ||
d49278e3 PF |
1532 | if (d40_psize_2_burst_size(is_log, conf->src_info.psize) * |
1533 | (1 << conf->src_info.data_width) != | |
1534 | d40_psize_2_burst_size(is_log, conf->dst_info.psize) * | |
1535 | (1 << conf->dst_info.data_width)) { | |
1536 | /* | |
1537 | * The DMAC hardware only supports | |
1538 | * src (burst x width) == dst (burst x width) | |
1539 | */ | |
1540 | ||
6db5a8ba | 1541 | chan_err(d40c, "src (burst x width) != dst (burst x width)\n"); |
d49278e3 PF |
1542 | res = -EINVAL; |
1543 | } | |
1544 | ||
8d318a50 LW |
1545 | return res; |
1546 | } | |
1547 | ||
5cd326fd N |
1548 | static bool d40_alloc_mask_set(struct d40_phy_res *phy, |
1549 | bool is_src, int log_event_line, bool is_log, | |
1550 | bool *first_user) | |
8d318a50 LW |
1551 | { |
1552 | unsigned long flags; | |
1553 | spin_lock_irqsave(&phy->lock, flags); | |
5cd326fd N |
1554 | |
1555 | *first_user = ((phy->allocated_src | phy->allocated_dst) | |
1556 | == D40_ALLOC_FREE); | |
1557 | ||
4aed79b2 | 1558 | if (!is_log) { |
8d318a50 LW |
1559 | /* Physical interrupts are masked per physical full channel */ |
1560 | if (phy->allocated_src == D40_ALLOC_FREE && | |
1561 | phy->allocated_dst == D40_ALLOC_FREE) { | |
1562 | phy->allocated_dst = D40_ALLOC_PHY; | |
1563 | phy->allocated_src = D40_ALLOC_PHY; | |
1564 | goto found; | |
1565 | } else | |
1566 | goto not_found; | |
1567 | } | |
1568 | ||
1569 | /* Logical channel */ | |
1570 | if (is_src) { | |
1571 | if (phy->allocated_src == D40_ALLOC_PHY) | |
1572 | goto not_found; | |
1573 | ||
1574 | if (phy->allocated_src == D40_ALLOC_FREE) | |
1575 | phy->allocated_src = D40_ALLOC_LOG_FREE; | |
1576 | ||
1577 | if (!(phy->allocated_src & (1 << log_event_line))) { | |
1578 | phy->allocated_src |= 1 << log_event_line; | |
1579 | goto found; | |
1580 | } else | |
1581 | goto not_found; | |
1582 | } else { | |
1583 | if (phy->allocated_dst == D40_ALLOC_PHY) | |
1584 | goto not_found; | |
1585 | ||
1586 | if (phy->allocated_dst == D40_ALLOC_FREE) | |
1587 | phy->allocated_dst = D40_ALLOC_LOG_FREE; | |
1588 | ||
1589 | if (!(phy->allocated_dst & (1 << log_event_line))) { | |
1590 | phy->allocated_dst |= 1 << log_event_line; | |
1591 | goto found; | |
1592 | } else | |
1593 | goto not_found; | |
1594 | } | |
1595 | ||
1596 | not_found: | |
1597 | spin_unlock_irqrestore(&phy->lock, flags); | |
1598 | return false; | |
1599 | found: | |
1600 | spin_unlock_irqrestore(&phy->lock, flags); | |
1601 | return true; | |
1602 | } | |
1603 | ||
1604 | static bool d40_alloc_mask_free(struct d40_phy_res *phy, bool is_src, | |
1605 | int log_event_line) | |
1606 | { | |
1607 | unsigned long flags; | |
1608 | bool is_free = false; | |
1609 | ||
1610 | spin_lock_irqsave(&phy->lock, flags); | |
1611 | if (!log_event_line) { | |
8d318a50 LW |
1612 | phy->allocated_dst = D40_ALLOC_FREE; |
1613 | phy->allocated_src = D40_ALLOC_FREE; | |
1614 | is_free = true; | |
1615 | goto out; | |
1616 | } | |
1617 | ||
1618 | /* Logical channel */ | |
1619 | if (is_src) { | |
1620 | phy->allocated_src &= ~(1 << log_event_line); | |
1621 | if (phy->allocated_src == D40_ALLOC_LOG_FREE) | |
1622 | phy->allocated_src = D40_ALLOC_FREE; | |
1623 | } else { | |
1624 | phy->allocated_dst &= ~(1 << log_event_line); | |
1625 | if (phy->allocated_dst == D40_ALLOC_LOG_FREE) | |
1626 | phy->allocated_dst = D40_ALLOC_FREE; | |
1627 | } | |
1628 | ||
1629 | is_free = ((phy->allocated_src | phy->allocated_dst) == | |
1630 | D40_ALLOC_FREE); | |
1631 | ||
1632 | out: | |
1633 | spin_unlock_irqrestore(&phy->lock, flags); | |
1634 | ||
1635 | return is_free; | |
1636 | } | |
1637 | ||
5cd326fd | 1638 | static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user) |
8d318a50 LW |
1639 | { |
1640 | int dev_type; | |
1641 | int event_group; | |
1642 | int event_line; | |
1643 | struct d40_phy_res *phys; | |
1644 | int i; | |
1645 | int j; | |
1646 | int log_num; | |
1647 | bool is_src; | |
38bdbf02 | 1648 | bool is_log = d40c->dma_cfg.mode == STEDMA40_MODE_LOGICAL; |
8d318a50 LW |
1649 | |
1650 | phys = d40c->base->phy_res; | |
1651 | ||
1652 | if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) { | |
1653 | dev_type = d40c->dma_cfg.src_dev_type; | |
1654 | log_num = 2 * dev_type; | |
1655 | is_src = true; | |
1656 | } else if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH || | |
1657 | d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) { | |
1658 | /* dst event lines are used for logical memcpy */ | |
1659 | dev_type = d40c->dma_cfg.dst_dev_type; | |
1660 | log_num = 2 * dev_type + 1; | |
1661 | is_src = false; | |
1662 | } else | |
1663 | return -EINVAL; | |
1664 | ||
1665 | event_group = D40_TYPE_TO_GROUP(dev_type); | |
1666 | event_line = D40_TYPE_TO_EVENT(dev_type); | |
1667 | ||
1668 | if (!is_log) { | |
1669 | if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) { | |
1670 | /* Find physical half channel */ | |
1671 | for (i = 0; i < d40c->base->num_phy_chans; i++) { | |
1672 | ||
4aed79b2 | 1673 | if (d40_alloc_mask_set(&phys[i], is_src, |
5cd326fd N |
1674 | 0, is_log, |
1675 | first_phy_user)) | |
8d318a50 LW |
1676 | goto found_phy; |
1677 | } | |
1678 | } else | |
1679 | for (j = 0; j < d40c->base->num_phy_chans; j += 8) { | |
1680 | int phy_num = j + event_group * 2; | |
1681 | for (i = phy_num; i < phy_num + 2; i++) { | |
508849ad LW |
1682 | if (d40_alloc_mask_set(&phys[i], |
1683 | is_src, | |
1684 | 0, | |
5cd326fd N |
1685 | is_log, |
1686 | first_phy_user)) | |
8d318a50 LW |
1687 | goto found_phy; |
1688 | } | |
1689 | } | |
1690 | return -EINVAL; | |
1691 | found_phy: | |
1692 | d40c->phy_chan = &phys[i]; | |
1693 | d40c->log_num = D40_PHY_CHAN; | |
1694 | goto out; | |
1695 | } | |
1696 | if (dev_type == -1) | |
1697 | return -EINVAL; | |
1698 | ||
1699 | /* Find logical channel */ | |
1700 | for (j = 0; j < d40c->base->num_phy_chans; j += 8) { | |
1701 | int phy_num = j + event_group * 2; | |
5cd326fd N |
1702 | |
1703 | if (d40c->dma_cfg.use_fixed_channel) { | |
1704 | i = d40c->dma_cfg.phy_channel; | |
1705 | ||
1706 | if ((i != phy_num) && (i != phy_num + 1)) { | |
1707 | dev_err(chan2dev(d40c), | |
1708 | "invalid fixed phy channel %d\n", i); | |
1709 | return -EINVAL; | |
1710 | } | |
1711 | ||
1712 | if (d40_alloc_mask_set(&phys[i], is_src, event_line, | |
1713 | is_log, first_phy_user)) | |
1714 | goto found_log; | |
1715 | ||
1716 | dev_err(chan2dev(d40c), | |
1717 | "could not allocate fixed phy channel %d\n", i); | |
1718 | return -EINVAL; | |
1719 | } | |
1720 | ||
8d318a50 LW |
1721 | /* |
1722 | * Spread logical channels across all available physical rather | |
1723 | * than pack every logical channel at the first available phy | |
1724 | * channels. | |
1725 | */ | |
1726 | if (is_src) { | |
1727 | for (i = phy_num; i < phy_num + 2; i++) { | |
1728 | if (d40_alloc_mask_set(&phys[i], is_src, | |
5cd326fd N |
1729 | event_line, is_log, |
1730 | first_phy_user)) | |
8d318a50 LW |
1731 | goto found_log; |
1732 | } | |
1733 | } else { | |
1734 | for (i = phy_num + 1; i >= phy_num; i--) { | |
1735 | if (d40_alloc_mask_set(&phys[i], is_src, | |
5cd326fd N |
1736 | event_line, is_log, |
1737 | first_phy_user)) | |
8d318a50 LW |
1738 | goto found_log; |
1739 | } | |
1740 | } | |
1741 | } | |
1742 | return -EINVAL; | |
1743 | ||
1744 | found_log: | |
1745 | d40c->phy_chan = &phys[i]; | |
1746 | d40c->log_num = log_num; | |
1747 | out: | |
1748 | ||
1749 | if (is_log) | |
1750 | d40c->base->lookup_log_chans[d40c->log_num] = d40c; | |
1751 | else | |
1752 | d40c->base->lookup_phy_chans[d40c->phy_chan->num] = d40c; | |
1753 | ||
1754 | return 0; | |
1755 | ||
1756 | } | |
1757 | ||
8d318a50 LW |
1758 | static int d40_config_memcpy(struct d40_chan *d40c) |
1759 | { | |
1760 | dma_cap_mask_t cap = d40c->chan.device->cap_mask; | |
1761 | ||
1762 | if (dma_has_cap(DMA_MEMCPY, cap) && !dma_has_cap(DMA_SLAVE, cap)) { | |
1763 | d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_log; | |
1764 | d40c->dma_cfg.src_dev_type = STEDMA40_DEV_SRC_MEMORY; | |
1765 | d40c->dma_cfg.dst_dev_type = d40c->base->plat_data-> | |
1766 | memcpy[d40c->chan.chan_id]; | |
1767 | ||
1768 | } else if (dma_has_cap(DMA_MEMCPY, cap) && | |
1769 | dma_has_cap(DMA_SLAVE, cap)) { | |
1770 | d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_phy; | |
1771 | } else { | |
6db5a8ba | 1772 | chan_err(d40c, "No memcpy\n"); |
8d318a50 LW |
1773 | return -EINVAL; |
1774 | } | |
1775 | ||
1776 | return 0; | |
1777 | } | |
1778 | ||
1779 | ||
1780 | static int d40_free_dma(struct d40_chan *d40c) | |
1781 | { | |
1782 | ||
1783 | int res = 0; | |
d181b3a8 | 1784 | u32 event; |
8d318a50 LW |
1785 | struct d40_phy_res *phy = d40c->phy_chan; |
1786 | bool is_src; | |
1787 | ||
1788 | /* Terminate all queued and active transfers */ | |
1789 | d40_term_all(d40c); | |
1790 | ||
1791 | if (phy == NULL) { | |
6db5a8ba | 1792 | chan_err(d40c, "phy == null\n"); |
8d318a50 LW |
1793 | return -EINVAL; |
1794 | } | |
1795 | ||
1796 | if (phy->allocated_src == D40_ALLOC_FREE && | |
1797 | phy->allocated_dst == D40_ALLOC_FREE) { | |
6db5a8ba | 1798 | chan_err(d40c, "channel already free\n"); |
8d318a50 LW |
1799 | return -EINVAL; |
1800 | } | |
1801 | ||
8d318a50 LW |
1802 | if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH || |
1803 | d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) { | |
1804 | event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type); | |
8d318a50 LW |
1805 | is_src = false; |
1806 | } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) { | |
1807 | event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type); | |
8d318a50 LW |
1808 | is_src = true; |
1809 | } else { | |
6db5a8ba | 1810 | chan_err(d40c, "Unknown direction\n"); |
8d318a50 LW |
1811 | return -EINVAL; |
1812 | } | |
1813 | ||
7fb3e75e | 1814 | pm_runtime_get_sync(d40c->base->dev); |
d181b3a8 JA |
1815 | res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ); |
1816 | if (res) { | |
6db5a8ba | 1817 | chan_err(d40c, "suspend failed\n"); |
7fb3e75e | 1818 | goto out; |
d181b3a8 JA |
1819 | } |
1820 | ||
724a8577 | 1821 | if (chan_is_logical(d40c)) { |
d181b3a8 | 1822 | /* Release logical channel, deactivate the event line */ |
8d318a50 | 1823 | |
d181b3a8 | 1824 | d40_config_set_event(d40c, false); |
8d318a50 LW |
1825 | d40c->base->lookup_log_chans[d40c->log_num] = NULL; |
1826 | ||
1827 | /* | |
1828 | * Check if there are more logical allocation | |
1829 | * on this phy channel. | |
1830 | */ | |
1831 | if (!d40_alloc_mask_free(phy, is_src, event)) { | |
1832 | /* Resume the other logical channels if any */ | |
1833 | if (d40_chan_has_events(d40c)) { | |
1834 | res = d40_channel_execute_command(d40c, | |
1835 | D40_DMA_RUN); | |
7fb3e75e | 1836 | if (res) |
6db5a8ba RV |
1837 | chan_err(d40c, |
1838 | "Executing RUN command\n"); | |
8d318a50 | 1839 | } |
7fb3e75e | 1840 | goto out; |
8d318a50 | 1841 | } |
d181b3a8 JA |
1842 | } else { |
1843 | (void) d40_alloc_mask_free(phy, is_src, 0); | |
1844 | } | |
8d318a50 LW |
1845 | |
1846 | /* Release physical channel */ | |
1847 | res = d40_channel_execute_command(d40c, D40_DMA_STOP); | |
1848 | if (res) { | |
6db5a8ba | 1849 | chan_err(d40c, "Failed to stop channel\n"); |
7fb3e75e | 1850 | goto out; |
8d318a50 | 1851 | } |
7fb3e75e N |
1852 | |
1853 | if (d40c->busy) { | |
1854 | pm_runtime_mark_last_busy(d40c->base->dev); | |
1855 | pm_runtime_put_autosuspend(d40c->base->dev); | |
1856 | } | |
1857 | ||
1858 | d40c->busy = false; | |
8d318a50 | 1859 | d40c->phy_chan = NULL; |
ce2ca125 | 1860 | d40c->configured = false; |
8d318a50 | 1861 | d40c->base->lookup_phy_chans[phy->num] = NULL; |
7fb3e75e | 1862 | out: |
8d318a50 | 1863 | |
7fb3e75e N |
1864 | pm_runtime_mark_last_busy(d40c->base->dev); |
1865 | pm_runtime_put_autosuspend(d40c->base->dev); | |
1866 | return res; | |
8d318a50 LW |
1867 | } |
1868 | ||
a5ebca47 JA |
1869 | static bool d40_is_paused(struct d40_chan *d40c) |
1870 | { | |
8ca84687 | 1871 | void __iomem *chanbase = chan_base(d40c); |
a5ebca47 JA |
1872 | bool is_paused = false; |
1873 | unsigned long flags; | |
1874 | void __iomem *active_reg; | |
1875 | u32 status; | |
1876 | u32 event; | |
a5ebca47 JA |
1877 | |
1878 | spin_lock_irqsave(&d40c->lock, flags); | |
1879 | ||
724a8577 | 1880 | if (chan_is_physical(d40c)) { |
a5ebca47 JA |
1881 | if (d40c->phy_chan->num % 2 == 0) |
1882 | active_reg = d40c->base->virtbase + D40_DREG_ACTIVE; | |
1883 | else | |
1884 | active_reg = d40c->base->virtbase + D40_DREG_ACTIVO; | |
1885 | ||
1886 | status = (readl(active_reg) & | |
1887 | D40_CHAN_POS_MASK(d40c->phy_chan->num)) >> | |
1888 | D40_CHAN_POS(d40c->phy_chan->num); | |
1889 | if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP) | |
1890 | is_paused = true; | |
1891 | ||
1892 | goto _exit; | |
1893 | } | |
1894 | ||
a5ebca47 | 1895 | if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH || |
9dbfbd35 | 1896 | d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) { |
a5ebca47 | 1897 | event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type); |
8ca84687 | 1898 | status = readl(chanbase + D40_CHAN_REG_SDLNK); |
9dbfbd35 | 1899 | } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) { |
a5ebca47 | 1900 | event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type); |
8ca84687 | 1901 | status = readl(chanbase + D40_CHAN_REG_SSLNK); |
9dbfbd35 | 1902 | } else { |
6db5a8ba | 1903 | chan_err(d40c, "Unknown direction\n"); |
a5ebca47 JA |
1904 | goto _exit; |
1905 | } | |
9dbfbd35 | 1906 | |
a5ebca47 JA |
1907 | status = (status & D40_EVENTLINE_MASK(event)) >> |
1908 | D40_EVENTLINE_POS(event); | |
1909 | ||
1910 | if (status != D40_DMA_RUN) | |
1911 | is_paused = true; | |
a5ebca47 JA |
1912 | _exit: |
1913 | spin_unlock_irqrestore(&d40c->lock, flags); | |
1914 | return is_paused; | |
1915 | ||
1916 | } | |
1917 | ||
1918 | ||
8d318a50 LW |
1919 | static u32 stedma40_residue(struct dma_chan *chan) |
1920 | { | |
1921 | struct d40_chan *d40c = | |
1922 | container_of(chan, struct d40_chan, chan); | |
1923 | u32 bytes_left; | |
1924 | unsigned long flags; | |
1925 | ||
1926 | spin_lock_irqsave(&d40c->lock, flags); | |
1927 | bytes_left = d40_residue(d40c); | |
1928 | spin_unlock_irqrestore(&d40c->lock, flags); | |
1929 | ||
1930 | return bytes_left; | |
1931 | } | |
1932 | ||
3e3a0763 RV |
1933 | static int |
1934 | d40_prep_sg_log(struct d40_chan *chan, struct d40_desc *desc, | |
1935 | struct scatterlist *sg_src, struct scatterlist *sg_dst, | |
822c5676 RV |
1936 | unsigned int sg_len, dma_addr_t src_dev_addr, |
1937 | dma_addr_t dst_dev_addr) | |
3e3a0763 RV |
1938 | { |
1939 | struct stedma40_chan_cfg *cfg = &chan->dma_cfg; | |
1940 | struct stedma40_half_channel_info *src_info = &cfg->src_info; | |
1941 | struct stedma40_half_channel_info *dst_info = &cfg->dst_info; | |
5ed04b85 | 1942 | int ret; |
3e3a0763 | 1943 | |
5ed04b85 RV |
1944 | ret = d40_log_sg_to_lli(sg_src, sg_len, |
1945 | src_dev_addr, | |
1946 | desc->lli_log.src, | |
1947 | chan->log_def.lcsp1, | |
1948 | src_info->data_width, | |
1949 | dst_info->data_width); | |
1950 | ||
1951 | ret = d40_log_sg_to_lli(sg_dst, sg_len, | |
1952 | dst_dev_addr, | |
1953 | desc->lli_log.dst, | |
1954 | chan->log_def.lcsp3, | |
1955 | dst_info->data_width, | |
1956 | src_info->data_width); | |
1957 | ||
1958 | return ret < 0 ? ret : 0; | |
3e3a0763 RV |
1959 | } |
1960 | ||
1961 | static int | |
1962 | d40_prep_sg_phy(struct d40_chan *chan, struct d40_desc *desc, | |
1963 | struct scatterlist *sg_src, struct scatterlist *sg_dst, | |
822c5676 RV |
1964 | unsigned int sg_len, dma_addr_t src_dev_addr, |
1965 | dma_addr_t dst_dev_addr) | |
3e3a0763 | 1966 | { |
3e3a0763 RV |
1967 | struct stedma40_chan_cfg *cfg = &chan->dma_cfg; |
1968 | struct stedma40_half_channel_info *src_info = &cfg->src_info; | |
1969 | struct stedma40_half_channel_info *dst_info = &cfg->dst_info; | |
0c842b55 | 1970 | unsigned long flags = 0; |
3e3a0763 RV |
1971 | int ret; |
1972 | ||
0c842b55 RV |
1973 | if (desc->cyclic) |
1974 | flags |= LLI_CYCLIC | LLI_TERM_INT; | |
1975 | ||
3e3a0763 RV |
1976 | ret = d40_phy_sg_to_lli(sg_src, sg_len, src_dev_addr, |
1977 | desc->lli_phy.src, | |
1978 | virt_to_phys(desc->lli_phy.src), | |
1979 | chan->src_def_cfg, | |
0c842b55 | 1980 | src_info, dst_info, flags); |
3e3a0763 RV |
1981 | |
1982 | ret = d40_phy_sg_to_lli(sg_dst, sg_len, dst_dev_addr, | |
1983 | desc->lli_phy.dst, | |
1984 | virt_to_phys(desc->lli_phy.dst), | |
1985 | chan->dst_def_cfg, | |
0c842b55 | 1986 | dst_info, src_info, flags); |
3e3a0763 RV |
1987 | |
1988 | dma_sync_single_for_device(chan->base->dev, desc->lli_pool.dma_addr, | |
1989 | desc->lli_pool.size, DMA_TO_DEVICE); | |
1990 | ||
1991 | return ret < 0 ? ret : 0; | |
1992 | } | |
1993 | ||
1994 | ||
5f81158f RV |
1995 | static struct d40_desc * |
1996 | d40_prep_desc(struct d40_chan *chan, struct scatterlist *sg, | |
1997 | unsigned int sg_len, unsigned long dma_flags) | |
1998 | { | |
1999 | struct stedma40_chan_cfg *cfg = &chan->dma_cfg; | |
2000 | struct d40_desc *desc; | |
dbd88788 | 2001 | int ret; |
5f81158f RV |
2002 | |
2003 | desc = d40_desc_get(chan); | |
2004 | if (!desc) | |
2005 | return NULL; | |
2006 | ||
2007 | desc->lli_len = d40_sg_2_dmalen(sg, sg_len, cfg->src_info.data_width, | |
2008 | cfg->dst_info.data_width); | |
2009 | if (desc->lli_len < 0) { | |
2010 | chan_err(chan, "Unaligned size\n"); | |
dbd88788 RV |
2011 | goto err; |
2012 | } | |
5f81158f | 2013 | |
dbd88788 RV |
2014 | ret = d40_pool_lli_alloc(chan, desc, desc->lli_len); |
2015 | if (ret < 0) { | |
2016 | chan_err(chan, "Could not allocate lli\n"); | |
2017 | goto err; | |
5f81158f RV |
2018 | } |
2019 | ||
dbd88788 | 2020 | |
5f81158f RV |
2021 | desc->lli_current = 0; |
2022 | desc->txd.flags = dma_flags; | |
2023 | desc->txd.tx_submit = d40_tx_submit; | |
2024 | ||
2025 | dma_async_tx_descriptor_init(&desc->txd, &chan->chan); | |
2026 | ||
2027 | return desc; | |
dbd88788 RV |
2028 | |
2029 | err: | |
2030 | d40_desc_free(chan, desc); | |
2031 | return NULL; | |
5f81158f RV |
2032 | } |
2033 | ||
cade1d30 | 2034 | static dma_addr_t |
db8196df | 2035 | d40_get_dev_addr(struct d40_chan *chan, enum dma_transfer_direction direction) |
8d318a50 | 2036 | { |
cade1d30 RV |
2037 | struct stedma40_platform_data *plat = chan->base->plat_data; |
2038 | struct stedma40_chan_cfg *cfg = &chan->dma_cfg; | |
711b9cea | 2039 | dma_addr_t addr = 0; |
cade1d30 RV |
2040 | |
2041 | if (chan->runtime_addr) | |
2042 | return chan->runtime_addr; | |
2043 | ||
db8196df | 2044 | if (direction == DMA_DEV_TO_MEM) |
cade1d30 | 2045 | addr = plat->dev_rx[cfg->src_dev_type]; |
db8196df | 2046 | else if (direction == DMA_MEM_TO_DEV) |
cade1d30 RV |
2047 | addr = plat->dev_tx[cfg->dst_dev_type]; |
2048 | ||
2049 | return addr; | |
2050 | } | |
2051 | ||
2052 | static struct dma_async_tx_descriptor * | |
2053 | d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src, | |
2054 | struct scatterlist *sg_dst, unsigned int sg_len, | |
db8196df | 2055 | enum dma_transfer_direction direction, unsigned long dma_flags) |
cade1d30 RV |
2056 | { |
2057 | struct d40_chan *chan = container_of(dchan, struct d40_chan, chan); | |
822c5676 RV |
2058 | dma_addr_t src_dev_addr = 0; |
2059 | dma_addr_t dst_dev_addr = 0; | |
cade1d30 | 2060 | struct d40_desc *desc; |
2a614340 | 2061 | unsigned long flags; |
cade1d30 | 2062 | int ret; |
8d318a50 | 2063 | |
cade1d30 RV |
2064 | if (!chan->phy_chan) { |
2065 | chan_err(chan, "Cannot prepare unallocated channel\n"); | |
2066 | return NULL; | |
0d0f6b8b JA |
2067 | } |
2068 | ||
0c842b55 | 2069 | |
cade1d30 | 2070 | spin_lock_irqsave(&chan->lock, flags); |
8d318a50 | 2071 | |
cade1d30 RV |
2072 | desc = d40_prep_desc(chan, sg_src, sg_len, dma_flags); |
2073 | if (desc == NULL) | |
8d318a50 LW |
2074 | goto err; |
2075 | ||
0c842b55 RV |
2076 | if (sg_next(&sg_src[sg_len - 1]) == sg_src) |
2077 | desc->cyclic = true; | |
2078 | ||
822c5676 RV |
2079 | if (direction != DMA_NONE) { |
2080 | dma_addr_t dev_addr = d40_get_dev_addr(chan, direction); | |
2081 | ||
db8196df | 2082 | if (direction == DMA_DEV_TO_MEM) |
822c5676 | 2083 | src_dev_addr = dev_addr; |
db8196df | 2084 | else if (direction == DMA_MEM_TO_DEV) |
822c5676 RV |
2085 | dst_dev_addr = dev_addr; |
2086 | } | |
cade1d30 RV |
2087 | |
2088 | if (chan_is_logical(chan)) | |
2089 | ret = d40_prep_sg_log(chan, desc, sg_src, sg_dst, | |
822c5676 | 2090 | sg_len, src_dev_addr, dst_dev_addr); |
cade1d30 RV |
2091 | else |
2092 | ret = d40_prep_sg_phy(chan, desc, sg_src, sg_dst, | |
822c5676 | 2093 | sg_len, src_dev_addr, dst_dev_addr); |
cade1d30 RV |
2094 | |
2095 | if (ret) { | |
2096 | chan_err(chan, "Failed to prepare %s sg job: %d\n", | |
2097 | chan_is_logical(chan) ? "log" : "phy", ret); | |
2098 | goto err; | |
8d318a50 LW |
2099 | } |
2100 | ||
82babbb3 PF |
2101 | /* |
2102 | * add descriptor to the prepare queue in order to be able | |
2103 | * to free them later in terminate_all | |
2104 | */ | |
2105 | list_add_tail(&desc->node, &chan->prepare_queue); | |
2106 | ||
cade1d30 RV |
2107 | spin_unlock_irqrestore(&chan->lock, flags); |
2108 | ||
2109 | return &desc->txd; | |
8d318a50 | 2110 | |
8d318a50 | 2111 | err: |
cade1d30 RV |
2112 | if (desc) |
2113 | d40_desc_free(chan, desc); | |
2114 | spin_unlock_irqrestore(&chan->lock, flags); | |
8d318a50 LW |
2115 | return NULL; |
2116 | } | |
8d318a50 LW |
2117 | |
2118 | bool stedma40_filter(struct dma_chan *chan, void *data) | |
2119 | { | |
2120 | struct stedma40_chan_cfg *info = data; | |
2121 | struct d40_chan *d40c = | |
2122 | container_of(chan, struct d40_chan, chan); | |
2123 | int err; | |
2124 | ||
2125 | if (data) { | |
2126 | err = d40_validate_conf(d40c, info); | |
2127 | if (!err) | |
2128 | d40c->dma_cfg = *info; | |
2129 | } else | |
2130 | err = d40_config_memcpy(d40c); | |
2131 | ||
ce2ca125 RV |
2132 | if (!err) |
2133 | d40c->configured = true; | |
2134 | ||
8d318a50 LW |
2135 | return err == 0; |
2136 | } | |
2137 | EXPORT_SYMBOL(stedma40_filter); | |
2138 | ||
ac2c0a38 RV |
2139 | static void __d40_set_prio_rt(struct d40_chan *d40c, int dev_type, bool src) |
2140 | { | |
2141 | bool realtime = d40c->dma_cfg.realtime; | |
2142 | bool highprio = d40c->dma_cfg.high_priority; | |
2143 | u32 prioreg = highprio ? D40_DREG_PSEG1 : D40_DREG_PCEG1; | |
2144 | u32 rtreg = realtime ? D40_DREG_RSEG1 : D40_DREG_RCEG1; | |
2145 | u32 event = D40_TYPE_TO_EVENT(dev_type); | |
2146 | u32 group = D40_TYPE_TO_GROUP(dev_type); | |
2147 | u32 bit = 1 << event; | |
2148 | ||
2149 | /* Destination event lines are stored in the upper halfword */ | |
2150 | if (!src) | |
2151 | bit <<= 16; | |
2152 | ||
2153 | writel(bit, d40c->base->virtbase + prioreg + group * 4); | |
2154 | writel(bit, d40c->base->virtbase + rtreg + group * 4); | |
2155 | } | |
2156 | ||
2157 | static void d40_set_prio_realtime(struct d40_chan *d40c) | |
2158 | { | |
2159 | if (d40c->base->rev < 3) | |
2160 | return; | |
2161 | ||
2162 | if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) || | |
2163 | (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) | |
2164 | __d40_set_prio_rt(d40c, d40c->dma_cfg.src_dev_type, true); | |
2165 | ||
2166 | if ((d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH) || | |
2167 | (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) | |
2168 | __d40_set_prio_rt(d40c, d40c->dma_cfg.dst_dev_type, false); | |
2169 | } | |
2170 | ||
8d318a50 LW |
2171 | /* DMA ENGINE functions */ |
2172 | static int d40_alloc_chan_resources(struct dma_chan *chan) | |
2173 | { | |
2174 | int err; | |
2175 | unsigned long flags; | |
2176 | struct d40_chan *d40c = | |
2177 | container_of(chan, struct d40_chan, chan); | |
ef1872ec | 2178 | bool is_free_phy; |
8d318a50 LW |
2179 | spin_lock_irqsave(&d40c->lock, flags); |
2180 | ||
4d4e58de | 2181 | chan->completed_cookie = chan->cookie = 1; |
8d318a50 | 2182 | |
ce2ca125 RV |
2183 | /* If no dma configuration is set use default configuration (memcpy) */ |
2184 | if (!d40c->configured) { | |
8d318a50 | 2185 | err = d40_config_memcpy(d40c); |
ff0b12ba | 2186 | if (err) { |
6db5a8ba | 2187 | chan_err(d40c, "Failed to configure memcpy channel\n"); |
ff0b12ba JA |
2188 | goto fail; |
2189 | } | |
8d318a50 LW |
2190 | } |
2191 | ||
5cd326fd | 2192 | err = d40_allocate_channel(d40c, &is_free_phy); |
8d318a50 | 2193 | if (err) { |
6db5a8ba | 2194 | chan_err(d40c, "Failed to allocate channel\n"); |
7fb3e75e | 2195 | d40c->configured = false; |
ff0b12ba | 2196 | goto fail; |
8d318a50 LW |
2197 | } |
2198 | ||
7fb3e75e | 2199 | pm_runtime_get_sync(d40c->base->dev); |
ef1872ec LW |
2200 | /* Fill in basic CFG register values */ |
2201 | d40_phy_cfg(&d40c->dma_cfg, &d40c->src_def_cfg, | |
724a8577 | 2202 | &d40c->dst_def_cfg, chan_is_logical(d40c)); |
ef1872ec | 2203 | |
ac2c0a38 RV |
2204 | d40_set_prio_realtime(d40c); |
2205 | ||
724a8577 | 2206 | if (chan_is_logical(d40c)) { |
ef1872ec LW |
2207 | d40_log_cfg(&d40c->dma_cfg, |
2208 | &d40c->log_def.lcsp1, &d40c->log_def.lcsp3); | |
2209 | ||
2210 | if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) | |
2211 | d40c->lcpa = d40c->base->lcpa_base + | |
2212 | d40c->dma_cfg.src_dev_type * D40_LCPA_CHAN_SIZE; | |
2213 | else | |
2214 | d40c->lcpa = d40c->base->lcpa_base + | |
2215 | d40c->dma_cfg.dst_dev_type * | |
2216 | D40_LCPA_CHAN_SIZE + D40_LCPA_CHAN_DST_DELTA; | |
2217 | } | |
2218 | ||
5cd326fd N |
2219 | dev_dbg(chan2dev(d40c), "allocated %s channel (phy %d%s)\n", |
2220 | chan_is_logical(d40c) ? "logical" : "physical", | |
2221 | d40c->phy_chan->num, | |
2222 | d40c->dma_cfg.use_fixed_channel ? ", fixed" : ""); | |
2223 | ||
2224 | ||
ef1872ec LW |
2225 | /* |
2226 | * Only write channel configuration to the DMA if the physical | |
2227 | * resource is free. In case of multiple logical channels | |
2228 | * on the same physical resource, only the first write is necessary. | |
2229 | */ | |
b55912c6 JA |
2230 | if (is_free_phy) |
2231 | d40_config_write(d40c); | |
ff0b12ba | 2232 | fail: |
7fb3e75e N |
2233 | pm_runtime_mark_last_busy(d40c->base->dev); |
2234 | pm_runtime_put_autosuspend(d40c->base->dev); | |
8d318a50 | 2235 | spin_unlock_irqrestore(&d40c->lock, flags); |
ff0b12ba | 2236 | return err; |
8d318a50 LW |
2237 | } |
2238 | ||
2239 | static void d40_free_chan_resources(struct dma_chan *chan) | |
2240 | { | |
2241 | struct d40_chan *d40c = | |
2242 | container_of(chan, struct d40_chan, chan); | |
2243 | int err; | |
2244 | unsigned long flags; | |
2245 | ||
0d0f6b8b | 2246 | if (d40c->phy_chan == NULL) { |
6db5a8ba | 2247 | chan_err(d40c, "Cannot free unallocated channel\n"); |
0d0f6b8b JA |
2248 | return; |
2249 | } | |
2250 | ||
2251 | ||
8d318a50 LW |
2252 | spin_lock_irqsave(&d40c->lock, flags); |
2253 | ||
2254 | err = d40_free_dma(d40c); | |
2255 | ||
2256 | if (err) | |
6db5a8ba | 2257 | chan_err(d40c, "Failed to free channel\n"); |
8d318a50 LW |
2258 | spin_unlock_irqrestore(&d40c->lock, flags); |
2259 | } | |
2260 | ||
2261 | static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan, | |
2262 | dma_addr_t dst, | |
2263 | dma_addr_t src, | |
2264 | size_t size, | |
2a614340 | 2265 | unsigned long dma_flags) |
8d318a50 | 2266 | { |
95944c6e RV |
2267 | struct scatterlist dst_sg; |
2268 | struct scatterlist src_sg; | |
8d318a50 | 2269 | |
95944c6e RV |
2270 | sg_init_table(&dst_sg, 1); |
2271 | sg_init_table(&src_sg, 1); | |
8d318a50 | 2272 | |
95944c6e RV |
2273 | sg_dma_address(&dst_sg) = dst; |
2274 | sg_dma_address(&src_sg) = src; | |
8d318a50 | 2275 | |
95944c6e RV |
2276 | sg_dma_len(&dst_sg) = size; |
2277 | sg_dma_len(&src_sg) = size; | |
8d318a50 | 2278 | |
cade1d30 | 2279 | return d40_prep_sg(chan, &src_sg, &dst_sg, 1, DMA_NONE, dma_flags); |
8d318a50 LW |
2280 | } |
2281 | ||
0d688662 | 2282 | static struct dma_async_tx_descriptor * |
cade1d30 RV |
2283 | d40_prep_memcpy_sg(struct dma_chan *chan, |
2284 | struct scatterlist *dst_sg, unsigned int dst_nents, | |
2285 | struct scatterlist *src_sg, unsigned int src_nents, | |
2286 | unsigned long dma_flags) | |
0d688662 IS |
2287 | { |
2288 | if (dst_nents != src_nents) | |
2289 | return NULL; | |
2290 | ||
cade1d30 | 2291 | return d40_prep_sg(chan, src_sg, dst_sg, src_nents, DMA_NONE, dma_flags); |
00ac0341 RV |
2292 | } |
2293 | ||
8d318a50 LW |
2294 | static struct dma_async_tx_descriptor *d40_prep_slave_sg(struct dma_chan *chan, |
2295 | struct scatterlist *sgl, | |
2296 | unsigned int sg_len, | |
db8196df | 2297 | enum dma_transfer_direction direction, |
2a614340 | 2298 | unsigned long dma_flags) |
8d318a50 | 2299 | { |
db8196df | 2300 | if (direction != DMA_DEV_TO_MEM && direction != DMA_MEM_TO_DEV) |
00ac0341 RV |
2301 | return NULL; |
2302 | ||
cade1d30 | 2303 | return d40_prep_sg(chan, sgl, sgl, sg_len, direction, dma_flags); |
8d318a50 LW |
2304 | } |
2305 | ||
0c842b55 RV |
2306 | static struct dma_async_tx_descriptor * |
2307 | dma40_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr, | |
2308 | size_t buf_len, size_t period_len, | |
db8196df | 2309 | enum dma_transfer_direction direction) |
0c842b55 RV |
2310 | { |
2311 | unsigned int periods = buf_len / period_len; | |
2312 | struct dma_async_tx_descriptor *txd; | |
2313 | struct scatterlist *sg; | |
2314 | int i; | |
2315 | ||
79ca7ec3 | 2316 | sg = kcalloc(periods + 1, sizeof(struct scatterlist), GFP_NOWAIT); |
0c842b55 RV |
2317 | for (i = 0; i < periods; i++) { |
2318 | sg_dma_address(&sg[i]) = dma_addr; | |
2319 | sg_dma_len(&sg[i]) = period_len; | |
2320 | dma_addr += period_len; | |
2321 | } | |
2322 | ||
2323 | sg[periods].offset = 0; | |
2324 | sg[periods].length = 0; | |
2325 | sg[periods].page_link = | |
2326 | ((unsigned long)sg | 0x01) & ~0x02; | |
2327 | ||
2328 | txd = d40_prep_sg(chan, sg, sg, periods, direction, | |
2329 | DMA_PREP_INTERRUPT); | |
2330 | ||
2331 | kfree(sg); | |
2332 | ||
2333 | return txd; | |
2334 | } | |
2335 | ||
8d318a50 LW |
2336 | static enum dma_status d40_tx_status(struct dma_chan *chan, |
2337 | dma_cookie_t cookie, | |
2338 | struct dma_tx_state *txstate) | |
2339 | { | |
2340 | struct d40_chan *d40c = container_of(chan, struct d40_chan, chan); | |
2341 | dma_cookie_t last_used; | |
2342 | dma_cookie_t last_complete; | |
2343 | int ret; | |
2344 | ||
0d0f6b8b | 2345 | if (d40c->phy_chan == NULL) { |
6db5a8ba | 2346 | chan_err(d40c, "Cannot read status of unallocated channel\n"); |
0d0f6b8b JA |
2347 | return -EINVAL; |
2348 | } | |
2349 | ||
4d4e58de | 2350 | last_complete = chan->completed_cookie; |
8d318a50 LW |
2351 | last_used = chan->cookie; |
2352 | ||
a5ebca47 JA |
2353 | if (d40_is_paused(d40c)) |
2354 | ret = DMA_PAUSED; | |
2355 | else | |
2356 | ret = dma_async_is_complete(cookie, last_complete, last_used); | |
8d318a50 | 2357 | |
a5ebca47 JA |
2358 | dma_set_tx_state(txstate, last_complete, last_used, |
2359 | stedma40_residue(chan)); | |
8d318a50 LW |
2360 | |
2361 | return ret; | |
2362 | } | |
2363 | ||
2364 | static void d40_issue_pending(struct dma_chan *chan) | |
2365 | { | |
2366 | struct d40_chan *d40c = container_of(chan, struct d40_chan, chan); | |
2367 | unsigned long flags; | |
2368 | ||
0d0f6b8b | 2369 | if (d40c->phy_chan == NULL) { |
6db5a8ba | 2370 | chan_err(d40c, "Channel is not allocated!\n"); |
0d0f6b8b JA |
2371 | return; |
2372 | } | |
2373 | ||
8d318a50 LW |
2374 | spin_lock_irqsave(&d40c->lock, flags); |
2375 | ||
a8f3067b PF |
2376 | list_splice_tail_init(&d40c->pending_queue, &d40c->queue); |
2377 | ||
2378 | /* Busy means that queued jobs are already being processed */ | |
8d318a50 LW |
2379 | if (!d40c->busy) |
2380 | (void) d40_queue_start(d40c); | |
2381 | ||
2382 | spin_unlock_irqrestore(&d40c->lock, flags); | |
2383 | } | |
2384 | ||
98ca5289 RV |
2385 | static int |
2386 | dma40_config_to_halfchannel(struct d40_chan *d40c, | |
2387 | struct stedma40_half_channel_info *info, | |
2388 | enum dma_slave_buswidth width, | |
2389 | u32 maxburst) | |
2390 | { | |
2391 | enum stedma40_periph_data_width addr_width; | |
2392 | int psize; | |
2393 | ||
2394 | switch (width) { | |
2395 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
2396 | addr_width = STEDMA40_BYTE_WIDTH; | |
2397 | break; | |
2398 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
2399 | addr_width = STEDMA40_HALFWORD_WIDTH; | |
2400 | break; | |
2401 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
2402 | addr_width = STEDMA40_WORD_WIDTH; | |
2403 | break; | |
2404 | case DMA_SLAVE_BUSWIDTH_8_BYTES: | |
2405 | addr_width = STEDMA40_DOUBLEWORD_WIDTH; | |
2406 | break; | |
2407 | default: | |
2408 | dev_err(d40c->base->dev, | |
2409 | "illegal peripheral address width " | |
2410 | "requested (%d)\n", | |
2411 | width); | |
2412 | return -EINVAL; | |
2413 | } | |
2414 | ||
2415 | if (chan_is_logical(d40c)) { | |
2416 | if (maxburst >= 16) | |
2417 | psize = STEDMA40_PSIZE_LOG_16; | |
2418 | else if (maxburst >= 8) | |
2419 | psize = STEDMA40_PSIZE_LOG_8; | |
2420 | else if (maxburst >= 4) | |
2421 | psize = STEDMA40_PSIZE_LOG_4; | |
2422 | else | |
2423 | psize = STEDMA40_PSIZE_LOG_1; | |
2424 | } else { | |
2425 | if (maxburst >= 16) | |
2426 | psize = STEDMA40_PSIZE_PHY_16; | |
2427 | else if (maxburst >= 8) | |
2428 | psize = STEDMA40_PSIZE_PHY_8; | |
2429 | else if (maxburst >= 4) | |
2430 | psize = STEDMA40_PSIZE_PHY_4; | |
2431 | else | |
2432 | psize = STEDMA40_PSIZE_PHY_1; | |
2433 | } | |
2434 | ||
2435 | info->data_width = addr_width; | |
2436 | info->psize = psize; | |
2437 | info->flow_ctrl = STEDMA40_NO_FLOW_CTRL; | |
2438 | ||
2439 | return 0; | |
2440 | } | |
2441 | ||
95e1400f | 2442 | /* Runtime reconfiguration extension */ |
98ca5289 RV |
2443 | static int d40_set_runtime_config(struct dma_chan *chan, |
2444 | struct dma_slave_config *config) | |
95e1400f LW |
2445 | { |
2446 | struct d40_chan *d40c = container_of(chan, struct d40_chan, chan); | |
2447 | struct stedma40_chan_cfg *cfg = &d40c->dma_cfg; | |
98ca5289 | 2448 | enum dma_slave_buswidth src_addr_width, dst_addr_width; |
95e1400f | 2449 | dma_addr_t config_addr; |
98ca5289 RV |
2450 | u32 src_maxburst, dst_maxburst; |
2451 | int ret; | |
2452 | ||
2453 | src_addr_width = config->src_addr_width; | |
2454 | src_maxburst = config->src_maxburst; | |
2455 | dst_addr_width = config->dst_addr_width; | |
2456 | dst_maxburst = config->dst_maxburst; | |
95e1400f | 2457 | |
db8196df | 2458 | if (config->direction == DMA_DEV_TO_MEM) { |
95e1400f LW |
2459 | dma_addr_t dev_addr_rx = |
2460 | d40c->base->plat_data->dev_rx[cfg->src_dev_type]; | |
2461 | ||
2462 | config_addr = config->src_addr; | |
2463 | if (dev_addr_rx) | |
2464 | dev_dbg(d40c->base->dev, | |
2465 | "channel has a pre-wired RX address %08x " | |
2466 | "overriding with %08x\n", | |
2467 | dev_addr_rx, config_addr); | |
2468 | if (cfg->dir != STEDMA40_PERIPH_TO_MEM) | |
2469 | dev_dbg(d40c->base->dev, | |
2470 | "channel was not configured for peripheral " | |
2471 | "to memory transfer (%d) overriding\n", | |
2472 | cfg->dir); | |
2473 | cfg->dir = STEDMA40_PERIPH_TO_MEM; | |
2474 | ||
98ca5289 RV |
2475 | /* Configure the memory side */ |
2476 | if (dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) | |
2477 | dst_addr_width = src_addr_width; | |
2478 | if (dst_maxburst == 0) | |
2479 | dst_maxburst = src_maxburst; | |
95e1400f | 2480 | |
db8196df | 2481 | } else if (config->direction == DMA_MEM_TO_DEV) { |
95e1400f LW |
2482 | dma_addr_t dev_addr_tx = |
2483 | d40c->base->plat_data->dev_tx[cfg->dst_dev_type]; | |
2484 | ||
2485 | config_addr = config->dst_addr; | |
2486 | if (dev_addr_tx) | |
2487 | dev_dbg(d40c->base->dev, | |
2488 | "channel has a pre-wired TX address %08x " | |
2489 | "overriding with %08x\n", | |
2490 | dev_addr_tx, config_addr); | |
2491 | if (cfg->dir != STEDMA40_MEM_TO_PERIPH) | |
2492 | dev_dbg(d40c->base->dev, | |
2493 | "channel was not configured for memory " | |
2494 | "to peripheral transfer (%d) overriding\n", | |
2495 | cfg->dir); | |
2496 | cfg->dir = STEDMA40_MEM_TO_PERIPH; | |
2497 | ||
98ca5289 RV |
2498 | /* Configure the memory side */ |
2499 | if (src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) | |
2500 | src_addr_width = dst_addr_width; | |
2501 | if (src_maxburst == 0) | |
2502 | src_maxburst = dst_maxburst; | |
95e1400f LW |
2503 | } else { |
2504 | dev_err(d40c->base->dev, | |
2505 | "unrecognized channel direction %d\n", | |
2506 | config->direction); | |
98ca5289 | 2507 | return -EINVAL; |
95e1400f LW |
2508 | } |
2509 | ||
98ca5289 | 2510 | if (src_maxburst * src_addr_width != dst_maxburst * dst_addr_width) { |
95e1400f | 2511 | dev_err(d40c->base->dev, |
98ca5289 RV |
2512 | "src/dst width/maxburst mismatch: %d*%d != %d*%d\n", |
2513 | src_maxburst, | |
2514 | src_addr_width, | |
2515 | dst_maxburst, | |
2516 | dst_addr_width); | |
2517 | return -EINVAL; | |
95e1400f LW |
2518 | } |
2519 | ||
98ca5289 RV |
2520 | ret = dma40_config_to_halfchannel(d40c, &cfg->src_info, |
2521 | src_addr_width, | |
2522 | src_maxburst); | |
2523 | if (ret) | |
2524 | return ret; | |
95e1400f | 2525 | |
98ca5289 RV |
2526 | ret = dma40_config_to_halfchannel(d40c, &cfg->dst_info, |
2527 | dst_addr_width, | |
2528 | dst_maxburst); | |
2529 | if (ret) | |
2530 | return ret; | |
95e1400f | 2531 | |
a59670a4 | 2532 | /* Fill in register values */ |
724a8577 | 2533 | if (chan_is_logical(d40c)) |
a59670a4 PF |
2534 | d40_log_cfg(cfg, &d40c->log_def.lcsp1, &d40c->log_def.lcsp3); |
2535 | else | |
2536 | d40_phy_cfg(cfg, &d40c->src_def_cfg, | |
2537 | &d40c->dst_def_cfg, false); | |
2538 | ||
95e1400f LW |
2539 | /* These settings will take precedence later */ |
2540 | d40c->runtime_addr = config_addr; | |
2541 | d40c->runtime_direction = config->direction; | |
2542 | dev_dbg(d40c->base->dev, | |
98ca5289 RV |
2543 | "configured channel %s for %s, data width %d/%d, " |
2544 | "maxburst %d/%d elements, LE, no flow control\n", | |
95e1400f | 2545 | dma_chan_name(chan), |
db8196df | 2546 | (config->direction == DMA_DEV_TO_MEM) ? "RX" : "TX", |
98ca5289 RV |
2547 | src_addr_width, dst_addr_width, |
2548 | src_maxburst, dst_maxburst); | |
2549 | ||
2550 | return 0; | |
95e1400f LW |
2551 | } |
2552 | ||
05827630 LW |
2553 | static int d40_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
2554 | unsigned long arg) | |
8d318a50 | 2555 | { |
8d318a50 LW |
2556 | struct d40_chan *d40c = container_of(chan, struct d40_chan, chan); |
2557 | ||
0d0f6b8b | 2558 | if (d40c->phy_chan == NULL) { |
6db5a8ba | 2559 | chan_err(d40c, "Channel is not allocated!\n"); |
0d0f6b8b JA |
2560 | return -EINVAL; |
2561 | } | |
2562 | ||
8d318a50 LW |
2563 | switch (cmd) { |
2564 | case DMA_TERMINATE_ALL: | |
86eb5fb6 | 2565 | return d40_terminate_all(d40c); |
8d318a50 | 2566 | case DMA_PAUSE: |
86eb5fb6 | 2567 | return d40_pause(d40c); |
8d318a50 | 2568 | case DMA_RESUME: |
86eb5fb6 | 2569 | return d40_resume(d40c); |
95e1400f | 2570 | case DMA_SLAVE_CONFIG: |
98ca5289 | 2571 | return d40_set_runtime_config(chan, |
95e1400f | 2572 | (struct dma_slave_config *) arg); |
95e1400f LW |
2573 | default: |
2574 | break; | |
8d318a50 LW |
2575 | } |
2576 | ||
2577 | /* Other commands are unimplemented */ | |
2578 | return -ENXIO; | |
2579 | } | |
2580 | ||
2581 | /* Initialization functions */ | |
2582 | ||
2583 | static void __init d40_chan_init(struct d40_base *base, struct dma_device *dma, | |
2584 | struct d40_chan *chans, int offset, | |
2585 | int num_chans) | |
2586 | { | |
2587 | int i = 0; | |
2588 | struct d40_chan *d40c; | |
2589 | ||
2590 | INIT_LIST_HEAD(&dma->channels); | |
2591 | ||
2592 | for (i = offset; i < offset + num_chans; i++) { | |
2593 | d40c = &chans[i]; | |
2594 | d40c->base = base; | |
2595 | d40c->chan.device = dma; | |
2596 | ||
8d318a50 LW |
2597 | spin_lock_init(&d40c->lock); |
2598 | ||
2599 | d40c->log_num = D40_PHY_CHAN; | |
2600 | ||
8d318a50 LW |
2601 | INIT_LIST_HEAD(&d40c->active); |
2602 | INIT_LIST_HEAD(&d40c->queue); | |
a8f3067b | 2603 | INIT_LIST_HEAD(&d40c->pending_queue); |
8d318a50 | 2604 | INIT_LIST_HEAD(&d40c->client); |
82babbb3 | 2605 | INIT_LIST_HEAD(&d40c->prepare_queue); |
8d318a50 | 2606 | |
8d318a50 LW |
2607 | tasklet_init(&d40c->tasklet, dma_tasklet, |
2608 | (unsigned long) d40c); | |
2609 | ||
2610 | list_add_tail(&d40c->chan.device_node, | |
2611 | &dma->channels); | |
2612 | } | |
2613 | } | |
2614 | ||
7ad74a7c RV |
2615 | static void d40_ops_init(struct d40_base *base, struct dma_device *dev) |
2616 | { | |
2617 | if (dma_has_cap(DMA_SLAVE, dev->cap_mask)) | |
2618 | dev->device_prep_slave_sg = d40_prep_slave_sg; | |
2619 | ||
2620 | if (dma_has_cap(DMA_MEMCPY, dev->cap_mask)) { | |
2621 | dev->device_prep_dma_memcpy = d40_prep_memcpy; | |
2622 | ||
2623 | /* | |
2624 | * This controller can only access address at even | |
2625 | * 32bit boundaries, i.e. 2^2 | |
2626 | */ | |
2627 | dev->copy_align = 2; | |
2628 | } | |
2629 | ||
2630 | if (dma_has_cap(DMA_SG, dev->cap_mask)) | |
2631 | dev->device_prep_dma_sg = d40_prep_memcpy_sg; | |
2632 | ||
0c842b55 RV |
2633 | if (dma_has_cap(DMA_CYCLIC, dev->cap_mask)) |
2634 | dev->device_prep_dma_cyclic = dma40_prep_dma_cyclic; | |
2635 | ||
7ad74a7c RV |
2636 | dev->device_alloc_chan_resources = d40_alloc_chan_resources; |
2637 | dev->device_free_chan_resources = d40_free_chan_resources; | |
2638 | dev->device_issue_pending = d40_issue_pending; | |
2639 | dev->device_tx_status = d40_tx_status; | |
2640 | dev->device_control = d40_control; | |
2641 | dev->dev = base->dev; | |
2642 | } | |
2643 | ||
8d318a50 LW |
2644 | static int __init d40_dmaengine_init(struct d40_base *base, |
2645 | int num_reserved_chans) | |
2646 | { | |
2647 | int err ; | |
2648 | ||
2649 | d40_chan_init(base, &base->dma_slave, base->log_chans, | |
2650 | 0, base->num_log_chans); | |
2651 | ||
2652 | dma_cap_zero(base->dma_slave.cap_mask); | |
2653 | dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask); | |
0c842b55 | 2654 | dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask); |
8d318a50 | 2655 | |
7ad74a7c | 2656 | d40_ops_init(base, &base->dma_slave); |
8d318a50 LW |
2657 | |
2658 | err = dma_async_device_register(&base->dma_slave); | |
2659 | ||
2660 | if (err) { | |
6db5a8ba | 2661 | d40_err(base->dev, "Failed to register slave channels\n"); |
8d318a50 LW |
2662 | goto failure1; |
2663 | } | |
2664 | ||
2665 | d40_chan_init(base, &base->dma_memcpy, base->log_chans, | |
2666 | base->num_log_chans, base->plat_data->memcpy_len); | |
2667 | ||
2668 | dma_cap_zero(base->dma_memcpy.cap_mask); | |
2669 | dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask); | |
7ad74a7c RV |
2670 | dma_cap_set(DMA_SG, base->dma_memcpy.cap_mask); |
2671 | ||
2672 | d40_ops_init(base, &base->dma_memcpy); | |
8d318a50 LW |
2673 | |
2674 | err = dma_async_device_register(&base->dma_memcpy); | |
2675 | ||
2676 | if (err) { | |
6db5a8ba RV |
2677 | d40_err(base->dev, |
2678 | "Failed to regsiter memcpy only channels\n"); | |
8d318a50 LW |
2679 | goto failure2; |
2680 | } | |
2681 | ||
2682 | d40_chan_init(base, &base->dma_both, base->phy_chans, | |
2683 | 0, num_reserved_chans); | |
2684 | ||
2685 | dma_cap_zero(base->dma_both.cap_mask); | |
2686 | dma_cap_set(DMA_SLAVE, base->dma_both.cap_mask); | |
2687 | dma_cap_set(DMA_MEMCPY, base->dma_both.cap_mask); | |
7ad74a7c | 2688 | dma_cap_set(DMA_SG, base->dma_both.cap_mask); |
0c842b55 | 2689 | dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask); |
7ad74a7c RV |
2690 | |
2691 | d40_ops_init(base, &base->dma_both); | |
8d318a50 LW |
2692 | err = dma_async_device_register(&base->dma_both); |
2693 | ||
2694 | if (err) { | |
6db5a8ba RV |
2695 | d40_err(base->dev, |
2696 | "Failed to register logical and physical capable channels\n"); | |
8d318a50 LW |
2697 | goto failure3; |
2698 | } | |
2699 | return 0; | |
2700 | failure3: | |
2701 | dma_async_device_unregister(&base->dma_memcpy); | |
2702 | failure2: | |
2703 | dma_async_device_unregister(&base->dma_slave); | |
2704 | failure1: | |
2705 | return err; | |
2706 | } | |
2707 | ||
7fb3e75e N |
2708 | /* Suspend resume functionality */ |
2709 | #ifdef CONFIG_PM | |
2710 | static int dma40_pm_suspend(struct device *dev) | |
2711 | { | |
28c7a19d N |
2712 | struct platform_device *pdev = to_platform_device(dev); |
2713 | struct d40_base *base = platform_get_drvdata(pdev); | |
2714 | int ret = 0; | |
7fb3e75e N |
2715 | if (!pm_runtime_suspended(dev)) |
2716 | return -EBUSY; | |
2717 | ||
28c7a19d N |
2718 | if (base->lcpa_regulator) |
2719 | ret = regulator_disable(base->lcpa_regulator); | |
2720 | return ret; | |
7fb3e75e N |
2721 | } |
2722 | ||
2723 | static int dma40_runtime_suspend(struct device *dev) | |
2724 | { | |
2725 | struct platform_device *pdev = to_platform_device(dev); | |
2726 | struct d40_base *base = platform_get_drvdata(pdev); | |
2727 | ||
2728 | d40_save_restore_registers(base, true); | |
2729 | ||
2730 | /* Don't disable/enable clocks for v1 due to HW bugs */ | |
2731 | if (base->rev != 1) | |
2732 | writel_relaxed(base->gcc_pwr_off_mask, | |
2733 | base->virtbase + D40_DREG_GCC); | |
2734 | ||
2735 | return 0; | |
2736 | } | |
2737 | ||
2738 | static int dma40_runtime_resume(struct device *dev) | |
2739 | { | |
2740 | struct platform_device *pdev = to_platform_device(dev); | |
2741 | struct d40_base *base = platform_get_drvdata(pdev); | |
2742 | ||
2743 | if (base->initialized) | |
2744 | d40_save_restore_registers(base, false); | |
2745 | ||
2746 | writel_relaxed(D40_DREG_GCC_ENABLE_ALL, | |
2747 | base->virtbase + D40_DREG_GCC); | |
2748 | return 0; | |
2749 | } | |
2750 | ||
28c7a19d N |
2751 | static int dma40_resume(struct device *dev) |
2752 | { | |
2753 | struct platform_device *pdev = to_platform_device(dev); | |
2754 | struct d40_base *base = platform_get_drvdata(pdev); | |
2755 | int ret = 0; | |
2756 | ||
2757 | if (base->lcpa_regulator) | |
2758 | ret = regulator_enable(base->lcpa_regulator); | |
2759 | ||
2760 | return ret; | |
2761 | } | |
7fb3e75e N |
2762 | |
2763 | static const struct dev_pm_ops dma40_pm_ops = { | |
2764 | .suspend = dma40_pm_suspend, | |
2765 | .runtime_suspend = dma40_runtime_suspend, | |
2766 | .runtime_resume = dma40_runtime_resume, | |
28c7a19d | 2767 | .resume = dma40_resume, |
7fb3e75e N |
2768 | }; |
2769 | #define DMA40_PM_OPS (&dma40_pm_ops) | |
2770 | #else | |
2771 | #define DMA40_PM_OPS NULL | |
2772 | #endif | |
2773 | ||
8d318a50 LW |
2774 | /* Initialization functions. */ |
2775 | ||
2776 | static int __init d40_phy_res_init(struct d40_base *base) | |
2777 | { | |
2778 | int i; | |
2779 | int num_phy_chans_avail = 0; | |
2780 | u32 val[2]; | |
2781 | int odd_even_bit = -2; | |
7fb3e75e | 2782 | int gcc = D40_DREG_GCC_ENA; |
8d318a50 LW |
2783 | |
2784 | val[0] = readl(base->virtbase + D40_DREG_PRSME); | |
2785 | val[1] = readl(base->virtbase + D40_DREG_PRSMO); | |
2786 | ||
2787 | for (i = 0; i < base->num_phy_chans; i++) { | |
2788 | base->phy_res[i].num = i; | |
2789 | odd_even_bit += 2 * ((i % 2) == 0); | |
2790 | if (((val[i % 2] >> odd_even_bit) & 3) == 1) { | |
2791 | /* Mark security only channels as occupied */ | |
2792 | base->phy_res[i].allocated_src = D40_ALLOC_PHY; | |
2793 | base->phy_res[i].allocated_dst = D40_ALLOC_PHY; | |
7fb3e75e N |
2794 | base->phy_res[i].reserved = true; |
2795 | gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i), | |
2796 | D40_DREG_GCC_SRC); | |
2797 | gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i), | |
2798 | D40_DREG_GCC_DST); | |
2799 | ||
2800 | ||
8d318a50 LW |
2801 | } else { |
2802 | base->phy_res[i].allocated_src = D40_ALLOC_FREE; | |
2803 | base->phy_res[i].allocated_dst = D40_ALLOC_FREE; | |
7fb3e75e | 2804 | base->phy_res[i].reserved = false; |
8d318a50 LW |
2805 | num_phy_chans_avail++; |
2806 | } | |
2807 | spin_lock_init(&base->phy_res[i].lock); | |
2808 | } | |
6b7acd84 JA |
2809 | |
2810 | /* Mark disabled channels as occupied */ | |
2811 | for (i = 0; base->plat_data->disabled_channels[i] != -1; i++) { | |
f57b407c RV |
2812 | int chan = base->plat_data->disabled_channels[i]; |
2813 | ||
2814 | base->phy_res[chan].allocated_src = D40_ALLOC_PHY; | |
2815 | base->phy_res[chan].allocated_dst = D40_ALLOC_PHY; | |
7fb3e75e N |
2816 | base->phy_res[chan].reserved = true; |
2817 | gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan), | |
2818 | D40_DREG_GCC_SRC); | |
2819 | gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan), | |
2820 | D40_DREG_GCC_DST); | |
f57b407c | 2821 | num_phy_chans_avail--; |
6b7acd84 JA |
2822 | } |
2823 | ||
8d318a50 LW |
2824 | dev_info(base->dev, "%d of %d physical DMA channels available\n", |
2825 | num_phy_chans_avail, base->num_phy_chans); | |
2826 | ||
2827 | /* Verify settings extended vs standard */ | |
2828 | val[0] = readl(base->virtbase + D40_DREG_PRTYP); | |
2829 | ||
2830 | for (i = 0; i < base->num_phy_chans; i++) { | |
2831 | ||
2832 | if (base->phy_res[i].allocated_src == D40_ALLOC_FREE && | |
2833 | (val[0] & 0x3) != 1) | |
2834 | dev_info(base->dev, | |
2835 | "[%s] INFO: channel %d is misconfigured (%d)\n", | |
2836 | __func__, i, val[0] & 0x3); | |
2837 | ||
2838 | val[0] = val[0] >> 2; | |
2839 | } | |
2840 | ||
7fb3e75e N |
2841 | /* |
2842 | * To keep things simple, Enable all clocks initially. | |
2843 | * The clocks will get managed later post channel allocation. | |
2844 | * The clocks for the event lines on which reserved channels exists | |
2845 | * are not managed here. | |
2846 | */ | |
2847 | writel(D40_DREG_GCC_ENABLE_ALL, base->virtbase + D40_DREG_GCC); | |
2848 | base->gcc_pwr_off_mask = gcc; | |
2849 | ||
8d318a50 LW |
2850 | return num_phy_chans_avail; |
2851 | } | |
2852 | ||
2853 | static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev) | |
2854 | { | |
8d318a50 LW |
2855 | struct stedma40_platform_data *plat_data; |
2856 | struct clk *clk = NULL; | |
2857 | void __iomem *virtbase = NULL; | |
2858 | struct resource *res = NULL; | |
2859 | struct d40_base *base = NULL; | |
2860 | int num_log_chans = 0; | |
2861 | int num_phy_chans; | |
2862 | int i; | |
f4b89764 LW |
2863 | u32 pid; |
2864 | u32 cid; | |
2865 | u8 rev; | |
8d318a50 LW |
2866 | |
2867 | clk = clk_get(&pdev->dev, NULL); | |
2868 | ||
2869 | if (IS_ERR(clk)) { | |
6db5a8ba | 2870 | d40_err(&pdev->dev, "No matching clock found\n"); |
8d318a50 LW |
2871 | goto failure; |
2872 | } | |
2873 | ||
2874 | clk_enable(clk); | |
2875 | ||
2876 | /* Get IO for DMAC base address */ | |
2877 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base"); | |
2878 | if (!res) | |
2879 | goto failure; | |
2880 | ||
2881 | if (request_mem_region(res->start, resource_size(res), | |
2882 | D40_NAME " I/O base") == NULL) | |
2883 | goto failure; | |
2884 | ||
2885 | virtbase = ioremap(res->start, resource_size(res)); | |
2886 | if (!virtbase) | |
2887 | goto failure; | |
2888 | ||
f4b89764 LW |
2889 | /* This is just a regular AMBA PrimeCell ID actually */ |
2890 | for (pid = 0, i = 0; i < 4; i++) | |
2891 | pid |= (readl(virtbase + resource_size(res) - 0x20 + 4 * i) | |
2892 | & 255) << (i * 8); | |
2893 | for (cid = 0, i = 0; i < 4; i++) | |
2894 | cid |= (readl(virtbase + resource_size(res) - 0x10 + 4 * i) | |
2895 | & 255) << (i * 8); | |
8d318a50 | 2896 | |
f4b89764 LW |
2897 | if (cid != AMBA_CID) { |
2898 | d40_err(&pdev->dev, "Unknown hardware! No PrimeCell ID\n"); | |
2899 | goto failure; | |
2900 | } | |
2901 | if (AMBA_MANF_BITS(pid) != AMBA_VENDOR_ST) { | |
6db5a8ba | 2902 | d40_err(&pdev->dev, "Unknown designer! Got %x wanted %x\n", |
f4b89764 LW |
2903 | AMBA_MANF_BITS(pid), |
2904 | AMBA_VENDOR_ST); | |
8d318a50 LW |
2905 | goto failure; |
2906 | } | |
f4b89764 LW |
2907 | /* |
2908 | * HW revision: | |
2909 | * DB8500ed has revision 0 | |
2910 | * ? has revision 1 | |
2911 | * DB8500v1 has revision 2 | |
2912 | * DB8500v2 has revision 3 | |
2913 | */ | |
2914 | rev = AMBA_REV_BITS(pid); | |
3ae0267f | 2915 | |
8d318a50 LW |
2916 | /* The number of physical channels on this HW */ |
2917 | num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4; | |
2918 | ||
2919 | dev_info(&pdev->dev, "hardware revision: %d @ 0x%x\n", | |
3ae0267f | 2920 | rev, res->start); |
8d318a50 LW |
2921 | |
2922 | plat_data = pdev->dev.platform_data; | |
2923 | ||
2924 | /* Count the number of logical channels in use */ | |
2925 | for (i = 0; i < plat_data->dev_len; i++) | |
2926 | if (plat_data->dev_rx[i] != 0) | |
2927 | num_log_chans++; | |
2928 | ||
2929 | for (i = 0; i < plat_data->dev_len; i++) | |
2930 | if (plat_data->dev_tx[i] != 0) | |
2931 | num_log_chans++; | |
2932 | ||
2933 | base = kzalloc(ALIGN(sizeof(struct d40_base), 4) + | |
2934 | (num_phy_chans + num_log_chans + plat_data->memcpy_len) * | |
2935 | sizeof(struct d40_chan), GFP_KERNEL); | |
2936 | ||
2937 | if (base == NULL) { | |
6db5a8ba | 2938 | d40_err(&pdev->dev, "Out of memory\n"); |
8d318a50 LW |
2939 | goto failure; |
2940 | } | |
2941 | ||
3ae0267f | 2942 | base->rev = rev; |
8d318a50 LW |
2943 | base->clk = clk; |
2944 | base->num_phy_chans = num_phy_chans; | |
2945 | base->num_log_chans = num_log_chans; | |
2946 | base->phy_start = res->start; | |
2947 | base->phy_size = resource_size(res); | |
2948 | base->virtbase = virtbase; | |
2949 | base->plat_data = plat_data; | |
2950 | base->dev = &pdev->dev; | |
2951 | base->phy_chans = ((void *)base) + ALIGN(sizeof(struct d40_base), 4); | |
2952 | base->log_chans = &base->phy_chans[num_phy_chans]; | |
2953 | ||
2954 | base->phy_res = kzalloc(num_phy_chans * sizeof(struct d40_phy_res), | |
2955 | GFP_KERNEL); | |
2956 | if (!base->phy_res) | |
2957 | goto failure; | |
2958 | ||
2959 | base->lookup_phy_chans = kzalloc(num_phy_chans * | |
2960 | sizeof(struct d40_chan *), | |
2961 | GFP_KERNEL); | |
2962 | if (!base->lookup_phy_chans) | |
2963 | goto failure; | |
2964 | ||
2965 | if (num_log_chans + plat_data->memcpy_len) { | |
2966 | /* | |
2967 | * The max number of logical channels are event lines for all | |
2968 | * src devices and dst devices | |
2969 | */ | |
2970 | base->lookup_log_chans = kzalloc(plat_data->dev_len * 2 * | |
2971 | sizeof(struct d40_chan *), | |
2972 | GFP_KERNEL); | |
2973 | if (!base->lookup_log_chans) | |
2974 | goto failure; | |
2975 | } | |
698e4732 | 2976 | |
7fb3e75e N |
2977 | base->reg_val_backup_chan = kmalloc(base->num_phy_chans * |
2978 | sizeof(d40_backup_regs_chan), | |
8d318a50 | 2979 | GFP_KERNEL); |
7fb3e75e N |
2980 | if (!base->reg_val_backup_chan) |
2981 | goto failure; | |
2982 | ||
2983 | base->lcla_pool.alloc_map = | |
2984 | kzalloc(num_phy_chans * sizeof(struct d40_desc *) | |
2985 | * D40_LCLA_LINK_PER_EVENT_GRP, GFP_KERNEL); | |
8d318a50 LW |
2986 | if (!base->lcla_pool.alloc_map) |
2987 | goto failure; | |
2988 | ||
c675b1b4 JA |
2989 | base->desc_slab = kmem_cache_create(D40_NAME, sizeof(struct d40_desc), |
2990 | 0, SLAB_HWCACHE_ALIGN, | |
2991 | NULL); | |
2992 | if (base->desc_slab == NULL) | |
2993 | goto failure; | |
2994 | ||
8d318a50 LW |
2995 | return base; |
2996 | ||
2997 | failure: | |
c6134c96 | 2998 | if (!IS_ERR(clk)) { |
8d318a50 LW |
2999 | clk_disable(clk); |
3000 | clk_put(clk); | |
3001 | } | |
3002 | if (virtbase) | |
3003 | iounmap(virtbase); | |
3004 | if (res) | |
3005 | release_mem_region(res->start, | |
3006 | resource_size(res)); | |
3007 | if (virtbase) | |
3008 | iounmap(virtbase); | |
3009 | ||
3010 | if (base) { | |
3011 | kfree(base->lcla_pool.alloc_map); | |
3012 | kfree(base->lookup_log_chans); | |
3013 | kfree(base->lookup_phy_chans); | |
3014 | kfree(base->phy_res); | |
3015 | kfree(base); | |
3016 | } | |
3017 | ||
3018 | return NULL; | |
3019 | } | |
3020 | ||
3021 | static void __init d40_hw_init(struct d40_base *base) | |
3022 | { | |
3023 | ||
7fb3e75e | 3024 | static struct d40_reg_val dma_init_reg[] = { |
8d318a50 | 3025 | /* Clock every part of the DMA block from start */ |
7fb3e75e | 3026 | { .reg = D40_DREG_GCC, .val = D40_DREG_GCC_ENABLE_ALL}, |
8d318a50 LW |
3027 | |
3028 | /* Interrupts on all logical channels */ | |
3029 | { .reg = D40_DREG_LCMIS0, .val = 0xFFFFFFFF}, | |
3030 | { .reg = D40_DREG_LCMIS1, .val = 0xFFFFFFFF}, | |
3031 | { .reg = D40_DREG_LCMIS2, .val = 0xFFFFFFFF}, | |
3032 | { .reg = D40_DREG_LCMIS3, .val = 0xFFFFFFFF}, | |
3033 | { .reg = D40_DREG_LCICR0, .val = 0xFFFFFFFF}, | |
3034 | { .reg = D40_DREG_LCICR1, .val = 0xFFFFFFFF}, | |
3035 | { .reg = D40_DREG_LCICR2, .val = 0xFFFFFFFF}, | |
3036 | { .reg = D40_DREG_LCICR3, .val = 0xFFFFFFFF}, | |
3037 | { .reg = D40_DREG_LCTIS0, .val = 0xFFFFFFFF}, | |
3038 | { .reg = D40_DREG_LCTIS1, .val = 0xFFFFFFFF}, | |
3039 | { .reg = D40_DREG_LCTIS2, .val = 0xFFFFFFFF}, | |
3040 | { .reg = D40_DREG_LCTIS3, .val = 0xFFFFFFFF} | |
3041 | }; | |
3042 | int i; | |
3043 | u32 prmseo[2] = {0, 0}; | |
3044 | u32 activeo[2] = {0xFFFFFFFF, 0xFFFFFFFF}; | |
3045 | u32 pcmis = 0; | |
3046 | u32 pcicr = 0; | |
3047 | ||
3048 | for (i = 0; i < ARRAY_SIZE(dma_init_reg); i++) | |
3049 | writel(dma_init_reg[i].val, | |
3050 | base->virtbase + dma_init_reg[i].reg); | |
3051 | ||
3052 | /* Configure all our dma channels to default settings */ | |
3053 | for (i = 0; i < base->num_phy_chans; i++) { | |
3054 | ||
3055 | activeo[i % 2] = activeo[i % 2] << 2; | |
3056 | ||
3057 | if (base->phy_res[base->num_phy_chans - i - 1].allocated_src | |
3058 | == D40_ALLOC_PHY) { | |
3059 | activeo[i % 2] |= 3; | |
3060 | continue; | |
3061 | } | |
3062 | ||
3063 | /* Enable interrupt # */ | |
3064 | pcmis = (pcmis << 1) | 1; | |
3065 | ||
3066 | /* Clear interrupt # */ | |
3067 | pcicr = (pcicr << 1) | 1; | |
3068 | ||
3069 | /* Set channel to physical mode */ | |
3070 | prmseo[i % 2] = prmseo[i % 2] << 2; | |
3071 | prmseo[i % 2] |= 1; | |
3072 | ||
3073 | } | |
3074 | ||
3075 | writel(prmseo[1], base->virtbase + D40_DREG_PRMSE); | |
3076 | writel(prmseo[0], base->virtbase + D40_DREG_PRMSO); | |
3077 | writel(activeo[1], base->virtbase + D40_DREG_ACTIVE); | |
3078 | writel(activeo[0], base->virtbase + D40_DREG_ACTIVO); | |
3079 | ||
3080 | /* Write which interrupt to enable */ | |
3081 | writel(pcmis, base->virtbase + D40_DREG_PCMIS); | |
3082 | ||
3083 | /* Write which interrupt to clear */ | |
3084 | writel(pcicr, base->virtbase + D40_DREG_PCICR); | |
3085 | ||
3086 | } | |
3087 | ||
508849ad LW |
3088 | static int __init d40_lcla_allocate(struct d40_base *base) |
3089 | { | |
026cbc42 | 3090 | struct d40_lcla_pool *pool = &base->lcla_pool; |
508849ad LW |
3091 | unsigned long *page_list; |
3092 | int i, j; | |
3093 | int ret = 0; | |
3094 | ||
3095 | /* | |
3096 | * This is somewhat ugly. We need 8192 bytes that are 18 bit aligned, | |
3097 | * To full fill this hardware requirement without wasting 256 kb | |
3098 | * we allocate pages until we get an aligned one. | |
3099 | */ | |
3100 | page_list = kmalloc(sizeof(unsigned long) * MAX_LCLA_ALLOC_ATTEMPTS, | |
3101 | GFP_KERNEL); | |
3102 | ||
3103 | if (!page_list) { | |
3104 | ret = -ENOMEM; | |
3105 | goto failure; | |
3106 | } | |
3107 | ||
3108 | /* Calculating how many pages that are required */ | |
3109 | base->lcla_pool.pages = SZ_1K * base->num_phy_chans / PAGE_SIZE; | |
3110 | ||
3111 | for (i = 0; i < MAX_LCLA_ALLOC_ATTEMPTS; i++) { | |
3112 | page_list[i] = __get_free_pages(GFP_KERNEL, | |
3113 | base->lcla_pool.pages); | |
3114 | if (!page_list[i]) { | |
3115 | ||
6db5a8ba RV |
3116 | d40_err(base->dev, "Failed to allocate %d pages.\n", |
3117 | base->lcla_pool.pages); | |
508849ad LW |
3118 | |
3119 | for (j = 0; j < i; j++) | |
3120 | free_pages(page_list[j], base->lcla_pool.pages); | |
3121 | goto failure; | |
3122 | } | |
3123 | ||
3124 | if ((virt_to_phys((void *)page_list[i]) & | |
3125 | (LCLA_ALIGNMENT - 1)) == 0) | |
3126 | break; | |
3127 | } | |
3128 | ||
3129 | for (j = 0; j < i; j++) | |
3130 | free_pages(page_list[j], base->lcla_pool.pages); | |
3131 | ||
3132 | if (i < MAX_LCLA_ALLOC_ATTEMPTS) { | |
3133 | base->lcla_pool.base = (void *)page_list[i]; | |
3134 | } else { | |
767a9675 JA |
3135 | /* |
3136 | * After many attempts and no succees with finding the correct | |
3137 | * alignment, try with allocating a big buffer. | |
3138 | */ | |
508849ad LW |
3139 | dev_warn(base->dev, |
3140 | "[%s] Failed to get %d pages @ 18 bit align.\n", | |
3141 | __func__, base->lcla_pool.pages); | |
3142 | base->lcla_pool.base_unaligned = kmalloc(SZ_1K * | |
3143 | base->num_phy_chans + | |
3144 | LCLA_ALIGNMENT, | |
3145 | GFP_KERNEL); | |
3146 | if (!base->lcla_pool.base_unaligned) { | |
3147 | ret = -ENOMEM; | |
3148 | goto failure; | |
3149 | } | |
3150 | ||
3151 | base->lcla_pool.base = PTR_ALIGN(base->lcla_pool.base_unaligned, | |
3152 | LCLA_ALIGNMENT); | |
3153 | } | |
3154 | ||
026cbc42 RV |
3155 | pool->dma_addr = dma_map_single(base->dev, pool->base, |
3156 | SZ_1K * base->num_phy_chans, | |
3157 | DMA_TO_DEVICE); | |
3158 | if (dma_mapping_error(base->dev, pool->dma_addr)) { | |
3159 | pool->dma_addr = 0; | |
3160 | ret = -ENOMEM; | |
3161 | goto failure; | |
3162 | } | |
3163 | ||
508849ad LW |
3164 | writel(virt_to_phys(base->lcla_pool.base), |
3165 | base->virtbase + D40_DREG_LCLA); | |
3166 | failure: | |
3167 | kfree(page_list); | |
3168 | return ret; | |
3169 | } | |
3170 | ||
8d318a50 LW |
3171 | static int __init d40_probe(struct platform_device *pdev) |
3172 | { | |
3173 | int err; | |
3174 | int ret = -ENOENT; | |
3175 | struct d40_base *base; | |
3176 | struct resource *res = NULL; | |
3177 | int num_reserved_chans; | |
3178 | u32 val; | |
3179 | ||
3180 | base = d40_hw_detect_init(pdev); | |
3181 | ||
3182 | if (!base) | |
3183 | goto failure; | |
3184 | ||
3185 | num_reserved_chans = d40_phy_res_init(base); | |
3186 | ||
3187 | platform_set_drvdata(pdev, base); | |
3188 | ||
3189 | spin_lock_init(&base->interrupt_lock); | |
3190 | spin_lock_init(&base->execmd_lock); | |
3191 | ||
3192 | /* Get IO for logical channel parameter address */ | |
3193 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lcpa"); | |
3194 | if (!res) { | |
3195 | ret = -ENOENT; | |
6db5a8ba | 3196 | d40_err(&pdev->dev, "No \"lcpa\" memory resource\n"); |
8d318a50 LW |
3197 | goto failure; |
3198 | } | |
3199 | base->lcpa_size = resource_size(res); | |
3200 | base->phy_lcpa = res->start; | |
3201 | ||
3202 | if (request_mem_region(res->start, resource_size(res), | |
3203 | D40_NAME " I/O lcpa") == NULL) { | |
3204 | ret = -EBUSY; | |
6db5a8ba RV |
3205 | d40_err(&pdev->dev, |
3206 | "Failed to request LCPA region 0x%x-0x%x\n", | |
3207 | res->start, res->end); | |
8d318a50 LW |
3208 | goto failure; |
3209 | } | |
3210 | ||
3211 | /* We make use of ESRAM memory for this. */ | |
3212 | val = readl(base->virtbase + D40_DREG_LCPA); | |
3213 | if (res->start != val && val != 0) { | |
3214 | dev_warn(&pdev->dev, | |
3215 | "[%s] Mismatch LCPA dma 0x%x, def 0x%x\n", | |
3216 | __func__, val, res->start); | |
3217 | } else | |
3218 | writel(res->start, base->virtbase + D40_DREG_LCPA); | |
3219 | ||
3220 | base->lcpa_base = ioremap(res->start, resource_size(res)); | |
3221 | if (!base->lcpa_base) { | |
3222 | ret = -ENOMEM; | |
6db5a8ba | 3223 | d40_err(&pdev->dev, "Failed to ioremap LCPA region\n"); |
8d318a50 LW |
3224 | goto failure; |
3225 | } | |
28c7a19d N |
3226 | /* If lcla has to be located in ESRAM we don't need to allocate */ |
3227 | if (base->plat_data->use_esram_lcla) { | |
3228 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, | |
3229 | "lcla_esram"); | |
3230 | if (!res) { | |
3231 | ret = -ENOENT; | |
3232 | d40_err(&pdev->dev, | |
3233 | "No \"lcla_esram\" memory resource\n"); | |
3234 | goto failure; | |
3235 | } | |
3236 | base->lcla_pool.base = ioremap(res->start, | |
3237 | resource_size(res)); | |
3238 | if (!base->lcla_pool.base) { | |
3239 | ret = -ENOMEM; | |
3240 | d40_err(&pdev->dev, "Failed to ioremap LCLA region\n"); | |
3241 | goto failure; | |
3242 | } | |
3243 | writel(res->start, base->virtbase + D40_DREG_LCLA); | |
8d318a50 | 3244 | |
28c7a19d N |
3245 | } else { |
3246 | ret = d40_lcla_allocate(base); | |
3247 | if (ret) { | |
3248 | d40_err(&pdev->dev, "Failed to allocate LCLA area\n"); | |
3249 | goto failure; | |
3250 | } | |
8d318a50 LW |
3251 | } |
3252 | ||
3253 | spin_lock_init(&base->lcla_pool.lock); | |
3254 | ||
8d318a50 LW |
3255 | base->irq = platform_get_irq(pdev, 0); |
3256 | ||
3257 | ret = request_irq(base->irq, d40_handle_interrupt, 0, D40_NAME, base); | |
8d318a50 | 3258 | if (ret) { |
6db5a8ba | 3259 | d40_err(&pdev->dev, "No IRQ defined\n"); |
8d318a50 LW |
3260 | goto failure; |
3261 | } | |
3262 | ||
7fb3e75e N |
3263 | pm_runtime_irq_safe(base->dev); |
3264 | pm_runtime_set_autosuspend_delay(base->dev, DMA40_AUTOSUSPEND_DELAY); | |
3265 | pm_runtime_use_autosuspend(base->dev); | |
3266 | pm_runtime_enable(base->dev); | |
3267 | pm_runtime_resume(base->dev); | |
28c7a19d N |
3268 | |
3269 | if (base->plat_data->use_esram_lcla) { | |
3270 | ||
3271 | base->lcpa_regulator = regulator_get(base->dev, "lcla_esram"); | |
3272 | if (IS_ERR(base->lcpa_regulator)) { | |
3273 | d40_err(&pdev->dev, "Failed to get lcpa_regulator\n"); | |
3274 | base->lcpa_regulator = NULL; | |
3275 | goto failure; | |
3276 | } | |
3277 | ||
3278 | ret = regulator_enable(base->lcpa_regulator); | |
3279 | if (ret) { | |
3280 | d40_err(&pdev->dev, | |
3281 | "Failed to enable lcpa_regulator\n"); | |
3282 | regulator_put(base->lcpa_regulator); | |
3283 | base->lcpa_regulator = NULL; | |
3284 | goto failure; | |
3285 | } | |
3286 | } | |
3287 | ||
7fb3e75e | 3288 | base->initialized = true; |
8d318a50 LW |
3289 | err = d40_dmaengine_init(base, num_reserved_chans); |
3290 | if (err) | |
3291 | goto failure; | |
3292 | ||
3293 | d40_hw_init(base); | |
3294 | ||
3295 | dev_info(base->dev, "initialized\n"); | |
3296 | return 0; | |
3297 | ||
3298 | failure: | |
3299 | if (base) { | |
c675b1b4 JA |
3300 | if (base->desc_slab) |
3301 | kmem_cache_destroy(base->desc_slab); | |
8d318a50 LW |
3302 | if (base->virtbase) |
3303 | iounmap(base->virtbase); | |
026cbc42 | 3304 | |
28c7a19d N |
3305 | if (base->lcla_pool.base && base->plat_data->use_esram_lcla) { |
3306 | iounmap(base->lcla_pool.base); | |
3307 | base->lcla_pool.base = NULL; | |
3308 | } | |
3309 | ||
026cbc42 RV |
3310 | if (base->lcla_pool.dma_addr) |
3311 | dma_unmap_single(base->dev, base->lcla_pool.dma_addr, | |
3312 | SZ_1K * base->num_phy_chans, | |
3313 | DMA_TO_DEVICE); | |
3314 | ||
508849ad LW |
3315 | if (!base->lcla_pool.base_unaligned && base->lcla_pool.base) |
3316 | free_pages((unsigned long)base->lcla_pool.base, | |
3317 | base->lcla_pool.pages); | |
767a9675 JA |
3318 | |
3319 | kfree(base->lcla_pool.base_unaligned); | |
3320 | ||
8d318a50 LW |
3321 | if (base->phy_lcpa) |
3322 | release_mem_region(base->phy_lcpa, | |
3323 | base->lcpa_size); | |
3324 | if (base->phy_start) | |
3325 | release_mem_region(base->phy_start, | |
3326 | base->phy_size); | |
3327 | if (base->clk) { | |
3328 | clk_disable(base->clk); | |
3329 | clk_put(base->clk); | |
3330 | } | |
3331 | ||
28c7a19d N |
3332 | if (base->lcpa_regulator) { |
3333 | regulator_disable(base->lcpa_regulator); | |
3334 | regulator_put(base->lcpa_regulator); | |
3335 | } | |
3336 | ||
8d318a50 LW |
3337 | kfree(base->lcla_pool.alloc_map); |
3338 | kfree(base->lookup_log_chans); | |
3339 | kfree(base->lookup_phy_chans); | |
3340 | kfree(base->phy_res); | |
3341 | kfree(base); | |
3342 | } | |
3343 | ||
6db5a8ba | 3344 | d40_err(&pdev->dev, "probe failed\n"); |
8d318a50 LW |
3345 | return ret; |
3346 | } | |
3347 | ||
3348 | static struct platform_driver d40_driver = { | |
3349 | .driver = { | |
3350 | .owner = THIS_MODULE, | |
3351 | .name = D40_NAME, | |
7fb3e75e | 3352 | .pm = DMA40_PM_OPS, |
8d318a50 LW |
3353 | }, |
3354 | }; | |
3355 | ||
cb9ab2d8 | 3356 | static int __init stedma40_init(void) |
8d318a50 LW |
3357 | { |
3358 | return platform_driver_probe(&d40_driver, d40_probe); | |
3359 | } | |
a0eb221a | 3360 | subsys_initcall(stedma40_init); |