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mfd: mfd_cell is now implicitly available to timberdale drivers
[deliverable/linux.git] / drivers / dma / timb_dma.c
CommitLineData
de5d4453
RR		 1/*
2 * timb_dma.c timberdale FPGA DMA driver
3 * Copyright (c) 2010 Intel Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19/* Supports:
20 * Timberdale FPGA DMA engine
21 */
22
23#include <linux/dmaengine.h>
24#include <linux/dma-mapping.h>
25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/io.h>
28#include <linux/module.h>
29#include <linux/platform_device.h>
e46dccff 30#include <linux/mfd/core.h>
6a3cd3ea 31#include <linux/slab.h>
de5d4453
RR		 32
33#include <linux/timb_dma.h>
34
35#define DRIVER_NAME "timb-dma"
36
37/* Global DMA registers */
38#define TIMBDMA_ACR 0x34
39#define TIMBDMA_32BIT_ADDR 0x01
40
41#define TIMBDMA_ISR 0x080000
42#define TIMBDMA_IPR 0x080004
43#define TIMBDMA_IER 0x080008
44
45/* Channel specific registers */
46/* RX instances base addresses are 0x00, 0x40, 0x80 ...
47 * TX instances base addresses are 0x18, 0x58, 0x98 ...
48 */
49#define TIMBDMA_INSTANCE_OFFSET 0x40
50#define TIMBDMA_INSTANCE_TX_OFFSET 0x18
51
52/* RX registers, relative the instance base */
53#define TIMBDMA_OFFS_RX_DHAR 0x00
54#define TIMBDMA_OFFS_RX_DLAR 0x04
55#define TIMBDMA_OFFS_RX_LR 0x0C
56#define TIMBDMA_OFFS_RX_BLR 0x10
57#define TIMBDMA_OFFS_RX_ER 0x14
58#define TIMBDMA_RX_EN 0x01
59/* bytes per Row, video specific register
60 * which is placed after the TX registers...
61 */
62#define TIMBDMA_OFFS_RX_BPRR 0x30
63
64/* TX registers, relative the instance base */
65#define TIMBDMA_OFFS_TX_DHAR 0x00
66#define TIMBDMA_OFFS_TX_DLAR 0x04
67#define TIMBDMA_OFFS_TX_BLR 0x0C
68#define TIMBDMA_OFFS_TX_LR 0x14
69
70
71#define TIMB_DMA_DESC_SIZE 8
72
73struct timb_dma_desc {
74 struct list_head desc_node;
75 struct dma_async_tx_descriptor txd;
76 u8 *desc_list;
77 unsigned int desc_list_len;
78 bool interrupt;
79};
80
81struct timb_dma_chan {
82 struct dma_chan chan;
83 void __iomem *membase;
0f65169b
RR		 84 spinlock_t lock; /* Used to protect data structures,
85 especially the lists and descriptors,
86 from races between the tasklet and calls
87 from above */
de5d4453
RR		 88 dma_cookie_t last_completed_cookie;
89 bool ongoing;
90 struct list_head active_list;
91 struct list_head queue;
92 struct list_head free_list;
93 unsigned int bytes_per_line;
94 enum dma_data_direction direction;
95 unsigned int descs; /* Descriptors to allocate */
96 unsigned int desc_elems; /* number of elems per descriptor */
97};
98
99struct timb_dma {
100 struct dma_device dma;
101 void __iomem *membase;
102 struct tasklet_struct tasklet;
103 struct timb_dma_chan channels[0];
104};
105
106static struct device *chan2dev(struct dma_chan *chan)
107{
108 return &chan->dev->device;
109}
110static struct device *chan2dmadev(struct dma_chan *chan)
111{
112 return chan2dev(chan)->parent->parent;
113}
114
115static struct timb_dma *tdchantotd(struct timb_dma_chan *td_chan)
116{
117 int id = td_chan->chan.chan_id;
118 return (struct timb_dma *)((u8 *)td_chan -
119 id * sizeof(struct timb_dma_chan) - sizeof(struct timb_dma));
120}
121
122/* Must be called with the spinlock held */
123static void __td_enable_chan_irq(struct timb_dma_chan *td_chan)
124{
125 int id = td_chan->chan.chan_id;
126 struct timb_dma *td = tdchantotd(td_chan);
127 u32 ier;
128
129 /* enable interrupt for this channel */
130 ier = ioread32(td->membase + TIMBDMA_IER);
131 ier |= 1 << id;
132 dev_dbg(chan2dev(&td_chan->chan), "Enabling irq: %d, IER: 0x%x\n", id,
133 ier);
134 iowrite32(ier, td->membase + TIMBDMA_IER);
135}
136
137/* Should be called with the spinlock held */
138static bool __td_dma_done_ack(struct timb_dma_chan *td_chan)
139{
140 int id = td_chan->chan.chan_id;
141 struct timb_dma *td = (struct timb_dma *)((u8 *)td_chan -
142 id * sizeof(struct timb_dma_chan) - sizeof(struct timb_dma));
143 u32 isr;
144 bool done = false;
145
146 dev_dbg(chan2dev(&td_chan->chan), "Checking irq: %d, td: %p\n", id, td);
147
148 isr = ioread32(td->membase + TIMBDMA_ISR) & (1 << id);
149 if (isr) {
150 iowrite32(isr, td->membase + TIMBDMA_ISR);
151 done = true;
152 }
153
154 return done;
155}
156
157static void __td_unmap_desc(struct timb_dma_chan *td_chan, const u8 *dma_desc,
158 bool single)
159{
160 dma_addr_t addr;
161 int len;
162
163 addr = (dma_desc[7] << 24) | (dma_desc[6] << 16) | (dma_desc[5] << 8) |
164 dma_desc[4];
165
166 len = (dma_desc[3] << 8) | dma_desc[2];
167
168 if (single)
169 dma_unmap_single(chan2dev(&td_chan->chan), addr, len,
170 td_chan->direction);
171 else
172 dma_unmap_page(chan2dev(&td_chan->chan), addr, len,
173 td_chan->direction);
174}
175
176static void __td_unmap_descs(struct timb_dma_desc *td_desc, bool single)
177{
178 struct timb_dma_chan *td_chan = container_of(td_desc->txd.chan,
179 struct timb_dma_chan, chan);
180 u8 *descs;
181
182 for (descs = td_desc->desc_list; ; descs += TIMB_DMA_DESC_SIZE) {
183 __td_unmap_desc(td_chan, descs, single);
184 if (descs[0] & 0x02)
185 break;
186 }
187}
188
189static int td_fill_desc(struct timb_dma_chan *td_chan, u8 *dma_desc,
190 struct scatterlist *sg, bool last)
191{
4be929be 192 if (sg_dma_len(sg) > USHRT_MAX) {
de5d4453
RR		 193 dev_err(chan2dev(&td_chan->chan), "Too big sg element\n");
194 return -EINVAL;
195 }
196
197 /* length must be word aligned */
198 if (sg_dma_len(sg) % sizeof(u32)) {
199 dev_err(chan2dev(&td_chan->chan), "Incorrect length: %d\n",
200 sg_dma_len(sg));
201 return -EINVAL;
202 }
203
efcc2898
DC		 204 dev_dbg(chan2dev(&td_chan->chan), "desc: %p, addr: 0x%llx\n",
205 dma_desc, (unsigned long long)sg_dma_address(sg));
de5d4453
RR		 206
207 dma_desc[7] = (sg_dma_address(sg) >> 24) & 0xff;
208 dma_desc[6] = (sg_dma_address(sg) >> 16) & 0xff;
209 dma_desc[5] = (sg_dma_address(sg) >> 8) & 0xff;
210 dma_desc[4] = (sg_dma_address(sg) >> 0) & 0xff;
211
212 dma_desc[3] = (sg_dma_len(sg) >> 8) & 0xff;
213 dma_desc[2] = (sg_dma_len(sg) >> 0) & 0xff;
214
215 dma_desc[1] = 0x00;
216 dma_desc[0] = 0x21 | (last ? 0x02 : 0); /* tran, valid */
217
218 return 0;
219}
220
221/* Must be called with the spinlock held */
222static void __td_start_dma(struct timb_dma_chan *td_chan)
223{
224 struct timb_dma_desc *td_desc;
225
226 if (td_chan->ongoing) {
227 dev_err(chan2dev(&td_chan->chan),
228 "Transfer already ongoing\n");
229 return;
230 }
231
232 td_desc = list_entry(td_chan->active_list.next, struct timb_dma_desc,
233 desc_node);
234
235 dev_dbg(chan2dev(&td_chan->chan),
236 "td_chan: %p, chan: %d, membase: %p\n",
237 td_chan, td_chan->chan.chan_id, td_chan->membase);
238
239 if (td_chan->direction == DMA_FROM_DEVICE) {
240
241 /* descriptor address */
242 iowrite32(0, td_chan->membase + TIMBDMA_OFFS_RX_DHAR);
243 iowrite32(td_desc->txd.phys, td_chan->membase +
244 TIMBDMA_OFFS_RX_DLAR);
245 /* Bytes per line */
246 iowrite32(td_chan->bytes_per_line, td_chan->membase +
247 TIMBDMA_OFFS_RX_BPRR);
248 /* enable RX */
249 iowrite32(TIMBDMA_RX_EN, td_chan->membase + TIMBDMA_OFFS_RX_ER);
250 } else {
251 /* address high */
252 iowrite32(0, td_chan->membase + TIMBDMA_OFFS_TX_DHAR);
253 iowrite32(td_desc->txd.phys, td_chan->membase +
254 TIMBDMA_OFFS_TX_DLAR);
255 }
256
257 td_chan->ongoing = true;
258
259 if (td_desc->interrupt)
260 __td_enable_chan_irq(td_chan);
261}
262
263static void __td_finish(struct timb_dma_chan *td_chan)
264{
265 dma_async_tx_callback callback;
266 void *param;
267 struct dma_async_tx_descriptor *txd;
268 struct timb_dma_desc *td_desc;
269
270 /* can happen if the descriptor is canceled */
271 if (list_empty(&td_chan->active_list))
272 return;
273
274 td_desc = list_entry(td_chan->active_list.next, struct timb_dma_desc,
275 desc_node);
276 txd = &td_desc->txd;
277
278 dev_dbg(chan2dev(&td_chan->chan), "descriptor %u complete\n",
279 txd->cookie);
280
281 /* make sure to stop the transfer */
282 if (td_chan->direction == DMA_FROM_DEVICE)
283 iowrite32(0, td_chan->membase + TIMBDMA_OFFS_RX_ER);
284/* Currently no support for stopping DMA transfers
285 else
286 iowrite32(0, td_chan->membase + TIMBDMA_OFFS_TX_DLAR);
287*/
288 td_chan->last_completed_cookie = txd->cookie;
289 td_chan->ongoing = false;
290
291 callback = txd->callback;
292 param = txd->callback_param;
293
294 list_move(&td_desc->desc_node, &td_chan->free_list);
295
296 if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP))
297 __td_unmap_descs(td_desc,
298 txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE);
299
300 /*
301 * The API requires that no submissions are done from a
302 * callback, so we don't need to drop the lock here
303 */
304 if (callback)
305 callback(param);
306}
307
308static u32 __td_ier_mask(struct timb_dma *td)
309{
310 int i;
311 u32 ret = 0;
312
313 for (i = 0; i < td->dma.chancnt; i++) {
314 struct timb_dma_chan *td_chan = td->channels + i;
315 if (td_chan->ongoing) {
316 struct timb_dma_desc *td_desc =
317 list_entry(td_chan->active_list.next,
318 struct timb_dma_desc, desc_node);
319 if (td_desc->interrupt)
320 ret |= 1 << i;
321 }
322 }
323
324 return ret;
325}
326
327static void __td_start_next(struct timb_dma_chan *td_chan)
328{
329 struct timb_dma_desc *td_desc;
330
331 BUG_ON(list_empty(&td_chan->queue));
332 BUG_ON(td_chan->ongoing);
333
334 td_desc = list_entry(td_chan->queue.next, struct timb_dma_desc,
335 desc_node);
336
337 dev_dbg(chan2dev(&td_chan->chan), "%s: started %u\n",
338 __func__, td_desc->txd.cookie);
339
340 list_move(&td_desc->desc_node, &td_chan->active_list);
341 __td_start_dma(td_chan);
342}
343
344static dma_cookie_t td_tx_submit(struct dma_async_tx_descriptor *txd)
345{
346 struct timb_dma_desc *td_desc = container_of(txd, struct timb_dma_desc,
347 txd);
348 struct timb_dma_chan *td_chan = container_of(txd->chan,
349 struct timb_dma_chan, chan);
350 dma_cookie_t cookie;
351
352 spin_lock_bh(&td_chan->lock);
353
354 cookie = txd->chan->cookie;
355 if (++cookie < 0)
356 cookie = 1;
357 txd->chan->cookie = cookie;
358 txd->cookie = cookie;
359
360 if (list_empty(&td_chan->active_list)) {
361 dev_dbg(chan2dev(txd->chan), "%s: started %u\n", __func__,
362 txd->cookie);
363 list_add_tail(&td_desc->desc_node, &td_chan->active_list);
364 __td_start_dma(td_chan);
365 } else {
366 dev_dbg(chan2dev(txd->chan), "tx_submit: queued %u\n",
367 txd->cookie);
368
369 list_add_tail(&td_desc->desc_node, &td_chan->queue);
370 }
371
372 spin_unlock_bh(&td_chan->lock);
373
374 return cookie;
375}
376
377static struct timb_dma_desc *td_alloc_init_desc(struct timb_dma_chan *td_chan)
378{
379 struct dma_chan *chan = &td_chan->chan;
380 struct timb_dma_desc *td_desc;
381 int err;
382
383 td_desc = kzalloc(sizeof(struct timb_dma_desc), GFP_KERNEL);
384 if (!td_desc) {
385 dev_err(chan2dev(chan), "Failed to alloc descriptor\n");
48568005 386 goto out;
de5d4453
RR		 387 }
388
389 td_desc->desc_list_len = td_chan->desc_elems * TIMB_DMA_DESC_SIZE;
390
391 td_desc->desc_list = kzalloc(td_desc->desc_list_len, GFP_KERNEL);
392 if (!td_desc->desc_list) {
393 dev_err(chan2dev(chan), "Failed to alloc descriptor\n");
394 goto err;
395 }
396
397 dma_async_tx_descriptor_init(&td_desc->txd, chan);
398 td_desc->txd.tx_submit = td_tx_submit;
399 td_desc->txd.flags = DMA_CTRL_ACK;
400
401 td_desc->txd.phys = dma_map_single(chan2dmadev(chan),
402 td_desc->desc_list, td_desc->desc_list_len, DMA_TO_DEVICE);
403
404 err = dma_mapping_error(chan2dmadev(chan), td_desc->txd.phys);
405 if (err) {
406 dev_err(chan2dev(chan), "DMA mapping error: %d\n", err);
407 goto err;
408 }
409
410 return td_desc;
411err:
412 kfree(td_desc->desc_list);
413 kfree(td_desc);
48568005 414out:
de5d4453
RR		 415 return NULL;
416
417}
418
419static void td_free_desc(struct timb_dma_desc *td_desc)
420{
421 dev_dbg(chan2dev(td_desc->txd.chan), "Freeing desc: %p\n", td_desc);
422 dma_unmap_single(chan2dmadev(td_desc->txd.chan), td_desc->txd.phys,
423 td_desc->desc_list_len, DMA_TO_DEVICE);
424
425 kfree(td_desc->desc_list);
426 kfree(td_desc);
427}
428
429static void td_desc_put(struct timb_dma_chan *td_chan,
430 struct timb_dma_desc *td_desc)
431{
432 dev_dbg(chan2dev(&td_chan->chan), "Putting desc: %p\n", td_desc);
433
434 spin_lock_bh(&td_chan->lock);
435 list_add(&td_desc->desc_node, &td_chan->free_list);
436 spin_unlock_bh(&td_chan->lock);
437}
438
439static struct timb_dma_desc *td_desc_get(struct timb_dma_chan *td_chan)
440{
441 struct timb_dma_desc *td_desc, *_td_desc;
442 struct timb_dma_desc *ret = NULL;
443
444 spin_lock_bh(&td_chan->lock);
445 list_for_each_entry_safe(td_desc, _td_desc, &td_chan->free_list,
446 desc_node) {
447 if (async_tx_test_ack(&td_desc->txd)) {
448 list_del(&td_desc->desc_node);
449 ret = td_desc;
450 break;
451 }
452 dev_dbg(chan2dev(&td_chan->chan), "desc %p not ACKed\n",
453 td_desc);
454 }
455 spin_unlock_bh(&td_chan->lock);
456
457 return ret;
458}
459
460static int td_alloc_chan_resources(struct dma_chan *chan)
461{
462 struct timb_dma_chan *td_chan =
463 container_of(chan, struct timb_dma_chan, chan);
464 int i;
465
466 dev_dbg(chan2dev(chan), "%s: entry\n", __func__);
467
468 BUG_ON(!list_empty(&td_chan->free_list));
469 for (i = 0; i < td_chan->descs; i++) {
470 struct timb_dma_desc *td_desc = td_alloc_init_desc(td_chan);
471 if (!td_desc) {
472 if (i)
473 break;
474 else {
475 dev_err(chan2dev(chan),
476 "Couldnt allocate any descriptors\n");
477 return -ENOMEM;
478 }
479 }
480
481 td_desc_put(td_chan, td_desc);
482 }
483
484 spin_lock_bh(&td_chan->lock);
485 td_chan->last_completed_cookie = 1;
486 chan->cookie = 1;
487 spin_unlock_bh(&td_chan->lock);
488
489 return 0;
490}
491
492static void td_free_chan_resources(struct dma_chan *chan)
493{
494 struct timb_dma_chan *td_chan =
495 container_of(chan, struct timb_dma_chan, chan);
496 struct timb_dma_desc *td_desc, *_td_desc;
497 LIST_HEAD(list);
498
499 dev_dbg(chan2dev(chan), "%s: Entry\n", __func__);
500
501 /* check that all descriptors are free */
502 BUG_ON(!list_empty(&td_chan->active_list));
503 BUG_ON(!list_empty(&td_chan->queue));
504
505 spin_lock_bh(&td_chan->lock);
506 list_splice_init(&td_chan->free_list, &list);
507 spin_unlock_bh(&td_chan->lock);
508
509 list_for_each_entry_safe(td_desc, _td_desc, &list, desc_node) {
510 dev_dbg(chan2dev(chan), "%s: Freeing desc: %p\n", __func__,
511 td_desc);
512 td_free_desc(td_desc);
513 }
514}
515
07934481
LW		 516static enum dma_status td_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
517 struct dma_tx_state *txstate)
de5d4453
RR		 518{
519 struct timb_dma_chan *td_chan =
520 container_of(chan, struct timb_dma_chan, chan);
521 dma_cookie_t last_used;
522 dma_cookie_t last_complete;
523 int ret;
524
525 dev_dbg(chan2dev(chan), "%s: Entry\n", __func__);
526
527 last_complete = td_chan->last_completed_cookie;
528 last_used = chan->cookie;
529
530 ret = dma_async_is_complete(cookie, last_complete, last_used);
531
bca34692 532 dma_set_tx_state(txstate, last_complete, last_used, 0);
de5d4453
RR		 533
534 dev_dbg(chan2dev(chan),
535 "%s: exit, ret: %d, last_complete: %d, last_used: %d\n",
536 __func__, ret, last_complete, last_used);
537
538 return ret;
539}
540
541static void td_issue_pending(struct dma_chan *chan)
542{
543 struct timb_dma_chan *td_chan =
544 container_of(chan, struct timb_dma_chan, chan);
545
546 dev_dbg(chan2dev(chan), "%s: Entry\n", __func__);
547 spin_lock_bh(&td_chan->lock);
548
549 if (!list_empty(&td_chan->active_list))
550 /* transfer ongoing */
551 if (__td_dma_done_ack(td_chan))
552 __td_finish(td_chan);
553
554 if (list_empty(&td_chan->active_list) && !list_empty(&td_chan->queue))
555 __td_start_next(td_chan);
556
557 spin_unlock_bh(&td_chan->lock);
558}
559
560static struct dma_async_tx_descriptor *td_prep_slave_sg(struct dma_chan *chan,
561 struct scatterlist *sgl, unsigned int sg_len,
562 enum dma_data_direction direction, unsigned long flags)
563{
564 struct timb_dma_chan *td_chan =
565 container_of(chan, struct timb_dma_chan, chan);
566 struct timb_dma_desc *td_desc;
567 struct scatterlist *sg;
568 unsigned int i;
569 unsigned int desc_usage = 0;
570
571 if (!sgl || !sg_len) {
572 dev_err(chan2dev(chan), "%s: No SG list\n", __func__);
573 return NULL;
574 }
575
576 /* even channels are for RX, odd for TX */
577 if (td_chan->direction != direction) {
578 dev_err(chan2dev(chan),
579 "Requesting channel in wrong direction\n");
580 return NULL;
581 }
582
583 td_desc = td_desc_get(td_chan);
584 if (!td_desc) {
585 dev_err(chan2dev(chan), "Not enough descriptors available\n");
586 return NULL;
587 }
588
589 td_desc->interrupt = (flags & DMA_PREP_INTERRUPT) != 0;
590
591 for_each_sg(sgl, sg, sg_len, i) {
592 int err;
593 if (desc_usage > td_desc->desc_list_len) {
594 dev_err(chan2dev(chan), "No descriptor space\n");
595 return NULL;
596 }
597
598 err = td_fill_desc(td_chan, td_desc->desc_list + desc_usage, sg,
599 i == (sg_len - 1));
600 if (err) {
601 dev_err(chan2dev(chan), "Failed to update desc: %d\n",
602 err);
603 td_desc_put(td_chan, td_desc);
604 return NULL;
605 }
606 desc_usage += TIMB_DMA_DESC_SIZE;
607 }
608
609 dma_sync_single_for_device(chan2dmadev(chan), td_desc->txd.phys,
610 td_desc->desc_list_len, DMA_TO_DEVICE);
611
612 return &td_desc->txd;
613}
614
05827630
LW		 615static int td_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
616 unsigned long arg)
de5d4453
RR		 617{
618 struct timb_dma_chan *td_chan =
619 container_of(chan, struct timb_dma_chan, chan);
620 struct timb_dma_desc *td_desc, *_td_desc;
621
622 dev_dbg(chan2dev(chan), "%s: Entry\n", __func__);
623
c3635c78
LW		 624 if (cmd != DMA_TERMINATE_ALL)
625 return -ENXIO;
626
de5d4453
RR		 627 /* first the easy part, put the queue into the free list */
628 spin_lock_bh(&td_chan->lock);
629 list_for_each_entry_safe(td_desc, _td_desc, &td_chan->queue,
630 desc_node)
631 list_move(&td_desc->desc_node, &td_chan->free_list);
632
ae0e47f0 633 /* now tear down the running */
de5d4453
RR		 634 __td_finish(td_chan);
635 spin_unlock_bh(&td_chan->lock);
c3635c78
LW		 636
637 return 0;
de5d4453
RR		 638}
639
640static void td_tasklet(unsigned long data)
641{
642 struct timb_dma *td = (struct timb_dma *)data;
643 u32 isr;
644 u32 ipr;
645 u32 ier;
646 int i;
647
648 isr = ioread32(td->membase + TIMBDMA_ISR);
649 ipr = isr & __td_ier_mask(td);
650
651 /* ack the interrupts */
652 iowrite32(ipr, td->membase + TIMBDMA_ISR);
653
654 for (i = 0; i < td->dma.chancnt; i++)
655 if (ipr & (1 << i)) {
656 struct timb_dma_chan *td_chan = td->channels + i;
657 spin_lock(&td_chan->lock);
658 __td_finish(td_chan);
659 if (!list_empty(&td_chan->queue))
660 __td_start_next(td_chan);
661 spin_unlock(&td_chan->lock);
662 }
663
664 ier = __td_ier_mask(td);
665 iowrite32(ier, td->membase + TIMBDMA_IER);
666}
667
668
669static irqreturn_t td_irq(int irq, void *devid)
670{
671 struct timb_dma *td = devid;
672 u32 ipr = ioread32(td->membase + TIMBDMA_IPR);
673
674 if (ipr) {
675 /* disable interrupts, will be re-enabled in tasklet */
676 iowrite32(0, td->membase + TIMBDMA_IER);
677
678 tasklet_schedule(&td->tasklet);
679
680 return IRQ_HANDLED;
681 } else
682 return IRQ_NONE;
683}
684
685
686static int __devinit td_probe(struct platform_device *pdev)
687{
e46dccff 688 struct timb_dma_platform_data *pdata = mfd_get_data(pdev);
de5d4453
RR		 689 struct timb_dma *td;
690 struct resource *iomem;
691 int irq;
692 int err;
693 int i;
694
695 if (!pdata) {
696 dev_err(&pdev->dev, "No platform data\n");
697 return -EINVAL;
698 }
699
700 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
701 if (!iomem)
702 return -EINVAL;
703
704 irq = platform_get_irq(pdev, 0);
705 if (irq < 0)
706 return irq;
707
708 if (!request_mem_region(iomem->start, resource_size(iomem),
709 DRIVER_NAME))
710 return -EBUSY;
711
712 td = kzalloc(sizeof(struct timb_dma) +
713 sizeof(struct timb_dma_chan) * pdata->nr_channels, GFP_KERNEL);
714 if (!td) {
715 err = -ENOMEM;
716 goto err_release_region;
717 }
718
719 dev_dbg(&pdev->dev, "Allocated TD: %p\n", td);
720
721 td->membase = ioremap(iomem->start, resource_size(iomem));
722 if (!td->membase) {
723 dev_err(&pdev->dev, "Failed to remap I/O memory\n");
724 err = -ENOMEM;
725 goto err_free_mem;
726 }
727
728 /* 32bit addressing */
729 iowrite32(TIMBDMA_32BIT_ADDR, td->membase + TIMBDMA_ACR);
730
731 /* disable and clear any interrupts */
732 iowrite32(0x0, td->membase + TIMBDMA_IER);
733 iowrite32(0xFFFFFFFF, td->membase + TIMBDMA_ISR);
734
735 tasklet_init(&td->tasklet, td_tasklet, (unsigned long)td);
736
737 err = request_irq(irq, td_irq, IRQF_SHARED, DRIVER_NAME, td);
738 if (err) {
739 dev_err(&pdev->dev, "Failed to request IRQ\n");
740 goto err_tasklet_kill;
741 }
742
743 td->dma.device_alloc_chan_resources = td_alloc_chan_resources;
744 td->dma.device_free_chan_resources = td_free_chan_resources;
07934481 745 td->dma.device_tx_status = td_tx_status;
de5d4453
RR		 746 td->dma.device_issue_pending = td_issue_pending;
747
748 dma_cap_set(DMA_SLAVE, td->dma.cap_mask);
749 dma_cap_set(DMA_PRIVATE, td->dma.cap_mask);
750 td->dma.device_prep_slave_sg = td_prep_slave_sg;
c3635c78 751 td->dma.device_control = td_control;
de5d4453
RR		 752
753 td->dma.dev = &pdev->dev;
754
755 INIT_LIST_HEAD(&td->dma.channels);
756
757 for (i = 0; i < pdata->nr_channels; i++, td->dma.chancnt++) {
758 struct timb_dma_chan *td_chan = &td->channels[i];
759 struct timb_dma_platform_data_channel *pchan =
760 pdata->channels + i;
761
762 /* even channels are RX, odd are TX */
9cb047d4 763 if ((i % 2) == pchan->rx) {
de5d4453
RR		 764 dev_err(&pdev->dev, "Wrong channel configuration\n");
765 err = -EINVAL;
766 goto err_tasklet_kill;
767 }
768
769 td_chan->chan.device = &td->dma;
770 td_chan->chan.cookie = 1;
771 td_chan->chan.chan_id = i;
772 spin_lock_init(&td_chan->lock);
773 INIT_LIST_HEAD(&td_chan->active_list);
774 INIT_LIST_HEAD(&td_chan->queue);
775 INIT_LIST_HEAD(&td_chan->free_list);
776
777 td_chan->descs = pchan->descriptors;
778 td_chan->desc_elems = pchan->descriptor_elements;
779 td_chan->bytes_per_line = pchan->bytes_per_line;
780 td_chan->direction = pchan->rx ? DMA_FROM_DEVICE :
781 DMA_TO_DEVICE;
782
783 td_chan->membase = td->membase +
784 (i / 2) * TIMBDMA_INSTANCE_OFFSET +
785 (pchan->rx ? 0 : TIMBDMA_INSTANCE_TX_OFFSET);
786
787 dev_dbg(&pdev->dev, "Chan: %d, membase: %p\n",
788 i, td_chan->membase);
789
790 list_add_tail(&td_chan->chan.device_node, &td->dma.channels);
791 }
792
793 err = dma_async_device_register(&td->dma);
794 if (err) {
795 dev_err(&pdev->dev, "Failed to register async device\n");
796 goto err_free_irq;
797 }
798
799 platform_set_drvdata(pdev, td);
800
801 dev_dbg(&pdev->dev, "Probe result: %d\n", err);
802 return err;
803
804err_free_irq:
805 free_irq(irq, td);
806err_tasklet_kill:
807 tasklet_kill(&td->tasklet);
808 iounmap(td->membase);
809err_free_mem:
810 kfree(td);
811err_release_region:
812 release_mem_region(iomem->start, resource_size(iomem));
813
814 return err;
815
816}
817
818static int __devexit td_remove(struct platform_device *pdev)
819{
820 struct timb_dma *td = platform_get_drvdata(pdev);
821 struct resource *iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
822 int irq = platform_get_irq(pdev, 0);
823
824 dma_async_device_unregister(&td->dma);
825 free_irq(irq, td);
826 tasklet_kill(&td->tasklet);
827 iounmap(td->membase);
828 kfree(td);
829 release_mem_region(iomem->start, resource_size(iomem));
830
831 platform_set_drvdata(pdev, NULL);
832
833 dev_dbg(&pdev->dev, "Removed...\n");
834 return 0;
835}
836
837static struct platform_driver td_driver = {
838 .driver = {
839 .name = DRIVER_NAME,
840 .owner = THIS_MODULE,
841 },
842 .probe = td_probe,
843 .remove = __exit_p(td_remove),
844};
845
846static int __init td_init(void)
847{
848 return platform_driver_register(&td_driver);
849}
850module_init(td_init);
851
852static void __exit td_exit(void)
853{
854 platform_driver_unregister(&td_driver);
855}
856module_exit(td_exit);
857
858MODULE_LICENSE("GPL v2");
859MODULE_DESCRIPTION("Timberdale DMA controller driver");
860MODULE_AUTHOR("Pelagicore AB <info@pelagicore.com>");
861MODULE_ALIAS("platform:"DRIVER_NAME);
Linux kernel - Deliverables
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