Commit | Line | Data |
---|---|---|
2bc65418 | 1 | #include "amd64_edac.h" |
23ac4ae8 | 2 | #include <asm/amd_nb.h> |
2bc65418 | 3 | |
d1ea71cd | 4 | static struct edac_pci_ctl_info *pci_ctl; |
2bc65418 DT |
5 | |
6 | static int report_gart_errors; | |
7 | module_param(report_gart_errors, int, 0644); | |
8 | ||
9 | /* | |
10 | * Set by command line parameter. If BIOS has enabled the ECC, this override is | |
11 | * cleared to prevent re-enabling the hardware by this driver. | |
12 | */ | |
13 | static int ecc_enable_override; | |
14 | module_param(ecc_enable_override, int, 0644); | |
15 | ||
a29d8b8e | 16 | static struct msr __percpu *msrs; |
50542251 | 17 | |
360b7f3c BP |
18 | /* |
19 | * count successfully initialized driver instances for setup_pci_device() | |
20 | */ | |
21 | static atomic_t drv_instances = ATOMIC_INIT(0); | |
22 | ||
cc4d8860 BP |
23 | /* Per-node driver instances */ |
24 | static struct mem_ctl_info **mcis; | |
ae7bb7c6 | 25 | static struct ecc_settings **ecc_stngs; |
2bc65418 | 26 | |
b70ef010 BP |
27 | /* |
28 | * Valid scrub rates for the K8 hardware memory scrubber. We map the scrubbing | |
29 | * bandwidth to a valid bit pattern. The 'set' operation finds the 'matching- | |
30 | * or higher value'. | |
31 | * | |
32 | *FIXME: Produce a better mapping/linearisation. | |
33 | */ | |
c7e5301a | 34 | static const struct scrubrate { |
39094443 BP |
35 | u32 scrubval; /* bit pattern for scrub rate */ |
36 | u32 bandwidth; /* bandwidth consumed (bytes/sec) */ | |
37 | } scrubrates[] = { | |
b70ef010 BP |
38 | { 0x01, 1600000000UL}, |
39 | { 0x02, 800000000UL}, | |
40 | { 0x03, 400000000UL}, | |
41 | { 0x04, 200000000UL}, | |
42 | { 0x05, 100000000UL}, | |
43 | { 0x06, 50000000UL}, | |
44 | { 0x07, 25000000UL}, | |
45 | { 0x08, 12284069UL}, | |
46 | { 0x09, 6274509UL}, | |
47 | { 0x0A, 3121951UL}, | |
48 | { 0x0B, 1560975UL}, | |
49 | { 0x0C, 781440UL}, | |
50 | { 0x0D, 390720UL}, | |
51 | { 0x0E, 195300UL}, | |
52 | { 0x0F, 97650UL}, | |
53 | { 0x10, 48854UL}, | |
54 | { 0x11, 24427UL}, | |
55 | { 0x12, 12213UL}, | |
56 | { 0x13, 6101UL}, | |
57 | { 0x14, 3051UL}, | |
58 | { 0x15, 1523UL}, | |
59 | { 0x16, 761UL}, | |
60 | { 0x00, 0UL}, /* scrubbing off */ | |
61 | }; | |
62 | ||
66fed2d4 BP |
63 | int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset, |
64 | u32 *val, const char *func) | |
b2b0c605 BP |
65 | { |
66 | int err = 0; | |
67 | ||
68 | err = pci_read_config_dword(pdev, offset, val); | |
69 | if (err) | |
70 | amd64_warn("%s: error reading F%dx%03x.\n", | |
71 | func, PCI_FUNC(pdev->devfn), offset); | |
72 | ||
73 | return err; | |
74 | } | |
75 | ||
76 | int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset, | |
77 | u32 val, const char *func) | |
78 | { | |
79 | int err = 0; | |
80 | ||
81 | err = pci_write_config_dword(pdev, offset, val); | |
82 | if (err) | |
83 | amd64_warn("%s: error writing to F%dx%03x.\n", | |
84 | func, PCI_FUNC(pdev->devfn), offset); | |
85 | ||
86 | return err; | |
87 | } | |
88 | ||
7981a28f AG |
89 | /* |
90 | * Select DCT to which PCI cfg accesses are routed | |
91 | */ | |
92 | static void f15h_select_dct(struct amd64_pvt *pvt, u8 dct) | |
93 | { | |
94 | u32 reg = 0; | |
95 | ||
96 | amd64_read_pci_cfg(pvt->F1, DCT_CFG_SEL, ®); | |
97 | reg &= (pvt->model == 0x30) ? ~3 : ~1; | |
98 | reg |= dct; | |
99 | amd64_write_pci_cfg(pvt->F1, DCT_CFG_SEL, reg); | |
100 | } | |
101 | ||
b2b0c605 BP |
102 | /* |
103 | * | |
104 | * Depending on the family, F2 DCT reads need special handling: | |
105 | * | |
7981a28f | 106 | * K8: has a single DCT only and no address offsets >= 0x100 |
b2b0c605 BP |
107 | * |
108 | * F10h: each DCT has its own set of regs | |
109 | * DCT0 -> F2x040.. | |
110 | * DCT1 -> F2x140.. | |
111 | * | |
94c1acf2 | 112 | * F16h: has only 1 DCT |
7981a28f AG |
113 | * |
114 | * F15h: we select which DCT we access using F1x10C[DctCfgSel] | |
b2b0c605 | 115 | */ |
7981a28f AG |
116 | static inline int amd64_read_dct_pci_cfg(struct amd64_pvt *pvt, u8 dct, |
117 | int offset, u32 *val) | |
b2b0c605 | 118 | { |
7981a28f AG |
119 | switch (pvt->fam) { |
120 | case 0xf: | |
121 | if (dct || offset >= 0x100) | |
122 | return -EINVAL; | |
123 | break; | |
b2b0c605 | 124 | |
7981a28f AG |
125 | case 0x10: |
126 | if (dct) { | |
127 | /* | |
128 | * Note: If ganging is enabled, barring the regs | |
129 | * F2x[1,0]98 and F2x[1,0]9C; reads reads to F2x1xx | |
130 | * return 0. (cf. Section 2.8.1 F10h BKDG) | |
131 | */ | |
132 | if (dct_ganging_enabled(pvt)) | |
133 | return 0; | |
b2b0c605 | 134 | |
7981a28f AG |
135 | offset += 0x100; |
136 | } | |
137 | break; | |
73ba8593 | 138 | |
7981a28f AG |
139 | case 0x15: |
140 | /* | |
141 | * F15h: F2x1xx addresses do not map explicitly to DCT1. | |
142 | * We should select which DCT we access using F1x10C[DctCfgSel] | |
143 | */ | |
144 | dct = (dct && pvt->model == 0x30) ? 3 : dct; | |
145 | f15h_select_dct(pvt, dct); | |
146 | break; | |
73ba8593 | 147 | |
7981a28f AG |
148 | case 0x16: |
149 | if (dct) | |
150 | return -EINVAL; | |
151 | break; | |
b2b0c605 | 152 | |
7981a28f AG |
153 | default: |
154 | break; | |
b2b0c605 | 155 | } |
7981a28f | 156 | return amd64_read_pci_cfg(pvt->F2, offset, val); |
b2b0c605 BP |
157 | } |
158 | ||
2bc65418 DT |
159 | /* |
160 | * Memory scrubber control interface. For K8, memory scrubbing is handled by | |
161 | * hardware and can involve L2 cache, dcache as well as the main memory. With | |
162 | * F10, this is extended to L3 cache scrubbing on CPU models sporting that | |
163 | * functionality. | |
164 | * | |
165 | * This causes the "units" for the scrubbing speed to vary from 64 byte blocks | |
166 | * (dram) over to cache lines. This is nasty, so we will use bandwidth in | |
167 | * bytes/sec for the setting. | |
168 | * | |
169 | * Currently, we only do dram scrubbing. If the scrubbing is done in software on | |
170 | * other archs, we might not have access to the caches directly. | |
171 | */ | |
172 | ||
173 | /* | |
174 | * scan the scrub rate mapping table for a close or matching bandwidth value to | |
175 | * issue. If requested is too big, then use last maximum value found. | |
176 | */ | |
d1ea71cd | 177 | static int __set_scrub_rate(struct pci_dev *ctl, u32 new_bw, u32 min_rate) |
2bc65418 DT |
178 | { |
179 | u32 scrubval; | |
180 | int i; | |
181 | ||
182 | /* | |
183 | * map the configured rate (new_bw) to a value specific to the AMD64 | |
184 | * memory controller and apply to register. Search for the first | |
185 | * bandwidth entry that is greater or equal than the setting requested | |
186 | * and program that. If at last entry, turn off DRAM scrubbing. | |
168bfeef AM |
187 | * |
188 | * If no suitable bandwidth is found, turn off DRAM scrubbing entirely | |
189 | * by falling back to the last element in scrubrates[]. | |
2bc65418 | 190 | */ |
168bfeef | 191 | for (i = 0; i < ARRAY_SIZE(scrubrates) - 1; i++) { |
2bc65418 DT |
192 | /* |
193 | * skip scrub rates which aren't recommended | |
194 | * (see F10 BKDG, F3x58) | |
195 | */ | |
395ae783 | 196 | if (scrubrates[i].scrubval < min_rate) |
2bc65418 DT |
197 | continue; |
198 | ||
199 | if (scrubrates[i].bandwidth <= new_bw) | |
200 | break; | |
2bc65418 DT |
201 | } |
202 | ||
203 | scrubval = scrubrates[i].scrubval; | |
2bc65418 | 204 | |
5980bb9c | 205 | pci_write_bits32(ctl, SCRCTRL, scrubval, 0x001F); |
2bc65418 | 206 | |
39094443 BP |
207 | if (scrubval) |
208 | return scrubrates[i].bandwidth; | |
209 | ||
2bc65418 DT |
210 | return 0; |
211 | } | |
212 | ||
d1ea71cd | 213 | static int set_scrub_rate(struct mem_ctl_info *mci, u32 bw) |
2bc65418 DT |
214 | { |
215 | struct amd64_pvt *pvt = mci->pvt_info; | |
87b3e0e6 | 216 | u32 min_scrubrate = 0x5; |
2bc65418 | 217 | |
a4b4bedc | 218 | if (pvt->fam == 0xf) |
87b3e0e6 BP |
219 | min_scrubrate = 0x0; |
220 | ||
3f0aba4f BP |
221 | /* Erratum #505 */ |
222 | if (pvt->fam == 0x15 && pvt->model < 0x10) | |
73ba8593 BP |
223 | f15h_select_dct(pvt, 0); |
224 | ||
d1ea71cd | 225 | return __set_scrub_rate(pvt->F3, bw, min_scrubrate); |
2bc65418 DT |
226 | } |
227 | ||
d1ea71cd | 228 | static int get_scrub_rate(struct mem_ctl_info *mci) |
2bc65418 DT |
229 | { |
230 | struct amd64_pvt *pvt = mci->pvt_info; | |
231 | u32 scrubval = 0; | |
39094443 | 232 | int i, retval = -EINVAL; |
2bc65418 | 233 | |
3f0aba4f BP |
234 | /* Erratum #505 */ |
235 | if (pvt->fam == 0x15 && pvt->model < 0x10) | |
73ba8593 BP |
236 | f15h_select_dct(pvt, 0); |
237 | ||
5980bb9c | 238 | amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval); |
2bc65418 DT |
239 | |
240 | scrubval = scrubval & 0x001F; | |
241 | ||
926311fd | 242 | for (i = 0; i < ARRAY_SIZE(scrubrates); i++) { |
2bc65418 | 243 | if (scrubrates[i].scrubval == scrubval) { |
39094443 | 244 | retval = scrubrates[i].bandwidth; |
2bc65418 DT |
245 | break; |
246 | } | |
247 | } | |
39094443 | 248 | return retval; |
2bc65418 DT |
249 | } |
250 | ||
6775763a | 251 | /* |
7f19bf75 BP |
252 | * returns true if the SysAddr given by sys_addr matches the |
253 | * DRAM base/limit associated with node_id | |
6775763a | 254 | */ |
d1ea71cd | 255 | static bool base_limit_match(struct amd64_pvt *pvt, u64 sys_addr, u8 nid) |
6775763a | 256 | { |
7f19bf75 | 257 | u64 addr; |
6775763a DT |
258 | |
259 | /* The K8 treats this as a 40-bit value. However, bits 63-40 will be | |
260 | * all ones if the most significant implemented address bit is 1. | |
261 | * Here we discard bits 63-40. See section 3.4.2 of AMD publication | |
262 | * 24592: AMD x86-64 Architecture Programmer's Manual Volume 1 | |
263 | * Application Programming. | |
264 | */ | |
265 | addr = sys_addr & 0x000000ffffffffffull; | |
266 | ||
7f19bf75 BP |
267 | return ((addr >= get_dram_base(pvt, nid)) && |
268 | (addr <= get_dram_limit(pvt, nid))); | |
6775763a DT |
269 | } |
270 | ||
271 | /* | |
272 | * Attempt to map a SysAddr to a node. On success, return a pointer to the | |
273 | * mem_ctl_info structure for the node that the SysAddr maps to. | |
274 | * | |
275 | * On failure, return NULL. | |
276 | */ | |
277 | static struct mem_ctl_info *find_mc_by_sys_addr(struct mem_ctl_info *mci, | |
278 | u64 sys_addr) | |
279 | { | |
280 | struct amd64_pvt *pvt; | |
c7e5301a | 281 | u8 node_id; |
6775763a DT |
282 | u32 intlv_en, bits; |
283 | ||
284 | /* | |
285 | * Here we use the DRAM Base (section 3.4.4.1) and DRAM Limit (section | |
286 | * 3.4.4.2) registers to map the SysAddr to a node ID. | |
287 | */ | |
288 | pvt = mci->pvt_info; | |
289 | ||
290 | /* | |
291 | * The value of this field should be the same for all DRAM Base | |
292 | * registers. Therefore we arbitrarily choose to read it from the | |
293 | * register for node 0. | |
294 | */ | |
7f19bf75 | 295 | intlv_en = dram_intlv_en(pvt, 0); |
6775763a DT |
296 | |
297 | if (intlv_en == 0) { | |
7f19bf75 | 298 | for (node_id = 0; node_id < DRAM_RANGES; node_id++) { |
d1ea71cd | 299 | if (base_limit_match(pvt, sys_addr, node_id)) |
8edc5445 | 300 | goto found; |
6775763a | 301 | } |
8edc5445 | 302 | goto err_no_match; |
6775763a DT |
303 | } |
304 | ||
72f158fe BP |
305 | if (unlikely((intlv_en != 0x01) && |
306 | (intlv_en != 0x03) && | |
307 | (intlv_en != 0x07))) { | |
24f9a7fe | 308 | amd64_warn("DRAM Base[IntlvEn] junk value: 0x%x, BIOS bug?\n", intlv_en); |
6775763a DT |
309 | return NULL; |
310 | } | |
311 | ||
312 | bits = (((u32) sys_addr) >> 12) & intlv_en; | |
313 | ||
314 | for (node_id = 0; ; ) { | |
7f19bf75 | 315 | if ((dram_intlv_sel(pvt, node_id) & intlv_en) == bits) |
6775763a DT |
316 | break; /* intlv_sel field matches */ |
317 | ||
7f19bf75 | 318 | if (++node_id >= DRAM_RANGES) |
6775763a DT |
319 | goto err_no_match; |
320 | } | |
321 | ||
322 | /* sanity test for sys_addr */ | |
d1ea71cd | 323 | if (unlikely(!base_limit_match(pvt, sys_addr, node_id))) { |
24f9a7fe BP |
324 | amd64_warn("%s: sys_addr 0x%llx falls outside base/limit address" |
325 | "range for node %d with node interleaving enabled.\n", | |
326 | __func__, sys_addr, node_id); | |
6775763a DT |
327 | return NULL; |
328 | } | |
329 | ||
330 | found: | |
b487c33e | 331 | return edac_mc_find((int)node_id); |
6775763a DT |
332 | |
333 | err_no_match: | |
956b9ba1 JP |
334 | edac_dbg(2, "sys_addr 0x%lx doesn't match any node\n", |
335 | (unsigned long)sys_addr); | |
6775763a DT |
336 | |
337 | return NULL; | |
338 | } | |
e2ce7255 DT |
339 | |
340 | /* | |
11c75ead BP |
341 | * compute the CS base address of the @csrow on the DRAM controller @dct. |
342 | * For details see F2x[5C:40] in the processor's BKDG | |
e2ce7255 | 343 | */ |
11c75ead BP |
344 | static void get_cs_base_and_mask(struct amd64_pvt *pvt, int csrow, u8 dct, |
345 | u64 *base, u64 *mask) | |
e2ce7255 | 346 | { |
11c75ead BP |
347 | u64 csbase, csmask, base_bits, mask_bits; |
348 | u8 addr_shift; | |
e2ce7255 | 349 | |
18b94f66 | 350 | if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) { |
11c75ead BP |
351 | csbase = pvt->csels[dct].csbases[csrow]; |
352 | csmask = pvt->csels[dct].csmasks[csrow]; | |
10ef6b0d CG |
353 | base_bits = GENMASK_ULL(31, 21) | GENMASK_ULL(15, 9); |
354 | mask_bits = GENMASK_ULL(29, 21) | GENMASK_ULL(15, 9); | |
11c75ead | 355 | addr_shift = 4; |
94c1acf2 AG |
356 | |
357 | /* | |
18b94f66 AG |
358 | * F16h and F15h, models 30h and later need two addr_shift values: |
359 | * 8 for high and 6 for low (cf. F16h BKDG). | |
360 | */ | |
361 | } else if (pvt->fam == 0x16 || | |
362 | (pvt->fam == 0x15 && pvt->model >= 0x30)) { | |
94c1acf2 AG |
363 | csbase = pvt->csels[dct].csbases[csrow]; |
364 | csmask = pvt->csels[dct].csmasks[csrow >> 1]; | |
365 | ||
10ef6b0d CG |
366 | *base = (csbase & GENMASK_ULL(15, 5)) << 6; |
367 | *base |= (csbase & GENMASK_ULL(30, 19)) << 8; | |
94c1acf2 AG |
368 | |
369 | *mask = ~0ULL; | |
370 | /* poke holes for the csmask */ | |
10ef6b0d CG |
371 | *mask &= ~((GENMASK_ULL(15, 5) << 6) | |
372 | (GENMASK_ULL(30, 19) << 8)); | |
94c1acf2 | 373 | |
10ef6b0d CG |
374 | *mask |= (csmask & GENMASK_ULL(15, 5)) << 6; |
375 | *mask |= (csmask & GENMASK_ULL(30, 19)) << 8; | |
94c1acf2 AG |
376 | |
377 | return; | |
11c75ead BP |
378 | } else { |
379 | csbase = pvt->csels[dct].csbases[csrow]; | |
380 | csmask = pvt->csels[dct].csmasks[csrow >> 1]; | |
381 | addr_shift = 8; | |
e2ce7255 | 382 | |
a4b4bedc | 383 | if (pvt->fam == 0x15) |
10ef6b0d CG |
384 | base_bits = mask_bits = |
385 | GENMASK_ULL(30,19) | GENMASK_ULL(13,5); | |
11c75ead | 386 | else |
10ef6b0d CG |
387 | base_bits = mask_bits = |
388 | GENMASK_ULL(28,19) | GENMASK_ULL(13,5); | |
11c75ead | 389 | } |
e2ce7255 | 390 | |
11c75ead | 391 | *base = (csbase & base_bits) << addr_shift; |
e2ce7255 | 392 | |
11c75ead BP |
393 | *mask = ~0ULL; |
394 | /* poke holes for the csmask */ | |
395 | *mask &= ~(mask_bits << addr_shift); | |
396 | /* OR them in */ | |
397 | *mask |= (csmask & mask_bits) << addr_shift; | |
e2ce7255 DT |
398 | } |
399 | ||
11c75ead BP |
400 | #define for_each_chip_select(i, dct, pvt) \ |
401 | for (i = 0; i < pvt->csels[dct].b_cnt; i++) | |
402 | ||
614ec9d8 BP |
403 | #define chip_select_base(i, dct, pvt) \ |
404 | pvt->csels[dct].csbases[i] | |
405 | ||
11c75ead BP |
406 | #define for_each_chip_select_mask(i, dct, pvt) \ |
407 | for (i = 0; i < pvt->csels[dct].m_cnt; i++) | |
408 | ||
e2ce7255 DT |
409 | /* |
410 | * @input_addr is an InputAddr associated with the node given by mci. Return the | |
411 | * csrow that input_addr maps to, or -1 on failure (no csrow claims input_addr). | |
412 | */ | |
413 | static int input_addr_to_csrow(struct mem_ctl_info *mci, u64 input_addr) | |
414 | { | |
415 | struct amd64_pvt *pvt; | |
416 | int csrow; | |
417 | u64 base, mask; | |
418 | ||
419 | pvt = mci->pvt_info; | |
420 | ||
11c75ead BP |
421 | for_each_chip_select(csrow, 0, pvt) { |
422 | if (!csrow_enabled(csrow, 0, pvt)) | |
e2ce7255 DT |
423 | continue; |
424 | ||
11c75ead BP |
425 | get_cs_base_and_mask(pvt, csrow, 0, &base, &mask); |
426 | ||
427 | mask = ~mask; | |
e2ce7255 DT |
428 | |
429 | if ((input_addr & mask) == (base & mask)) { | |
956b9ba1 JP |
430 | edac_dbg(2, "InputAddr 0x%lx matches csrow %d (node %d)\n", |
431 | (unsigned long)input_addr, csrow, | |
432 | pvt->mc_node_id); | |
e2ce7255 DT |
433 | |
434 | return csrow; | |
435 | } | |
436 | } | |
956b9ba1 JP |
437 | edac_dbg(2, "no matching csrow for InputAddr 0x%lx (MC node %d)\n", |
438 | (unsigned long)input_addr, pvt->mc_node_id); | |
e2ce7255 DT |
439 | |
440 | return -1; | |
441 | } | |
442 | ||
e2ce7255 DT |
443 | /* |
444 | * Obtain info from the DRAM Hole Address Register (section 3.4.8, pub #26094) | |
445 | * for the node represented by mci. Info is passed back in *hole_base, | |
446 | * *hole_offset, and *hole_size. Function returns 0 if info is valid or 1 if | |
447 | * info is invalid. Info may be invalid for either of the following reasons: | |
448 | * | |
449 | * - The revision of the node is not E or greater. In this case, the DRAM Hole | |
450 | * Address Register does not exist. | |
451 | * | |
452 | * - The DramHoleValid bit is cleared in the DRAM Hole Address Register, | |
453 | * indicating that its contents are not valid. | |
454 | * | |
455 | * The values passed back in *hole_base, *hole_offset, and *hole_size are | |
456 | * complete 32-bit values despite the fact that the bitfields in the DHAR | |
457 | * only represent bits 31-24 of the base and offset values. | |
458 | */ | |
459 | int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base, | |
460 | u64 *hole_offset, u64 *hole_size) | |
461 | { | |
462 | struct amd64_pvt *pvt = mci->pvt_info; | |
e2ce7255 DT |
463 | |
464 | /* only revE and later have the DRAM Hole Address Register */ | |
a4b4bedc | 465 | if (pvt->fam == 0xf && pvt->ext_model < K8_REV_E) { |
956b9ba1 JP |
466 | edac_dbg(1, " revision %d for node %d does not support DHAR\n", |
467 | pvt->ext_model, pvt->mc_node_id); | |
e2ce7255 DT |
468 | return 1; |
469 | } | |
470 | ||
bc21fa57 | 471 | /* valid for Fam10h and above */ |
a4b4bedc | 472 | if (pvt->fam >= 0x10 && !dhar_mem_hoist_valid(pvt)) { |
956b9ba1 | 473 | edac_dbg(1, " Dram Memory Hoisting is DISABLED on this system\n"); |
e2ce7255 DT |
474 | return 1; |
475 | } | |
476 | ||
c8e518d5 | 477 | if (!dhar_valid(pvt)) { |
956b9ba1 JP |
478 | edac_dbg(1, " Dram Memory Hoisting is DISABLED on this node %d\n", |
479 | pvt->mc_node_id); | |
e2ce7255 DT |
480 | return 1; |
481 | } | |
482 | ||
483 | /* This node has Memory Hoisting */ | |
484 | ||
485 | /* +------------------+--------------------+--------------------+----- | |
486 | * | memory | DRAM hole | relocated | | |
487 | * | [0, (x - 1)] | [x, 0xffffffff] | addresses from | | |
488 | * | | | DRAM hole | | |
489 | * | | | [0x100000000, | | |
490 | * | | | (0x100000000+ | | |
491 | * | | | (0xffffffff-x))] | | |
492 | * +------------------+--------------------+--------------------+----- | |
493 | * | |
494 | * Above is a diagram of physical memory showing the DRAM hole and the | |
495 | * relocated addresses from the DRAM hole. As shown, the DRAM hole | |
496 | * starts at address x (the base address) and extends through address | |
497 | * 0xffffffff. The DRAM Hole Address Register (DHAR) relocates the | |
498 | * addresses in the hole so that they start at 0x100000000. | |
499 | */ | |
500 | ||
1f31677e BP |
501 | *hole_base = dhar_base(pvt); |
502 | *hole_size = (1ULL << 32) - *hole_base; | |
e2ce7255 | 503 | |
a4b4bedc BP |
504 | *hole_offset = (pvt->fam > 0xf) ? f10_dhar_offset(pvt) |
505 | : k8_dhar_offset(pvt); | |
e2ce7255 | 506 | |
956b9ba1 JP |
507 | edac_dbg(1, " DHAR info for node %d base 0x%lx offset 0x%lx size 0x%lx\n", |
508 | pvt->mc_node_id, (unsigned long)*hole_base, | |
509 | (unsigned long)*hole_offset, (unsigned long)*hole_size); | |
e2ce7255 DT |
510 | |
511 | return 0; | |
512 | } | |
513 | EXPORT_SYMBOL_GPL(amd64_get_dram_hole_info); | |
514 | ||
93c2df58 DT |
515 | /* |
516 | * Return the DramAddr that the SysAddr given by @sys_addr maps to. It is | |
517 | * assumed that sys_addr maps to the node given by mci. | |
518 | * | |
519 | * The first part of section 3.4.4 (p. 70) shows how the DRAM Base (section | |
520 | * 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers are used to translate a | |
521 | * SysAddr to a DramAddr. If the DRAM Hole Address Register (DHAR) is enabled, | |
522 | * then it is also involved in translating a SysAddr to a DramAddr. Sections | |
523 | * 3.4.8 and 3.5.8.2 describe the DHAR and how it is used for memory hoisting. | |
524 | * These parts of the documentation are unclear. I interpret them as follows: | |
525 | * | |
526 | * When node n receives a SysAddr, it processes the SysAddr as follows: | |
527 | * | |
528 | * 1. It extracts the DRAMBase and DRAMLimit values from the DRAM Base and DRAM | |
529 | * Limit registers for node n. If the SysAddr is not within the range | |
530 | * specified by the base and limit values, then node n ignores the Sysaddr | |
531 | * (since it does not map to node n). Otherwise continue to step 2 below. | |
532 | * | |
533 | * 2. If the DramHoleValid bit of the DHAR for node n is clear, the DHAR is | |
534 | * disabled so skip to step 3 below. Otherwise see if the SysAddr is within | |
535 | * the range of relocated addresses (starting at 0x100000000) from the DRAM | |
536 | * hole. If not, skip to step 3 below. Else get the value of the | |
537 | * DramHoleOffset field from the DHAR. To obtain the DramAddr, subtract the | |
538 | * offset defined by this value from the SysAddr. | |
539 | * | |
540 | * 3. Obtain the base address for node n from the DRAMBase field of the DRAM | |
541 | * Base register for node n. To obtain the DramAddr, subtract the base | |
542 | * address from the SysAddr, as shown near the start of section 3.4.4 (p.70). | |
543 | */ | |
544 | static u64 sys_addr_to_dram_addr(struct mem_ctl_info *mci, u64 sys_addr) | |
545 | { | |
7f19bf75 | 546 | struct amd64_pvt *pvt = mci->pvt_info; |
93c2df58 | 547 | u64 dram_base, hole_base, hole_offset, hole_size, dram_addr; |
1f31677e | 548 | int ret; |
93c2df58 | 549 | |
7f19bf75 | 550 | dram_base = get_dram_base(pvt, pvt->mc_node_id); |
93c2df58 DT |
551 | |
552 | ret = amd64_get_dram_hole_info(mci, &hole_base, &hole_offset, | |
553 | &hole_size); | |
554 | if (!ret) { | |
1f31677e BP |
555 | if ((sys_addr >= (1ULL << 32)) && |
556 | (sys_addr < ((1ULL << 32) + hole_size))) { | |
93c2df58 DT |
557 | /* use DHAR to translate SysAddr to DramAddr */ |
558 | dram_addr = sys_addr - hole_offset; | |
559 | ||
956b9ba1 JP |
560 | edac_dbg(2, "using DHAR to translate SysAddr 0x%lx to DramAddr 0x%lx\n", |
561 | (unsigned long)sys_addr, | |
562 | (unsigned long)dram_addr); | |
93c2df58 DT |
563 | |
564 | return dram_addr; | |
565 | } | |
566 | } | |
567 | ||
568 | /* | |
569 | * Translate the SysAddr to a DramAddr as shown near the start of | |
570 | * section 3.4.4 (p. 70). Although sys_addr is a 64-bit value, the k8 | |
571 | * only deals with 40-bit values. Therefore we discard bits 63-40 of | |
572 | * sys_addr below. If bit 39 of sys_addr is 1 then the bits we | |
573 | * discard are all 1s. Otherwise the bits we discard are all 0s. See | |
574 | * section 3.4.2 of AMD publication 24592: AMD x86-64 Architecture | |
575 | * Programmer's Manual Volume 1 Application Programming. | |
576 | */ | |
10ef6b0d | 577 | dram_addr = (sys_addr & GENMASK_ULL(39, 0)) - dram_base; |
93c2df58 | 578 | |
956b9ba1 JP |
579 | edac_dbg(2, "using DRAM Base register to translate SysAddr 0x%lx to DramAddr 0x%lx\n", |
580 | (unsigned long)sys_addr, (unsigned long)dram_addr); | |
93c2df58 DT |
581 | return dram_addr; |
582 | } | |
583 | ||
584 | /* | |
585 | * @intlv_en is the value of the IntlvEn field from a DRAM Base register | |
586 | * (section 3.4.4.1). Return the number of bits from a SysAddr that are used | |
587 | * for node interleaving. | |
588 | */ | |
589 | static int num_node_interleave_bits(unsigned intlv_en) | |
590 | { | |
591 | static const int intlv_shift_table[] = { 0, 1, 0, 2, 0, 0, 0, 3 }; | |
592 | int n; | |
593 | ||
594 | BUG_ON(intlv_en > 7); | |
595 | n = intlv_shift_table[intlv_en]; | |
596 | return n; | |
597 | } | |
598 | ||
599 | /* Translate the DramAddr given by @dram_addr to an InputAddr. */ | |
600 | static u64 dram_addr_to_input_addr(struct mem_ctl_info *mci, u64 dram_addr) | |
601 | { | |
602 | struct amd64_pvt *pvt; | |
603 | int intlv_shift; | |
604 | u64 input_addr; | |
605 | ||
606 | pvt = mci->pvt_info; | |
607 | ||
608 | /* | |
609 | * See the start of section 3.4.4 (p. 70, BKDG #26094, K8, revA-E) | |
610 | * concerning translating a DramAddr to an InputAddr. | |
611 | */ | |
7f19bf75 | 612 | intlv_shift = num_node_interleave_bits(dram_intlv_en(pvt, 0)); |
10ef6b0d | 613 | input_addr = ((dram_addr >> intlv_shift) & GENMASK_ULL(35, 12)) + |
f678b8cc | 614 | (dram_addr & 0xfff); |
93c2df58 | 615 | |
956b9ba1 JP |
616 | edac_dbg(2, " Intlv Shift=%d DramAddr=0x%lx maps to InputAddr=0x%lx\n", |
617 | intlv_shift, (unsigned long)dram_addr, | |
618 | (unsigned long)input_addr); | |
93c2df58 DT |
619 | |
620 | return input_addr; | |
621 | } | |
622 | ||
623 | /* | |
624 | * Translate the SysAddr represented by @sys_addr to an InputAddr. It is | |
625 | * assumed that @sys_addr maps to the node given by mci. | |
626 | */ | |
627 | static u64 sys_addr_to_input_addr(struct mem_ctl_info *mci, u64 sys_addr) | |
628 | { | |
629 | u64 input_addr; | |
630 | ||
631 | input_addr = | |
632 | dram_addr_to_input_addr(mci, sys_addr_to_dram_addr(mci, sys_addr)); | |
633 | ||
956b9ba1 JP |
634 | edac_dbg(2, "SysAdddr 0x%lx translates to InputAddr 0x%lx\n", |
635 | (unsigned long)sys_addr, (unsigned long)input_addr); | |
93c2df58 DT |
636 | |
637 | return input_addr; | |
638 | } | |
639 | ||
93c2df58 DT |
640 | /* Map the Error address to a PAGE and PAGE OFFSET. */ |
641 | static inline void error_address_to_page_and_offset(u64 error_address, | |
33ca0643 | 642 | struct err_info *err) |
93c2df58 | 643 | { |
33ca0643 BP |
644 | err->page = (u32) (error_address >> PAGE_SHIFT); |
645 | err->offset = ((u32) error_address) & ~PAGE_MASK; | |
93c2df58 DT |
646 | } |
647 | ||
648 | /* | |
649 | * @sys_addr is an error address (a SysAddr) extracted from the MCA NB Address | |
650 | * Low (section 3.6.4.5) and MCA NB Address High (section 3.6.4.6) registers | |
651 | * of a node that detected an ECC memory error. mci represents the node that | |
652 | * the error address maps to (possibly different from the node that detected | |
653 | * the error). Return the number of the csrow that sys_addr maps to, or -1 on | |
654 | * error. | |
655 | */ | |
656 | static int sys_addr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr) | |
657 | { | |
658 | int csrow; | |
659 | ||
660 | csrow = input_addr_to_csrow(mci, sys_addr_to_input_addr(mci, sys_addr)); | |
661 | ||
662 | if (csrow == -1) | |
24f9a7fe BP |
663 | amd64_mc_err(mci, "Failed to translate InputAddr to csrow for " |
664 | "address 0x%lx\n", (unsigned long)sys_addr); | |
93c2df58 DT |
665 | return csrow; |
666 | } | |
e2ce7255 | 667 | |
bfc04aec | 668 | static int get_channel_from_ecc_syndrome(struct mem_ctl_info *, u16); |
2da11654 | 669 | |
2da11654 DT |
670 | /* |
671 | * Determine if the DIMMs have ECC enabled. ECC is enabled ONLY if all the DIMMs | |
672 | * are ECC capable. | |
673 | */ | |
d1ea71cd | 674 | static unsigned long determine_edac_cap(struct amd64_pvt *pvt) |
2da11654 | 675 | { |
cb328507 | 676 | u8 bit; |
1f6189ed | 677 | unsigned long edac_cap = EDAC_FLAG_NONE; |
2da11654 | 678 | |
a4b4bedc | 679 | bit = (pvt->fam > 0xf || pvt->ext_model >= K8_REV_F) |
2da11654 DT |
680 | ? 19 |
681 | : 17; | |
682 | ||
584fcff4 | 683 | if (pvt->dclr0 & BIT(bit)) |
2da11654 DT |
684 | edac_cap = EDAC_FLAG_SECDED; |
685 | ||
686 | return edac_cap; | |
687 | } | |
688 | ||
d1ea71cd | 689 | static void debug_display_dimm_sizes(struct amd64_pvt *, u8); |
2da11654 | 690 | |
d1ea71cd | 691 | static void debug_dump_dramcfg_low(struct amd64_pvt *pvt, u32 dclr, int chan) |
68798e17 | 692 | { |
956b9ba1 | 693 | edac_dbg(1, "F2x%d90 (DRAM Cfg Low): 0x%08x\n", chan, dclr); |
68798e17 | 694 | |
a597d2a5 AG |
695 | if (pvt->dram_type == MEM_LRDDR3) { |
696 | u32 dcsm = pvt->csels[chan].csmasks[0]; | |
697 | /* | |
698 | * It's assumed all LRDIMMs in a DCT are going to be of | |
699 | * same 'type' until proven otherwise. So, use a cs | |
700 | * value of '0' here to get dcsm value. | |
701 | */ | |
702 | edac_dbg(1, " LRDIMM %dx rank multiply\n", (dcsm & 0x3)); | |
703 | } | |
704 | ||
705 | edac_dbg(1, "All DIMMs support ECC:%s\n", | |
706 | (dclr & BIT(19)) ? "yes" : "no"); | |
707 | ||
68798e17 | 708 | |
956b9ba1 JP |
709 | edac_dbg(1, " PAR/ERR parity: %s\n", |
710 | (dclr & BIT(8)) ? "enabled" : "disabled"); | |
68798e17 | 711 | |
a4b4bedc | 712 | if (pvt->fam == 0x10) |
956b9ba1 JP |
713 | edac_dbg(1, " DCT 128bit mode width: %s\n", |
714 | (dclr & BIT(11)) ? "128b" : "64b"); | |
68798e17 | 715 | |
956b9ba1 JP |
716 | edac_dbg(1, " x4 logical DIMMs present: L0: %s L1: %s L2: %s L3: %s\n", |
717 | (dclr & BIT(12)) ? "yes" : "no", | |
718 | (dclr & BIT(13)) ? "yes" : "no", | |
719 | (dclr & BIT(14)) ? "yes" : "no", | |
720 | (dclr & BIT(15)) ? "yes" : "no"); | |
68798e17 BP |
721 | } |
722 | ||
2da11654 | 723 | /* Display and decode various NB registers for debug purposes. */ |
b2b0c605 | 724 | static void dump_misc_regs(struct amd64_pvt *pvt) |
2da11654 | 725 | { |
956b9ba1 | 726 | edac_dbg(1, "F3xE8 (NB Cap): 0x%08x\n", pvt->nbcap); |
68798e17 | 727 | |
956b9ba1 JP |
728 | edac_dbg(1, " NB two channel DRAM capable: %s\n", |
729 | (pvt->nbcap & NBCAP_DCT_DUAL) ? "yes" : "no"); | |
2da11654 | 730 | |
956b9ba1 JP |
731 | edac_dbg(1, " ECC capable: %s, ChipKill ECC capable: %s\n", |
732 | (pvt->nbcap & NBCAP_SECDED) ? "yes" : "no", | |
733 | (pvt->nbcap & NBCAP_CHIPKILL) ? "yes" : "no"); | |
68798e17 | 734 | |
d1ea71cd | 735 | debug_dump_dramcfg_low(pvt, pvt->dclr0, 0); |
2da11654 | 736 | |
956b9ba1 | 737 | edac_dbg(1, "F3xB0 (Online Spare): 0x%08x\n", pvt->online_spare); |
2da11654 | 738 | |
956b9ba1 JP |
739 | edac_dbg(1, "F1xF0 (DRAM Hole Address): 0x%08x, base: 0x%08x, offset: 0x%08x\n", |
740 | pvt->dhar, dhar_base(pvt), | |
a4b4bedc BP |
741 | (pvt->fam == 0xf) ? k8_dhar_offset(pvt) |
742 | : f10_dhar_offset(pvt)); | |
2da11654 | 743 | |
956b9ba1 | 744 | edac_dbg(1, " DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no"); |
2da11654 | 745 | |
d1ea71cd | 746 | debug_display_dimm_sizes(pvt, 0); |
4d796364 | 747 | |
8de1d91e | 748 | /* everything below this point is Fam10h and above */ |
a4b4bedc | 749 | if (pvt->fam == 0xf) |
2da11654 | 750 | return; |
4d796364 | 751 | |
d1ea71cd | 752 | debug_display_dimm_sizes(pvt, 1); |
2da11654 | 753 | |
a3b7db09 | 754 | amd64_info("using %s syndromes.\n", ((pvt->ecc_sym_sz == 8) ? "x8" : "x4")); |
ad6a32e9 | 755 | |
8de1d91e | 756 | /* Only if NOT ganged does dclr1 have valid info */ |
68798e17 | 757 | if (!dct_ganging_enabled(pvt)) |
d1ea71cd | 758 | debug_dump_dramcfg_low(pvt, pvt->dclr1, 1); |
2da11654 DT |
759 | } |
760 | ||
94be4bff | 761 | /* |
18b94f66 | 762 | * See BKDG, F2x[1,0][5C:40], F2[1,0][6C:60] |
94be4bff | 763 | */ |
11c75ead | 764 | static void prep_chip_selects(struct amd64_pvt *pvt) |
94be4bff | 765 | { |
18b94f66 | 766 | if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) { |
11c75ead BP |
767 | pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8; |
768 | pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 8; | |
a597d2a5 | 769 | } else if (pvt->fam == 0x15 && pvt->model == 0x30) { |
18b94f66 AG |
770 | pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 4; |
771 | pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 2; | |
9d858bb1 | 772 | } else { |
11c75ead BP |
773 | pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8; |
774 | pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 4; | |
94be4bff DT |
775 | } |
776 | } | |
777 | ||
778 | /* | |
11c75ead | 779 | * Function 2 Offset F10_DCSB0; read in the DCS Base and DCS Mask registers |
94be4bff | 780 | */ |
b2b0c605 | 781 | static void read_dct_base_mask(struct amd64_pvt *pvt) |
94be4bff | 782 | { |
11c75ead | 783 | int cs; |
94be4bff | 784 | |
11c75ead | 785 | prep_chip_selects(pvt); |
94be4bff | 786 | |
11c75ead | 787 | for_each_chip_select(cs, 0, pvt) { |
71d2a32e BP |
788 | int reg0 = DCSB0 + (cs * 4); |
789 | int reg1 = DCSB1 + (cs * 4); | |
11c75ead BP |
790 | u32 *base0 = &pvt->csels[0].csbases[cs]; |
791 | u32 *base1 = &pvt->csels[1].csbases[cs]; | |
b2b0c605 | 792 | |
7981a28f | 793 | if (!amd64_read_dct_pci_cfg(pvt, 0, reg0, base0)) |
956b9ba1 JP |
794 | edac_dbg(0, " DCSB0[%d]=0x%08x reg: F2x%x\n", |
795 | cs, *base0, reg0); | |
94be4bff | 796 | |
7981a28f | 797 | if (pvt->fam == 0xf) |
11c75ead | 798 | continue; |
b2b0c605 | 799 | |
7981a28f | 800 | if (!amd64_read_dct_pci_cfg(pvt, 1, reg0, base1)) |
956b9ba1 | 801 | edac_dbg(0, " DCSB1[%d]=0x%08x reg: F2x%x\n", |
7981a28f AG |
802 | cs, *base1, (pvt->fam == 0x10) ? reg1 |
803 | : reg0); | |
94be4bff DT |
804 | } |
805 | ||
11c75ead | 806 | for_each_chip_select_mask(cs, 0, pvt) { |
71d2a32e BP |
807 | int reg0 = DCSM0 + (cs * 4); |
808 | int reg1 = DCSM1 + (cs * 4); | |
11c75ead BP |
809 | u32 *mask0 = &pvt->csels[0].csmasks[cs]; |
810 | u32 *mask1 = &pvt->csels[1].csmasks[cs]; | |
b2b0c605 | 811 | |
7981a28f | 812 | if (!amd64_read_dct_pci_cfg(pvt, 0, reg0, mask0)) |
956b9ba1 JP |
813 | edac_dbg(0, " DCSM0[%d]=0x%08x reg: F2x%x\n", |
814 | cs, *mask0, reg0); | |
94be4bff | 815 | |
7981a28f | 816 | if (pvt->fam == 0xf) |
11c75ead | 817 | continue; |
b2b0c605 | 818 | |
7981a28f | 819 | if (!amd64_read_dct_pci_cfg(pvt, 1, reg0, mask1)) |
956b9ba1 | 820 | edac_dbg(0, " DCSM1[%d]=0x%08x reg: F2x%x\n", |
7981a28f AG |
821 | cs, *mask1, (pvt->fam == 0x10) ? reg1 |
822 | : reg0); | |
94be4bff DT |
823 | } |
824 | } | |
825 | ||
a597d2a5 | 826 | static void determine_memory_type(struct amd64_pvt *pvt) |
94be4bff | 827 | { |
a597d2a5 | 828 | u32 dram_ctrl, dcsm; |
94be4bff | 829 | |
a597d2a5 AG |
830 | switch (pvt->fam) { |
831 | case 0xf: | |
832 | if (pvt->ext_model >= K8_REV_F) | |
833 | goto ddr3; | |
834 | ||
835 | pvt->dram_type = (pvt->dclr0 & BIT(18)) ? MEM_DDR : MEM_RDDR; | |
836 | return; | |
837 | ||
838 | case 0x10: | |
6b4c0bde | 839 | if (pvt->dchr0 & DDR3_MODE) |
a597d2a5 AG |
840 | goto ddr3; |
841 | ||
842 | pvt->dram_type = (pvt->dclr0 & BIT(16)) ? MEM_DDR2 : MEM_RDDR2; | |
843 | return; | |
844 | ||
845 | case 0x15: | |
846 | if (pvt->model < 0x60) | |
847 | goto ddr3; | |
848 | ||
849 | /* | |
850 | * Model 0x60h needs special handling: | |
851 | * | |
852 | * We use a Chip Select value of '0' to obtain dcsm. | |
853 | * Theoretically, it is possible to populate LRDIMMs of different | |
854 | * 'Rank' value on a DCT. But this is not the common case. So, | |
855 | * it's reasonable to assume all DIMMs are going to be of same | |
856 | * 'type' until proven otherwise. | |
857 | */ | |
858 | amd64_read_dct_pci_cfg(pvt, 0, DRAM_CONTROL, &dram_ctrl); | |
859 | dcsm = pvt->csels[0].csmasks[0]; | |
860 | ||
861 | if (((dram_ctrl >> 8) & 0x7) == 0x2) | |
862 | pvt->dram_type = MEM_DDR4; | |
863 | else if (pvt->dclr0 & BIT(16)) | |
864 | pvt->dram_type = MEM_DDR3; | |
865 | else if (dcsm & 0x3) | |
866 | pvt->dram_type = MEM_LRDDR3; | |
6b4c0bde | 867 | else |
a597d2a5 | 868 | pvt->dram_type = MEM_RDDR3; |
94be4bff | 869 | |
a597d2a5 AG |
870 | return; |
871 | ||
872 | case 0x16: | |
873 | goto ddr3; | |
874 | ||
875 | default: | |
876 | WARN(1, KERN_ERR "%s: Family??? 0x%x\n", __func__, pvt->fam); | |
877 | pvt->dram_type = MEM_EMPTY; | |
878 | } | |
879 | return; | |
94be4bff | 880 | |
a597d2a5 AG |
881 | ddr3: |
882 | pvt->dram_type = (pvt->dclr0 & BIT(16)) ? MEM_DDR3 : MEM_RDDR3; | |
94be4bff DT |
883 | } |
884 | ||
cb328507 | 885 | /* Get the number of DCT channels the memory controller is using. */ |
ddff876d DT |
886 | static int k8_early_channel_count(struct amd64_pvt *pvt) |
887 | { | |
cb328507 | 888 | int flag; |
ddff876d | 889 | |
9f56da0e | 890 | if (pvt->ext_model >= K8_REV_F) |
ddff876d | 891 | /* RevF (NPT) and later */ |
41d8bfab | 892 | flag = pvt->dclr0 & WIDTH_128; |
9f56da0e | 893 | else |
ddff876d DT |
894 | /* RevE and earlier */ |
895 | flag = pvt->dclr0 & REVE_WIDTH_128; | |
ddff876d DT |
896 | |
897 | /* not used */ | |
898 | pvt->dclr1 = 0; | |
899 | ||
900 | return (flag) ? 2 : 1; | |
901 | } | |
902 | ||
70046624 | 903 | /* On F10h and later ErrAddr is MC4_ADDR[47:1] */ |
a4b4bedc | 904 | static u64 get_error_address(struct amd64_pvt *pvt, struct mce *m) |
ddff876d | 905 | { |
c1ae6830 | 906 | u64 addr; |
70046624 BP |
907 | u8 start_bit = 1; |
908 | u8 end_bit = 47; | |
909 | ||
a4b4bedc | 910 | if (pvt->fam == 0xf) { |
70046624 BP |
911 | start_bit = 3; |
912 | end_bit = 39; | |
913 | } | |
914 | ||
10ef6b0d | 915 | addr = m->addr & GENMASK_ULL(end_bit, start_bit); |
c1ae6830 BP |
916 | |
917 | /* | |
918 | * Erratum 637 workaround | |
919 | */ | |
a4b4bedc | 920 | if (pvt->fam == 0x15) { |
c1ae6830 BP |
921 | struct amd64_pvt *pvt; |
922 | u64 cc6_base, tmp_addr; | |
923 | u32 tmp; | |
8b84c8df DB |
924 | u16 mce_nid; |
925 | u8 intlv_en; | |
c1ae6830 | 926 | |
10ef6b0d | 927 | if ((addr & GENMASK_ULL(47, 24)) >> 24 != 0x00fdf7) |
c1ae6830 BP |
928 | return addr; |
929 | ||
930 | mce_nid = amd_get_nb_id(m->extcpu); | |
931 | pvt = mcis[mce_nid]->pvt_info; | |
932 | ||
933 | amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_LIM, &tmp); | |
934 | intlv_en = tmp >> 21 & 0x7; | |
935 | ||
936 | /* add [47:27] + 3 trailing bits */ | |
10ef6b0d | 937 | cc6_base = (tmp & GENMASK_ULL(20, 0)) << 3; |
c1ae6830 BP |
938 | |
939 | /* reverse and add DramIntlvEn */ | |
940 | cc6_base |= intlv_en ^ 0x7; | |
941 | ||
942 | /* pin at [47:24] */ | |
943 | cc6_base <<= 24; | |
944 | ||
945 | if (!intlv_en) | |
10ef6b0d | 946 | return cc6_base | (addr & GENMASK_ULL(23, 0)); |
c1ae6830 BP |
947 | |
948 | amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_BASE, &tmp); | |
949 | ||
950 | /* faster log2 */ | |
10ef6b0d | 951 | tmp_addr = (addr & GENMASK_ULL(23, 12)) << __fls(intlv_en + 1); |
c1ae6830 BP |
952 | |
953 | /* OR DramIntlvSel into bits [14:12] */ | |
10ef6b0d | 954 | tmp_addr |= (tmp & GENMASK_ULL(23, 21)) >> 9; |
c1ae6830 BP |
955 | |
956 | /* add remaining [11:0] bits from original MC4_ADDR */ | |
10ef6b0d | 957 | tmp_addr |= addr & GENMASK_ULL(11, 0); |
c1ae6830 BP |
958 | |
959 | return cc6_base | tmp_addr; | |
960 | } | |
961 | ||
962 | return addr; | |
ddff876d DT |
963 | } |
964 | ||
e2c0bffe DB |
965 | static struct pci_dev *pci_get_related_function(unsigned int vendor, |
966 | unsigned int device, | |
967 | struct pci_dev *related) | |
968 | { | |
969 | struct pci_dev *dev = NULL; | |
970 | ||
971 | while ((dev = pci_get_device(vendor, device, dev))) { | |
972 | if (pci_domain_nr(dev->bus) == pci_domain_nr(related->bus) && | |
973 | (dev->bus->number == related->bus->number) && | |
974 | (PCI_SLOT(dev->devfn) == PCI_SLOT(related->devfn))) | |
975 | break; | |
976 | } | |
977 | ||
978 | return dev; | |
979 | } | |
980 | ||
7f19bf75 | 981 | static void read_dram_base_limit_regs(struct amd64_pvt *pvt, unsigned range) |
ddff876d | 982 | { |
e2c0bffe | 983 | struct amd_northbridge *nb; |
18b94f66 AG |
984 | struct pci_dev *f1 = NULL; |
985 | unsigned int pci_func; | |
71d2a32e | 986 | int off = range << 3; |
e2c0bffe | 987 | u32 llim; |
ddff876d | 988 | |
7f19bf75 BP |
989 | amd64_read_pci_cfg(pvt->F1, DRAM_BASE_LO + off, &pvt->ranges[range].base.lo); |
990 | amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_LO + off, &pvt->ranges[range].lim.lo); | |
ddff876d | 991 | |
18b94f66 | 992 | if (pvt->fam == 0xf) |
7f19bf75 | 993 | return; |
ddff876d | 994 | |
7f19bf75 BP |
995 | if (!dram_rw(pvt, range)) |
996 | return; | |
ddff876d | 997 | |
7f19bf75 BP |
998 | amd64_read_pci_cfg(pvt->F1, DRAM_BASE_HI + off, &pvt->ranges[range].base.hi); |
999 | amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_HI + off, &pvt->ranges[range].lim.hi); | |
f08e457c | 1000 | |
e2c0bffe | 1001 | /* F15h: factor in CC6 save area by reading dst node's limit reg */ |
18b94f66 | 1002 | if (pvt->fam != 0x15) |
e2c0bffe | 1003 | return; |
f08e457c | 1004 | |
e2c0bffe DB |
1005 | nb = node_to_amd_nb(dram_dst_node(pvt, range)); |
1006 | if (WARN_ON(!nb)) | |
1007 | return; | |
f08e457c | 1008 | |
a597d2a5 AG |
1009 | if (pvt->model == 0x60) |
1010 | pci_func = PCI_DEVICE_ID_AMD_15H_M60H_NB_F1; | |
1011 | else if (pvt->model == 0x30) | |
1012 | pci_func = PCI_DEVICE_ID_AMD_15H_M30H_NB_F1; | |
1013 | else | |
1014 | pci_func = PCI_DEVICE_ID_AMD_15H_NB_F1; | |
18b94f66 AG |
1015 | |
1016 | f1 = pci_get_related_function(nb->misc->vendor, pci_func, nb->misc); | |
e2c0bffe DB |
1017 | if (WARN_ON(!f1)) |
1018 | return; | |
f08e457c | 1019 | |
e2c0bffe | 1020 | amd64_read_pci_cfg(f1, DRAM_LOCAL_NODE_LIM, &llim); |
f08e457c | 1021 | |
10ef6b0d | 1022 | pvt->ranges[range].lim.lo &= GENMASK_ULL(15, 0); |
f08e457c | 1023 | |
e2c0bffe DB |
1024 | /* {[39:27],111b} */ |
1025 | pvt->ranges[range].lim.lo |= ((llim & 0x1fff) << 3 | 0x7) << 16; | |
f08e457c | 1026 | |
10ef6b0d | 1027 | pvt->ranges[range].lim.hi &= GENMASK_ULL(7, 0); |
f08e457c | 1028 | |
e2c0bffe DB |
1029 | /* [47:40] */ |
1030 | pvt->ranges[range].lim.hi |= llim >> 13; | |
1031 | ||
1032 | pci_dev_put(f1); | |
ddff876d DT |
1033 | } |
1034 | ||
f192c7b1 | 1035 | static void k8_map_sysaddr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr, |
33ca0643 | 1036 | struct err_info *err) |
ddff876d | 1037 | { |
f192c7b1 | 1038 | struct amd64_pvt *pvt = mci->pvt_info; |
ddff876d | 1039 | |
33ca0643 | 1040 | error_address_to_page_and_offset(sys_addr, err); |
ab5a503c MCC |
1041 | |
1042 | /* | |
1043 | * Find out which node the error address belongs to. This may be | |
1044 | * different from the node that detected the error. | |
1045 | */ | |
33ca0643 BP |
1046 | err->src_mci = find_mc_by_sys_addr(mci, sys_addr); |
1047 | if (!err->src_mci) { | |
ab5a503c MCC |
1048 | amd64_mc_err(mci, "failed to map error addr 0x%lx to a node\n", |
1049 | (unsigned long)sys_addr); | |
33ca0643 | 1050 | err->err_code = ERR_NODE; |
ab5a503c MCC |
1051 | return; |
1052 | } | |
1053 | ||
1054 | /* Now map the sys_addr to a CSROW */ | |
33ca0643 BP |
1055 | err->csrow = sys_addr_to_csrow(err->src_mci, sys_addr); |
1056 | if (err->csrow < 0) { | |
1057 | err->err_code = ERR_CSROW; | |
ab5a503c MCC |
1058 | return; |
1059 | } | |
1060 | ||
ddff876d | 1061 | /* CHIPKILL enabled */ |
f192c7b1 | 1062 | if (pvt->nbcfg & NBCFG_CHIPKILL) { |
33ca0643 BP |
1063 | err->channel = get_channel_from_ecc_syndrome(mci, err->syndrome); |
1064 | if (err->channel < 0) { | |
ddff876d DT |
1065 | /* |
1066 | * Syndrome didn't map, so we don't know which of the | |
1067 | * 2 DIMMs is in error. So we need to ID 'both' of them | |
1068 | * as suspect. | |
1069 | */ | |
33ca0643 | 1070 | amd64_mc_warn(err->src_mci, "unknown syndrome 0x%04x - " |
ab5a503c | 1071 | "possible error reporting race\n", |
33ca0643 BP |
1072 | err->syndrome); |
1073 | err->err_code = ERR_CHANNEL; | |
ddff876d DT |
1074 | return; |
1075 | } | |
1076 | } else { | |
1077 | /* | |
1078 | * non-chipkill ecc mode | |
1079 | * | |
1080 | * The k8 documentation is unclear about how to determine the | |
1081 | * channel number when using non-chipkill memory. This method | |
1082 | * was obtained from email communication with someone at AMD. | |
1083 | * (Wish the email was placed in this comment - norsk) | |
1084 | */ | |
33ca0643 | 1085 | err->channel = ((sys_addr & BIT(3)) != 0); |
ddff876d | 1086 | } |
ddff876d DT |
1087 | } |
1088 | ||
41d8bfab | 1089 | static int ddr2_cs_size(unsigned i, bool dct_width) |
ddff876d | 1090 | { |
41d8bfab | 1091 | unsigned shift = 0; |
ddff876d | 1092 | |
41d8bfab BP |
1093 | if (i <= 2) |
1094 | shift = i; | |
1095 | else if (!(i & 0x1)) | |
1096 | shift = i >> 1; | |
1433eb99 | 1097 | else |
41d8bfab | 1098 | shift = (i + 1) >> 1; |
ddff876d | 1099 | |
41d8bfab BP |
1100 | return 128 << (shift + !!dct_width); |
1101 | } | |
1102 | ||
1103 | static int k8_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, | |
a597d2a5 | 1104 | unsigned cs_mode, int cs_mask_nr) |
41d8bfab BP |
1105 | { |
1106 | u32 dclr = dct ? pvt->dclr1 : pvt->dclr0; | |
1107 | ||
1108 | if (pvt->ext_model >= K8_REV_F) { | |
1109 | WARN_ON(cs_mode > 11); | |
1110 | return ddr2_cs_size(cs_mode, dclr & WIDTH_128); | |
1111 | } | |
1112 | else if (pvt->ext_model >= K8_REV_D) { | |
11b0a314 | 1113 | unsigned diff; |
41d8bfab BP |
1114 | WARN_ON(cs_mode > 10); |
1115 | ||
11b0a314 BP |
1116 | /* |
1117 | * the below calculation, besides trying to win an obfuscated C | |
1118 | * contest, maps cs_mode values to DIMM chip select sizes. The | |
1119 | * mappings are: | |
1120 | * | |
1121 | * cs_mode CS size (mb) | |
1122 | * ======= ============ | |
1123 | * 0 32 | |
1124 | * 1 64 | |
1125 | * 2 128 | |
1126 | * 3 128 | |
1127 | * 4 256 | |
1128 | * 5 512 | |
1129 | * 6 256 | |
1130 | * 7 512 | |
1131 | * 8 1024 | |
1132 | * 9 1024 | |
1133 | * 10 2048 | |
1134 | * | |
1135 | * Basically, it calculates a value with which to shift the | |
1136 | * smallest CS size of 32MB. | |
1137 | * | |
1138 | * ddr[23]_cs_size have a similar purpose. | |
1139 | */ | |
1140 | diff = cs_mode/3 + (unsigned)(cs_mode > 5); | |
1141 | ||
1142 | return 32 << (cs_mode - diff); | |
41d8bfab BP |
1143 | } |
1144 | else { | |
1145 | WARN_ON(cs_mode > 6); | |
1146 | return 32 << cs_mode; | |
1147 | } | |
ddff876d DT |
1148 | } |
1149 | ||
1afd3c98 DT |
1150 | /* |
1151 | * Get the number of DCT channels in use. | |
1152 | * | |
1153 | * Return: | |
1154 | * number of Memory Channels in operation | |
1155 | * Pass back: | |
1156 | * contents of the DCL0_LOW register | |
1157 | */ | |
7d20d14d | 1158 | static int f1x_early_channel_count(struct amd64_pvt *pvt) |
1afd3c98 | 1159 | { |
6ba5dcdc | 1160 | int i, j, channels = 0; |
1afd3c98 | 1161 | |
7d20d14d | 1162 | /* On F10h, if we are in 128 bit mode, then we are using 2 channels */ |
a4b4bedc | 1163 | if (pvt->fam == 0x10 && (pvt->dclr0 & WIDTH_128)) |
7d20d14d | 1164 | return 2; |
1afd3c98 DT |
1165 | |
1166 | /* | |
d16149e8 BP |
1167 | * Need to check if in unganged mode: In such, there are 2 channels, |
1168 | * but they are not in 128 bit mode and thus the above 'dclr0' status | |
1169 | * bit will be OFF. | |
1afd3c98 DT |
1170 | * |
1171 | * Need to check DCT0[0] and DCT1[0] to see if only one of them has | |
1172 | * their CSEnable bit on. If so, then SINGLE DIMM case. | |
1173 | */ | |
956b9ba1 | 1174 | edac_dbg(0, "Data width is not 128 bits - need more decoding\n"); |
ddff876d | 1175 | |
1afd3c98 DT |
1176 | /* |
1177 | * Check DRAM Bank Address Mapping values for each DIMM to see if there | |
1178 | * is more than just one DIMM present in unganged mode. Need to check | |
1179 | * both controllers since DIMMs can be placed in either one. | |
1180 | */ | |
525a1b20 BP |
1181 | for (i = 0; i < 2; i++) { |
1182 | u32 dbam = (i ? pvt->dbam1 : pvt->dbam0); | |
1afd3c98 | 1183 | |
57a30854 WW |
1184 | for (j = 0; j < 4; j++) { |
1185 | if (DBAM_DIMM(j, dbam) > 0) { | |
1186 | channels++; | |
1187 | break; | |
1188 | } | |
1189 | } | |
1afd3c98 DT |
1190 | } |
1191 | ||
d16149e8 BP |
1192 | if (channels > 2) |
1193 | channels = 2; | |
1194 | ||
24f9a7fe | 1195 | amd64_info("MCT channel count: %d\n", channels); |
1afd3c98 DT |
1196 | |
1197 | return channels; | |
1afd3c98 DT |
1198 | } |
1199 | ||
41d8bfab | 1200 | static int ddr3_cs_size(unsigned i, bool dct_width) |
1afd3c98 | 1201 | { |
41d8bfab BP |
1202 | unsigned shift = 0; |
1203 | int cs_size = 0; | |
1204 | ||
1205 | if (i == 0 || i == 3 || i == 4) | |
1206 | cs_size = -1; | |
1207 | else if (i <= 2) | |
1208 | shift = i; | |
1209 | else if (i == 12) | |
1210 | shift = 7; | |
1211 | else if (!(i & 0x1)) | |
1212 | shift = i >> 1; | |
1213 | else | |
1214 | shift = (i + 1) >> 1; | |
1215 | ||
1216 | if (cs_size != -1) | |
1217 | cs_size = (128 * (1 << !!dct_width)) << shift; | |
1218 | ||
1219 | return cs_size; | |
1220 | } | |
1221 | ||
a597d2a5 AG |
1222 | static int ddr3_lrdimm_cs_size(unsigned i, unsigned rank_multiply) |
1223 | { | |
1224 | unsigned shift = 0; | |
1225 | int cs_size = 0; | |
1226 | ||
1227 | if (i < 4 || i == 6) | |
1228 | cs_size = -1; | |
1229 | else if (i == 12) | |
1230 | shift = 7; | |
1231 | else if (!(i & 0x1)) | |
1232 | shift = i >> 1; | |
1233 | else | |
1234 | shift = (i + 1) >> 1; | |
1235 | ||
1236 | if (cs_size != -1) | |
1237 | cs_size = rank_multiply * (128 << shift); | |
1238 | ||
1239 | return cs_size; | |
1240 | } | |
1241 | ||
1242 | static int ddr4_cs_size(unsigned i) | |
1243 | { | |
1244 | int cs_size = 0; | |
1245 | ||
1246 | if (i == 0) | |
1247 | cs_size = -1; | |
1248 | else if (i == 1) | |
1249 | cs_size = 1024; | |
1250 | else | |
1251 | /* Min cs_size = 1G */ | |
1252 | cs_size = 1024 * (1 << (i >> 1)); | |
1253 | ||
1254 | return cs_size; | |
1255 | } | |
1256 | ||
41d8bfab | 1257 | static int f10_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, |
a597d2a5 | 1258 | unsigned cs_mode, int cs_mask_nr) |
41d8bfab BP |
1259 | { |
1260 | u32 dclr = dct ? pvt->dclr1 : pvt->dclr0; | |
1261 | ||
1262 | WARN_ON(cs_mode > 11); | |
1433eb99 BP |
1263 | |
1264 | if (pvt->dchr0 & DDR3_MODE || pvt->dchr1 & DDR3_MODE) | |
41d8bfab | 1265 | return ddr3_cs_size(cs_mode, dclr & WIDTH_128); |
1433eb99 | 1266 | else |
41d8bfab BP |
1267 | return ddr2_cs_size(cs_mode, dclr & WIDTH_128); |
1268 | } | |
1269 | ||
1270 | /* | |
1271 | * F15h supports only 64bit DCT interfaces | |
1272 | */ | |
1273 | static int f15_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, | |
a597d2a5 | 1274 | unsigned cs_mode, int cs_mask_nr) |
41d8bfab BP |
1275 | { |
1276 | WARN_ON(cs_mode > 12); | |
1433eb99 | 1277 | |
41d8bfab | 1278 | return ddr3_cs_size(cs_mode, false); |
1afd3c98 DT |
1279 | } |
1280 | ||
a597d2a5 AG |
1281 | /* F15h M60h supports DDR4 mapping as well.. */ |
1282 | static int f15_m60h_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, | |
1283 | unsigned cs_mode, int cs_mask_nr) | |
1284 | { | |
1285 | int cs_size; | |
1286 | u32 dcsm = pvt->csels[dct].csmasks[cs_mask_nr]; | |
1287 | ||
1288 | WARN_ON(cs_mode > 12); | |
1289 | ||
1290 | if (pvt->dram_type == MEM_DDR4) { | |
1291 | if (cs_mode > 9) | |
1292 | return -1; | |
1293 | ||
1294 | cs_size = ddr4_cs_size(cs_mode); | |
1295 | } else if (pvt->dram_type == MEM_LRDDR3) { | |
1296 | unsigned rank_multiply = dcsm & 0xf; | |
1297 | ||
1298 | if (rank_multiply == 3) | |
1299 | rank_multiply = 4; | |
1300 | cs_size = ddr3_lrdimm_cs_size(cs_mode, rank_multiply); | |
1301 | } else { | |
1302 | /* Minimum cs size is 512mb for F15hM60h*/ | |
1303 | if (cs_mode == 0x1) | |
1304 | return -1; | |
1305 | ||
1306 | cs_size = ddr3_cs_size(cs_mode, false); | |
1307 | } | |
1308 | ||
1309 | return cs_size; | |
1310 | } | |
1311 | ||
94c1acf2 | 1312 | /* |
18b94f66 | 1313 | * F16h and F15h model 30h have only limited cs_modes. |
94c1acf2 AG |
1314 | */ |
1315 | static int f16_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, | |
a597d2a5 | 1316 | unsigned cs_mode, int cs_mask_nr) |
94c1acf2 AG |
1317 | { |
1318 | WARN_ON(cs_mode > 12); | |
1319 | ||
1320 | if (cs_mode == 6 || cs_mode == 8 || | |
1321 | cs_mode == 9 || cs_mode == 12) | |
1322 | return -1; | |
1323 | else | |
1324 | return ddr3_cs_size(cs_mode, false); | |
1325 | } | |
1326 | ||
5a5d2371 | 1327 | static void read_dram_ctl_register(struct amd64_pvt *pvt) |
6163b5d4 | 1328 | { |
6163b5d4 | 1329 | |
a4b4bedc | 1330 | if (pvt->fam == 0xf) |
5a5d2371 BP |
1331 | return; |
1332 | ||
7981a28f | 1333 | if (!amd64_read_pci_cfg(pvt->F2, DCT_SEL_LO, &pvt->dct_sel_lo)) { |
956b9ba1 JP |
1334 | edac_dbg(0, "F2x110 (DCTSelLow): 0x%08x, High range addrs at: 0x%x\n", |
1335 | pvt->dct_sel_lo, dct_sel_baseaddr(pvt)); | |
72381bd5 | 1336 | |
956b9ba1 JP |
1337 | edac_dbg(0, " DCTs operate in %s mode\n", |
1338 | (dct_ganging_enabled(pvt) ? "ganged" : "unganged")); | |
72381bd5 BP |
1339 | |
1340 | if (!dct_ganging_enabled(pvt)) | |
956b9ba1 JP |
1341 | edac_dbg(0, " Address range split per DCT: %s\n", |
1342 | (dct_high_range_enabled(pvt) ? "yes" : "no")); | |
72381bd5 | 1343 | |
956b9ba1 JP |
1344 | edac_dbg(0, " data interleave for ECC: %s, DRAM cleared since last warm reset: %s\n", |
1345 | (dct_data_intlv_enabled(pvt) ? "enabled" : "disabled"), | |
1346 | (dct_memory_cleared(pvt) ? "yes" : "no")); | |
72381bd5 | 1347 | |
956b9ba1 JP |
1348 | edac_dbg(0, " channel interleave: %s, " |
1349 | "interleave bits selector: 0x%x\n", | |
1350 | (dct_interleave_enabled(pvt) ? "enabled" : "disabled"), | |
1351 | dct_sel_interleave_addr(pvt)); | |
6163b5d4 DT |
1352 | } |
1353 | ||
7981a28f | 1354 | amd64_read_pci_cfg(pvt->F2, DCT_SEL_HI, &pvt->dct_sel_hi); |
6163b5d4 DT |
1355 | } |
1356 | ||
18b94f66 AG |
1357 | /* |
1358 | * Determine channel (DCT) based on the interleaving mode (see F15h M30h BKDG, | |
1359 | * 2.10.12 Memory Interleaving Modes). | |
1360 | */ | |
1361 | static u8 f15_m30h_determine_channel(struct amd64_pvt *pvt, u64 sys_addr, | |
1362 | u8 intlv_en, int num_dcts_intlv, | |
1363 | u32 dct_sel) | |
1364 | { | |
1365 | u8 channel = 0; | |
1366 | u8 select; | |
1367 | ||
1368 | if (!(intlv_en)) | |
1369 | return (u8)(dct_sel); | |
1370 | ||
1371 | if (num_dcts_intlv == 2) { | |
1372 | select = (sys_addr >> 8) & 0x3; | |
1373 | channel = select ? 0x3 : 0; | |
9d0e8d83 AG |
1374 | } else if (num_dcts_intlv == 4) { |
1375 | u8 intlv_addr = dct_sel_interleave_addr(pvt); | |
1376 | switch (intlv_addr) { | |
1377 | case 0x4: | |
1378 | channel = (sys_addr >> 8) & 0x3; | |
1379 | break; | |
1380 | case 0x5: | |
1381 | channel = (sys_addr >> 9) & 0x3; | |
1382 | break; | |
1383 | } | |
1384 | } | |
18b94f66 AG |
1385 | return channel; |
1386 | } | |
1387 | ||
f71d0a05 | 1388 | /* |
229a7a11 | 1389 | * Determine channel (DCT) based on the interleaving mode: F10h BKDG, 2.8.9 Memory |
f71d0a05 DT |
1390 | * Interleaving Modes. |
1391 | */ | |
b15f0fca | 1392 | static u8 f1x_determine_channel(struct amd64_pvt *pvt, u64 sys_addr, |
229a7a11 | 1393 | bool hi_range_sel, u8 intlv_en) |
6163b5d4 | 1394 | { |
151fa71c | 1395 | u8 dct_sel_high = (pvt->dct_sel_lo >> 1) & 1; |
6163b5d4 DT |
1396 | |
1397 | if (dct_ganging_enabled(pvt)) | |
229a7a11 | 1398 | return 0; |
6163b5d4 | 1399 | |
229a7a11 BP |
1400 | if (hi_range_sel) |
1401 | return dct_sel_high; | |
6163b5d4 | 1402 | |
229a7a11 BP |
1403 | /* |
1404 | * see F2x110[DctSelIntLvAddr] - channel interleave mode | |
1405 | */ | |
1406 | if (dct_interleave_enabled(pvt)) { | |
1407 | u8 intlv_addr = dct_sel_interleave_addr(pvt); | |
1408 | ||
1409 | /* return DCT select function: 0=DCT0, 1=DCT1 */ | |
1410 | if (!intlv_addr) | |
1411 | return sys_addr >> 6 & 1; | |
1412 | ||
1413 | if (intlv_addr & 0x2) { | |
1414 | u8 shift = intlv_addr & 0x1 ? 9 : 6; | |
1415 | u32 temp = hweight_long((u32) ((sys_addr >> 16) & 0x1F)) % 2; | |
1416 | ||
1417 | return ((sys_addr >> shift) & 1) ^ temp; | |
1418 | } | |
1419 | ||
1420 | return (sys_addr >> (12 + hweight8(intlv_en))) & 1; | |
1421 | } | |
1422 | ||
1423 | if (dct_high_range_enabled(pvt)) | |
1424 | return ~dct_sel_high & 1; | |
6163b5d4 DT |
1425 | |
1426 | return 0; | |
1427 | } | |
1428 | ||
c8e518d5 | 1429 | /* Convert the sys_addr to the normalized DCT address */ |
c7e5301a | 1430 | static u64 f1x_get_norm_dct_addr(struct amd64_pvt *pvt, u8 range, |
c8e518d5 BP |
1431 | u64 sys_addr, bool hi_rng, |
1432 | u32 dct_sel_base_addr) | |
6163b5d4 DT |
1433 | { |
1434 | u64 chan_off; | |
c8e518d5 BP |
1435 | u64 dram_base = get_dram_base(pvt, range); |
1436 | u64 hole_off = f10_dhar_offset(pvt); | |
c8e518d5 | 1437 | u64 dct_sel_base_off = (pvt->dct_sel_hi & 0xFFFFFC00) << 16; |
6163b5d4 | 1438 | |
c8e518d5 BP |
1439 | if (hi_rng) { |
1440 | /* | |
1441 | * if | |
1442 | * base address of high range is below 4Gb | |
1443 | * (bits [47:27] at [31:11]) | |
1444 | * DRAM address space on this DCT is hoisted above 4Gb && | |
1445 | * sys_addr > 4Gb | |
1446 | * | |
1447 | * remove hole offset from sys_addr | |
1448 | * else | |
1449 | * remove high range offset from sys_addr | |
1450 | */ | |
1451 | if ((!(dct_sel_base_addr >> 16) || | |
1452 | dct_sel_base_addr < dhar_base(pvt)) && | |
972ea17a | 1453 | dhar_valid(pvt) && |
c8e518d5 | 1454 | (sys_addr >= BIT_64(32))) |
bc21fa57 | 1455 | chan_off = hole_off; |
6163b5d4 DT |
1456 | else |
1457 | chan_off = dct_sel_base_off; | |
1458 | } else { | |
c8e518d5 BP |
1459 | /* |
1460 | * if | |
1461 | * we have a valid hole && | |
1462 | * sys_addr > 4Gb | |
1463 | * | |
1464 | * remove hole | |
1465 | * else | |
1466 | * remove dram base to normalize to DCT address | |
1467 | */ | |
972ea17a | 1468 | if (dhar_valid(pvt) && (sys_addr >= BIT_64(32))) |
bc21fa57 | 1469 | chan_off = hole_off; |
6163b5d4 | 1470 | else |
c8e518d5 | 1471 | chan_off = dram_base; |
6163b5d4 DT |
1472 | } |
1473 | ||
10ef6b0d | 1474 | return (sys_addr & GENMASK_ULL(47,6)) - (chan_off & GENMASK_ULL(47,23)); |
6163b5d4 DT |
1475 | } |
1476 | ||
6163b5d4 DT |
1477 | /* |
1478 | * checks if the csrow passed in is marked as SPARED, if so returns the new | |
1479 | * spare row | |
1480 | */ | |
11c75ead | 1481 | static int f10_process_possible_spare(struct amd64_pvt *pvt, u8 dct, int csrow) |
6163b5d4 | 1482 | { |
614ec9d8 BP |
1483 | int tmp_cs; |
1484 | ||
1485 | if (online_spare_swap_done(pvt, dct) && | |
1486 | csrow == online_spare_bad_dramcs(pvt, dct)) { | |
1487 | ||
1488 | for_each_chip_select(tmp_cs, dct, pvt) { | |
1489 | if (chip_select_base(tmp_cs, dct, pvt) & 0x2) { | |
1490 | csrow = tmp_cs; | |
1491 | break; | |
1492 | } | |
1493 | } | |
6163b5d4 DT |
1494 | } |
1495 | return csrow; | |
1496 | } | |
1497 | ||
1498 | /* | |
1499 | * Iterate over the DRAM DCT "base" and "mask" registers looking for a | |
1500 | * SystemAddr match on the specified 'ChannelSelect' and 'NodeID' | |
1501 | * | |
1502 | * Return: | |
1503 | * -EINVAL: NOT FOUND | |
1504 | * 0..csrow = Chip-Select Row | |
1505 | */ | |
c7e5301a | 1506 | static int f1x_lookup_addr_in_dct(u64 in_addr, u8 nid, u8 dct) |
6163b5d4 DT |
1507 | { |
1508 | struct mem_ctl_info *mci; | |
1509 | struct amd64_pvt *pvt; | |
11c75ead | 1510 | u64 cs_base, cs_mask; |
6163b5d4 DT |
1511 | int cs_found = -EINVAL; |
1512 | int csrow; | |
1513 | ||
cc4d8860 | 1514 | mci = mcis[nid]; |
6163b5d4 DT |
1515 | if (!mci) |
1516 | return cs_found; | |
1517 | ||
1518 | pvt = mci->pvt_info; | |
1519 | ||
956b9ba1 | 1520 | edac_dbg(1, "input addr: 0x%llx, DCT: %d\n", in_addr, dct); |
6163b5d4 | 1521 | |
11c75ead BP |
1522 | for_each_chip_select(csrow, dct, pvt) { |
1523 | if (!csrow_enabled(csrow, dct, pvt)) | |
6163b5d4 DT |
1524 | continue; |
1525 | ||
11c75ead | 1526 | get_cs_base_and_mask(pvt, csrow, dct, &cs_base, &cs_mask); |
6163b5d4 | 1527 | |
956b9ba1 JP |
1528 | edac_dbg(1, " CSROW=%d CSBase=0x%llx CSMask=0x%llx\n", |
1529 | csrow, cs_base, cs_mask); | |
6163b5d4 | 1530 | |
11c75ead | 1531 | cs_mask = ~cs_mask; |
6163b5d4 | 1532 | |
956b9ba1 JP |
1533 | edac_dbg(1, " (InputAddr & ~CSMask)=0x%llx (CSBase & ~CSMask)=0x%llx\n", |
1534 | (in_addr & cs_mask), (cs_base & cs_mask)); | |
6163b5d4 | 1535 | |
11c75ead | 1536 | if ((in_addr & cs_mask) == (cs_base & cs_mask)) { |
18b94f66 AG |
1537 | if (pvt->fam == 0x15 && pvt->model >= 0x30) { |
1538 | cs_found = csrow; | |
1539 | break; | |
1540 | } | |
11c75ead | 1541 | cs_found = f10_process_possible_spare(pvt, dct, csrow); |
6163b5d4 | 1542 | |
956b9ba1 | 1543 | edac_dbg(1, " MATCH csrow=%d\n", cs_found); |
6163b5d4 DT |
1544 | break; |
1545 | } | |
1546 | } | |
1547 | return cs_found; | |
1548 | } | |
1549 | ||
95b0ef55 BP |
1550 | /* |
1551 | * See F2x10C. Non-interleaved graphics framebuffer memory under the 16G is | |
1552 | * swapped with a region located at the bottom of memory so that the GPU can use | |
1553 | * the interleaved region and thus two channels. | |
1554 | */ | |
b15f0fca | 1555 | static u64 f1x_swap_interleaved_region(struct amd64_pvt *pvt, u64 sys_addr) |
95b0ef55 BP |
1556 | { |
1557 | u32 swap_reg, swap_base, swap_limit, rgn_size, tmp_addr; | |
1558 | ||
a4b4bedc | 1559 | if (pvt->fam == 0x10) { |
95b0ef55 | 1560 | /* only revC3 and revE have that feature */ |
a4b4bedc | 1561 | if (pvt->model < 4 || (pvt->model < 0xa && pvt->stepping < 3)) |
95b0ef55 BP |
1562 | return sys_addr; |
1563 | } | |
1564 | ||
7981a28f | 1565 | amd64_read_pci_cfg(pvt->F2, SWAP_INTLV_REG, &swap_reg); |
95b0ef55 BP |
1566 | |
1567 | if (!(swap_reg & 0x1)) | |
1568 | return sys_addr; | |
1569 | ||
1570 | swap_base = (swap_reg >> 3) & 0x7f; | |
1571 | swap_limit = (swap_reg >> 11) & 0x7f; | |
1572 | rgn_size = (swap_reg >> 20) & 0x7f; | |
1573 | tmp_addr = sys_addr >> 27; | |
1574 | ||
1575 | if (!(sys_addr >> 34) && | |
1576 | (((tmp_addr >= swap_base) && | |
1577 | (tmp_addr <= swap_limit)) || | |
1578 | (tmp_addr < rgn_size))) | |
1579 | return sys_addr ^ (u64)swap_base << 27; | |
1580 | ||
1581 | return sys_addr; | |
1582 | } | |
1583 | ||
f71d0a05 | 1584 | /* For a given @dram_range, check if @sys_addr falls within it. */ |
e761359a | 1585 | static int f1x_match_to_this_node(struct amd64_pvt *pvt, unsigned range, |
33ca0643 | 1586 | u64 sys_addr, int *chan_sel) |
f71d0a05 | 1587 | { |
229a7a11 | 1588 | int cs_found = -EINVAL; |
c8e518d5 | 1589 | u64 chan_addr; |
5d4b58e8 | 1590 | u32 dct_sel_base; |
11c75ead | 1591 | u8 channel; |
229a7a11 | 1592 | bool high_range = false; |
f71d0a05 | 1593 | |
7f19bf75 | 1594 | u8 node_id = dram_dst_node(pvt, range); |
229a7a11 | 1595 | u8 intlv_en = dram_intlv_en(pvt, range); |
7f19bf75 | 1596 | u32 intlv_sel = dram_intlv_sel(pvt, range); |
f71d0a05 | 1597 | |
956b9ba1 JP |
1598 | edac_dbg(1, "(range %d) SystemAddr= 0x%llx Limit=0x%llx\n", |
1599 | range, sys_addr, get_dram_limit(pvt, range)); | |
f71d0a05 | 1600 | |
355fba60 BP |
1601 | if (dhar_valid(pvt) && |
1602 | dhar_base(pvt) <= sys_addr && | |
1603 | sys_addr < BIT_64(32)) { | |
1604 | amd64_warn("Huh? Address is in the MMIO hole: 0x%016llx\n", | |
1605 | sys_addr); | |
1606 | return -EINVAL; | |
1607 | } | |
1608 | ||
f030ddfb | 1609 | if (intlv_en && (intlv_sel != ((sys_addr >> 12) & intlv_en))) |
f71d0a05 DT |
1610 | return -EINVAL; |
1611 | ||
b15f0fca | 1612 | sys_addr = f1x_swap_interleaved_region(pvt, sys_addr); |
95b0ef55 | 1613 | |
f71d0a05 DT |
1614 | dct_sel_base = dct_sel_baseaddr(pvt); |
1615 | ||
1616 | /* | |
1617 | * check whether addresses >= DctSelBaseAddr[47:27] are to be used to | |
1618 | * select between DCT0 and DCT1. | |
1619 | */ | |
1620 | if (dct_high_range_enabled(pvt) && | |
1621 | !dct_ganging_enabled(pvt) && | |
1622 | ((sys_addr >> 27) >= (dct_sel_base >> 11))) | |
229a7a11 | 1623 | high_range = true; |
f71d0a05 | 1624 | |
b15f0fca | 1625 | channel = f1x_determine_channel(pvt, sys_addr, high_range, intlv_en); |
f71d0a05 | 1626 | |
b15f0fca | 1627 | chan_addr = f1x_get_norm_dct_addr(pvt, range, sys_addr, |
c8e518d5 | 1628 | high_range, dct_sel_base); |
f71d0a05 | 1629 | |
e2f79dbd BP |
1630 | /* Remove node interleaving, see F1x120 */ |
1631 | if (intlv_en) | |
1632 | chan_addr = ((chan_addr >> (12 + hweight8(intlv_en))) << 12) | | |
1633 | (chan_addr & 0xfff); | |
f71d0a05 | 1634 | |
5d4b58e8 | 1635 | /* remove channel interleave */ |
f71d0a05 DT |
1636 | if (dct_interleave_enabled(pvt) && |
1637 | !dct_high_range_enabled(pvt) && | |
1638 | !dct_ganging_enabled(pvt)) { | |
5d4b58e8 BP |
1639 | |
1640 | if (dct_sel_interleave_addr(pvt) != 1) { | |
1641 | if (dct_sel_interleave_addr(pvt) == 0x3) | |
1642 | /* hash 9 */ | |
1643 | chan_addr = ((chan_addr >> 10) << 9) | | |
1644 | (chan_addr & 0x1ff); | |
1645 | else | |
1646 | /* A[6] or hash 6 */ | |
1647 | chan_addr = ((chan_addr >> 7) << 6) | | |
1648 | (chan_addr & 0x3f); | |
1649 | } else | |
1650 | /* A[12] */ | |
1651 | chan_addr = ((chan_addr >> 13) << 12) | | |
1652 | (chan_addr & 0xfff); | |
f71d0a05 DT |
1653 | } |
1654 | ||
956b9ba1 | 1655 | edac_dbg(1, " Normalized DCT addr: 0x%llx\n", chan_addr); |
f71d0a05 | 1656 | |
b15f0fca | 1657 | cs_found = f1x_lookup_addr_in_dct(chan_addr, node_id, channel); |
f71d0a05 | 1658 | |
33ca0643 | 1659 | if (cs_found >= 0) |
f71d0a05 | 1660 | *chan_sel = channel; |
33ca0643 | 1661 | |
f71d0a05 DT |
1662 | return cs_found; |
1663 | } | |
1664 | ||
18b94f66 AG |
1665 | static int f15_m30h_match_to_this_node(struct amd64_pvt *pvt, unsigned range, |
1666 | u64 sys_addr, int *chan_sel) | |
1667 | { | |
1668 | int cs_found = -EINVAL; | |
1669 | int num_dcts_intlv = 0; | |
1670 | u64 chan_addr, chan_offset; | |
1671 | u64 dct_base, dct_limit; | |
1672 | u32 dct_cont_base_reg, dct_cont_limit_reg, tmp; | |
1673 | u8 channel, alias_channel, leg_mmio_hole, dct_sel, dct_offset_en; | |
1674 | ||
1675 | u64 dhar_offset = f10_dhar_offset(pvt); | |
1676 | u8 intlv_addr = dct_sel_interleave_addr(pvt); | |
1677 | u8 node_id = dram_dst_node(pvt, range); | |
1678 | u8 intlv_en = dram_intlv_en(pvt, range); | |
1679 | ||
1680 | amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &dct_cont_base_reg); | |
1681 | amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &dct_cont_limit_reg); | |
1682 | ||
1683 | dct_offset_en = (u8) ((dct_cont_base_reg >> 3) & BIT(0)); | |
1684 | dct_sel = (u8) ((dct_cont_base_reg >> 4) & 0x7); | |
1685 | ||
1686 | edac_dbg(1, "(range %d) SystemAddr= 0x%llx Limit=0x%llx\n", | |
1687 | range, sys_addr, get_dram_limit(pvt, range)); | |
1688 | ||
1689 | if (!(get_dram_base(pvt, range) <= sys_addr) && | |
1690 | !(get_dram_limit(pvt, range) >= sys_addr)) | |
1691 | return -EINVAL; | |
1692 | ||
1693 | if (dhar_valid(pvt) && | |
1694 | dhar_base(pvt) <= sys_addr && | |
1695 | sys_addr < BIT_64(32)) { | |
1696 | amd64_warn("Huh? Address is in the MMIO hole: 0x%016llx\n", | |
1697 | sys_addr); | |
1698 | return -EINVAL; | |
1699 | } | |
1700 | ||
1701 | /* Verify sys_addr is within DCT Range. */ | |
4fc06b31 AG |
1702 | dct_base = (u64) dct_sel_baseaddr(pvt); |
1703 | dct_limit = (dct_cont_limit_reg >> 11) & 0x1FFF; | |
18b94f66 AG |
1704 | |
1705 | if (!(dct_cont_base_reg & BIT(0)) && | |
4fc06b31 AG |
1706 | !(dct_base <= (sys_addr >> 27) && |
1707 | dct_limit >= (sys_addr >> 27))) | |
18b94f66 AG |
1708 | return -EINVAL; |
1709 | ||
1710 | /* Verify number of dct's that participate in channel interleaving. */ | |
1711 | num_dcts_intlv = (int) hweight8(intlv_en); | |
1712 | ||
1713 | if (!(num_dcts_intlv % 2 == 0) || (num_dcts_intlv > 4)) | |
1714 | return -EINVAL; | |
1715 | ||
1716 | channel = f15_m30h_determine_channel(pvt, sys_addr, intlv_en, | |
1717 | num_dcts_intlv, dct_sel); | |
1718 | ||
1719 | /* Verify we stay within the MAX number of channels allowed */ | |
7f3f5240 | 1720 | if (channel > 3) |
18b94f66 AG |
1721 | return -EINVAL; |
1722 | ||
1723 | leg_mmio_hole = (u8) (dct_cont_base_reg >> 1 & BIT(0)); | |
1724 | ||
1725 | /* Get normalized DCT addr */ | |
1726 | if (leg_mmio_hole && (sys_addr >= BIT_64(32))) | |
1727 | chan_offset = dhar_offset; | |
1728 | else | |
4fc06b31 | 1729 | chan_offset = dct_base << 27; |
18b94f66 AG |
1730 | |
1731 | chan_addr = sys_addr - chan_offset; | |
1732 | ||
1733 | /* remove channel interleave */ | |
1734 | if (num_dcts_intlv == 2) { | |
1735 | if (intlv_addr == 0x4) | |
1736 | chan_addr = ((chan_addr >> 9) << 8) | | |
1737 | (chan_addr & 0xff); | |
1738 | else if (intlv_addr == 0x5) | |
1739 | chan_addr = ((chan_addr >> 10) << 9) | | |
1740 | (chan_addr & 0x1ff); | |
1741 | else | |
1742 | return -EINVAL; | |
1743 | ||
1744 | } else if (num_dcts_intlv == 4) { | |
1745 | if (intlv_addr == 0x4) | |
1746 | chan_addr = ((chan_addr >> 10) << 8) | | |
1747 | (chan_addr & 0xff); | |
1748 | else if (intlv_addr == 0x5) | |
1749 | chan_addr = ((chan_addr >> 11) << 9) | | |
1750 | (chan_addr & 0x1ff); | |
1751 | else | |
1752 | return -EINVAL; | |
1753 | } | |
1754 | ||
1755 | if (dct_offset_en) { | |
1756 | amd64_read_pci_cfg(pvt->F1, | |
1757 | DRAM_CONT_HIGH_OFF + (int) channel * 4, | |
1758 | &tmp); | |
4fc06b31 | 1759 | chan_addr += (u64) ((tmp >> 11) & 0xfff) << 27; |
18b94f66 AG |
1760 | } |
1761 | ||
1762 | f15h_select_dct(pvt, channel); | |
1763 | ||
1764 | edac_dbg(1, " Normalized DCT addr: 0x%llx\n", chan_addr); | |
1765 | ||
1766 | /* | |
1767 | * Find Chip select: | |
1768 | * if channel = 3, then alias it to 1. This is because, in F15 M30h, | |
1769 | * there is support for 4 DCT's, but only 2 are currently functional. | |
1770 | * They are DCT0 and DCT3. But we have read all registers of DCT3 into | |
1771 | * pvt->csels[1]. So we need to use '1' here to get correct info. | |
1772 | * Refer F15 M30h BKDG Section 2.10 and 2.10.3 for clarifications. | |
1773 | */ | |
1774 | alias_channel = (channel == 3) ? 1 : channel; | |
1775 | ||
1776 | cs_found = f1x_lookup_addr_in_dct(chan_addr, node_id, alias_channel); | |
1777 | ||
1778 | if (cs_found >= 0) | |
1779 | *chan_sel = alias_channel; | |
1780 | ||
1781 | return cs_found; | |
1782 | } | |
1783 | ||
1784 | static int f1x_translate_sysaddr_to_cs(struct amd64_pvt *pvt, | |
1785 | u64 sys_addr, | |
1786 | int *chan_sel) | |
f71d0a05 | 1787 | { |
e761359a BP |
1788 | int cs_found = -EINVAL; |
1789 | unsigned range; | |
f71d0a05 | 1790 | |
7f19bf75 | 1791 | for (range = 0; range < DRAM_RANGES; range++) { |
7f19bf75 | 1792 | if (!dram_rw(pvt, range)) |
f71d0a05 DT |
1793 | continue; |
1794 | ||
18b94f66 AG |
1795 | if (pvt->fam == 0x15 && pvt->model >= 0x30) |
1796 | cs_found = f15_m30h_match_to_this_node(pvt, range, | |
1797 | sys_addr, | |
1798 | chan_sel); | |
f71d0a05 | 1799 | |
18b94f66 AG |
1800 | else if ((get_dram_base(pvt, range) <= sys_addr) && |
1801 | (get_dram_limit(pvt, range) >= sys_addr)) { | |
b15f0fca | 1802 | cs_found = f1x_match_to_this_node(pvt, range, |
33ca0643 | 1803 | sys_addr, chan_sel); |
f71d0a05 DT |
1804 | if (cs_found >= 0) |
1805 | break; | |
1806 | } | |
1807 | } | |
1808 | return cs_found; | |
1809 | } | |
1810 | ||
1811 | /* | |
bdc30a0c BP |
1812 | * For reference see "2.8.5 Routing DRAM Requests" in F10 BKDG. This code maps |
1813 | * a @sys_addr to NodeID, DCT (channel) and chip select (CSROW). | |
f71d0a05 | 1814 | * |
bdc30a0c BP |
1815 | * The @sys_addr is usually an error address received from the hardware |
1816 | * (MCX_ADDR). | |
f71d0a05 | 1817 | */ |
b15f0fca | 1818 | static void f1x_map_sysaddr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr, |
33ca0643 | 1819 | struct err_info *err) |
f71d0a05 DT |
1820 | { |
1821 | struct amd64_pvt *pvt = mci->pvt_info; | |
f71d0a05 | 1822 | |
33ca0643 | 1823 | error_address_to_page_and_offset(sys_addr, err); |
ab5a503c | 1824 | |
33ca0643 BP |
1825 | err->csrow = f1x_translate_sysaddr_to_cs(pvt, sys_addr, &err->channel); |
1826 | if (err->csrow < 0) { | |
1827 | err->err_code = ERR_CSROW; | |
bdc30a0c BP |
1828 | return; |
1829 | } | |
1830 | ||
bdc30a0c BP |
1831 | /* |
1832 | * We need the syndromes for channel detection only when we're | |
1833 | * ganged. Otherwise @chan should already contain the channel at | |
1834 | * this point. | |
1835 | */ | |
a97fa68e | 1836 | if (dct_ganging_enabled(pvt)) |
33ca0643 | 1837 | err->channel = get_channel_from_ecc_syndrome(mci, err->syndrome); |
f71d0a05 DT |
1838 | } |
1839 | ||
f71d0a05 | 1840 | /* |
8566c4df | 1841 | * debug routine to display the memory sizes of all logical DIMMs and its |
cb328507 | 1842 | * CSROWs |
f71d0a05 | 1843 | */ |
d1ea71cd | 1844 | static void debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl) |
f71d0a05 | 1845 | { |
bb89f5a0 | 1846 | int dimm, size0, size1; |
525a1b20 BP |
1847 | u32 *dcsb = ctrl ? pvt->csels[1].csbases : pvt->csels[0].csbases; |
1848 | u32 dbam = ctrl ? pvt->dbam1 : pvt->dbam0; | |
f71d0a05 | 1849 | |
a4b4bedc | 1850 | if (pvt->fam == 0xf) { |
8566c4df | 1851 | /* K8 families < revF not supported yet */ |
1433eb99 | 1852 | if (pvt->ext_model < K8_REV_F) |
8566c4df BP |
1853 | return; |
1854 | else | |
1855 | WARN_ON(ctrl != 0); | |
1856 | } | |
1857 | ||
7981a28f AG |
1858 | if (pvt->fam == 0x10) { |
1859 | dbam = (ctrl && !dct_ganging_enabled(pvt)) ? pvt->dbam1 | |
1860 | : pvt->dbam0; | |
1861 | dcsb = (ctrl && !dct_ganging_enabled(pvt)) ? | |
1862 | pvt->csels[1].csbases : | |
1863 | pvt->csels[0].csbases; | |
1864 | } else if (ctrl) { | |
1865 | dbam = pvt->dbam0; | |
1866 | dcsb = pvt->csels[1].csbases; | |
1867 | } | |
956b9ba1 JP |
1868 | edac_dbg(1, "F2x%d80 (DRAM Bank Address Mapping): 0x%08x\n", |
1869 | ctrl, dbam); | |
f71d0a05 | 1870 | |
8566c4df BP |
1871 | edac_printk(KERN_DEBUG, EDAC_MC, "DCT%d chip selects:\n", ctrl); |
1872 | ||
f71d0a05 DT |
1873 | /* Dump memory sizes for DIMM and its CSROWs */ |
1874 | for (dimm = 0; dimm < 4; dimm++) { | |
1875 | ||
1876 | size0 = 0; | |
11c75ead | 1877 | if (dcsb[dimm*2] & DCSB_CS_ENABLE) |
a597d2a5 AG |
1878 | /* For f15m60h, need multiplier for LRDIMM cs_size |
1879 | * calculation. We pass 'dimm' value to the dbam_to_cs | |
1880 | * mapper so we can find the multiplier from the | |
1881 | * corresponding DCSM. | |
1882 | */ | |
41d8bfab | 1883 | size0 = pvt->ops->dbam_to_cs(pvt, ctrl, |
a597d2a5 AG |
1884 | DBAM_DIMM(dimm, dbam), |
1885 | dimm); | |
f71d0a05 DT |
1886 | |
1887 | size1 = 0; | |
11c75ead | 1888 | if (dcsb[dimm*2 + 1] & DCSB_CS_ENABLE) |
41d8bfab | 1889 | size1 = pvt->ops->dbam_to_cs(pvt, ctrl, |
a597d2a5 AG |
1890 | DBAM_DIMM(dimm, dbam), |
1891 | dimm); | |
f71d0a05 | 1892 | |
24f9a7fe | 1893 | amd64_info(EDAC_MC ": %d: %5dMB %d: %5dMB\n", |
bb89f5a0 BP |
1894 | dimm * 2, size0, |
1895 | dimm * 2 + 1, size1); | |
f71d0a05 DT |
1896 | } |
1897 | } | |
1898 | ||
d1ea71cd | 1899 | static struct amd64_family_type family_types[] = { |
4d37607a | 1900 | [K8_CPUS] = { |
0092b20d | 1901 | .ctl_name = "K8", |
8d5b5d9c BP |
1902 | .f1_id = PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP, |
1903 | .f3_id = PCI_DEVICE_ID_AMD_K8_NB_MISC, | |
4d37607a | 1904 | .ops = { |
1433eb99 | 1905 | .early_channel_count = k8_early_channel_count, |
1433eb99 BP |
1906 | .map_sysaddr_to_csrow = k8_map_sysaddr_to_csrow, |
1907 | .dbam_to_cs = k8_dbam_to_chip_select, | |
4d37607a DT |
1908 | } |
1909 | }, | |
1910 | [F10_CPUS] = { | |
0092b20d | 1911 | .ctl_name = "F10h", |
8d5b5d9c BP |
1912 | .f1_id = PCI_DEVICE_ID_AMD_10H_NB_MAP, |
1913 | .f3_id = PCI_DEVICE_ID_AMD_10H_NB_MISC, | |
4d37607a | 1914 | .ops = { |
7d20d14d | 1915 | .early_channel_count = f1x_early_channel_count, |
b15f0fca | 1916 | .map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow, |
1433eb99 | 1917 | .dbam_to_cs = f10_dbam_to_chip_select, |
b2b0c605 BP |
1918 | } |
1919 | }, | |
1920 | [F15_CPUS] = { | |
1921 | .ctl_name = "F15h", | |
df71a053 BP |
1922 | .f1_id = PCI_DEVICE_ID_AMD_15H_NB_F1, |
1923 | .f3_id = PCI_DEVICE_ID_AMD_15H_NB_F3, | |
b2b0c605 | 1924 | .ops = { |
7d20d14d | 1925 | .early_channel_count = f1x_early_channel_count, |
b15f0fca | 1926 | .map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow, |
41d8bfab | 1927 | .dbam_to_cs = f15_dbam_to_chip_select, |
4d37607a DT |
1928 | } |
1929 | }, | |
18b94f66 AG |
1930 | [F15_M30H_CPUS] = { |
1931 | .ctl_name = "F15h_M30h", | |
1932 | .f1_id = PCI_DEVICE_ID_AMD_15H_M30H_NB_F1, | |
1933 | .f3_id = PCI_DEVICE_ID_AMD_15H_M30H_NB_F3, | |
1934 | .ops = { | |
1935 | .early_channel_count = f1x_early_channel_count, | |
1936 | .map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow, | |
1937 | .dbam_to_cs = f16_dbam_to_chip_select, | |
18b94f66 AG |
1938 | } |
1939 | }, | |
a597d2a5 AG |
1940 | [F15_M60H_CPUS] = { |
1941 | .ctl_name = "F15h_M60h", | |
1942 | .f1_id = PCI_DEVICE_ID_AMD_15H_M60H_NB_F1, | |
1943 | .f3_id = PCI_DEVICE_ID_AMD_15H_M60H_NB_F3, | |
1944 | .ops = { | |
1945 | .early_channel_count = f1x_early_channel_count, | |
1946 | .map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow, | |
1947 | .dbam_to_cs = f15_m60h_dbam_to_chip_select, | |
1948 | } | |
1949 | }, | |
94c1acf2 AG |
1950 | [F16_CPUS] = { |
1951 | .ctl_name = "F16h", | |
1952 | .f1_id = PCI_DEVICE_ID_AMD_16H_NB_F1, | |
1953 | .f3_id = PCI_DEVICE_ID_AMD_16H_NB_F3, | |
1954 | .ops = { | |
1955 | .early_channel_count = f1x_early_channel_count, | |
1956 | .map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow, | |
1957 | .dbam_to_cs = f16_dbam_to_chip_select, | |
94c1acf2 AG |
1958 | } |
1959 | }, | |
85a8885b AG |
1960 | [F16_M30H_CPUS] = { |
1961 | .ctl_name = "F16h_M30h", | |
1962 | .f1_id = PCI_DEVICE_ID_AMD_16H_M30H_NB_F1, | |
1963 | .f3_id = PCI_DEVICE_ID_AMD_16H_M30H_NB_F3, | |
1964 | .ops = { | |
1965 | .early_channel_count = f1x_early_channel_count, | |
1966 | .map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow, | |
1967 | .dbam_to_cs = f16_dbam_to_chip_select, | |
85a8885b AG |
1968 | } |
1969 | }, | |
4d37607a DT |
1970 | }; |
1971 | ||
b1289d6f | 1972 | /* |
bfc04aec BP |
1973 | * These are tables of eigenvectors (one per line) which can be used for the |
1974 | * construction of the syndrome tables. The modified syndrome search algorithm | |
1975 | * uses those to find the symbol in error and thus the DIMM. | |
b1289d6f | 1976 | * |
bfc04aec | 1977 | * Algorithm courtesy of Ross LaFetra from AMD. |
b1289d6f | 1978 | */ |
c7e5301a | 1979 | static const u16 x4_vectors[] = { |
bfc04aec BP |
1980 | 0x2f57, 0x1afe, 0x66cc, 0xdd88, |
1981 | 0x11eb, 0x3396, 0x7f4c, 0xeac8, | |
1982 | 0x0001, 0x0002, 0x0004, 0x0008, | |
1983 | 0x1013, 0x3032, 0x4044, 0x8088, | |
1984 | 0x106b, 0x30d6, 0x70fc, 0xe0a8, | |
1985 | 0x4857, 0xc4fe, 0x13cc, 0x3288, | |
1986 | 0x1ac5, 0x2f4a, 0x5394, 0xa1e8, | |
1987 | 0x1f39, 0x251e, 0xbd6c, 0x6bd8, | |
1988 | 0x15c1, 0x2a42, 0x89ac, 0x4758, | |
1989 | 0x2b03, 0x1602, 0x4f0c, 0xca08, | |
1990 | 0x1f07, 0x3a0e, 0x6b04, 0xbd08, | |
1991 | 0x8ba7, 0x465e, 0x244c, 0x1cc8, | |
1992 | 0x2b87, 0x164e, 0x642c, 0xdc18, | |
1993 | 0x40b9, 0x80de, 0x1094, 0x20e8, | |
1994 | 0x27db, 0x1eb6, 0x9dac, 0x7b58, | |
1995 | 0x11c1, 0x2242, 0x84ac, 0x4c58, | |
1996 | 0x1be5, 0x2d7a, 0x5e34, 0xa718, | |
1997 | 0x4b39, 0x8d1e, 0x14b4, 0x28d8, | |
1998 | 0x4c97, 0xc87e, 0x11fc, 0x33a8, | |
1999 | 0x8e97, 0x497e, 0x2ffc, 0x1aa8, | |
2000 | 0x16b3, 0x3d62, 0x4f34, 0x8518, | |
2001 | 0x1e2f, 0x391a, 0x5cac, 0xf858, | |
2002 | 0x1d9f, 0x3b7a, 0x572c, 0xfe18, | |
2003 | 0x15f5, 0x2a5a, 0x5264, 0xa3b8, | |
2004 | 0x1dbb, 0x3b66, 0x715c, 0xe3f8, | |
2005 | 0x4397, 0xc27e, 0x17fc, 0x3ea8, | |
2006 | 0x1617, 0x3d3e, 0x6464, 0xb8b8, | |
2007 | 0x23ff, 0x12aa, 0xab6c, 0x56d8, | |
2008 | 0x2dfb, 0x1ba6, 0x913c, 0x7328, | |
2009 | 0x185d, 0x2ca6, 0x7914, 0x9e28, | |
2010 | 0x171b, 0x3e36, 0x7d7c, 0xebe8, | |
2011 | 0x4199, 0x82ee, 0x19f4, 0x2e58, | |
2012 | 0x4807, 0xc40e, 0x130c, 0x3208, | |
2013 | 0x1905, 0x2e0a, 0x5804, 0xac08, | |
2014 | 0x213f, 0x132a, 0xadfc, 0x5ba8, | |
2015 | 0x19a9, 0x2efe, 0xb5cc, 0x6f88, | |
b1289d6f DT |
2016 | }; |
2017 | ||
c7e5301a | 2018 | static const u16 x8_vectors[] = { |
bfc04aec BP |
2019 | 0x0145, 0x028a, 0x2374, 0x43c8, 0xa1f0, 0x0520, 0x0a40, 0x1480, |
2020 | 0x0211, 0x0422, 0x0844, 0x1088, 0x01b0, 0x44e0, 0x23c0, 0xed80, | |
2021 | 0x1011, 0x0116, 0x022c, 0x0458, 0x08b0, 0x8c60, 0x2740, 0x4e80, | |
2022 | 0x0411, 0x0822, 0x1044, 0x0158, 0x02b0, 0x2360, 0x46c0, 0xab80, | |
2023 | 0x0811, 0x1022, 0x012c, 0x0258, 0x04b0, 0x4660, 0x8cc0, 0x2780, | |
2024 | 0x2071, 0x40e2, 0xa0c4, 0x0108, 0x0210, 0x0420, 0x0840, 0x1080, | |
2025 | 0x4071, 0x80e2, 0x0104, 0x0208, 0x0410, 0x0820, 0x1040, 0x2080, | |
2026 | 0x8071, 0x0102, 0x0204, 0x0408, 0x0810, 0x1020, 0x2040, 0x4080, | |
2027 | 0x019d, 0x03d6, 0x136c, 0x2198, 0x50b0, 0xb2e0, 0x0740, 0x0e80, | |
2028 | 0x0189, 0x03ea, 0x072c, 0x0e58, 0x1cb0, 0x56e0, 0x37c0, 0xf580, | |
2029 | 0x01fd, 0x0376, 0x06ec, 0x0bb8, 0x1110, 0x2220, 0x4440, 0x8880, | |
2030 | 0x0163, 0x02c6, 0x1104, 0x0758, 0x0eb0, 0x2be0, 0x6140, 0xc280, | |
2031 | 0x02fd, 0x01c6, 0x0b5c, 0x1108, 0x07b0, 0x25a0, 0x8840, 0x6180, | |
2032 | 0x0801, 0x012e, 0x025c, 0x04b8, 0x1370, 0x26e0, 0x57c0, 0xb580, | |
2033 | 0x0401, 0x0802, 0x015c, 0x02b8, 0x22b0, 0x13e0, 0x7140, 0xe280, | |
2034 | 0x0201, 0x0402, 0x0804, 0x01b8, 0x11b0, 0x31a0, 0x8040, 0x7180, | |
2035 | 0x0101, 0x0202, 0x0404, 0x0808, 0x1010, 0x2020, 0x4040, 0x8080, | |
2036 | 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080, | |
2037 | 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000, | |
2038 | }; | |
2039 | ||
c7e5301a | 2040 | static int decode_syndrome(u16 syndrome, const u16 *vectors, unsigned num_vecs, |
d34a6ecd | 2041 | unsigned v_dim) |
b1289d6f | 2042 | { |
bfc04aec BP |
2043 | unsigned int i, err_sym; |
2044 | ||
2045 | for (err_sym = 0; err_sym < num_vecs / v_dim; err_sym++) { | |
2046 | u16 s = syndrome; | |
d34a6ecd BP |
2047 | unsigned v_idx = err_sym * v_dim; |
2048 | unsigned v_end = (err_sym + 1) * v_dim; | |
bfc04aec BP |
2049 | |
2050 | /* walk over all 16 bits of the syndrome */ | |
2051 | for (i = 1; i < (1U << 16); i <<= 1) { | |
2052 | ||
2053 | /* if bit is set in that eigenvector... */ | |
2054 | if (v_idx < v_end && vectors[v_idx] & i) { | |
2055 | u16 ev_comp = vectors[v_idx++]; | |
2056 | ||
2057 | /* ... and bit set in the modified syndrome, */ | |
2058 | if (s & i) { | |
2059 | /* remove it. */ | |
2060 | s ^= ev_comp; | |
4d37607a | 2061 | |
bfc04aec BP |
2062 | if (!s) |
2063 | return err_sym; | |
2064 | } | |
b1289d6f | 2065 | |
bfc04aec BP |
2066 | } else if (s & i) |
2067 | /* can't get to zero, move to next symbol */ | |
2068 | break; | |
2069 | } | |
b1289d6f DT |
2070 | } |
2071 | ||
956b9ba1 | 2072 | edac_dbg(0, "syndrome(%x) not found\n", syndrome); |
b1289d6f DT |
2073 | return -1; |
2074 | } | |
d27bf6fa | 2075 | |
bfc04aec BP |
2076 | static int map_err_sym_to_channel(int err_sym, int sym_size) |
2077 | { | |
2078 | if (sym_size == 4) | |
2079 | switch (err_sym) { | |
2080 | case 0x20: | |
2081 | case 0x21: | |
2082 | return 0; | |
2083 | break; | |
2084 | case 0x22: | |
2085 | case 0x23: | |
2086 | return 1; | |
2087 | break; | |
2088 | default: | |
2089 | return err_sym >> 4; | |
2090 | break; | |
2091 | } | |
2092 | /* x8 symbols */ | |
2093 | else | |
2094 | switch (err_sym) { | |
2095 | /* imaginary bits not in a DIMM */ | |
2096 | case 0x10: | |
2097 | WARN(1, KERN_ERR "Invalid error symbol: 0x%x\n", | |
2098 | err_sym); | |
2099 | return -1; | |
2100 | break; | |
2101 | ||
2102 | case 0x11: | |
2103 | return 0; | |
2104 | break; | |
2105 | case 0x12: | |
2106 | return 1; | |
2107 | break; | |
2108 | default: | |
2109 | return err_sym >> 3; | |
2110 | break; | |
2111 | } | |
2112 | return -1; | |
2113 | } | |
2114 | ||
2115 | static int get_channel_from_ecc_syndrome(struct mem_ctl_info *mci, u16 syndrome) | |
2116 | { | |
2117 | struct amd64_pvt *pvt = mci->pvt_info; | |
ad6a32e9 BP |
2118 | int err_sym = -1; |
2119 | ||
a3b7db09 | 2120 | if (pvt->ecc_sym_sz == 8) |
ad6a32e9 BP |
2121 | err_sym = decode_syndrome(syndrome, x8_vectors, |
2122 | ARRAY_SIZE(x8_vectors), | |
a3b7db09 BP |
2123 | pvt->ecc_sym_sz); |
2124 | else if (pvt->ecc_sym_sz == 4) | |
ad6a32e9 BP |
2125 | err_sym = decode_syndrome(syndrome, x4_vectors, |
2126 | ARRAY_SIZE(x4_vectors), | |
a3b7db09 | 2127 | pvt->ecc_sym_sz); |
ad6a32e9 | 2128 | else { |
a3b7db09 | 2129 | amd64_warn("Illegal syndrome type: %u\n", pvt->ecc_sym_sz); |
ad6a32e9 | 2130 | return err_sym; |
bfc04aec | 2131 | } |
ad6a32e9 | 2132 | |
a3b7db09 | 2133 | return map_err_sym_to_channel(err_sym, pvt->ecc_sym_sz); |
bfc04aec BP |
2134 | } |
2135 | ||
33ca0643 BP |
2136 | static void __log_bus_error(struct mem_ctl_info *mci, struct err_info *err, |
2137 | u8 ecc_type) | |
d27bf6fa | 2138 | { |
33ca0643 BP |
2139 | enum hw_event_mc_err_type err_type; |
2140 | const char *string; | |
d27bf6fa | 2141 | |
33ca0643 BP |
2142 | if (ecc_type == 2) |
2143 | err_type = HW_EVENT_ERR_CORRECTED; | |
2144 | else if (ecc_type == 1) | |
2145 | err_type = HW_EVENT_ERR_UNCORRECTED; | |
2146 | else { | |
2147 | WARN(1, "Something is rotten in the state of Denmark.\n"); | |
d27bf6fa DT |
2148 | return; |
2149 | } | |
2150 | ||
33ca0643 BP |
2151 | switch (err->err_code) { |
2152 | case DECODE_OK: | |
2153 | string = ""; | |
2154 | break; | |
2155 | case ERR_NODE: | |
2156 | string = "Failed to map error addr to a node"; | |
2157 | break; | |
2158 | case ERR_CSROW: | |
2159 | string = "Failed to map error addr to a csrow"; | |
2160 | break; | |
2161 | case ERR_CHANNEL: | |
2162 | string = "unknown syndrome - possible error reporting race"; | |
2163 | break; | |
2164 | default: | |
2165 | string = "WTF error"; | |
2166 | break; | |
d27bf6fa | 2167 | } |
33ca0643 BP |
2168 | |
2169 | edac_mc_handle_error(err_type, mci, 1, | |
2170 | err->page, err->offset, err->syndrome, | |
2171 | err->csrow, err->channel, -1, | |
2172 | string, ""); | |
d27bf6fa DT |
2173 | } |
2174 | ||
df781d03 | 2175 | static inline void decode_bus_error(int node_id, struct mce *m) |
d27bf6fa | 2176 | { |
df781d03 | 2177 | struct mem_ctl_info *mci = mcis[node_id]; |
33ca0643 | 2178 | struct amd64_pvt *pvt = mci->pvt_info; |
f192c7b1 | 2179 | u8 ecc_type = (m->status >> 45) & 0x3; |
66fed2d4 BP |
2180 | u8 xec = XEC(m->status, 0x1f); |
2181 | u16 ec = EC(m->status); | |
33ca0643 BP |
2182 | u64 sys_addr; |
2183 | struct err_info err; | |
d27bf6fa | 2184 | |
66fed2d4 | 2185 | /* Bail out early if this was an 'observed' error */ |
5980bb9c | 2186 | if (PP(ec) == NBSL_PP_OBS) |
b70ef010 | 2187 | return; |
d27bf6fa | 2188 | |
ecaf5606 BP |
2189 | /* Do only ECC errors */ |
2190 | if (xec && xec != F10_NBSL_EXT_ERR_ECC) | |
d27bf6fa | 2191 | return; |
d27bf6fa | 2192 | |
33ca0643 BP |
2193 | memset(&err, 0, sizeof(err)); |
2194 | ||
a4b4bedc | 2195 | sys_addr = get_error_address(pvt, m); |
33ca0643 | 2196 | |
ecaf5606 | 2197 | if (ecc_type == 2) |
33ca0643 BP |
2198 | err.syndrome = extract_syndrome(m->status); |
2199 | ||
2200 | pvt->ops->map_sysaddr_to_csrow(mci, sys_addr, &err); | |
2201 | ||
2202 | __log_bus_error(mci, &err, ecc_type); | |
d27bf6fa DT |
2203 | } |
2204 | ||
0ec449ee | 2205 | /* |
8d5b5d9c | 2206 | * Use pvt->F2 which contains the F2 CPU PCI device to get the related |
bbd0c1f6 | 2207 | * F1 (AddrMap) and F3 (Misc) devices. Return negative value on error. |
0ec449ee | 2208 | */ |
360b7f3c | 2209 | static int reserve_mc_sibling_devs(struct amd64_pvt *pvt, u16 f1_id, u16 f3_id) |
0ec449ee | 2210 | { |
0ec449ee | 2211 | /* Reserve the ADDRESS MAP Device */ |
8d5b5d9c BP |
2212 | pvt->F1 = pci_get_related_function(pvt->F2->vendor, f1_id, pvt->F2); |
2213 | if (!pvt->F1) { | |
24f9a7fe BP |
2214 | amd64_err("error address map device not found: " |
2215 | "vendor %x device 0x%x (broken BIOS?)\n", | |
2216 | PCI_VENDOR_ID_AMD, f1_id); | |
bbd0c1f6 | 2217 | return -ENODEV; |
0ec449ee DT |
2218 | } |
2219 | ||
2220 | /* Reserve the MISC Device */ | |
8d5b5d9c BP |
2221 | pvt->F3 = pci_get_related_function(pvt->F2->vendor, f3_id, pvt->F2); |
2222 | if (!pvt->F3) { | |
2223 | pci_dev_put(pvt->F1); | |
2224 | pvt->F1 = NULL; | |
0ec449ee | 2225 | |
24f9a7fe BP |
2226 | amd64_err("error F3 device not found: " |
2227 | "vendor %x device 0x%x (broken BIOS?)\n", | |
2228 | PCI_VENDOR_ID_AMD, f3_id); | |
0ec449ee | 2229 | |
bbd0c1f6 | 2230 | return -ENODEV; |
0ec449ee | 2231 | } |
956b9ba1 JP |
2232 | edac_dbg(1, "F1: %s\n", pci_name(pvt->F1)); |
2233 | edac_dbg(1, "F2: %s\n", pci_name(pvt->F2)); | |
2234 | edac_dbg(1, "F3: %s\n", pci_name(pvt->F3)); | |
0ec449ee DT |
2235 | |
2236 | return 0; | |
2237 | } | |
2238 | ||
360b7f3c | 2239 | static void free_mc_sibling_devs(struct amd64_pvt *pvt) |
0ec449ee | 2240 | { |
8d5b5d9c BP |
2241 | pci_dev_put(pvt->F1); |
2242 | pci_dev_put(pvt->F3); | |
0ec449ee DT |
2243 | } |
2244 | ||
2245 | /* | |
2246 | * Retrieve the hardware registers of the memory controller (this includes the | |
2247 | * 'Address Map' and 'Misc' device regs) | |
2248 | */ | |
360b7f3c | 2249 | static void read_mc_regs(struct amd64_pvt *pvt) |
0ec449ee | 2250 | { |
a4b4bedc | 2251 | unsigned range; |
0ec449ee | 2252 | u64 msr_val; |
ad6a32e9 | 2253 | u32 tmp; |
0ec449ee DT |
2254 | |
2255 | /* | |
2256 | * Retrieve TOP_MEM and TOP_MEM2; no masking off of reserved bits since | |
2257 | * those are Read-As-Zero | |
2258 | */ | |
e97f8bb8 | 2259 | rdmsrl(MSR_K8_TOP_MEM1, pvt->top_mem); |
956b9ba1 | 2260 | edac_dbg(0, " TOP_MEM: 0x%016llx\n", pvt->top_mem); |
0ec449ee DT |
2261 | |
2262 | /* check first whether TOP_MEM2 is enabled */ | |
2263 | rdmsrl(MSR_K8_SYSCFG, msr_val); | |
2264 | if (msr_val & (1U << 21)) { | |
e97f8bb8 | 2265 | rdmsrl(MSR_K8_TOP_MEM2, pvt->top_mem2); |
956b9ba1 | 2266 | edac_dbg(0, " TOP_MEM2: 0x%016llx\n", pvt->top_mem2); |
0ec449ee | 2267 | } else |
956b9ba1 | 2268 | edac_dbg(0, " TOP_MEM2 disabled\n"); |
0ec449ee | 2269 | |
5980bb9c | 2270 | amd64_read_pci_cfg(pvt->F3, NBCAP, &pvt->nbcap); |
0ec449ee | 2271 | |
5a5d2371 | 2272 | read_dram_ctl_register(pvt); |
0ec449ee | 2273 | |
7f19bf75 BP |
2274 | for (range = 0; range < DRAM_RANGES; range++) { |
2275 | u8 rw; | |
0ec449ee | 2276 | |
7f19bf75 BP |
2277 | /* read settings for this DRAM range */ |
2278 | read_dram_base_limit_regs(pvt, range); | |
2279 | ||
2280 | rw = dram_rw(pvt, range); | |
2281 | if (!rw) | |
2282 | continue; | |
2283 | ||
956b9ba1 JP |
2284 | edac_dbg(1, " DRAM range[%d], base: 0x%016llx; limit: 0x%016llx\n", |
2285 | range, | |
2286 | get_dram_base(pvt, range), | |
2287 | get_dram_limit(pvt, range)); | |
7f19bf75 | 2288 | |
956b9ba1 JP |
2289 | edac_dbg(1, " IntlvEn=%s; Range access: %s%s IntlvSel=%d DstNode=%d\n", |
2290 | dram_intlv_en(pvt, range) ? "Enabled" : "Disabled", | |
2291 | (rw & 0x1) ? "R" : "-", | |
2292 | (rw & 0x2) ? "W" : "-", | |
2293 | dram_intlv_sel(pvt, range), | |
2294 | dram_dst_node(pvt, range)); | |
0ec449ee DT |
2295 | } |
2296 | ||
b2b0c605 | 2297 | read_dct_base_mask(pvt); |
0ec449ee | 2298 | |
bc21fa57 | 2299 | amd64_read_pci_cfg(pvt->F1, DHAR, &pvt->dhar); |
7981a28f | 2300 | amd64_read_dct_pci_cfg(pvt, 0, DBAM0, &pvt->dbam0); |
0ec449ee | 2301 | |
8d5b5d9c | 2302 | amd64_read_pci_cfg(pvt->F3, F10_ONLINE_SPARE, &pvt->online_spare); |
0ec449ee | 2303 | |
7981a28f AG |
2304 | amd64_read_dct_pci_cfg(pvt, 0, DCLR0, &pvt->dclr0); |
2305 | amd64_read_dct_pci_cfg(pvt, 0, DCHR0, &pvt->dchr0); | |
0ec449ee | 2306 | |
78da121e | 2307 | if (!dct_ganging_enabled(pvt)) { |
7981a28f AG |
2308 | amd64_read_dct_pci_cfg(pvt, 1, DCLR0, &pvt->dclr1); |
2309 | amd64_read_dct_pci_cfg(pvt, 1, DCHR0, &pvt->dchr1); | |
0ec449ee | 2310 | } |
ad6a32e9 | 2311 | |
a3b7db09 | 2312 | pvt->ecc_sym_sz = 4; |
a597d2a5 AG |
2313 | determine_memory_type(pvt); |
2314 | edac_dbg(1, " DIMM type: %s\n", edac_mem_types[pvt->dram_type]); | |
a3b7db09 | 2315 | |
a4b4bedc | 2316 | if (pvt->fam >= 0x10) { |
b2b0c605 | 2317 | amd64_read_pci_cfg(pvt->F3, EXT_NB_MCA_CFG, &tmp); |
7981a28f | 2318 | /* F16h has only DCT0, so no need to read dbam1 */ |
a4b4bedc | 2319 | if (pvt->fam != 0x16) |
7981a28f | 2320 | amd64_read_dct_pci_cfg(pvt, 1, DBAM0, &pvt->dbam1); |
ad6a32e9 | 2321 | |
a3b7db09 | 2322 | /* F10h, revD and later can do x8 ECC too */ |
a4b4bedc | 2323 | if ((pvt->fam > 0x10 || pvt->model > 7) && tmp & BIT(25)) |
a3b7db09 BP |
2324 | pvt->ecc_sym_sz = 8; |
2325 | } | |
b2b0c605 | 2326 | dump_misc_regs(pvt); |
0ec449ee DT |
2327 | } |
2328 | ||
2329 | /* | |
2330 | * NOTE: CPU Revision Dependent code | |
2331 | * | |
2332 | * Input: | |
11c75ead | 2333 | * @csrow_nr ChipSelect Row Number (0..NUM_CHIPSELECTS-1) |
0ec449ee DT |
2334 | * k8 private pointer to --> |
2335 | * DRAM Bank Address mapping register | |
2336 | * node_id | |
2337 | * DCL register where dual_channel_active is | |
2338 | * | |
2339 | * The DBAM register consists of 4 sets of 4 bits each definitions: | |
2340 | * | |
2341 | * Bits: CSROWs | |
2342 | * 0-3 CSROWs 0 and 1 | |
2343 | * 4-7 CSROWs 2 and 3 | |
2344 | * 8-11 CSROWs 4 and 5 | |
2345 | * 12-15 CSROWs 6 and 7 | |
2346 | * | |
2347 | * Values range from: 0 to 15 | |
2348 | * The meaning of the values depends on CPU revision and dual-channel state, | |
2349 | * see relevant BKDG more info. | |
2350 | * | |
2351 | * The memory controller provides for total of only 8 CSROWs in its current | |
2352 | * architecture. Each "pair" of CSROWs normally represents just one DIMM in | |
2353 | * single channel or two (2) DIMMs in dual channel mode. | |
2354 | * | |
2355 | * The following code logic collapses the various tables for CSROW based on CPU | |
2356 | * revision. | |
2357 | * | |
2358 | * Returns: | |
2359 | * The number of PAGE_SIZE pages on the specified CSROW number it | |
2360 | * encompasses | |
2361 | * | |
2362 | */ | |
d1ea71cd | 2363 | static u32 get_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr) |
0ec449ee | 2364 | { |
1433eb99 | 2365 | u32 cs_mode, nr_pages; |
f92cae45 | 2366 | u32 dbam = dct ? pvt->dbam1 : pvt->dbam0; |
0ec449ee | 2367 | |
10de6497 | 2368 | |
0ec449ee DT |
2369 | /* |
2370 | * The math on this doesn't look right on the surface because x/2*4 can | |
2371 | * be simplified to x*2 but this expression makes use of the fact that | |
2372 | * it is integral math where 1/2=0. This intermediate value becomes the | |
2373 | * number of bits to shift the DBAM register to extract the proper CSROW | |
2374 | * field. | |
2375 | */ | |
0a5dfc31 | 2376 | cs_mode = DBAM_DIMM(csrow_nr / 2, dbam); |
0ec449ee | 2377 | |
a597d2a5 AG |
2378 | nr_pages = pvt->ops->dbam_to_cs(pvt, dct, cs_mode, (csrow_nr / 2)) |
2379 | << (20 - PAGE_SHIFT); | |
0ec449ee | 2380 | |
10de6497 BP |
2381 | edac_dbg(0, "csrow: %d, channel: %d, DBAM idx: %d\n", |
2382 | csrow_nr, dct, cs_mode); | |
2383 | edac_dbg(0, "nr_pages/channel: %u\n", nr_pages); | |
0ec449ee DT |
2384 | |
2385 | return nr_pages; | |
2386 | } | |
2387 | ||
2388 | /* | |
2389 | * Initialize the array of csrow attribute instances, based on the values | |
2390 | * from pci config hardware registers. | |
2391 | */ | |
360b7f3c | 2392 | static int init_csrows(struct mem_ctl_info *mci) |
0ec449ee | 2393 | { |
10de6497 | 2394 | struct amd64_pvt *pvt = mci->pvt_info; |
0ec449ee | 2395 | struct csrow_info *csrow; |
de3910eb | 2396 | struct dimm_info *dimm; |
084a4fcc | 2397 | enum edac_type edac_mode; |
10de6497 | 2398 | int i, j, empty = 1; |
a895bf8b | 2399 | int nr_pages = 0; |
10de6497 | 2400 | u32 val; |
0ec449ee | 2401 | |
a97fa68e | 2402 | amd64_read_pci_cfg(pvt->F3, NBCFG, &val); |
0ec449ee | 2403 | |
2299ef71 | 2404 | pvt->nbcfg = val; |
0ec449ee | 2405 | |
956b9ba1 JP |
2406 | edac_dbg(0, "node %d, NBCFG=0x%08x[ChipKillEccCap: %d|DramEccEn: %d]\n", |
2407 | pvt->mc_node_id, val, | |
2408 | !!(val & NBCFG_CHIPKILL), !!(val & NBCFG_ECC_ENABLE)); | |
0ec449ee | 2409 | |
10de6497 BP |
2410 | /* |
2411 | * We iterate over DCT0 here but we look at DCT1 in parallel, if needed. | |
2412 | */ | |
11c75ead | 2413 | for_each_chip_select(i, 0, pvt) { |
10de6497 BP |
2414 | bool row_dct0 = !!csrow_enabled(i, 0, pvt); |
2415 | bool row_dct1 = false; | |
0ec449ee | 2416 | |
a4b4bedc | 2417 | if (pvt->fam != 0xf) |
10de6497 BP |
2418 | row_dct1 = !!csrow_enabled(i, 1, pvt); |
2419 | ||
2420 | if (!row_dct0 && !row_dct1) | |
0ec449ee | 2421 | continue; |
0ec449ee | 2422 | |
10de6497 | 2423 | csrow = mci->csrows[i]; |
0ec449ee | 2424 | empty = 0; |
10de6497 BP |
2425 | |
2426 | edac_dbg(1, "MC node: %d, csrow: %d\n", | |
2427 | pvt->mc_node_id, i); | |
2428 | ||
1eef1282 | 2429 | if (row_dct0) { |
d1ea71cd | 2430 | nr_pages = get_csrow_nr_pages(pvt, 0, i); |
1eef1282 MCC |
2431 | csrow->channels[0]->dimm->nr_pages = nr_pages; |
2432 | } | |
11c75ead | 2433 | |
10de6497 | 2434 | /* K8 has only one DCT */ |
a4b4bedc | 2435 | if (pvt->fam != 0xf && row_dct1) { |
d1ea71cd | 2436 | int row_dct1_pages = get_csrow_nr_pages(pvt, 1, i); |
1eef1282 MCC |
2437 | |
2438 | csrow->channels[1]->dimm->nr_pages = row_dct1_pages; | |
2439 | nr_pages += row_dct1_pages; | |
2440 | } | |
0ec449ee | 2441 | |
10de6497 | 2442 | edac_dbg(1, "Total csrow%d pages: %u\n", i, nr_pages); |
0ec449ee DT |
2443 | |
2444 | /* | |
2445 | * determine whether CHIPKILL or JUST ECC or NO ECC is operating | |
2446 | */ | |
a97fa68e | 2447 | if (pvt->nbcfg & NBCFG_ECC_ENABLE) |
084a4fcc MCC |
2448 | edac_mode = (pvt->nbcfg & NBCFG_CHIPKILL) ? |
2449 | EDAC_S4ECD4ED : EDAC_SECDED; | |
0ec449ee | 2450 | else |
084a4fcc MCC |
2451 | edac_mode = EDAC_NONE; |
2452 | ||
2453 | for (j = 0; j < pvt->channel_count; j++) { | |
de3910eb | 2454 | dimm = csrow->channels[j]->dimm; |
a597d2a5 | 2455 | dimm->mtype = pvt->dram_type; |
de3910eb | 2456 | dimm->edac_mode = edac_mode; |
084a4fcc | 2457 | } |
0ec449ee DT |
2458 | } |
2459 | ||
2460 | return empty; | |
2461 | } | |
d27bf6fa | 2462 | |
f6d6ae96 | 2463 | /* get all cores on this DCT */ |
8b84c8df | 2464 | static void get_cpus_on_this_dct_cpumask(struct cpumask *mask, u16 nid) |
f6d6ae96 BP |
2465 | { |
2466 | int cpu; | |
2467 | ||
2468 | for_each_online_cpu(cpu) | |
2469 | if (amd_get_nb_id(cpu) == nid) | |
2470 | cpumask_set_cpu(cpu, mask); | |
2471 | } | |
2472 | ||
2473 | /* check MCG_CTL on all the cpus on this node */ | |
d1ea71cd | 2474 | static bool nb_mce_bank_enabled_on_node(u16 nid) |
f6d6ae96 BP |
2475 | { |
2476 | cpumask_var_t mask; | |
50542251 | 2477 | int cpu, nbe; |
f6d6ae96 BP |
2478 | bool ret = false; |
2479 | ||
2480 | if (!zalloc_cpumask_var(&mask, GFP_KERNEL)) { | |
24f9a7fe | 2481 | amd64_warn("%s: Error allocating mask\n", __func__); |
f6d6ae96 BP |
2482 | return false; |
2483 | } | |
2484 | ||
2485 | get_cpus_on_this_dct_cpumask(mask, nid); | |
2486 | ||
f6d6ae96 BP |
2487 | rdmsr_on_cpus(mask, MSR_IA32_MCG_CTL, msrs); |
2488 | ||
2489 | for_each_cpu(cpu, mask) { | |
50542251 | 2490 | struct msr *reg = per_cpu_ptr(msrs, cpu); |
5980bb9c | 2491 | nbe = reg->l & MSR_MCGCTL_NBE; |
f6d6ae96 | 2492 | |
956b9ba1 JP |
2493 | edac_dbg(0, "core: %u, MCG_CTL: 0x%llx, NB MSR is %s\n", |
2494 | cpu, reg->q, | |
2495 | (nbe ? "enabled" : "disabled")); | |
f6d6ae96 BP |
2496 | |
2497 | if (!nbe) | |
2498 | goto out; | |
f6d6ae96 BP |
2499 | } |
2500 | ret = true; | |
2501 | ||
2502 | out: | |
f6d6ae96 BP |
2503 | free_cpumask_var(mask); |
2504 | return ret; | |
2505 | } | |
2506 | ||
c7e5301a | 2507 | static int toggle_ecc_err_reporting(struct ecc_settings *s, u16 nid, bool on) |
f6d6ae96 BP |
2508 | { |
2509 | cpumask_var_t cmask; | |
50542251 | 2510 | int cpu; |
f6d6ae96 BP |
2511 | |
2512 | if (!zalloc_cpumask_var(&cmask, GFP_KERNEL)) { | |
24f9a7fe | 2513 | amd64_warn("%s: error allocating mask\n", __func__); |
f6d6ae96 BP |
2514 | return false; |
2515 | } | |
2516 | ||
ae7bb7c6 | 2517 | get_cpus_on_this_dct_cpumask(cmask, nid); |
f6d6ae96 | 2518 | |
f6d6ae96 BP |
2519 | rdmsr_on_cpus(cmask, MSR_IA32_MCG_CTL, msrs); |
2520 | ||
2521 | for_each_cpu(cpu, cmask) { | |
2522 | ||
50542251 BP |
2523 | struct msr *reg = per_cpu_ptr(msrs, cpu); |
2524 | ||
f6d6ae96 | 2525 | if (on) { |
5980bb9c | 2526 | if (reg->l & MSR_MCGCTL_NBE) |
ae7bb7c6 | 2527 | s->flags.nb_mce_enable = 1; |
f6d6ae96 | 2528 | |
5980bb9c | 2529 | reg->l |= MSR_MCGCTL_NBE; |
f6d6ae96 BP |
2530 | } else { |
2531 | /* | |
d95cf4de | 2532 | * Turn off NB MCE reporting only when it was off before |
f6d6ae96 | 2533 | */ |
ae7bb7c6 | 2534 | if (!s->flags.nb_mce_enable) |
5980bb9c | 2535 | reg->l &= ~MSR_MCGCTL_NBE; |
f6d6ae96 | 2536 | } |
f6d6ae96 BP |
2537 | } |
2538 | wrmsr_on_cpus(cmask, MSR_IA32_MCG_CTL, msrs); | |
2539 | ||
f6d6ae96 BP |
2540 | free_cpumask_var(cmask); |
2541 | ||
2542 | return 0; | |
2543 | } | |
2544 | ||
c7e5301a | 2545 | static bool enable_ecc_error_reporting(struct ecc_settings *s, u16 nid, |
2299ef71 | 2546 | struct pci_dev *F3) |
f9431992 | 2547 | { |
2299ef71 | 2548 | bool ret = true; |
c9f4f26e | 2549 | u32 value, mask = 0x3; /* UECC/CECC enable */ |
f9431992 | 2550 | |
2299ef71 BP |
2551 | if (toggle_ecc_err_reporting(s, nid, ON)) { |
2552 | amd64_warn("Error enabling ECC reporting over MCGCTL!\n"); | |
2553 | return false; | |
2554 | } | |
2555 | ||
c9f4f26e | 2556 | amd64_read_pci_cfg(F3, NBCTL, &value); |
f9431992 | 2557 | |
ae7bb7c6 BP |
2558 | s->old_nbctl = value & mask; |
2559 | s->nbctl_valid = true; | |
f9431992 DT |
2560 | |
2561 | value |= mask; | |
c9f4f26e | 2562 | amd64_write_pci_cfg(F3, NBCTL, value); |
f9431992 | 2563 | |
a97fa68e | 2564 | amd64_read_pci_cfg(F3, NBCFG, &value); |
f9431992 | 2565 | |
956b9ba1 JP |
2566 | edac_dbg(0, "1: node %d, NBCFG=0x%08x[DramEccEn: %d]\n", |
2567 | nid, value, !!(value & NBCFG_ECC_ENABLE)); | |
f9431992 | 2568 | |
a97fa68e | 2569 | if (!(value & NBCFG_ECC_ENABLE)) { |
24f9a7fe | 2570 | amd64_warn("DRAM ECC disabled on this node, enabling...\n"); |
f9431992 | 2571 | |
ae7bb7c6 | 2572 | s->flags.nb_ecc_prev = 0; |
d95cf4de | 2573 | |
f9431992 | 2574 | /* Attempt to turn on DRAM ECC Enable */ |
a97fa68e BP |
2575 | value |= NBCFG_ECC_ENABLE; |
2576 | amd64_write_pci_cfg(F3, NBCFG, value); | |
f9431992 | 2577 | |
a97fa68e | 2578 | amd64_read_pci_cfg(F3, NBCFG, &value); |
f9431992 | 2579 | |
a97fa68e | 2580 | if (!(value & NBCFG_ECC_ENABLE)) { |
24f9a7fe BP |
2581 | amd64_warn("Hardware rejected DRAM ECC enable," |
2582 | "check memory DIMM configuration.\n"); | |
2299ef71 | 2583 | ret = false; |
f9431992 | 2584 | } else { |
24f9a7fe | 2585 | amd64_info("Hardware accepted DRAM ECC Enable\n"); |
f9431992 | 2586 | } |
d95cf4de | 2587 | } else { |
ae7bb7c6 | 2588 | s->flags.nb_ecc_prev = 1; |
f9431992 | 2589 | } |
d95cf4de | 2590 | |
956b9ba1 JP |
2591 | edac_dbg(0, "2: node %d, NBCFG=0x%08x[DramEccEn: %d]\n", |
2592 | nid, value, !!(value & NBCFG_ECC_ENABLE)); | |
f9431992 | 2593 | |
2299ef71 | 2594 | return ret; |
f9431992 DT |
2595 | } |
2596 | ||
c7e5301a | 2597 | static void restore_ecc_error_reporting(struct ecc_settings *s, u16 nid, |
360b7f3c | 2598 | struct pci_dev *F3) |
f9431992 | 2599 | { |
c9f4f26e BP |
2600 | u32 value, mask = 0x3; /* UECC/CECC enable */ |
2601 | ||
f9431992 | 2602 | |
ae7bb7c6 | 2603 | if (!s->nbctl_valid) |
f9431992 DT |
2604 | return; |
2605 | ||
c9f4f26e | 2606 | amd64_read_pci_cfg(F3, NBCTL, &value); |
f9431992 | 2607 | value &= ~mask; |
ae7bb7c6 | 2608 | value |= s->old_nbctl; |
f9431992 | 2609 | |
c9f4f26e | 2610 | amd64_write_pci_cfg(F3, NBCTL, value); |
f9431992 | 2611 | |
ae7bb7c6 BP |
2612 | /* restore previous BIOS DRAM ECC "off" setting we force-enabled */ |
2613 | if (!s->flags.nb_ecc_prev) { | |
a97fa68e BP |
2614 | amd64_read_pci_cfg(F3, NBCFG, &value); |
2615 | value &= ~NBCFG_ECC_ENABLE; | |
2616 | amd64_write_pci_cfg(F3, NBCFG, value); | |
d95cf4de BP |
2617 | } |
2618 | ||
2619 | /* restore the NB Enable MCGCTL bit */ | |
2299ef71 | 2620 | if (toggle_ecc_err_reporting(s, nid, OFF)) |
24f9a7fe | 2621 | amd64_warn("Error restoring NB MCGCTL settings!\n"); |
f9431992 DT |
2622 | } |
2623 | ||
2624 | /* | |
2299ef71 BP |
2625 | * EDAC requires that the BIOS have ECC enabled before |
2626 | * taking over the processing of ECC errors. A command line | |
2627 | * option allows to force-enable hardware ECC later in | |
2628 | * enable_ecc_error_reporting(). | |
f9431992 | 2629 | */ |
cab4d277 BP |
2630 | static const char *ecc_msg = |
2631 | "ECC disabled in the BIOS or no ECC capability, module will not load.\n" | |
2632 | " Either enable ECC checking or force module loading by setting " | |
2633 | "'ecc_enable_override'.\n" | |
2634 | " (Note that use of the override may cause unknown side effects.)\n"; | |
be3468e8 | 2635 | |
c7e5301a | 2636 | static bool ecc_enabled(struct pci_dev *F3, u16 nid) |
f9431992 DT |
2637 | { |
2638 | u32 value; | |
2299ef71 | 2639 | u8 ecc_en = 0; |
06724535 | 2640 | bool nb_mce_en = false; |
f9431992 | 2641 | |
a97fa68e | 2642 | amd64_read_pci_cfg(F3, NBCFG, &value); |
f9431992 | 2643 | |
a97fa68e | 2644 | ecc_en = !!(value & NBCFG_ECC_ENABLE); |
2299ef71 | 2645 | amd64_info("DRAM ECC %s.\n", (ecc_en ? "enabled" : "disabled")); |
f9431992 | 2646 | |
d1ea71cd | 2647 | nb_mce_en = nb_mce_bank_enabled_on_node(nid); |
06724535 | 2648 | if (!nb_mce_en) |
2299ef71 BP |
2649 | amd64_notice("NB MCE bank disabled, set MSR " |
2650 | "0x%08x[4] on node %d to enable.\n", | |
2651 | MSR_IA32_MCG_CTL, nid); | |
f9431992 | 2652 | |
2299ef71 BP |
2653 | if (!ecc_en || !nb_mce_en) { |
2654 | amd64_notice("%s", ecc_msg); | |
2655 | return false; | |
2656 | } | |
2657 | return true; | |
f9431992 DT |
2658 | } |
2659 | ||
c5608759 | 2660 | static int set_mc_sysfs_attrs(struct mem_ctl_info *mci) |
7d6034d3 | 2661 | { |
a4b4bedc | 2662 | struct amd64_pvt *pvt = mci->pvt_info; |
c5608759 | 2663 | int rc; |
7d6034d3 | 2664 | |
c5608759 MCC |
2665 | rc = amd64_create_sysfs_dbg_files(mci); |
2666 | if (rc < 0) | |
2667 | return rc; | |
7d6034d3 | 2668 | |
a4b4bedc | 2669 | if (pvt->fam >= 0x10) { |
c5608759 MCC |
2670 | rc = amd64_create_sysfs_inject_files(mci); |
2671 | if (rc < 0) | |
2672 | return rc; | |
2673 | } | |
2674 | ||
2675 | return 0; | |
2676 | } | |
7d6034d3 | 2677 | |
c5608759 MCC |
2678 | static void del_mc_sysfs_attrs(struct mem_ctl_info *mci) |
2679 | { | |
a4b4bedc BP |
2680 | struct amd64_pvt *pvt = mci->pvt_info; |
2681 | ||
c5608759 | 2682 | amd64_remove_sysfs_dbg_files(mci); |
7d6034d3 | 2683 | |
a4b4bedc | 2684 | if (pvt->fam >= 0x10) |
c5608759 | 2685 | amd64_remove_sysfs_inject_files(mci); |
7d6034d3 DT |
2686 | } |
2687 | ||
df71a053 BP |
2688 | static void setup_mci_misc_attrs(struct mem_ctl_info *mci, |
2689 | struct amd64_family_type *fam) | |
7d6034d3 DT |
2690 | { |
2691 | struct amd64_pvt *pvt = mci->pvt_info; | |
2692 | ||
2693 | mci->mtype_cap = MEM_FLAG_DDR2 | MEM_FLAG_RDDR2; | |
2694 | mci->edac_ctl_cap = EDAC_FLAG_NONE; | |
7d6034d3 | 2695 | |
5980bb9c | 2696 | if (pvt->nbcap & NBCAP_SECDED) |
7d6034d3 DT |
2697 | mci->edac_ctl_cap |= EDAC_FLAG_SECDED; |
2698 | ||
5980bb9c | 2699 | if (pvt->nbcap & NBCAP_CHIPKILL) |
7d6034d3 DT |
2700 | mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED; |
2701 | ||
d1ea71cd | 2702 | mci->edac_cap = determine_edac_cap(pvt); |
7d6034d3 DT |
2703 | mci->mod_name = EDAC_MOD_STR; |
2704 | mci->mod_ver = EDAC_AMD64_VERSION; | |
df71a053 | 2705 | mci->ctl_name = fam->ctl_name; |
8d5b5d9c | 2706 | mci->dev_name = pci_name(pvt->F2); |
7d6034d3 DT |
2707 | mci->ctl_page_to_phys = NULL; |
2708 | ||
7d6034d3 | 2709 | /* memory scrubber interface */ |
d1ea71cd BP |
2710 | mci->set_sdram_scrub_rate = set_scrub_rate; |
2711 | mci->get_sdram_scrub_rate = get_scrub_rate; | |
7d6034d3 DT |
2712 | } |
2713 | ||
0092b20d BP |
2714 | /* |
2715 | * returns a pointer to the family descriptor on success, NULL otherwise. | |
2716 | */ | |
d1ea71cd | 2717 | static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt) |
395ae783 | 2718 | { |
0092b20d BP |
2719 | struct amd64_family_type *fam_type = NULL; |
2720 | ||
18b94f66 | 2721 | pvt->ext_model = boot_cpu_data.x86_model >> 4; |
a4b4bedc | 2722 | pvt->stepping = boot_cpu_data.x86_mask; |
18b94f66 AG |
2723 | pvt->model = boot_cpu_data.x86_model; |
2724 | pvt->fam = boot_cpu_data.x86; | |
2725 | ||
2726 | switch (pvt->fam) { | |
395ae783 | 2727 | case 0xf: |
d1ea71cd BP |
2728 | fam_type = &family_types[K8_CPUS]; |
2729 | pvt->ops = &family_types[K8_CPUS].ops; | |
395ae783 | 2730 | break; |
df71a053 | 2731 | |
395ae783 | 2732 | case 0x10: |
d1ea71cd BP |
2733 | fam_type = &family_types[F10_CPUS]; |
2734 | pvt->ops = &family_types[F10_CPUS].ops; | |
df71a053 BP |
2735 | break; |
2736 | ||
2737 | case 0x15: | |
18b94f66 | 2738 | if (pvt->model == 0x30) { |
d1ea71cd BP |
2739 | fam_type = &family_types[F15_M30H_CPUS]; |
2740 | pvt->ops = &family_types[F15_M30H_CPUS].ops; | |
18b94f66 | 2741 | break; |
a597d2a5 AG |
2742 | } else if (pvt->model == 0x60) { |
2743 | fam_type = &family_types[F15_M60H_CPUS]; | |
2744 | pvt->ops = &family_types[F15_M60H_CPUS].ops; | |
2745 | break; | |
18b94f66 AG |
2746 | } |
2747 | ||
d1ea71cd BP |
2748 | fam_type = &family_types[F15_CPUS]; |
2749 | pvt->ops = &family_types[F15_CPUS].ops; | |
395ae783 BP |
2750 | break; |
2751 | ||
94c1acf2 | 2752 | case 0x16: |
85a8885b AG |
2753 | if (pvt->model == 0x30) { |
2754 | fam_type = &family_types[F16_M30H_CPUS]; | |
2755 | pvt->ops = &family_types[F16_M30H_CPUS].ops; | |
2756 | break; | |
2757 | } | |
d1ea71cd BP |
2758 | fam_type = &family_types[F16_CPUS]; |
2759 | pvt->ops = &family_types[F16_CPUS].ops; | |
94c1acf2 AG |
2760 | break; |
2761 | ||
395ae783 | 2762 | default: |
24f9a7fe | 2763 | amd64_err("Unsupported family!\n"); |
0092b20d | 2764 | return NULL; |
395ae783 | 2765 | } |
0092b20d | 2766 | |
df71a053 | 2767 | amd64_info("%s %sdetected (node %d).\n", fam_type->ctl_name, |
18b94f66 | 2768 | (pvt->fam == 0xf ? |
24f9a7fe BP |
2769 | (pvt->ext_model >= K8_REV_F ? "revF or later " |
2770 | : "revE or earlier ") | |
2771 | : ""), pvt->mc_node_id); | |
0092b20d | 2772 | return fam_type; |
395ae783 BP |
2773 | } |
2774 | ||
d1ea71cd | 2775 | static int init_one_instance(struct pci_dev *F2) |
7d6034d3 DT |
2776 | { |
2777 | struct amd64_pvt *pvt = NULL; | |
0092b20d | 2778 | struct amd64_family_type *fam_type = NULL; |
360b7f3c | 2779 | struct mem_ctl_info *mci = NULL; |
ab5a503c | 2780 | struct edac_mc_layer layers[2]; |
7d6034d3 | 2781 | int err = 0, ret; |
772c3ff3 | 2782 | u16 nid = amd_get_node_id(F2); |
7d6034d3 DT |
2783 | |
2784 | ret = -ENOMEM; | |
2785 | pvt = kzalloc(sizeof(struct amd64_pvt), GFP_KERNEL); | |
2786 | if (!pvt) | |
360b7f3c | 2787 | goto err_ret; |
7d6034d3 | 2788 | |
360b7f3c | 2789 | pvt->mc_node_id = nid; |
8d5b5d9c | 2790 | pvt->F2 = F2; |
7d6034d3 | 2791 | |
395ae783 | 2792 | ret = -EINVAL; |
d1ea71cd | 2793 | fam_type = per_family_init(pvt); |
0092b20d | 2794 | if (!fam_type) |
395ae783 BP |
2795 | goto err_free; |
2796 | ||
7d6034d3 | 2797 | ret = -ENODEV; |
360b7f3c | 2798 | err = reserve_mc_sibling_devs(pvt, fam_type->f1_id, fam_type->f3_id); |
7d6034d3 DT |
2799 | if (err) |
2800 | goto err_free; | |
2801 | ||
360b7f3c | 2802 | read_mc_regs(pvt); |
7d6034d3 | 2803 | |
7d6034d3 DT |
2804 | /* |
2805 | * We need to determine how many memory channels there are. Then use | |
2806 | * that information for calculating the size of the dynamic instance | |
360b7f3c | 2807 | * tables in the 'mci' structure. |
7d6034d3 | 2808 | */ |
360b7f3c | 2809 | ret = -EINVAL; |
7d6034d3 DT |
2810 | pvt->channel_count = pvt->ops->early_channel_count(pvt); |
2811 | if (pvt->channel_count < 0) | |
360b7f3c | 2812 | goto err_siblings; |
7d6034d3 DT |
2813 | |
2814 | ret = -ENOMEM; | |
ab5a503c MCC |
2815 | layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; |
2816 | layers[0].size = pvt->csels[0].b_cnt; | |
2817 | layers[0].is_virt_csrow = true; | |
2818 | layers[1].type = EDAC_MC_LAYER_CHANNEL; | |
f0a56c48 BP |
2819 | |
2820 | /* | |
2821 | * Always allocate two channels since we can have setups with DIMMs on | |
2822 | * only one channel. Also, this simplifies handling later for the price | |
2823 | * of a couple of KBs tops. | |
2824 | */ | |
2825 | layers[1].size = 2; | |
ab5a503c | 2826 | layers[1].is_virt_csrow = false; |
f0a56c48 | 2827 | |
ca0907b9 | 2828 | mci = edac_mc_alloc(nid, ARRAY_SIZE(layers), layers, 0); |
7d6034d3 | 2829 | if (!mci) |
360b7f3c | 2830 | goto err_siblings; |
7d6034d3 DT |
2831 | |
2832 | mci->pvt_info = pvt; | |
fd687502 | 2833 | mci->pdev = &pvt->F2->dev; |
7d6034d3 | 2834 | |
df71a053 | 2835 | setup_mci_misc_attrs(mci, fam_type); |
360b7f3c BP |
2836 | |
2837 | if (init_csrows(mci)) | |
7d6034d3 DT |
2838 | mci->edac_cap = EDAC_FLAG_NONE; |
2839 | ||
7d6034d3 DT |
2840 | ret = -ENODEV; |
2841 | if (edac_mc_add_mc(mci)) { | |
956b9ba1 | 2842 | edac_dbg(1, "failed edac_mc_add_mc()\n"); |
7d6034d3 DT |
2843 | goto err_add_mc; |
2844 | } | |
c5608759 | 2845 | if (set_mc_sysfs_attrs(mci)) { |
956b9ba1 | 2846 | edac_dbg(1, "failed edac_mc_add_mc()\n"); |
c5608759 MCC |
2847 | goto err_add_sysfs; |
2848 | } | |
7d6034d3 | 2849 | |
549d042d BP |
2850 | /* register stuff with EDAC MCE */ |
2851 | if (report_gart_errors) | |
2852 | amd_report_gart_errors(true); | |
2853 | ||
df781d03 | 2854 | amd_register_ecc_decoder(decode_bus_error); |
549d042d | 2855 | |
360b7f3c BP |
2856 | mcis[nid] = mci; |
2857 | ||
2858 | atomic_inc(&drv_instances); | |
2859 | ||
7d6034d3 DT |
2860 | return 0; |
2861 | ||
c5608759 MCC |
2862 | err_add_sysfs: |
2863 | edac_mc_del_mc(mci->pdev); | |
7d6034d3 DT |
2864 | err_add_mc: |
2865 | edac_mc_free(mci); | |
2866 | ||
360b7f3c BP |
2867 | err_siblings: |
2868 | free_mc_sibling_devs(pvt); | |
7d6034d3 | 2869 | |
360b7f3c BP |
2870 | err_free: |
2871 | kfree(pvt); | |
7d6034d3 | 2872 | |
360b7f3c | 2873 | err_ret: |
7d6034d3 DT |
2874 | return ret; |
2875 | } | |
2876 | ||
d1ea71cd BP |
2877 | static int probe_one_instance(struct pci_dev *pdev, |
2878 | const struct pci_device_id *mc_type) | |
7d6034d3 | 2879 | { |
772c3ff3 | 2880 | u16 nid = amd_get_node_id(pdev); |
2299ef71 | 2881 | struct pci_dev *F3 = node_to_amd_nb(nid)->misc; |
ae7bb7c6 | 2882 | struct ecc_settings *s; |
2299ef71 | 2883 | int ret = 0; |
7d6034d3 | 2884 | |
7d6034d3 | 2885 | ret = pci_enable_device(pdev); |
b8cfa02f | 2886 | if (ret < 0) { |
956b9ba1 | 2887 | edac_dbg(0, "ret=%d\n", ret); |
b8cfa02f BP |
2888 | return -EIO; |
2889 | } | |
7d6034d3 | 2890 | |
ae7bb7c6 BP |
2891 | ret = -ENOMEM; |
2892 | s = kzalloc(sizeof(struct ecc_settings), GFP_KERNEL); | |
2893 | if (!s) | |
2299ef71 | 2894 | goto err_out; |
ae7bb7c6 BP |
2895 | |
2896 | ecc_stngs[nid] = s; | |
2897 | ||
2299ef71 BP |
2898 | if (!ecc_enabled(F3, nid)) { |
2899 | ret = -ENODEV; | |
2900 | ||
2901 | if (!ecc_enable_override) | |
2902 | goto err_enable; | |
2903 | ||
2904 | amd64_warn("Forcing ECC on!\n"); | |
2905 | ||
2906 | if (!enable_ecc_error_reporting(s, nid, F3)) | |
2907 | goto err_enable; | |
2908 | } | |
2909 | ||
d1ea71cd | 2910 | ret = init_one_instance(pdev); |
360b7f3c | 2911 | if (ret < 0) { |
ae7bb7c6 | 2912 | amd64_err("Error probing instance: %d\n", nid); |
360b7f3c BP |
2913 | restore_ecc_error_reporting(s, nid, F3); |
2914 | } | |
7d6034d3 DT |
2915 | |
2916 | return ret; | |
2299ef71 BP |
2917 | |
2918 | err_enable: | |
2919 | kfree(s); | |
2920 | ecc_stngs[nid] = NULL; | |
2921 | ||
2922 | err_out: | |
2923 | return ret; | |
7d6034d3 DT |
2924 | } |
2925 | ||
d1ea71cd | 2926 | static void remove_one_instance(struct pci_dev *pdev) |
7d6034d3 DT |
2927 | { |
2928 | struct mem_ctl_info *mci; | |
2929 | struct amd64_pvt *pvt; | |
772c3ff3 | 2930 | u16 nid = amd_get_node_id(pdev); |
360b7f3c BP |
2931 | struct pci_dev *F3 = node_to_amd_nb(nid)->misc; |
2932 | struct ecc_settings *s = ecc_stngs[nid]; | |
7d6034d3 | 2933 | |
c5608759 | 2934 | mci = find_mci_by_dev(&pdev->dev); |
a4b4bedc BP |
2935 | WARN_ON(!mci); |
2936 | ||
c5608759 | 2937 | del_mc_sysfs_attrs(mci); |
7d6034d3 DT |
2938 | /* Remove from EDAC CORE tracking list */ |
2939 | mci = edac_mc_del_mc(&pdev->dev); | |
2940 | if (!mci) | |
2941 | return; | |
2942 | ||
2943 | pvt = mci->pvt_info; | |
2944 | ||
360b7f3c | 2945 | restore_ecc_error_reporting(s, nid, F3); |
7d6034d3 | 2946 | |
360b7f3c | 2947 | free_mc_sibling_devs(pvt); |
7d6034d3 | 2948 | |
549d042d BP |
2949 | /* unregister from EDAC MCE */ |
2950 | amd_report_gart_errors(false); | |
df781d03 | 2951 | amd_unregister_ecc_decoder(decode_bus_error); |
549d042d | 2952 | |
360b7f3c BP |
2953 | kfree(ecc_stngs[nid]); |
2954 | ecc_stngs[nid] = NULL; | |
ae7bb7c6 | 2955 | |
7d6034d3 | 2956 | /* Free the EDAC CORE resources */ |
8f68ed97 | 2957 | mci->pvt_info = NULL; |
360b7f3c | 2958 | mcis[nid] = NULL; |
8f68ed97 BP |
2959 | |
2960 | kfree(pvt); | |
7d6034d3 DT |
2961 | edac_mc_free(mci); |
2962 | } | |
2963 | ||
2964 | /* | |
2965 | * This table is part of the interface for loading drivers for PCI devices. The | |
2966 | * PCI core identifies what devices are on a system during boot, and then | |
2967 | * inquiry this table to see if this driver is for a given device found. | |
2968 | */ | |
ba935f40 | 2969 | static const struct pci_device_id amd64_pci_table[] = { |
a597d2a5 AG |
2970 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_K8_NB_MEMCTL) }, |
2971 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_DRAM) }, | |
2972 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F2) }, | |
2973 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F2) }, | |
2974 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F2) }, | |
2975 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F2) }, | |
2976 | { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F2) }, | |
7d6034d3 DT |
2977 | {0, } |
2978 | }; | |
2979 | MODULE_DEVICE_TABLE(pci, amd64_pci_table); | |
2980 | ||
2981 | static struct pci_driver amd64_pci_driver = { | |
2982 | .name = EDAC_MOD_STR, | |
d1ea71cd BP |
2983 | .probe = probe_one_instance, |
2984 | .remove = remove_one_instance, | |
7d6034d3 DT |
2985 | .id_table = amd64_pci_table, |
2986 | }; | |
2987 | ||
360b7f3c | 2988 | static void setup_pci_device(void) |
7d6034d3 DT |
2989 | { |
2990 | struct mem_ctl_info *mci; | |
2991 | struct amd64_pvt *pvt; | |
2992 | ||
d1ea71cd | 2993 | if (pci_ctl) |
7d6034d3 DT |
2994 | return; |
2995 | ||
cc4d8860 | 2996 | mci = mcis[0]; |
d1ea71cd BP |
2997 | if (!mci) |
2998 | return; | |
7d6034d3 | 2999 | |
d1ea71cd BP |
3000 | pvt = mci->pvt_info; |
3001 | pci_ctl = edac_pci_create_generic_ctl(&pvt->F2->dev, EDAC_MOD_STR); | |
3002 | if (!pci_ctl) { | |
3003 | pr_warn("%s(): Unable to create PCI control\n", __func__); | |
3004 | pr_warn("%s(): PCI error report via EDAC not set\n", __func__); | |
7d6034d3 DT |
3005 | } |
3006 | } | |
3007 | ||
3008 | static int __init amd64_edac_init(void) | |
3009 | { | |
360b7f3c | 3010 | int err = -ENODEV; |
7d6034d3 | 3011 | |
df71a053 | 3012 | printk(KERN_INFO "AMD64 EDAC driver v%s\n", EDAC_AMD64_VERSION); |
7d6034d3 DT |
3013 | |
3014 | opstate_init(); | |
3015 | ||
9653a5c7 | 3016 | if (amd_cache_northbridges() < 0) |
56b34b91 | 3017 | goto err_ret; |
7d6034d3 | 3018 | |
cc4d8860 | 3019 | err = -ENOMEM; |
ae7bb7c6 BP |
3020 | mcis = kzalloc(amd_nb_num() * sizeof(mcis[0]), GFP_KERNEL); |
3021 | ecc_stngs = kzalloc(amd_nb_num() * sizeof(ecc_stngs[0]), GFP_KERNEL); | |
360b7f3c | 3022 | if (!(mcis && ecc_stngs)) |
a9f0fbe2 | 3023 | goto err_free; |
cc4d8860 | 3024 | |
50542251 | 3025 | msrs = msrs_alloc(); |
56b34b91 | 3026 | if (!msrs) |
360b7f3c | 3027 | goto err_free; |
50542251 | 3028 | |
7d6034d3 DT |
3029 | err = pci_register_driver(&amd64_pci_driver); |
3030 | if (err) | |
56b34b91 | 3031 | goto err_pci; |
7d6034d3 | 3032 | |
56b34b91 | 3033 | err = -ENODEV; |
360b7f3c BP |
3034 | if (!atomic_read(&drv_instances)) |
3035 | goto err_no_instances; | |
7d6034d3 | 3036 | |
360b7f3c | 3037 | setup_pci_device(); |
f5b10c45 TP |
3038 | |
3039 | #ifdef CONFIG_X86_32 | |
3040 | amd64_err("%s on 32-bit is unsupported. USE AT YOUR OWN RISK!\n", EDAC_MOD_STR); | |
3041 | #endif | |
3042 | ||
360b7f3c | 3043 | return 0; |
7d6034d3 | 3044 | |
360b7f3c | 3045 | err_no_instances: |
7d6034d3 | 3046 | pci_unregister_driver(&amd64_pci_driver); |
cc4d8860 | 3047 | |
56b34b91 BP |
3048 | err_pci: |
3049 | msrs_free(msrs); | |
3050 | msrs = NULL; | |
cc4d8860 | 3051 | |
360b7f3c BP |
3052 | err_free: |
3053 | kfree(mcis); | |
3054 | mcis = NULL; | |
3055 | ||
3056 | kfree(ecc_stngs); | |
3057 | ecc_stngs = NULL; | |
3058 | ||
56b34b91 | 3059 | err_ret: |
7d6034d3 DT |
3060 | return err; |
3061 | } | |
3062 | ||
3063 | static void __exit amd64_edac_exit(void) | |
3064 | { | |
d1ea71cd BP |
3065 | if (pci_ctl) |
3066 | edac_pci_release_generic_ctl(pci_ctl); | |
7d6034d3 DT |
3067 | |
3068 | pci_unregister_driver(&amd64_pci_driver); | |
50542251 | 3069 | |
ae7bb7c6 BP |
3070 | kfree(ecc_stngs); |
3071 | ecc_stngs = NULL; | |
3072 | ||
cc4d8860 BP |
3073 | kfree(mcis); |
3074 | mcis = NULL; | |
3075 | ||
50542251 BP |
3076 | msrs_free(msrs); |
3077 | msrs = NULL; | |
7d6034d3 DT |
3078 | } |
3079 | ||
3080 | module_init(amd64_edac_init); | |
3081 | module_exit(amd64_edac_exit); | |
3082 | ||
3083 | MODULE_LICENSE("GPL"); | |
3084 | MODULE_AUTHOR("SoftwareBitMaker: Doug Thompson, " | |
3085 | "Dave Peterson, Thayne Harbaugh"); | |
3086 | MODULE_DESCRIPTION("MC support for AMD64 memory controllers - " | |
3087 | EDAC_AMD64_VERSION); | |
3088 | ||
3089 | module_param(edac_op_state, int, 0444); | |
3090 | MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); |