Commit | Line | Data |
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2bc65418 | 1 | #include "amd64_edac.h" |
23ac4ae8 | 2 | #include <asm/amd_nb.h> |
2bc65418 DT |
3 | |
4 | static struct edac_pci_ctl_info *amd64_ctl_pci; | |
5 | ||
6 | static int report_gart_errors; | |
7 | module_param(report_gart_errors, int, 0644); | |
8 | ||
9 | /* | |
10 | * Set by command line parameter. If BIOS has enabled the ECC, this override is | |
11 | * cleared to prevent re-enabling the hardware by this driver. | |
12 | */ | |
13 | static int ecc_enable_override; | |
14 | module_param(ecc_enable_override, int, 0644); | |
15 | ||
a29d8b8e | 16 | static struct msr __percpu *msrs; |
50542251 | 17 | |
2bc65418 DT |
18 | /* Lookup table for all possible MC control instances */ |
19 | struct amd64_pvt; | |
3011b20d BP |
20 | static struct mem_ctl_info *mci_lookup[EDAC_MAX_NUMNODES]; |
21 | static struct amd64_pvt *pvt_lookup[EDAC_MAX_NUMNODES]; | |
2bc65418 | 22 | |
b70ef010 | 23 | /* |
1433eb99 BP |
24 | * Address to DRAM bank mapping: see F2x80 for K8 and F2x[1,0]80 for Fam10 and |
25 | * later. | |
b70ef010 | 26 | */ |
1433eb99 BP |
27 | static int ddr2_dbam_revCG[] = { |
28 | [0] = 32, | |
29 | [1] = 64, | |
30 | [2] = 128, | |
31 | [3] = 256, | |
32 | [4] = 512, | |
33 | [5] = 1024, | |
34 | [6] = 2048, | |
35 | }; | |
36 | ||
37 | static int ddr2_dbam_revD[] = { | |
38 | [0] = 32, | |
39 | [1] = 64, | |
40 | [2 ... 3] = 128, | |
41 | [4] = 256, | |
42 | [5] = 512, | |
43 | [6] = 256, | |
44 | [7] = 512, | |
45 | [8 ... 9] = 1024, | |
46 | [10] = 2048, | |
47 | }; | |
48 | ||
49 | static int ddr2_dbam[] = { [0] = 128, | |
50 | [1] = 256, | |
51 | [2 ... 4] = 512, | |
52 | [5 ... 6] = 1024, | |
53 | [7 ... 8] = 2048, | |
54 | [9 ... 10] = 4096, | |
55 | [11] = 8192, | |
56 | }; | |
57 | ||
58 | static int ddr3_dbam[] = { [0] = -1, | |
59 | [1] = 256, | |
60 | [2] = 512, | |
61 | [3 ... 4] = -1, | |
62 | [5 ... 6] = 1024, | |
63 | [7 ... 8] = 2048, | |
64 | [9 ... 10] = 4096, | |
65 | [11] = 8192, | |
b70ef010 BP |
66 | }; |
67 | ||
68 | /* | |
69 | * Valid scrub rates for the K8 hardware memory scrubber. We map the scrubbing | |
70 | * bandwidth to a valid bit pattern. The 'set' operation finds the 'matching- | |
71 | * or higher value'. | |
72 | * | |
73 | *FIXME: Produce a better mapping/linearisation. | |
74 | */ | |
75 | ||
76 | struct scrubrate scrubrates[] = { | |
77 | { 0x01, 1600000000UL}, | |
78 | { 0x02, 800000000UL}, | |
79 | { 0x03, 400000000UL}, | |
80 | { 0x04, 200000000UL}, | |
81 | { 0x05, 100000000UL}, | |
82 | { 0x06, 50000000UL}, | |
83 | { 0x07, 25000000UL}, | |
84 | { 0x08, 12284069UL}, | |
85 | { 0x09, 6274509UL}, | |
86 | { 0x0A, 3121951UL}, | |
87 | { 0x0B, 1560975UL}, | |
88 | { 0x0C, 781440UL}, | |
89 | { 0x0D, 390720UL}, | |
90 | { 0x0E, 195300UL}, | |
91 | { 0x0F, 97650UL}, | |
92 | { 0x10, 48854UL}, | |
93 | { 0x11, 24427UL}, | |
94 | { 0x12, 12213UL}, | |
95 | { 0x13, 6101UL}, | |
96 | { 0x14, 3051UL}, | |
97 | { 0x15, 1523UL}, | |
98 | { 0x16, 761UL}, | |
99 | { 0x00, 0UL}, /* scrubbing off */ | |
100 | }; | |
101 | ||
2bc65418 DT |
102 | /* |
103 | * Memory scrubber control interface. For K8, memory scrubbing is handled by | |
104 | * hardware and can involve L2 cache, dcache as well as the main memory. With | |
105 | * F10, this is extended to L3 cache scrubbing on CPU models sporting that | |
106 | * functionality. | |
107 | * | |
108 | * This causes the "units" for the scrubbing speed to vary from 64 byte blocks | |
109 | * (dram) over to cache lines. This is nasty, so we will use bandwidth in | |
110 | * bytes/sec for the setting. | |
111 | * | |
112 | * Currently, we only do dram scrubbing. If the scrubbing is done in software on | |
113 | * other archs, we might not have access to the caches directly. | |
114 | */ | |
115 | ||
116 | /* | |
117 | * scan the scrub rate mapping table for a close or matching bandwidth value to | |
118 | * issue. If requested is too big, then use last maximum value found. | |
119 | */ | |
395ae783 | 120 | static int __amd64_set_scrub_rate(struct pci_dev *ctl, u32 new_bw, u32 min_rate) |
2bc65418 DT |
121 | { |
122 | u32 scrubval; | |
123 | int i; | |
124 | ||
125 | /* | |
126 | * map the configured rate (new_bw) to a value specific to the AMD64 | |
127 | * memory controller and apply to register. Search for the first | |
128 | * bandwidth entry that is greater or equal than the setting requested | |
129 | * and program that. If at last entry, turn off DRAM scrubbing. | |
130 | */ | |
131 | for (i = 0; i < ARRAY_SIZE(scrubrates); i++) { | |
132 | /* | |
133 | * skip scrub rates which aren't recommended | |
134 | * (see F10 BKDG, F3x58) | |
135 | */ | |
395ae783 | 136 | if (scrubrates[i].scrubval < min_rate) |
2bc65418 DT |
137 | continue; |
138 | ||
139 | if (scrubrates[i].bandwidth <= new_bw) | |
140 | break; | |
141 | ||
142 | /* | |
143 | * if no suitable bandwidth found, turn off DRAM scrubbing | |
144 | * entirely by falling back to the last element in the | |
145 | * scrubrates array. | |
146 | */ | |
147 | } | |
148 | ||
149 | scrubval = scrubrates[i].scrubval; | |
150 | if (scrubval) | |
151 | edac_printk(KERN_DEBUG, EDAC_MC, | |
152 | "Setting scrub rate bandwidth: %u\n", | |
153 | scrubrates[i].bandwidth); | |
154 | else | |
155 | edac_printk(KERN_DEBUG, EDAC_MC, "Turning scrubbing off.\n"); | |
156 | ||
157 | pci_write_bits32(ctl, K8_SCRCTRL, scrubval, 0x001F); | |
158 | ||
159 | return 0; | |
160 | } | |
161 | ||
395ae783 | 162 | static int amd64_set_scrub_rate(struct mem_ctl_info *mci, u32 bw) |
2bc65418 DT |
163 | { |
164 | struct amd64_pvt *pvt = mci->pvt_info; | |
2bc65418 | 165 | |
395ae783 | 166 | return __amd64_set_scrub_rate(pvt->misc_f3_ctl, bw, pvt->min_scrubrate); |
2bc65418 DT |
167 | } |
168 | ||
169 | static int amd64_get_scrub_rate(struct mem_ctl_info *mci, u32 *bw) | |
170 | { | |
171 | struct amd64_pvt *pvt = mci->pvt_info; | |
172 | u32 scrubval = 0; | |
6ba5dcdc | 173 | int status = -1, i; |
2bc65418 | 174 | |
6ba5dcdc | 175 | amd64_read_pci_cfg(pvt->misc_f3_ctl, K8_SCRCTRL, &scrubval); |
2bc65418 DT |
176 | |
177 | scrubval = scrubval & 0x001F; | |
178 | ||
179 | edac_printk(KERN_DEBUG, EDAC_MC, | |
180 | "pci-read, sdram scrub control value: %d \n", scrubval); | |
181 | ||
926311fd | 182 | for (i = 0; i < ARRAY_SIZE(scrubrates); i++) { |
2bc65418 DT |
183 | if (scrubrates[i].scrubval == scrubval) { |
184 | *bw = scrubrates[i].bandwidth; | |
185 | status = 0; | |
186 | break; | |
187 | } | |
188 | } | |
189 | ||
190 | return status; | |
191 | } | |
192 | ||
6775763a DT |
193 | /* Map from a CSROW entry to the mask entry that operates on it */ |
194 | static inline u32 amd64_map_to_dcs_mask(struct amd64_pvt *pvt, int csrow) | |
195 | { | |
1433eb99 | 196 | if (boot_cpu_data.x86 == 0xf && pvt->ext_model < K8_REV_F) |
9d858bb1 BP |
197 | return csrow; |
198 | else | |
199 | return csrow >> 1; | |
6775763a DT |
200 | } |
201 | ||
202 | /* return the 'base' address the i'th CS entry of the 'dct' DRAM controller */ | |
203 | static u32 amd64_get_dct_base(struct amd64_pvt *pvt, int dct, int csrow) | |
204 | { | |
205 | if (dct == 0) | |
206 | return pvt->dcsb0[csrow]; | |
207 | else | |
208 | return pvt->dcsb1[csrow]; | |
209 | } | |
210 | ||
211 | /* | |
212 | * Return the 'mask' address the i'th CS entry. This function is needed because | |
213 | * there number of DCSM registers on Rev E and prior vs Rev F and later is | |
214 | * different. | |
215 | */ | |
216 | static u32 amd64_get_dct_mask(struct amd64_pvt *pvt, int dct, int csrow) | |
217 | { | |
218 | if (dct == 0) | |
219 | return pvt->dcsm0[amd64_map_to_dcs_mask(pvt, csrow)]; | |
220 | else | |
221 | return pvt->dcsm1[amd64_map_to_dcs_mask(pvt, csrow)]; | |
222 | } | |
223 | ||
224 | ||
225 | /* | |
226 | * In *base and *limit, pass back the full 40-bit base and limit physical | |
227 | * addresses for the node given by node_id. This information is obtained from | |
228 | * DRAM Base (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers. The | |
229 | * base and limit addresses are of type SysAddr, as defined at the start of | |
230 | * section 3.4.4 (p. 70). They are the lowest and highest physical addresses | |
231 | * in the address range they represent. | |
232 | */ | |
233 | static void amd64_get_base_and_limit(struct amd64_pvt *pvt, int node_id, | |
234 | u64 *base, u64 *limit) | |
235 | { | |
236 | *base = pvt->dram_base[node_id]; | |
237 | *limit = pvt->dram_limit[node_id]; | |
238 | } | |
239 | ||
240 | /* | |
241 | * Return 1 if the SysAddr given by sys_addr matches the base/limit associated | |
242 | * with node_id | |
243 | */ | |
244 | static int amd64_base_limit_match(struct amd64_pvt *pvt, | |
245 | u64 sys_addr, int node_id) | |
246 | { | |
247 | u64 base, limit, addr; | |
248 | ||
249 | amd64_get_base_and_limit(pvt, node_id, &base, &limit); | |
250 | ||
251 | /* The K8 treats this as a 40-bit value. However, bits 63-40 will be | |
252 | * all ones if the most significant implemented address bit is 1. | |
253 | * Here we discard bits 63-40. See section 3.4.2 of AMD publication | |
254 | * 24592: AMD x86-64 Architecture Programmer's Manual Volume 1 | |
255 | * Application Programming. | |
256 | */ | |
257 | addr = sys_addr & 0x000000ffffffffffull; | |
258 | ||
259 | return (addr >= base) && (addr <= limit); | |
260 | } | |
261 | ||
262 | /* | |
263 | * Attempt to map a SysAddr to a node. On success, return a pointer to the | |
264 | * mem_ctl_info structure for the node that the SysAddr maps to. | |
265 | * | |
266 | * On failure, return NULL. | |
267 | */ | |
268 | static struct mem_ctl_info *find_mc_by_sys_addr(struct mem_ctl_info *mci, | |
269 | u64 sys_addr) | |
270 | { | |
271 | struct amd64_pvt *pvt; | |
272 | int node_id; | |
273 | u32 intlv_en, bits; | |
274 | ||
275 | /* | |
276 | * Here we use the DRAM Base (section 3.4.4.1) and DRAM Limit (section | |
277 | * 3.4.4.2) registers to map the SysAddr to a node ID. | |
278 | */ | |
279 | pvt = mci->pvt_info; | |
280 | ||
281 | /* | |
282 | * The value of this field should be the same for all DRAM Base | |
283 | * registers. Therefore we arbitrarily choose to read it from the | |
284 | * register for node 0. | |
285 | */ | |
286 | intlv_en = pvt->dram_IntlvEn[0]; | |
287 | ||
288 | if (intlv_en == 0) { | |
8edc5445 | 289 | for (node_id = 0; node_id < DRAM_REG_COUNT; node_id++) { |
6775763a | 290 | if (amd64_base_limit_match(pvt, sys_addr, node_id)) |
8edc5445 | 291 | goto found; |
6775763a | 292 | } |
8edc5445 | 293 | goto err_no_match; |
6775763a DT |
294 | } |
295 | ||
72f158fe BP |
296 | if (unlikely((intlv_en != 0x01) && |
297 | (intlv_en != 0x03) && | |
298 | (intlv_en != 0x07))) { | |
6775763a DT |
299 | amd64_printk(KERN_WARNING, "junk value of 0x%x extracted from " |
300 | "IntlvEn field of DRAM Base Register for node 0: " | |
72f158fe | 301 | "this probably indicates a BIOS bug.\n", intlv_en); |
6775763a DT |
302 | return NULL; |
303 | } | |
304 | ||
305 | bits = (((u32) sys_addr) >> 12) & intlv_en; | |
306 | ||
307 | for (node_id = 0; ; ) { | |
8edc5445 | 308 | if ((pvt->dram_IntlvSel[node_id] & intlv_en) == bits) |
6775763a DT |
309 | break; /* intlv_sel field matches */ |
310 | ||
311 | if (++node_id >= DRAM_REG_COUNT) | |
312 | goto err_no_match; | |
313 | } | |
314 | ||
315 | /* sanity test for sys_addr */ | |
316 | if (unlikely(!amd64_base_limit_match(pvt, sys_addr, node_id))) { | |
317 | amd64_printk(KERN_WARNING, | |
8edc5445 BP |
318 | "%s(): sys_addr 0x%llx falls outside base/limit " |
319 | "address range for node %d with node interleaving " | |
320 | "enabled.\n", | |
321 | __func__, sys_addr, node_id); | |
6775763a DT |
322 | return NULL; |
323 | } | |
324 | ||
325 | found: | |
326 | return edac_mc_find(node_id); | |
327 | ||
328 | err_no_match: | |
329 | debugf2("sys_addr 0x%lx doesn't match any node\n", | |
330 | (unsigned long)sys_addr); | |
331 | ||
332 | return NULL; | |
333 | } | |
e2ce7255 DT |
334 | |
335 | /* | |
336 | * Extract the DRAM CS base address from selected csrow register. | |
337 | */ | |
338 | static u64 base_from_dct_base(struct amd64_pvt *pvt, int csrow) | |
339 | { | |
340 | return ((u64) (amd64_get_dct_base(pvt, 0, csrow) & pvt->dcsb_base)) << | |
341 | pvt->dcs_shift; | |
342 | } | |
343 | ||
344 | /* | |
345 | * Extract the mask from the dcsb0[csrow] entry in a CPU revision-specific way. | |
346 | */ | |
347 | static u64 mask_from_dct_mask(struct amd64_pvt *pvt, int csrow) | |
348 | { | |
349 | u64 dcsm_bits, other_bits; | |
350 | u64 mask; | |
351 | ||
352 | /* Extract bits from DRAM CS Mask. */ | |
353 | dcsm_bits = amd64_get_dct_mask(pvt, 0, csrow) & pvt->dcsm_mask; | |
354 | ||
355 | other_bits = pvt->dcsm_mask; | |
356 | other_bits = ~(other_bits << pvt->dcs_shift); | |
357 | ||
358 | /* | |
359 | * The extracted bits from DCSM belong in the spaces represented by | |
360 | * the cleared bits in other_bits. | |
361 | */ | |
362 | mask = (dcsm_bits << pvt->dcs_shift) | other_bits; | |
363 | ||
364 | return mask; | |
365 | } | |
366 | ||
367 | /* | |
368 | * @input_addr is an InputAddr associated with the node given by mci. Return the | |
369 | * csrow that input_addr maps to, or -1 on failure (no csrow claims input_addr). | |
370 | */ | |
371 | static int input_addr_to_csrow(struct mem_ctl_info *mci, u64 input_addr) | |
372 | { | |
373 | struct amd64_pvt *pvt; | |
374 | int csrow; | |
375 | u64 base, mask; | |
376 | ||
377 | pvt = mci->pvt_info; | |
378 | ||
379 | /* | |
380 | * Here we use the DRAM CS Base and DRAM CS Mask registers. For each CS | |
381 | * base/mask register pair, test the condition shown near the start of | |
382 | * section 3.5.4 (p. 84, BKDG #26094, K8, revA-E). | |
383 | */ | |
9d858bb1 | 384 | for (csrow = 0; csrow < pvt->cs_count; csrow++) { |
e2ce7255 DT |
385 | |
386 | /* This DRAM chip select is disabled on this node */ | |
387 | if ((pvt->dcsb0[csrow] & K8_DCSB_CS_ENABLE) == 0) | |
388 | continue; | |
389 | ||
390 | base = base_from_dct_base(pvt, csrow); | |
391 | mask = ~mask_from_dct_mask(pvt, csrow); | |
392 | ||
393 | if ((input_addr & mask) == (base & mask)) { | |
394 | debugf2("InputAddr 0x%lx matches csrow %d (node %d)\n", | |
395 | (unsigned long)input_addr, csrow, | |
396 | pvt->mc_node_id); | |
397 | ||
398 | return csrow; | |
399 | } | |
400 | } | |
401 | ||
402 | debugf2("no matching csrow for InputAddr 0x%lx (MC node %d)\n", | |
403 | (unsigned long)input_addr, pvt->mc_node_id); | |
404 | ||
405 | return -1; | |
406 | } | |
407 | ||
408 | /* | |
409 | * Return the base value defined by the DRAM Base register for the node | |
410 | * represented by mci. This function returns the full 40-bit value despite the | |
411 | * fact that the register only stores bits 39-24 of the value. See section | |
412 | * 3.4.4.1 (BKDG #26094, K8, revA-E) | |
413 | */ | |
414 | static inline u64 get_dram_base(struct mem_ctl_info *mci) | |
415 | { | |
416 | struct amd64_pvt *pvt = mci->pvt_info; | |
417 | ||
418 | return pvt->dram_base[pvt->mc_node_id]; | |
419 | } | |
420 | ||
421 | /* | |
422 | * Obtain info from the DRAM Hole Address Register (section 3.4.8, pub #26094) | |
423 | * for the node represented by mci. Info is passed back in *hole_base, | |
424 | * *hole_offset, and *hole_size. Function returns 0 if info is valid or 1 if | |
425 | * info is invalid. Info may be invalid for either of the following reasons: | |
426 | * | |
427 | * - The revision of the node is not E or greater. In this case, the DRAM Hole | |
428 | * Address Register does not exist. | |
429 | * | |
430 | * - The DramHoleValid bit is cleared in the DRAM Hole Address Register, | |
431 | * indicating that its contents are not valid. | |
432 | * | |
433 | * The values passed back in *hole_base, *hole_offset, and *hole_size are | |
434 | * complete 32-bit values despite the fact that the bitfields in the DHAR | |
435 | * only represent bits 31-24 of the base and offset values. | |
436 | */ | |
437 | int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base, | |
438 | u64 *hole_offset, u64 *hole_size) | |
439 | { | |
440 | struct amd64_pvt *pvt = mci->pvt_info; | |
441 | u64 base; | |
442 | ||
443 | /* only revE and later have the DRAM Hole Address Register */ | |
1433eb99 | 444 | if (boot_cpu_data.x86 == 0xf && pvt->ext_model < K8_REV_E) { |
e2ce7255 DT |
445 | debugf1(" revision %d for node %d does not support DHAR\n", |
446 | pvt->ext_model, pvt->mc_node_id); | |
447 | return 1; | |
448 | } | |
449 | ||
450 | /* only valid for Fam10h */ | |
451 | if (boot_cpu_data.x86 == 0x10 && | |
452 | (pvt->dhar & F10_DRAM_MEM_HOIST_VALID) == 0) { | |
453 | debugf1(" Dram Memory Hoisting is DISABLED on this system\n"); | |
454 | return 1; | |
455 | } | |
456 | ||
457 | if ((pvt->dhar & DHAR_VALID) == 0) { | |
458 | debugf1(" Dram Memory Hoisting is DISABLED on this node %d\n", | |
459 | pvt->mc_node_id); | |
460 | return 1; | |
461 | } | |
462 | ||
463 | /* This node has Memory Hoisting */ | |
464 | ||
465 | /* +------------------+--------------------+--------------------+----- | |
466 | * | memory | DRAM hole | relocated | | |
467 | * | [0, (x - 1)] | [x, 0xffffffff] | addresses from | | |
468 | * | | | DRAM hole | | |
469 | * | | | [0x100000000, | | |
470 | * | | | (0x100000000+ | | |
471 | * | | | (0xffffffff-x))] | | |
472 | * +------------------+--------------------+--------------------+----- | |
473 | * | |
474 | * Above is a diagram of physical memory showing the DRAM hole and the | |
475 | * relocated addresses from the DRAM hole. As shown, the DRAM hole | |
476 | * starts at address x (the base address) and extends through address | |
477 | * 0xffffffff. The DRAM Hole Address Register (DHAR) relocates the | |
478 | * addresses in the hole so that they start at 0x100000000. | |
479 | */ | |
480 | ||
481 | base = dhar_base(pvt->dhar); | |
482 | ||
483 | *hole_base = base; | |
484 | *hole_size = (0x1ull << 32) - base; | |
485 | ||
486 | if (boot_cpu_data.x86 > 0xf) | |
487 | *hole_offset = f10_dhar_offset(pvt->dhar); | |
488 | else | |
489 | *hole_offset = k8_dhar_offset(pvt->dhar); | |
490 | ||
491 | debugf1(" DHAR info for node %d base 0x%lx offset 0x%lx size 0x%lx\n", | |
492 | pvt->mc_node_id, (unsigned long)*hole_base, | |
493 | (unsigned long)*hole_offset, (unsigned long)*hole_size); | |
494 | ||
495 | return 0; | |
496 | } | |
497 | EXPORT_SYMBOL_GPL(amd64_get_dram_hole_info); | |
498 | ||
93c2df58 DT |
499 | /* |
500 | * Return the DramAddr that the SysAddr given by @sys_addr maps to. It is | |
501 | * assumed that sys_addr maps to the node given by mci. | |
502 | * | |
503 | * The first part of section 3.4.4 (p. 70) shows how the DRAM Base (section | |
504 | * 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers are used to translate a | |
505 | * SysAddr to a DramAddr. If the DRAM Hole Address Register (DHAR) is enabled, | |
506 | * then it is also involved in translating a SysAddr to a DramAddr. Sections | |
507 | * 3.4.8 and 3.5.8.2 describe the DHAR and how it is used for memory hoisting. | |
508 | * These parts of the documentation are unclear. I interpret them as follows: | |
509 | * | |
510 | * When node n receives a SysAddr, it processes the SysAddr as follows: | |
511 | * | |
512 | * 1. It extracts the DRAMBase and DRAMLimit values from the DRAM Base and DRAM | |
513 | * Limit registers for node n. If the SysAddr is not within the range | |
514 | * specified by the base and limit values, then node n ignores the Sysaddr | |
515 | * (since it does not map to node n). Otherwise continue to step 2 below. | |
516 | * | |
517 | * 2. If the DramHoleValid bit of the DHAR for node n is clear, the DHAR is | |
518 | * disabled so skip to step 3 below. Otherwise see if the SysAddr is within | |
519 | * the range of relocated addresses (starting at 0x100000000) from the DRAM | |
520 | * hole. If not, skip to step 3 below. Else get the value of the | |
521 | * DramHoleOffset field from the DHAR. To obtain the DramAddr, subtract the | |
522 | * offset defined by this value from the SysAddr. | |
523 | * | |
524 | * 3. Obtain the base address for node n from the DRAMBase field of the DRAM | |
525 | * Base register for node n. To obtain the DramAddr, subtract the base | |
526 | * address from the SysAddr, as shown near the start of section 3.4.4 (p.70). | |
527 | */ | |
528 | static u64 sys_addr_to_dram_addr(struct mem_ctl_info *mci, u64 sys_addr) | |
529 | { | |
530 | u64 dram_base, hole_base, hole_offset, hole_size, dram_addr; | |
531 | int ret = 0; | |
532 | ||
533 | dram_base = get_dram_base(mci); | |
534 | ||
535 | ret = amd64_get_dram_hole_info(mci, &hole_base, &hole_offset, | |
536 | &hole_size); | |
537 | if (!ret) { | |
538 | if ((sys_addr >= (1ull << 32)) && | |
539 | (sys_addr < ((1ull << 32) + hole_size))) { | |
540 | /* use DHAR to translate SysAddr to DramAddr */ | |
541 | dram_addr = sys_addr - hole_offset; | |
542 | ||
543 | debugf2("using DHAR to translate SysAddr 0x%lx to " | |
544 | "DramAddr 0x%lx\n", | |
545 | (unsigned long)sys_addr, | |
546 | (unsigned long)dram_addr); | |
547 | ||
548 | return dram_addr; | |
549 | } | |
550 | } | |
551 | ||
552 | /* | |
553 | * Translate the SysAddr to a DramAddr as shown near the start of | |
554 | * section 3.4.4 (p. 70). Although sys_addr is a 64-bit value, the k8 | |
555 | * only deals with 40-bit values. Therefore we discard bits 63-40 of | |
556 | * sys_addr below. If bit 39 of sys_addr is 1 then the bits we | |
557 | * discard are all 1s. Otherwise the bits we discard are all 0s. See | |
558 | * section 3.4.2 of AMD publication 24592: AMD x86-64 Architecture | |
559 | * Programmer's Manual Volume 1 Application Programming. | |
560 | */ | |
561 | dram_addr = (sys_addr & 0xffffffffffull) - dram_base; | |
562 | ||
563 | debugf2("using DRAM Base register to translate SysAddr 0x%lx to " | |
564 | "DramAddr 0x%lx\n", (unsigned long)sys_addr, | |
565 | (unsigned long)dram_addr); | |
566 | return dram_addr; | |
567 | } | |
568 | ||
569 | /* | |
570 | * @intlv_en is the value of the IntlvEn field from a DRAM Base register | |
571 | * (section 3.4.4.1). Return the number of bits from a SysAddr that are used | |
572 | * for node interleaving. | |
573 | */ | |
574 | static int num_node_interleave_bits(unsigned intlv_en) | |
575 | { | |
576 | static const int intlv_shift_table[] = { 0, 1, 0, 2, 0, 0, 0, 3 }; | |
577 | int n; | |
578 | ||
579 | BUG_ON(intlv_en > 7); | |
580 | n = intlv_shift_table[intlv_en]; | |
581 | return n; | |
582 | } | |
583 | ||
584 | /* Translate the DramAddr given by @dram_addr to an InputAddr. */ | |
585 | static u64 dram_addr_to_input_addr(struct mem_ctl_info *mci, u64 dram_addr) | |
586 | { | |
587 | struct amd64_pvt *pvt; | |
588 | int intlv_shift; | |
589 | u64 input_addr; | |
590 | ||
591 | pvt = mci->pvt_info; | |
592 | ||
593 | /* | |
594 | * See the start of section 3.4.4 (p. 70, BKDG #26094, K8, revA-E) | |
595 | * concerning translating a DramAddr to an InputAddr. | |
596 | */ | |
597 | intlv_shift = num_node_interleave_bits(pvt->dram_IntlvEn[0]); | |
598 | input_addr = ((dram_addr >> intlv_shift) & 0xffffff000ull) + | |
599 | (dram_addr & 0xfff); | |
600 | ||
601 | debugf2(" Intlv Shift=%d DramAddr=0x%lx maps to InputAddr=0x%lx\n", | |
602 | intlv_shift, (unsigned long)dram_addr, | |
603 | (unsigned long)input_addr); | |
604 | ||
605 | return input_addr; | |
606 | } | |
607 | ||
608 | /* | |
609 | * Translate the SysAddr represented by @sys_addr to an InputAddr. It is | |
610 | * assumed that @sys_addr maps to the node given by mci. | |
611 | */ | |
612 | static u64 sys_addr_to_input_addr(struct mem_ctl_info *mci, u64 sys_addr) | |
613 | { | |
614 | u64 input_addr; | |
615 | ||
616 | input_addr = | |
617 | dram_addr_to_input_addr(mci, sys_addr_to_dram_addr(mci, sys_addr)); | |
618 | ||
619 | debugf2("SysAdddr 0x%lx translates to InputAddr 0x%lx\n", | |
620 | (unsigned long)sys_addr, (unsigned long)input_addr); | |
621 | ||
622 | return input_addr; | |
623 | } | |
624 | ||
625 | ||
626 | /* | |
627 | * @input_addr is an InputAddr associated with the node represented by mci. | |
628 | * Translate @input_addr to a DramAddr and return the result. | |
629 | */ | |
630 | static u64 input_addr_to_dram_addr(struct mem_ctl_info *mci, u64 input_addr) | |
631 | { | |
632 | struct amd64_pvt *pvt; | |
633 | int node_id, intlv_shift; | |
634 | u64 bits, dram_addr; | |
635 | u32 intlv_sel; | |
636 | ||
637 | /* | |
638 | * Near the start of section 3.4.4 (p. 70, BKDG #26094, K8, revA-E) | |
639 | * shows how to translate a DramAddr to an InputAddr. Here we reverse | |
640 | * this procedure. When translating from a DramAddr to an InputAddr, the | |
641 | * bits used for node interleaving are discarded. Here we recover these | |
642 | * bits from the IntlvSel field of the DRAM Limit register (section | |
643 | * 3.4.4.2) for the node that input_addr is associated with. | |
644 | */ | |
645 | pvt = mci->pvt_info; | |
646 | node_id = pvt->mc_node_id; | |
647 | BUG_ON((node_id < 0) || (node_id > 7)); | |
648 | ||
649 | intlv_shift = num_node_interleave_bits(pvt->dram_IntlvEn[0]); | |
650 | ||
651 | if (intlv_shift == 0) { | |
652 | debugf1(" InputAddr 0x%lx translates to DramAddr of " | |
653 | "same value\n", (unsigned long)input_addr); | |
654 | ||
655 | return input_addr; | |
656 | } | |
657 | ||
658 | bits = ((input_addr & 0xffffff000ull) << intlv_shift) + | |
659 | (input_addr & 0xfff); | |
660 | ||
661 | intlv_sel = pvt->dram_IntlvSel[node_id] & ((1 << intlv_shift) - 1); | |
662 | dram_addr = bits + (intlv_sel << 12); | |
663 | ||
664 | debugf1("InputAddr 0x%lx translates to DramAddr 0x%lx " | |
665 | "(%d node interleave bits)\n", (unsigned long)input_addr, | |
666 | (unsigned long)dram_addr, intlv_shift); | |
667 | ||
668 | return dram_addr; | |
669 | } | |
670 | ||
671 | /* | |
672 | * @dram_addr is a DramAddr that maps to the node represented by mci. Convert | |
673 | * @dram_addr to a SysAddr. | |
674 | */ | |
675 | static u64 dram_addr_to_sys_addr(struct mem_ctl_info *mci, u64 dram_addr) | |
676 | { | |
677 | struct amd64_pvt *pvt = mci->pvt_info; | |
678 | u64 hole_base, hole_offset, hole_size, base, limit, sys_addr; | |
679 | int ret = 0; | |
680 | ||
681 | ret = amd64_get_dram_hole_info(mci, &hole_base, &hole_offset, | |
682 | &hole_size); | |
683 | if (!ret) { | |
684 | if ((dram_addr >= hole_base) && | |
685 | (dram_addr < (hole_base + hole_size))) { | |
686 | sys_addr = dram_addr + hole_offset; | |
687 | ||
688 | debugf1("using DHAR to translate DramAddr 0x%lx to " | |
689 | "SysAddr 0x%lx\n", (unsigned long)dram_addr, | |
690 | (unsigned long)sys_addr); | |
691 | ||
692 | return sys_addr; | |
693 | } | |
694 | } | |
695 | ||
696 | amd64_get_base_and_limit(pvt, pvt->mc_node_id, &base, &limit); | |
697 | sys_addr = dram_addr + base; | |
698 | ||
699 | /* | |
700 | * The sys_addr we have computed up to this point is a 40-bit value | |
701 | * because the k8 deals with 40-bit values. However, the value we are | |
702 | * supposed to return is a full 64-bit physical address. The AMD | |
703 | * x86-64 architecture specifies that the most significant implemented | |
704 | * address bit through bit 63 of a physical address must be either all | |
705 | * 0s or all 1s. Therefore we sign-extend the 40-bit sys_addr to a | |
706 | * 64-bit value below. See section 3.4.2 of AMD publication 24592: | |
707 | * AMD x86-64 Architecture Programmer's Manual Volume 1 Application | |
708 | * Programming. | |
709 | */ | |
710 | sys_addr |= ~((sys_addr & (1ull << 39)) - 1); | |
711 | ||
712 | debugf1(" Node %d, DramAddr 0x%lx to SysAddr 0x%lx\n", | |
713 | pvt->mc_node_id, (unsigned long)dram_addr, | |
714 | (unsigned long)sys_addr); | |
715 | ||
716 | return sys_addr; | |
717 | } | |
718 | ||
719 | /* | |
720 | * @input_addr is an InputAddr associated with the node given by mci. Translate | |
721 | * @input_addr to a SysAddr. | |
722 | */ | |
723 | static inline u64 input_addr_to_sys_addr(struct mem_ctl_info *mci, | |
724 | u64 input_addr) | |
725 | { | |
726 | return dram_addr_to_sys_addr(mci, | |
727 | input_addr_to_dram_addr(mci, input_addr)); | |
728 | } | |
729 | ||
730 | /* | |
731 | * Find the minimum and maximum InputAddr values that map to the given @csrow. | |
732 | * Pass back these values in *input_addr_min and *input_addr_max. | |
733 | */ | |
734 | static void find_csrow_limits(struct mem_ctl_info *mci, int csrow, | |
735 | u64 *input_addr_min, u64 *input_addr_max) | |
736 | { | |
737 | struct amd64_pvt *pvt; | |
738 | u64 base, mask; | |
739 | ||
740 | pvt = mci->pvt_info; | |
9d858bb1 | 741 | BUG_ON((csrow < 0) || (csrow >= pvt->cs_count)); |
93c2df58 DT |
742 | |
743 | base = base_from_dct_base(pvt, csrow); | |
744 | mask = mask_from_dct_mask(pvt, csrow); | |
745 | ||
746 | *input_addr_min = base & ~mask; | |
747 | *input_addr_max = base | mask | pvt->dcs_mask_notused; | |
748 | } | |
749 | ||
93c2df58 DT |
750 | /* Map the Error address to a PAGE and PAGE OFFSET. */ |
751 | static inline void error_address_to_page_and_offset(u64 error_address, | |
752 | u32 *page, u32 *offset) | |
753 | { | |
754 | *page = (u32) (error_address >> PAGE_SHIFT); | |
755 | *offset = ((u32) error_address) & ~PAGE_MASK; | |
756 | } | |
757 | ||
758 | /* | |
759 | * @sys_addr is an error address (a SysAddr) extracted from the MCA NB Address | |
760 | * Low (section 3.6.4.5) and MCA NB Address High (section 3.6.4.6) registers | |
761 | * of a node that detected an ECC memory error. mci represents the node that | |
762 | * the error address maps to (possibly different from the node that detected | |
763 | * the error). Return the number of the csrow that sys_addr maps to, or -1 on | |
764 | * error. | |
765 | */ | |
766 | static int sys_addr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr) | |
767 | { | |
768 | int csrow; | |
769 | ||
770 | csrow = input_addr_to_csrow(mci, sys_addr_to_input_addr(mci, sys_addr)); | |
771 | ||
772 | if (csrow == -1) | |
773 | amd64_mc_printk(mci, KERN_ERR, | |
774 | "Failed to translate InputAddr to csrow for " | |
775 | "address 0x%lx\n", (unsigned long)sys_addr); | |
776 | return csrow; | |
777 | } | |
e2ce7255 | 778 | |
bfc04aec | 779 | static int get_channel_from_ecc_syndrome(struct mem_ctl_info *, u16); |
2da11654 | 780 | |
ad6a32e9 BP |
781 | static u16 extract_syndrome(struct err_regs *err) |
782 | { | |
783 | return ((err->nbsh >> 15) & 0xff) | ((err->nbsl >> 16) & 0xff00); | |
784 | } | |
785 | ||
2da11654 DT |
786 | /* |
787 | * Determine if the DIMMs have ECC enabled. ECC is enabled ONLY if all the DIMMs | |
788 | * are ECC capable. | |
789 | */ | |
790 | static enum edac_type amd64_determine_edac_cap(struct amd64_pvt *pvt) | |
791 | { | |
792 | int bit; | |
584fcff4 | 793 | enum dev_type edac_cap = EDAC_FLAG_NONE; |
2da11654 | 794 | |
1433eb99 | 795 | bit = (boot_cpu_data.x86 > 0xf || pvt->ext_model >= K8_REV_F) |
2da11654 DT |
796 | ? 19 |
797 | : 17; | |
798 | ||
584fcff4 | 799 | if (pvt->dclr0 & BIT(bit)) |
2da11654 DT |
800 | edac_cap = EDAC_FLAG_SECDED; |
801 | ||
802 | return edac_cap; | |
803 | } | |
804 | ||
805 | ||
8566c4df | 806 | static void amd64_debug_display_dimm_sizes(int ctrl, struct amd64_pvt *pvt); |
2da11654 | 807 | |
68798e17 BP |
808 | static void amd64_dump_dramcfg_low(u32 dclr, int chan) |
809 | { | |
810 | debugf1("F2x%d90 (DRAM Cfg Low): 0x%08x\n", chan, dclr); | |
811 | ||
812 | debugf1(" DIMM type: %sbuffered; all DIMMs support ECC: %s\n", | |
813 | (dclr & BIT(16)) ? "un" : "", | |
814 | (dclr & BIT(19)) ? "yes" : "no"); | |
815 | ||
816 | debugf1(" PAR/ERR parity: %s\n", | |
817 | (dclr & BIT(8)) ? "enabled" : "disabled"); | |
818 | ||
819 | debugf1(" DCT 128bit mode width: %s\n", | |
820 | (dclr & BIT(11)) ? "128b" : "64b"); | |
821 | ||
822 | debugf1(" x4 logical DIMMs present: L0: %s L1: %s L2: %s L3: %s\n", | |
823 | (dclr & BIT(12)) ? "yes" : "no", | |
824 | (dclr & BIT(13)) ? "yes" : "no", | |
825 | (dclr & BIT(14)) ? "yes" : "no", | |
826 | (dclr & BIT(15)) ? "yes" : "no"); | |
827 | } | |
828 | ||
2da11654 DT |
829 | /* Display and decode various NB registers for debug purposes. */ |
830 | static void amd64_dump_misc_regs(struct amd64_pvt *pvt) | |
831 | { | |
832 | int ganged; | |
833 | ||
68798e17 BP |
834 | debugf1("F3xE8 (NB Cap): 0x%08x\n", pvt->nbcap); |
835 | ||
836 | debugf1(" NB two channel DRAM capable: %s\n", | |
837 | (pvt->nbcap & K8_NBCAP_DCT_DUAL) ? "yes" : "no"); | |
2da11654 | 838 | |
68798e17 BP |
839 | debugf1(" ECC capable: %s, ChipKill ECC capable: %s\n", |
840 | (pvt->nbcap & K8_NBCAP_SECDED) ? "yes" : "no", | |
841 | (pvt->nbcap & K8_NBCAP_CHIPKILL) ? "yes" : "no"); | |
842 | ||
843 | amd64_dump_dramcfg_low(pvt->dclr0, 0); | |
2da11654 | 844 | |
8de1d91e | 845 | debugf1("F3xB0 (Online Spare): 0x%08x\n", pvt->online_spare); |
2da11654 | 846 | |
8de1d91e BP |
847 | debugf1("F1xF0 (DRAM Hole Address): 0x%08x, base: 0x%08x, " |
848 | "offset: 0x%08x\n", | |
849 | pvt->dhar, | |
850 | dhar_base(pvt->dhar), | |
851 | (boot_cpu_data.x86 == 0xf) ? k8_dhar_offset(pvt->dhar) | |
852 | : f10_dhar_offset(pvt->dhar)); | |
2da11654 | 853 | |
8de1d91e BP |
854 | debugf1(" DramHoleValid: %s\n", |
855 | (pvt->dhar & DHAR_VALID) ? "yes" : "no"); | |
2da11654 | 856 | |
8de1d91e | 857 | /* everything below this point is Fam10h and above */ |
8566c4df BP |
858 | if (boot_cpu_data.x86 == 0xf) { |
859 | amd64_debug_display_dimm_sizes(0, pvt); | |
2da11654 | 860 | return; |
8566c4df | 861 | } |
2da11654 | 862 | |
ad6a32e9 BP |
863 | amd64_printk(KERN_INFO, "using %s syndromes.\n", |
864 | ((pvt->syn_type == 8) ? "x8" : "x4")); | |
865 | ||
8de1d91e | 866 | /* Only if NOT ganged does dclr1 have valid info */ |
68798e17 BP |
867 | if (!dct_ganging_enabled(pvt)) |
868 | amd64_dump_dramcfg_low(pvt->dclr1, 1); | |
2da11654 DT |
869 | |
870 | /* | |
871 | * Determine if ganged and then dump memory sizes for first controller, | |
872 | * and if NOT ganged dump info for 2nd controller. | |
873 | */ | |
874 | ganged = dct_ganging_enabled(pvt); | |
875 | ||
8566c4df | 876 | amd64_debug_display_dimm_sizes(0, pvt); |
2da11654 DT |
877 | |
878 | if (!ganged) | |
8566c4df | 879 | amd64_debug_display_dimm_sizes(1, pvt); |
2da11654 DT |
880 | } |
881 | ||
882 | /* Read in both of DBAM registers */ | |
883 | static void amd64_read_dbam_reg(struct amd64_pvt *pvt) | |
884 | { | |
6ba5dcdc | 885 | amd64_read_pci_cfg(pvt->dram_f2_ctl, DBAM0, &pvt->dbam0); |
2da11654 | 886 | |
6ba5dcdc BP |
887 | if (boot_cpu_data.x86 >= 0x10) |
888 | amd64_read_pci_cfg(pvt->dram_f2_ctl, DBAM1, &pvt->dbam1); | |
2da11654 DT |
889 | } |
890 | ||
94be4bff DT |
891 | /* |
892 | * NOTE: CPU Revision Dependent code: Rev E and Rev F | |
893 | * | |
894 | * Set the DCSB and DCSM mask values depending on the CPU revision value. Also | |
895 | * set the shift factor for the DCSB and DCSM values. | |
896 | * | |
897 | * ->dcs_mask_notused, RevE: | |
898 | * | |
899 | * To find the max InputAddr for the csrow, start with the base address and set | |
900 | * all bits that are "don't care" bits in the test at the start of section | |
901 | * 3.5.4 (p. 84). | |
902 | * | |
903 | * The "don't care" bits are all set bits in the mask and all bits in the gaps | |
904 | * between bit ranges [35:25] and [19:13]. The value REV_E_DCS_NOTUSED_BITS | |
905 | * represents bits [24:20] and [12:0], which are all bits in the above-mentioned | |
906 | * gaps. | |
907 | * | |
908 | * ->dcs_mask_notused, RevF and later: | |
909 | * | |
910 | * To find the max InputAddr for the csrow, start with the base address and set | |
911 | * all bits that are "don't care" bits in the test at the start of NPT section | |
912 | * 4.5.4 (p. 87). | |
913 | * | |
914 | * The "don't care" bits are all set bits in the mask and all bits in the gaps | |
915 | * between bit ranges [36:27] and [21:13]. | |
916 | * | |
917 | * The value REV_F_F1Xh_DCS_NOTUSED_BITS represents bits [26:22] and [12:0], | |
918 | * which are all bits in the above-mentioned gaps. | |
919 | */ | |
920 | static void amd64_set_dct_base_and_mask(struct amd64_pvt *pvt) | |
921 | { | |
9d858bb1 | 922 | |
1433eb99 | 923 | if (boot_cpu_data.x86 == 0xf && pvt->ext_model < K8_REV_F) { |
9d858bb1 BP |
924 | pvt->dcsb_base = REV_E_DCSB_BASE_BITS; |
925 | pvt->dcsm_mask = REV_E_DCSM_MASK_BITS; | |
926 | pvt->dcs_mask_notused = REV_E_DCS_NOTUSED_BITS; | |
927 | pvt->dcs_shift = REV_E_DCS_SHIFT; | |
928 | pvt->cs_count = 8; | |
929 | pvt->num_dcsm = 8; | |
930 | } else { | |
94be4bff DT |
931 | pvt->dcsb_base = REV_F_F1Xh_DCSB_BASE_BITS; |
932 | pvt->dcsm_mask = REV_F_F1Xh_DCSM_MASK_BITS; | |
933 | pvt->dcs_mask_notused = REV_F_F1Xh_DCS_NOTUSED_BITS; | |
934 | pvt->dcs_shift = REV_F_F1Xh_DCS_SHIFT; | |
3ab0e7dc BP |
935 | pvt->cs_count = 8; |
936 | pvt->num_dcsm = 4; | |
94be4bff DT |
937 | } |
938 | } | |
939 | ||
940 | /* | |
941 | * Function 2 Offset F10_DCSB0; read in the DCS Base and DCS Mask hw registers | |
942 | */ | |
943 | static void amd64_read_dct_base_mask(struct amd64_pvt *pvt) | |
944 | { | |
6ba5dcdc | 945 | int cs, reg; |
94be4bff DT |
946 | |
947 | amd64_set_dct_base_and_mask(pvt); | |
948 | ||
9d858bb1 | 949 | for (cs = 0; cs < pvt->cs_count; cs++) { |
94be4bff | 950 | reg = K8_DCSB0 + (cs * 4); |
6ba5dcdc | 951 | if (!amd64_read_pci_cfg(pvt->dram_f2_ctl, reg, &pvt->dcsb0[cs])) |
94be4bff DT |
952 | debugf0(" DCSB0[%d]=0x%08x reg: F2x%x\n", |
953 | cs, pvt->dcsb0[cs], reg); | |
954 | ||
955 | /* If DCT are NOT ganged, then read in DCT1's base */ | |
956 | if (boot_cpu_data.x86 >= 0x10 && !dct_ganging_enabled(pvt)) { | |
957 | reg = F10_DCSB1 + (cs * 4); | |
6ba5dcdc BP |
958 | if (!amd64_read_pci_cfg(pvt->dram_f2_ctl, reg, |
959 | &pvt->dcsb1[cs])) | |
94be4bff DT |
960 | debugf0(" DCSB1[%d]=0x%08x reg: F2x%x\n", |
961 | cs, pvt->dcsb1[cs], reg); | |
962 | } else { | |
963 | pvt->dcsb1[cs] = 0; | |
964 | } | |
965 | } | |
966 | ||
967 | for (cs = 0; cs < pvt->num_dcsm; cs++) { | |
4afcd2dc | 968 | reg = K8_DCSM0 + (cs * 4); |
6ba5dcdc | 969 | if (!amd64_read_pci_cfg(pvt->dram_f2_ctl, reg, &pvt->dcsm0[cs])) |
94be4bff DT |
970 | debugf0(" DCSM0[%d]=0x%08x reg: F2x%x\n", |
971 | cs, pvt->dcsm0[cs], reg); | |
972 | ||
973 | /* If DCT are NOT ganged, then read in DCT1's mask */ | |
974 | if (boot_cpu_data.x86 >= 0x10 && !dct_ganging_enabled(pvt)) { | |
975 | reg = F10_DCSM1 + (cs * 4); | |
6ba5dcdc BP |
976 | if (!amd64_read_pci_cfg(pvt->dram_f2_ctl, reg, |
977 | &pvt->dcsm1[cs])) | |
94be4bff DT |
978 | debugf0(" DCSM1[%d]=0x%08x reg: F2x%x\n", |
979 | cs, pvt->dcsm1[cs], reg); | |
6ba5dcdc | 980 | } else { |
94be4bff | 981 | pvt->dcsm1[cs] = 0; |
6ba5dcdc | 982 | } |
94be4bff DT |
983 | } |
984 | } | |
985 | ||
986 | static enum mem_type amd64_determine_memory_type(struct amd64_pvt *pvt) | |
987 | { | |
988 | enum mem_type type; | |
989 | ||
1433eb99 | 990 | if (boot_cpu_data.x86 >= 0x10 || pvt->ext_model >= K8_REV_F) { |
6b4c0bde BP |
991 | if (pvt->dchr0 & DDR3_MODE) |
992 | type = (pvt->dclr0 & BIT(16)) ? MEM_DDR3 : MEM_RDDR3; | |
993 | else | |
994 | type = (pvt->dclr0 & BIT(16)) ? MEM_DDR2 : MEM_RDDR2; | |
94be4bff | 995 | } else { |
94be4bff DT |
996 | type = (pvt->dclr0 & BIT(18)) ? MEM_DDR : MEM_RDDR; |
997 | } | |
998 | ||
239642fe | 999 | debugf1(" Memory type is: %s\n", edac_mem_types[type]); |
94be4bff DT |
1000 | |
1001 | return type; | |
1002 | } | |
1003 | ||
ddff876d DT |
1004 | /* |
1005 | * Read the DRAM Configuration Low register. It differs between CG, D & E revs | |
1006 | * and the later RevF memory controllers (DDR vs DDR2) | |
1007 | * | |
1008 | * Return: | |
1009 | * number of memory channels in operation | |
1010 | * Pass back: | |
1011 | * contents of the DCL0_LOW register | |
1012 | */ | |
1013 | static int k8_early_channel_count(struct amd64_pvt *pvt) | |
1014 | { | |
1015 | int flag, err = 0; | |
1016 | ||
6ba5dcdc | 1017 | err = amd64_read_pci_cfg(pvt->dram_f2_ctl, F10_DCLR_0, &pvt->dclr0); |
ddff876d DT |
1018 | if (err) |
1019 | return err; | |
1020 | ||
9f56da0e | 1021 | if (pvt->ext_model >= K8_REV_F) |
ddff876d DT |
1022 | /* RevF (NPT) and later */ |
1023 | flag = pvt->dclr0 & F10_WIDTH_128; | |
9f56da0e | 1024 | else |
ddff876d DT |
1025 | /* RevE and earlier */ |
1026 | flag = pvt->dclr0 & REVE_WIDTH_128; | |
ddff876d DT |
1027 | |
1028 | /* not used */ | |
1029 | pvt->dclr1 = 0; | |
1030 | ||
1031 | return (flag) ? 2 : 1; | |
1032 | } | |
1033 | ||
1034 | /* extract the ERROR ADDRESS for the K8 CPUs */ | |
1035 | static u64 k8_get_error_address(struct mem_ctl_info *mci, | |
ef44cc4c | 1036 | struct err_regs *info) |
ddff876d DT |
1037 | { |
1038 | return (((u64) (info->nbeah & 0xff)) << 32) + | |
1039 | (info->nbeal & ~0x03); | |
1040 | } | |
1041 | ||
1042 | /* | |
1043 | * Read the Base and Limit registers for K8 based Memory controllers; extract | |
1044 | * fields from the 'raw' reg into separate data fields | |
1045 | * | |
1046 | * Isolates: BASE, LIMIT, IntlvEn, IntlvSel, RW_EN | |
1047 | */ | |
1048 | static void k8_read_dram_base_limit(struct amd64_pvt *pvt, int dram) | |
1049 | { | |
1050 | u32 low; | |
1051 | u32 off = dram << 3; /* 8 bytes between DRAM entries */ | |
ddff876d | 1052 | |
6ba5dcdc | 1053 | amd64_read_pci_cfg(pvt->addr_f1_ctl, K8_DRAM_BASE_LOW + off, &low); |
ddff876d DT |
1054 | |
1055 | /* Extract parts into separate data entries */ | |
4997811e | 1056 | pvt->dram_base[dram] = ((u64) low & 0xFFFF0000) << 8; |
ddff876d DT |
1057 | pvt->dram_IntlvEn[dram] = (low >> 8) & 0x7; |
1058 | pvt->dram_rw_en[dram] = (low & 0x3); | |
1059 | ||
6ba5dcdc | 1060 | amd64_read_pci_cfg(pvt->addr_f1_ctl, K8_DRAM_LIMIT_LOW + off, &low); |
ddff876d DT |
1061 | |
1062 | /* | |
1063 | * Extract parts into separate data entries. Limit is the HIGHEST memory | |
1064 | * location of the region, so lower 24 bits need to be all ones | |
1065 | */ | |
4997811e | 1066 | pvt->dram_limit[dram] = (((u64) low & 0xFFFF0000) << 8) | 0x00FFFFFF; |
ddff876d DT |
1067 | pvt->dram_IntlvSel[dram] = (low >> 8) & 0x7; |
1068 | pvt->dram_DstNode[dram] = (low & 0x7); | |
1069 | } | |
1070 | ||
1071 | static void k8_map_sysaddr_to_csrow(struct mem_ctl_info *mci, | |
ad6a32e9 | 1072 | struct err_regs *err_info, u64 sys_addr) |
ddff876d DT |
1073 | { |
1074 | struct mem_ctl_info *src_mci; | |
ddff876d DT |
1075 | int channel, csrow; |
1076 | u32 page, offset; | |
ad6a32e9 | 1077 | u16 syndrome; |
ddff876d | 1078 | |
ad6a32e9 | 1079 | syndrome = extract_syndrome(err_info); |
ddff876d DT |
1080 | |
1081 | /* CHIPKILL enabled */ | |
ad6a32e9 | 1082 | if (err_info->nbcfg & K8_NBCFG_CHIPKILL) { |
bfc04aec | 1083 | channel = get_channel_from_ecc_syndrome(mci, syndrome); |
ddff876d DT |
1084 | if (channel < 0) { |
1085 | /* | |
1086 | * Syndrome didn't map, so we don't know which of the | |
1087 | * 2 DIMMs is in error. So we need to ID 'both' of them | |
1088 | * as suspect. | |
1089 | */ | |
1090 | amd64_mc_printk(mci, KERN_WARNING, | |
ad6a32e9 BP |
1091 | "unknown syndrome 0x%04x - possible " |
1092 | "error reporting race\n", syndrome); | |
ddff876d DT |
1093 | edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR); |
1094 | return; | |
1095 | } | |
1096 | } else { | |
1097 | /* | |
1098 | * non-chipkill ecc mode | |
1099 | * | |
1100 | * The k8 documentation is unclear about how to determine the | |
1101 | * channel number when using non-chipkill memory. This method | |
1102 | * was obtained from email communication with someone at AMD. | |
1103 | * (Wish the email was placed in this comment - norsk) | |
1104 | */ | |
44e9e2ee | 1105 | channel = ((sys_addr & BIT(3)) != 0); |
ddff876d DT |
1106 | } |
1107 | ||
1108 | /* | |
1109 | * Find out which node the error address belongs to. This may be | |
1110 | * different from the node that detected the error. | |
1111 | */ | |
44e9e2ee | 1112 | src_mci = find_mc_by_sys_addr(mci, sys_addr); |
2cff18c2 | 1113 | if (!src_mci) { |
ddff876d DT |
1114 | amd64_mc_printk(mci, KERN_ERR, |
1115 | "failed to map error address 0x%lx to a node\n", | |
44e9e2ee | 1116 | (unsigned long)sys_addr); |
ddff876d DT |
1117 | edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR); |
1118 | return; | |
1119 | } | |
1120 | ||
44e9e2ee BP |
1121 | /* Now map the sys_addr to a CSROW */ |
1122 | csrow = sys_addr_to_csrow(src_mci, sys_addr); | |
ddff876d DT |
1123 | if (csrow < 0) { |
1124 | edac_mc_handle_ce_no_info(src_mci, EDAC_MOD_STR); | |
1125 | } else { | |
44e9e2ee | 1126 | error_address_to_page_and_offset(sys_addr, &page, &offset); |
ddff876d DT |
1127 | |
1128 | edac_mc_handle_ce(src_mci, page, offset, syndrome, csrow, | |
1129 | channel, EDAC_MOD_STR); | |
1130 | } | |
1131 | } | |
1132 | ||
1433eb99 | 1133 | static int k8_dbam_to_chip_select(struct amd64_pvt *pvt, int cs_mode) |
ddff876d | 1134 | { |
1433eb99 | 1135 | int *dbam_map; |
ddff876d | 1136 | |
1433eb99 BP |
1137 | if (pvt->ext_model >= K8_REV_F) |
1138 | dbam_map = ddr2_dbam; | |
1139 | else if (pvt->ext_model >= K8_REV_D) | |
1140 | dbam_map = ddr2_dbam_revD; | |
1141 | else | |
1142 | dbam_map = ddr2_dbam_revCG; | |
ddff876d | 1143 | |
1433eb99 | 1144 | return dbam_map[cs_mode]; |
ddff876d DT |
1145 | } |
1146 | ||
1afd3c98 DT |
1147 | /* |
1148 | * Get the number of DCT channels in use. | |
1149 | * | |
1150 | * Return: | |
1151 | * number of Memory Channels in operation | |
1152 | * Pass back: | |
1153 | * contents of the DCL0_LOW register | |
1154 | */ | |
1155 | static int f10_early_channel_count(struct amd64_pvt *pvt) | |
1156 | { | |
57a30854 | 1157 | int dbams[] = { DBAM0, DBAM1 }; |
6ba5dcdc | 1158 | int i, j, channels = 0; |
1afd3c98 DT |
1159 | u32 dbam; |
1160 | ||
1afd3c98 DT |
1161 | /* If we are in 128 bit mode, then we are using 2 channels */ |
1162 | if (pvt->dclr0 & F10_WIDTH_128) { | |
1afd3c98 DT |
1163 | channels = 2; |
1164 | return channels; | |
1165 | } | |
1166 | ||
1167 | /* | |
d16149e8 BP |
1168 | * Need to check if in unganged mode: In such, there are 2 channels, |
1169 | * but they are not in 128 bit mode and thus the above 'dclr0' status | |
1170 | * bit will be OFF. | |
1afd3c98 DT |
1171 | * |
1172 | * Need to check DCT0[0] and DCT1[0] to see if only one of them has | |
1173 | * their CSEnable bit on. If so, then SINGLE DIMM case. | |
1174 | */ | |
d16149e8 | 1175 | debugf0("Data width is not 128 bits - need more decoding\n"); |
ddff876d | 1176 | |
1afd3c98 DT |
1177 | /* |
1178 | * Check DRAM Bank Address Mapping values for each DIMM to see if there | |
1179 | * is more than just one DIMM present in unganged mode. Need to check | |
1180 | * both controllers since DIMMs can be placed in either one. | |
1181 | */ | |
57a30854 | 1182 | for (i = 0; i < ARRAY_SIZE(dbams); i++) { |
6ba5dcdc | 1183 | if (amd64_read_pci_cfg(pvt->dram_f2_ctl, dbams[i], &dbam)) |
1afd3c98 DT |
1184 | goto err_reg; |
1185 | ||
57a30854 WW |
1186 | for (j = 0; j < 4; j++) { |
1187 | if (DBAM_DIMM(j, dbam) > 0) { | |
1188 | channels++; | |
1189 | break; | |
1190 | } | |
1191 | } | |
1afd3c98 DT |
1192 | } |
1193 | ||
d16149e8 BP |
1194 | if (channels > 2) |
1195 | channels = 2; | |
1196 | ||
37da0450 | 1197 | debugf0("MCT channel count: %d\n", channels); |
1afd3c98 DT |
1198 | |
1199 | return channels; | |
1200 | ||
1201 | err_reg: | |
1202 | return -1; | |
1203 | ||
1204 | } | |
1205 | ||
1433eb99 | 1206 | static int f10_dbam_to_chip_select(struct amd64_pvt *pvt, int cs_mode) |
1afd3c98 | 1207 | { |
1433eb99 BP |
1208 | int *dbam_map; |
1209 | ||
1210 | if (pvt->dchr0 & DDR3_MODE || pvt->dchr1 & DDR3_MODE) | |
1211 | dbam_map = ddr3_dbam; | |
1212 | else | |
1213 | dbam_map = ddr2_dbam; | |
1214 | ||
1215 | return dbam_map[cs_mode]; | |
1afd3c98 DT |
1216 | } |
1217 | ||
1218 | /* Enable extended configuration access via 0xCF8 feature */ | |
1219 | static void amd64_setup(struct amd64_pvt *pvt) | |
1220 | { | |
1221 | u32 reg; | |
1222 | ||
6ba5dcdc | 1223 | amd64_read_pci_cfg(pvt->misc_f3_ctl, F10_NB_CFG_HIGH, ®); |
1afd3c98 DT |
1224 | |
1225 | pvt->flags.cf8_extcfg = !!(reg & F10_NB_CFG_LOW_ENABLE_EXT_CFG); | |
1226 | reg |= F10_NB_CFG_LOW_ENABLE_EXT_CFG; | |
1227 | pci_write_config_dword(pvt->misc_f3_ctl, F10_NB_CFG_HIGH, reg); | |
1228 | } | |
1229 | ||
1230 | /* Restore the extended configuration access via 0xCF8 feature */ | |
1231 | static void amd64_teardown(struct amd64_pvt *pvt) | |
1232 | { | |
1233 | u32 reg; | |
1234 | ||
6ba5dcdc | 1235 | amd64_read_pci_cfg(pvt->misc_f3_ctl, F10_NB_CFG_HIGH, ®); |
1afd3c98 DT |
1236 | |
1237 | reg &= ~F10_NB_CFG_LOW_ENABLE_EXT_CFG; | |
1238 | if (pvt->flags.cf8_extcfg) | |
1239 | reg |= F10_NB_CFG_LOW_ENABLE_EXT_CFG; | |
1240 | pci_write_config_dword(pvt->misc_f3_ctl, F10_NB_CFG_HIGH, reg); | |
1241 | } | |
1242 | ||
1243 | static u64 f10_get_error_address(struct mem_ctl_info *mci, | |
ef44cc4c | 1244 | struct err_regs *info) |
1afd3c98 DT |
1245 | { |
1246 | return (((u64) (info->nbeah & 0xffff)) << 32) + | |
1247 | (info->nbeal & ~0x01); | |
1248 | } | |
1249 | ||
1250 | /* | |
1251 | * Read the Base and Limit registers for F10 based Memory controllers. Extract | |
1252 | * fields from the 'raw' reg into separate data fields. | |
1253 | * | |
1254 | * Isolates: BASE, LIMIT, IntlvEn, IntlvSel, RW_EN. | |
1255 | */ | |
1256 | static void f10_read_dram_base_limit(struct amd64_pvt *pvt, int dram) | |
1257 | { | |
1258 | u32 high_offset, low_offset, high_base, low_base, high_limit, low_limit; | |
1259 | ||
1260 | low_offset = K8_DRAM_BASE_LOW + (dram << 3); | |
1261 | high_offset = F10_DRAM_BASE_HIGH + (dram << 3); | |
1262 | ||
1263 | /* read the 'raw' DRAM BASE Address register */ | |
6ba5dcdc | 1264 | amd64_read_pci_cfg(pvt->addr_f1_ctl, low_offset, &low_base); |
1afd3c98 DT |
1265 | |
1266 | /* Read from the ECS data register */ | |
6ba5dcdc | 1267 | amd64_read_pci_cfg(pvt->addr_f1_ctl, high_offset, &high_base); |
1afd3c98 DT |
1268 | |
1269 | /* Extract parts into separate data entries */ | |
1270 | pvt->dram_rw_en[dram] = (low_base & 0x3); | |
1271 | ||
1272 | if (pvt->dram_rw_en[dram] == 0) | |
1273 | return; | |
1274 | ||
1275 | pvt->dram_IntlvEn[dram] = (low_base >> 8) & 0x7; | |
1276 | ||
66216a7a | 1277 | pvt->dram_base[dram] = (((u64)high_base & 0x000000FF) << 40) | |
4997811e | 1278 | (((u64)low_base & 0xFFFF0000) << 8); |
1afd3c98 DT |
1279 | |
1280 | low_offset = K8_DRAM_LIMIT_LOW + (dram << 3); | |
1281 | high_offset = F10_DRAM_LIMIT_HIGH + (dram << 3); | |
1282 | ||
1283 | /* read the 'raw' LIMIT registers */ | |
6ba5dcdc | 1284 | amd64_read_pci_cfg(pvt->addr_f1_ctl, low_offset, &low_limit); |
1afd3c98 DT |
1285 | |
1286 | /* Read from the ECS data register for the HIGH portion */ | |
6ba5dcdc | 1287 | amd64_read_pci_cfg(pvt->addr_f1_ctl, high_offset, &high_limit); |
1afd3c98 | 1288 | |
1afd3c98 DT |
1289 | pvt->dram_DstNode[dram] = (low_limit & 0x7); |
1290 | pvt->dram_IntlvSel[dram] = (low_limit >> 8) & 0x7; | |
1291 | ||
1292 | /* | |
1293 | * Extract address values and form a LIMIT address. Limit is the HIGHEST | |
1294 | * memory location of the region, so low 24 bits need to be all ones. | |
1295 | */ | |
66216a7a | 1296 | pvt->dram_limit[dram] = (((u64)high_limit & 0x000000FF) << 40) | |
4997811e | 1297 | (((u64) low_limit & 0xFFFF0000) << 8) | |
66216a7a | 1298 | 0x00FFFFFF; |
1afd3c98 | 1299 | } |
6163b5d4 DT |
1300 | |
1301 | static void f10_read_dram_ctl_register(struct amd64_pvt *pvt) | |
1302 | { | |
6163b5d4 | 1303 | |
6ba5dcdc BP |
1304 | if (!amd64_read_pci_cfg(pvt->dram_f2_ctl, F10_DCTL_SEL_LOW, |
1305 | &pvt->dram_ctl_select_low)) { | |
72381bd5 BP |
1306 | debugf0("F2x110 (DCTL Sel. Low): 0x%08x, " |
1307 | "High range addresses at: 0x%x\n", | |
1308 | pvt->dram_ctl_select_low, | |
1309 | dct_sel_baseaddr(pvt)); | |
1310 | ||
1311 | debugf0(" DCT mode: %s, All DCTs on: %s\n", | |
1312 | (dct_ganging_enabled(pvt) ? "ganged" : "unganged"), | |
1313 | (dct_dram_enabled(pvt) ? "yes" : "no")); | |
1314 | ||
1315 | if (!dct_ganging_enabled(pvt)) | |
1316 | debugf0(" Address range split per DCT: %s\n", | |
1317 | (dct_high_range_enabled(pvt) ? "yes" : "no")); | |
1318 | ||
1319 | debugf0(" DCT data interleave for ECC: %s, " | |
1320 | "DRAM cleared since last warm reset: %s\n", | |
1321 | (dct_data_intlv_enabled(pvt) ? "enabled" : "disabled"), | |
1322 | (dct_memory_cleared(pvt) ? "yes" : "no")); | |
1323 | ||
1324 | debugf0(" DCT channel interleave: %s, " | |
1325 | "DCT interleave bits selector: 0x%x\n", | |
1326 | (dct_interleave_enabled(pvt) ? "enabled" : "disabled"), | |
6163b5d4 DT |
1327 | dct_sel_interleave_addr(pvt)); |
1328 | } | |
1329 | ||
6ba5dcdc BP |
1330 | amd64_read_pci_cfg(pvt->dram_f2_ctl, F10_DCTL_SEL_HIGH, |
1331 | &pvt->dram_ctl_select_high); | |
6163b5d4 DT |
1332 | } |
1333 | ||
f71d0a05 DT |
1334 | /* |
1335 | * determine channel based on the interleaving mode: F10h BKDG, 2.8.9 Memory | |
1336 | * Interleaving Modes. | |
1337 | */ | |
6163b5d4 DT |
1338 | static u32 f10_determine_channel(struct amd64_pvt *pvt, u64 sys_addr, |
1339 | int hi_range_sel, u32 intlv_en) | |
1340 | { | |
1341 | u32 cs, temp, dct_sel_high = (pvt->dram_ctl_select_low >> 1) & 1; | |
1342 | ||
1343 | if (dct_ganging_enabled(pvt)) | |
1344 | cs = 0; | |
1345 | else if (hi_range_sel) | |
1346 | cs = dct_sel_high; | |
1347 | else if (dct_interleave_enabled(pvt)) { | |
f71d0a05 DT |
1348 | /* |
1349 | * see F2x110[DctSelIntLvAddr] - channel interleave mode | |
1350 | */ | |
6163b5d4 DT |
1351 | if (dct_sel_interleave_addr(pvt) == 0) |
1352 | cs = sys_addr >> 6 & 1; | |
1353 | else if ((dct_sel_interleave_addr(pvt) >> 1) & 1) { | |
1354 | temp = hweight_long((u32) ((sys_addr >> 16) & 0x1F)) % 2; | |
1355 | ||
1356 | if (dct_sel_interleave_addr(pvt) & 1) | |
1357 | cs = (sys_addr >> 9 & 1) ^ temp; | |
1358 | else | |
1359 | cs = (sys_addr >> 6 & 1) ^ temp; | |
1360 | } else if (intlv_en & 4) | |
1361 | cs = sys_addr >> 15 & 1; | |
1362 | else if (intlv_en & 2) | |
1363 | cs = sys_addr >> 14 & 1; | |
1364 | else if (intlv_en & 1) | |
1365 | cs = sys_addr >> 13 & 1; | |
1366 | else | |
1367 | cs = sys_addr >> 12 & 1; | |
1368 | } else if (dct_high_range_enabled(pvt) && !dct_ganging_enabled(pvt)) | |
1369 | cs = ~dct_sel_high & 1; | |
1370 | else | |
1371 | cs = 0; | |
1372 | ||
1373 | return cs; | |
1374 | } | |
1375 | ||
1376 | static inline u32 f10_map_intlv_en_to_shift(u32 intlv_en) | |
1377 | { | |
1378 | if (intlv_en == 1) | |
1379 | return 1; | |
1380 | else if (intlv_en == 3) | |
1381 | return 2; | |
1382 | else if (intlv_en == 7) | |
1383 | return 3; | |
1384 | ||
1385 | return 0; | |
1386 | } | |
1387 | ||
f71d0a05 DT |
1388 | /* See F10h BKDG, 2.8.10.2 DctSelBaseOffset Programming */ |
1389 | static inline u64 f10_get_base_addr_offset(u64 sys_addr, int hi_range_sel, | |
6163b5d4 DT |
1390 | u32 dct_sel_base_addr, |
1391 | u64 dct_sel_base_off, | |
f71d0a05 | 1392 | u32 hole_valid, u32 hole_off, |
6163b5d4 DT |
1393 | u64 dram_base) |
1394 | { | |
1395 | u64 chan_off; | |
1396 | ||
1397 | if (hi_range_sel) { | |
9975a5f2 | 1398 | if (!(dct_sel_base_addr & 0xFFFF0000) && |
f71d0a05 | 1399 | hole_valid && (sys_addr >= 0x100000000ULL)) |
6163b5d4 DT |
1400 | chan_off = hole_off << 16; |
1401 | else | |
1402 | chan_off = dct_sel_base_off; | |
1403 | } else { | |
f71d0a05 | 1404 | if (hole_valid && (sys_addr >= 0x100000000ULL)) |
6163b5d4 DT |
1405 | chan_off = hole_off << 16; |
1406 | else | |
1407 | chan_off = dram_base & 0xFFFFF8000000ULL; | |
1408 | } | |
1409 | ||
1410 | return (sys_addr & 0x0000FFFFFFFFFFC0ULL) - | |
1411 | (chan_off & 0x0000FFFFFF800000ULL); | |
1412 | } | |
1413 | ||
1414 | /* Hack for the time being - Can we get this from BIOS?? */ | |
1415 | #define CH0SPARE_RANK 0 | |
1416 | #define CH1SPARE_RANK 1 | |
1417 | ||
1418 | /* | |
1419 | * checks if the csrow passed in is marked as SPARED, if so returns the new | |
1420 | * spare row | |
1421 | */ | |
1422 | static inline int f10_process_possible_spare(int csrow, | |
1423 | u32 cs, struct amd64_pvt *pvt) | |
1424 | { | |
1425 | u32 swap_done; | |
1426 | u32 bad_dram_cs; | |
1427 | ||
1428 | /* Depending on channel, isolate respective SPARING info */ | |
1429 | if (cs) { | |
1430 | swap_done = F10_ONLINE_SPARE_SWAPDONE1(pvt->online_spare); | |
1431 | bad_dram_cs = F10_ONLINE_SPARE_BADDRAM_CS1(pvt->online_spare); | |
1432 | if (swap_done && (csrow == bad_dram_cs)) | |
1433 | csrow = CH1SPARE_RANK; | |
1434 | } else { | |
1435 | swap_done = F10_ONLINE_SPARE_SWAPDONE0(pvt->online_spare); | |
1436 | bad_dram_cs = F10_ONLINE_SPARE_BADDRAM_CS0(pvt->online_spare); | |
1437 | if (swap_done && (csrow == bad_dram_cs)) | |
1438 | csrow = CH0SPARE_RANK; | |
1439 | } | |
1440 | return csrow; | |
1441 | } | |
1442 | ||
1443 | /* | |
1444 | * Iterate over the DRAM DCT "base" and "mask" registers looking for a | |
1445 | * SystemAddr match on the specified 'ChannelSelect' and 'NodeID' | |
1446 | * | |
1447 | * Return: | |
1448 | * -EINVAL: NOT FOUND | |
1449 | * 0..csrow = Chip-Select Row | |
1450 | */ | |
1451 | static int f10_lookup_addr_in_dct(u32 in_addr, u32 nid, u32 cs) | |
1452 | { | |
1453 | struct mem_ctl_info *mci; | |
1454 | struct amd64_pvt *pvt; | |
1455 | u32 cs_base, cs_mask; | |
1456 | int cs_found = -EINVAL; | |
1457 | int csrow; | |
1458 | ||
1459 | mci = mci_lookup[nid]; | |
1460 | if (!mci) | |
1461 | return cs_found; | |
1462 | ||
1463 | pvt = mci->pvt_info; | |
1464 | ||
1465 | debugf1("InputAddr=0x%x channelselect=%d\n", in_addr, cs); | |
1466 | ||
9d858bb1 | 1467 | for (csrow = 0; csrow < pvt->cs_count; csrow++) { |
6163b5d4 DT |
1468 | |
1469 | cs_base = amd64_get_dct_base(pvt, cs, csrow); | |
1470 | if (!(cs_base & K8_DCSB_CS_ENABLE)) | |
1471 | continue; | |
1472 | ||
1473 | /* | |
1474 | * We have an ENABLED CSROW, Isolate just the MASK bits of the | |
1475 | * target: [28:19] and [13:5], which map to [36:27] and [21:13] | |
1476 | * of the actual address. | |
1477 | */ | |
1478 | cs_base &= REV_F_F1Xh_DCSB_BASE_BITS; | |
1479 | ||
1480 | /* | |
1481 | * Get the DCT Mask, and ENABLE the reserved bits: [18:16] and | |
1482 | * [4:0] to become ON. Then mask off bits [28:0] ([36:8]) | |
1483 | */ | |
1484 | cs_mask = amd64_get_dct_mask(pvt, cs, csrow); | |
1485 | ||
1486 | debugf1(" CSROW=%d CSBase=0x%x RAW CSMask=0x%x\n", | |
1487 | csrow, cs_base, cs_mask); | |
1488 | ||
1489 | cs_mask = (cs_mask | 0x0007C01F) & 0x1FFFFFFF; | |
1490 | ||
1491 | debugf1(" Final CSMask=0x%x\n", cs_mask); | |
1492 | debugf1(" (InputAddr & ~CSMask)=0x%x " | |
1493 | "(CSBase & ~CSMask)=0x%x\n", | |
1494 | (in_addr & ~cs_mask), (cs_base & ~cs_mask)); | |
1495 | ||
1496 | if ((in_addr & ~cs_mask) == (cs_base & ~cs_mask)) { | |
1497 | cs_found = f10_process_possible_spare(csrow, cs, pvt); | |
1498 | ||
1499 | debugf1(" MATCH csrow=%d\n", cs_found); | |
1500 | break; | |
1501 | } | |
1502 | } | |
1503 | return cs_found; | |
1504 | } | |
1505 | ||
f71d0a05 DT |
1506 | /* For a given @dram_range, check if @sys_addr falls within it. */ |
1507 | static int f10_match_to_this_node(struct amd64_pvt *pvt, int dram_range, | |
1508 | u64 sys_addr, int *nid, int *chan_sel) | |
1509 | { | |
1510 | int node_id, cs_found = -EINVAL, high_range = 0; | |
1511 | u32 intlv_en, intlv_sel, intlv_shift, hole_off; | |
1512 | u32 hole_valid, tmp, dct_sel_base, channel; | |
1513 | u64 dram_base, chan_addr, dct_sel_base_off; | |
1514 | ||
1515 | dram_base = pvt->dram_base[dram_range]; | |
1516 | intlv_en = pvt->dram_IntlvEn[dram_range]; | |
1517 | ||
1518 | node_id = pvt->dram_DstNode[dram_range]; | |
1519 | intlv_sel = pvt->dram_IntlvSel[dram_range]; | |
1520 | ||
1521 | debugf1("(dram=%d) Base=0x%llx SystemAddr= 0x%llx Limit=0x%llx\n", | |
1522 | dram_range, dram_base, sys_addr, pvt->dram_limit[dram_range]); | |
1523 | ||
1524 | /* | |
1525 | * This assumes that one node's DHAR is the same as all the other | |
1526 | * nodes' DHAR. | |
1527 | */ | |
1528 | hole_off = (pvt->dhar & 0x0000FF80); | |
1529 | hole_valid = (pvt->dhar & 0x1); | |
1530 | dct_sel_base_off = (pvt->dram_ctl_select_high & 0xFFFFFC00) << 16; | |
1531 | ||
1532 | debugf1(" HoleOffset=0x%x HoleValid=0x%x IntlvSel=0x%x\n", | |
1533 | hole_off, hole_valid, intlv_sel); | |
1534 | ||
e726f3c3 | 1535 | if (intlv_en && |
f71d0a05 DT |
1536 | (intlv_sel != ((sys_addr >> 12) & intlv_en))) |
1537 | return -EINVAL; | |
1538 | ||
1539 | dct_sel_base = dct_sel_baseaddr(pvt); | |
1540 | ||
1541 | /* | |
1542 | * check whether addresses >= DctSelBaseAddr[47:27] are to be used to | |
1543 | * select between DCT0 and DCT1. | |
1544 | */ | |
1545 | if (dct_high_range_enabled(pvt) && | |
1546 | !dct_ganging_enabled(pvt) && | |
1547 | ((sys_addr >> 27) >= (dct_sel_base >> 11))) | |
1548 | high_range = 1; | |
1549 | ||
1550 | channel = f10_determine_channel(pvt, sys_addr, high_range, intlv_en); | |
1551 | ||
1552 | chan_addr = f10_get_base_addr_offset(sys_addr, high_range, dct_sel_base, | |
1553 | dct_sel_base_off, hole_valid, | |
1554 | hole_off, dram_base); | |
1555 | ||
1556 | intlv_shift = f10_map_intlv_en_to_shift(intlv_en); | |
1557 | ||
1558 | /* remove Node ID (in case of memory interleaving) */ | |
1559 | tmp = chan_addr & 0xFC0; | |
1560 | ||
1561 | chan_addr = ((chan_addr >> intlv_shift) & 0xFFFFFFFFF000ULL) | tmp; | |
1562 | ||
1563 | /* remove channel interleave and hash */ | |
1564 | if (dct_interleave_enabled(pvt) && | |
1565 | !dct_high_range_enabled(pvt) && | |
1566 | !dct_ganging_enabled(pvt)) { | |
1567 | if (dct_sel_interleave_addr(pvt) != 1) | |
1568 | chan_addr = (chan_addr >> 1) & 0xFFFFFFFFFFFFFFC0ULL; | |
1569 | else { | |
1570 | tmp = chan_addr & 0xFC0; | |
1571 | chan_addr = ((chan_addr & 0xFFFFFFFFFFFFC000ULL) >> 1) | |
1572 | | tmp; | |
1573 | } | |
1574 | } | |
1575 | ||
1576 | debugf1(" (ChannelAddrLong=0x%llx) >> 8 becomes InputAddr=0x%x\n", | |
1577 | chan_addr, (u32)(chan_addr >> 8)); | |
1578 | ||
1579 | cs_found = f10_lookup_addr_in_dct(chan_addr >> 8, node_id, channel); | |
1580 | ||
1581 | if (cs_found >= 0) { | |
1582 | *nid = node_id; | |
1583 | *chan_sel = channel; | |
1584 | } | |
1585 | return cs_found; | |
1586 | } | |
1587 | ||
1588 | static int f10_translate_sysaddr_to_cs(struct amd64_pvt *pvt, u64 sys_addr, | |
1589 | int *node, int *chan_sel) | |
1590 | { | |
1591 | int dram_range, cs_found = -EINVAL; | |
1592 | u64 dram_base, dram_limit; | |
1593 | ||
1594 | for (dram_range = 0; dram_range < DRAM_REG_COUNT; dram_range++) { | |
1595 | ||
1596 | if (!pvt->dram_rw_en[dram_range]) | |
1597 | continue; | |
1598 | ||
1599 | dram_base = pvt->dram_base[dram_range]; | |
1600 | dram_limit = pvt->dram_limit[dram_range]; | |
1601 | ||
1602 | if ((dram_base <= sys_addr) && (sys_addr <= dram_limit)) { | |
1603 | ||
1604 | cs_found = f10_match_to_this_node(pvt, dram_range, | |
1605 | sys_addr, node, | |
1606 | chan_sel); | |
1607 | if (cs_found >= 0) | |
1608 | break; | |
1609 | } | |
1610 | } | |
1611 | return cs_found; | |
1612 | } | |
1613 | ||
1614 | /* | |
bdc30a0c BP |
1615 | * For reference see "2.8.5 Routing DRAM Requests" in F10 BKDG. This code maps |
1616 | * a @sys_addr to NodeID, DCT (channel) and chip select (CSROW). | |
f71d0a05 | 1617 | * |
bdc30a0c BP |
1618 | * The @sys_addr is usually an error address received from the hardware |
1619 | * (MCX_ADDR). | |
f71d0a05 DT |
1620 | */ |
1621 | static void f10_map_sysaddr_to_csrow(struct mem_ctl_info *mci, | |
ad6a32e9 | 1622 | struct err_regs *err_info, |
f71d0a05 DT |
1623 | u64 sys_addr) |
1624 | { | |
1625 | struct amd64_pvt *pvt = mci->pvt_info; | |
1626 | u32 page, offset; | |
f71d0a05 | 1627 | int nid, csrow, chan = 0; |
ad6a32e9 | 1628 | u16 syndrome; |
f71d0a05 DT |
1629 | |
1630 | csrow = f10_translate_sysaddr_to_cs(pvt, sys_addr, &nid, &chan); | |
1631 | ||
bdc30a0c BP |
1632 | if (csrow < 0) { |
1633 | edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR); | |
1634 | return; | |
1635 | } | |
1636 | ||
1637 | error_address_to_page_and_offset(sys_addr, &page, &offset); | |
f71d0a05 | 1638 | |
ad6a32e9 | 1639 | syndrome = extract_syndrome(err_info); |
bdc30a0c BP |
1640 | |
1641 | /* | |
1642 | * We need the syndromes for channel detection only when we're | |
1643 | * ganged. Otherwise @chan should already contain the channel at | |
1644 | * this point. | |
1645 | */ | |
962b70a1 | 1646 | if (dct_ganging_enabled(pvt) && (pvt->nbcfg & K8_NBCFG_CHIPKILL)) |
bdc30a0c | 1647 | chan = get_channel_from_ecc_syndrome(mci, syndrome); |
f71d0a05 | 1648 | |
bdc30a0c BP |
1649 | if (chan >= 0) |
1650 | edac_mc_handle_ce(mci, page, offset, syndrome, csrow, chan, | |
1651 | EDAC_MOD_STR); | |
1652 | else | |
f71d0a05 | 1653 | /* |
bdc30a0c | 1654 | * Channel unknown, report all channels on this CSROW as failed. |
f71d0a05 | 1655 | */ |
bdc30a0c | 1656 | for (chan = 0; chan < mci->csrows[csrow].nr_channels; chan++) |
f71d0a05 | 1657 | edac_mc_handle_ce(mci, page, offset, syndrome, |
bdc30a0c | 1658 | csrow, chan, EDAC_MOD_STR); |
f71d0a05 DT |
1659 | } |
1660 | ||
f71d0a05 | 1661 | /* |
8566c4df | 1662 | * debug routine to display the memory sizes of all logical DIMMs and its |
f71d0a05 DT |
1663 | * CSROWs as well |
1664 | */ | |
8566c4df | 1665 | static void amd64_debug_display_dimm_sizes(int ctrl, struct amd64_pvt *pvt) |
f71d0a05 | 1666 | { |
603adaf6 | 1667 | int dimm, size0, size1, factor = 0; |
f71d0a05 DT |
1668 | u32 dbam; |
1669 | u32 *dcsb; | |
1670 | ||
8566c4df | 1671 | if (boot_cpu_data.x86 == 0xf) { |
603adaf6 BP |
1672 | if (pvt->dclr0 & F10_WIDTH_128) |
1673 | factor = 1; | |
1674 | ||
8566c4df | 1675 | /* K8 families < revF not supported yet */ |
1433eb99 | 1676 | if (pvt->ext_model < K8_REV_F) |
8566c4df BP |
1677 | return; |
1678 | else | |
1679 | WARN_ON(ctrl != 0); | |
1680 | } | |
1681 | ||
1682 | debugf1("F2x%d80 (DRAM Bank Address Mapping): 0x%08x\n", | |
1683 | ctrl, ctrl ? pvt->dbam1 : pvt->dbam0); | |
f71d0a05 DT |
1684 | |
1685 | dbam = ctrl ? pvt->dbam1 : pvt->dbam0; | |
1686 | dcsb = ctrl ? pvt->dcsb1 : pvt->dcsb0; | |
1687 | ||
8566c4df BP |
1688 | edac_printk(KERN_DEBUG, EDAC_MC, "DCT%d chip selects:\n", ctrl); |
1689 | ||
f71d0a05 DT |
1690 | /* Dump memory sizes for DIMM and its CSROWs */ |
1691 | for (dimm = 0; dimm < 4; dimm++) { | |
1692 | ||
1693 | size0 = 0; | |
1694 | if (dcsb[dimm*2] & K8_DCSB_CS_ENABLE) | |
1433eb99 | 1695 | size0 = pvt->ops->dbam_to_cs(pvt, DBAM_DIMM(dimm, dbam)); |
f71d0a05 DT |
1696 | |
1697 | size1 = 0; | |
1698 | if (dcsb[dimm*2 + 1] & K8_DCSB_CS_ENABLE) | |
1433eb99 | 1699 | size1 = pvt->ops->dbam_to_cs(pvt, DBAM_DIMM(dimm, dbam)); |
f71d0a05 | 1700 | |
8566c4df | 1701 | edac_printk(KERN_DEBUG, EDAC_MC, " %d: %5dMB %d: %5dMB\n", |
603adaf6 BP |
1702 | dimm * 2, size0 << factor, |
1703 | dimm * 2 + 1, size1 << factor); | |
f71d0a05 DT |
1704 | } |
1705 | } | |
1706 | ||
4d37607a DT |
1707 | static struct amd64_family_type amd64_family_types[] = { |
1708 | [K8_CPUS] = { | |
0092b20d | 1709 | .ctl_name = "K8", |
4d37607a DT |
1710 | .addr_f1_ctl = PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP, |
1711 | .misc_f3_ctl = PCI_DEVICE_ID_AMD_K8_NB_MISC, | |
1712 | .ops = { | |
1433eb99 BP |
1713 | .early_channel_count = k8_early_channel_count, |
1714 | .get_error_address = k8_get_error_address, | |
1715 | .read_dram_base_limit = k8_read_dram_base_limit, | |
1716 | .map_sysaddr_to_csrow = k8_map_sysaddr_to_csrow, | |
1717 | .dbam_to_cs = k8_dbam_to_chip_select, | |
4d37607a DT |
1718 | } |
1719 | }, | |
1720 | [F10_CPUS] = { | |
0092b20d | 1721 | .ctl_name = "F10h", |
4d37607a DT |
1722 | .addr_f1_ctl = PCI_DEVICE_ID_AMD_10H_NB_MAP, |
1723 | .misc_f3_ctl = PCI_DEVICE_ID_AMD_10H_NB_MISC, | |
1724 | .ops = { | |
1433eb99 BP |
1725 | .early_channel_count = f10_early_channel_count, |
1726 | .get_error_address = f10_get_error_address, | |
1727 | .read_dram_base_limit = f10_read_dram_base_limit, | |
1728 | .read_dram_ctl_register = f10_read_dram_ctl_register, | |
1729 | .map_sysaddr_to_csrow = f10_map_sysaddr_to_csrow, | |
1730 | .dbam_to_cs = f10_dbam_to_chip_select, | |
4d37607a DT |
1731 | } |
1732 | }, | |
4d37607a DT |
1733 | }; |
1734 | ||
1735 | static struct pci_dev *pci_get_related_function(unsigned int vendor, | |
1736 | unsigned int device, | |
1737 | struct pci_dev *related) | |
1738 | { | |
1739 | struct pci_dev *dev = NULL; | |
1740 | ||
1741 | dev = pci_get_device(vendor, device, dev); | |
1742 | while (dev) { | |
1743 | if ((dev->bus->number == related->bus->number) && | |
1744 | (PCI_SLOT(dev->devfn) == PCI_SLOT(related->devfn))) | |
1745 | break; | |
1746 | dev = pci_get_device(vendor, device, dev); | |
1747 | } | |
1748 | ||
1749 | return dev; | |
1750 | } | |
1751 | ||
b1289d6f | 1752 | /* |
bfc04aec BP |
1753 | * These are tables of eigenvectors (one per line) which can be used for the |
1754 | * construction of the syndrome tables. The modified syndrome search algorithm | |
1755 | * uses those to find the symbol in error and thus the DIMM. | |
b1289d6f | 1756 | * |
bfc04aec | 1757 | * Algorithm courtesy of Ross LaFetra from AMD. |
b1289d6f | 1758 | */ |
bfc04aec BP |
1759 | static u16 x4_vectors[] = { |
1760 | 0x2f57, 0x1afe, 0x66cc, 0xdd88, | |
1761 | 0x11eb, 0x3396, 0x7f4c, 0xeac8, | |
1762 | 0x0001, 0x0002, 0x0004, 0x0008, | |
1763 | 0x1013, 0x3032, 0x4044, 0x8088, | |
1764 | 0x106b, 0x30d6, 0x70fc, 0xe0a8, | |
1765 | 0x4857, 0xc4fe, 0x13cc, 0x3288, | |
1766 | 0x1ac5, 0x2f4a, 0x5394, 0xa1e8, | |
1767 | 0x1f39, 0x251e, 0xbd6c, 0x6bd8, | |
1768 | 0x15c1, 0x2a42, 0x89ac, 0x4758, | |
1769 | 0x2b03, 0x1602, 0x4f0c, 0xca08, | |
1770 | 0x1f07, 0x3a0e, 0x6b04, 0xbd08, | |
1771 | 0x8ba7, 0x465e, 0x244c, 0x1cc8, | |
1772 | 0x2b87, 0x164e, 0x642c, 0xdc18, | |
1773 | 0x40b9, 0x80de, 0x1094, 0x20e8, | |
1774 | 0x27db, 0x1eb6, 0x9dac, 0x7b58, | |
1775 | 0x11c1, 0x2242, 0x84ac, 0x4c58, | |
1776 | 0x1be5, 0x2d7a, 0x5e34, 0xa718, | |
1777 | 0x4b39, 0x8d1e, 0x14b4, 0x28d8, | |
1778 | 0x4c97, 0xc87e, 0x11fc, 0x33a8, | |
1779 | 0x8e97, 0x497e, 0x2ffc, 0x1aa8, | |
1780 | 0x16b3, 0x3d62, 0x4f34, 0x8518, | |
1781 | 0x1e2f, 0x391a, 0x5cac, 0xf858, | |
1782 | 0x1d9f, 0x3b7a, 0x572c, 0xfe18, | |
1783 | 0x15f5, 0x2a5a, 0x5264, 0xa3b8, | |
1784 | 0x1dbb, 0x3b66, 0x715c, 0xe3f8, | |
1785 | 0x4397, 0xc27e, 0x17fc, 0x3ea8, | |
1786 | 0x1617, 0x3d3e, 0x6464, 0xb8b8, | |
1787 | 0x23ff, 0x12aa, 0xab6c, 0x56d8, | |
1788 | 0x2dfb, 0x1ba6, 0x913c, 0x7328, | |
1789 | 0x185d, 0x2ca6, 0x7914, 0x9e28, | |
1790 | 0x171b, 0x3e36, 0x7d7c, 0xebe8, | |
1791 | 0x4199, 0x82ee, 0x19f4, 0x2e58, | |
1792 | 0x4807, 0xc40e, 0x130c, 0x3208, | |
1793 | 0x1905, 0x2e0a, 0x5804, 0xac08, | |
1794 | 0x213f, 0x132a, 0xadfc, 0x5ba8, | |
1795 | 0x19a9, 0x2efe, 0xb5cc, 0x6f88, | |
b1289d6f DT |
1796 | }; |
1797 | ||
bfc04aec BP |
1798 | static u16 x8_vectors[] = { |
1799 | 0x0145, 0x028a, 0x2374, 0x43c8, 0xa1f0, 0x0520, 0x0a40, 0x1480, | |
1800 | 0x0211, 0x0422, 0x0844, 0x1088, 0x01b0, 0x44e0, 0x23c0, 0xed80, | |
1801 | 0x1011, 0x0116, 0x022c, 0x0458, 0x08b0, 0x8c60, 0x2740, 0x4e80, | |
1802 | 0x0411, 0x0822, 0x1044, 0x0158, 0x02b0, 0x2360, 0x46c0, 0xab80, | |
1803 | 0x0811, 0x1022, 0x012c, 0x0258, 0x04b0, 0x4660, 0x8cc0, 0x2780, | |
1804 | 0x2071, 0x40e2, 0xa0c4, 0x0108, 0x0210, 0x0420, 0x0840, 0x1080, | |
1805 | 0x4071, 0x80e2, 0x0104, 0x0208, 0x0410, 0x0820, 0x1040, 0x2080, | |
1806 | 0x8071, 0x0102, 0x0204, 0x0408, 0x0810, 0x1020, 0x2040, 0x4080, | |
1807 | 0x019d, 0x03d6, 0x136c, 0x2198, 0x50b0, 0xb2e0, 0x0740, 0x0e80, | |
1808 | 0x0189, 0x03ea, 0x072c, 0x0e58, 0x1cb0, 0x56e0, 0x37c0, 0xf580, | |
1809 | 0x01fd, 0x0376, 0x06ec, 0x0bb8, 0x1110, 0x2220, 0x4440, 0x8880, | |
1810 | 0x0163, 0x02c6, 0x1104, 0x0758, 0x0eb0, 0x2be0, 0x6140, 0xc280, | |
1811 | 0x02fd, 0x01c6, 0x0b5c, 0x1108, 0x07b0, 0x25a0, 0x8840, 0x6180, | |
1812 | 0x0801, 0x012e, 0x025c, 0x04b8, 0x1370, 0x26e0, 0x57c0, 0xb580, | |
1813 | 0x0401, 0x0802, 0x015c, 0x02b8, 0x22b0, 0x13e0, 0x7140, 0xe280, | |
1814 | 0x0201, 0x0402, 0x0804, 0x01b8, 0x11b0, 0x31a0, 0x8040, 0x7180, | |
1815 | 0x0101, 0x0202, 0x0404, 0x0808, 0x1010, 0x2020, 0x4040, 0x8080, | |
1816 | 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080, | |
1817 | 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000, | |
1818 | }; | |
1819 | ||
1820 | static int decode_syndrome(u16 syndrome, u16 *vectors, int num_vecs, | |
ad6a32e9 | 1821 | int v_dim) |
b1289d6f | 1822 | { |
bfc04aec BP |
1823 | unsigned int i, err_sym; |
1824 | ||
1825 | for (err_sym = 0; err_sym < num_vecs / v_dim; err_sym++) { | |
1826 | u16 s = syndrome; | |
1827 | int v_idx = err_sym * v_dim; | |
1828 | int v_end = (err_sym + 1) * v_dim; | |
1829 | ||
1830 | /* walk over all 16 bits of the syndrome */ | |
1831 | for (i = 1; i < (1U << 16); i <<= 1) { | |
1832 | ||
1833 | /* if bit is set in that eigenvector... */ | |
1834 | if (v_idx < v_end && vectors[v_idx] & i) { | |
1835 | u16 ev_comp = vectors[v_idx++]; | |
1836 | ||
1837 | /* ... and bit set in the modified syndrome, */ | |
1838 | if (s & i) { | |
1839 | /* remove it. */ | |
1840 | s ^= ev_comp; | |
4d37607a | 1841 | |
bfc04aec BP |
1842 | if (!s) |
1843 | return err_sym; | |
1844 | } | |
b1289d6f | 1845 | |
bfc04aec BP |
1846 | } else if (s & i) |
1847 | /* can't get to zero, move to next symbol */ | |
1848 | break; | |
1849 | } | |
b1289d6f DT |
1850 | } |
1851 | ||
1852 | debugf0("syndrome(%x) not found\n", syndrome); | |
1853 | return -1; | |
1854 | } | |
d27bf6fa | 1855 | |
bfc04aec BP |
1856 | static int map_err_sym_to_channel(int err_sym, int sym_size) |
1857 | { | |
1858 | if (sym_size == 4) | |
1859 | switch (err_sym) { | |
1860 | case 0x20: | |
1861 | case 0x21: | |
1862 | return 0; | |
1863 | break; | |
1864 | case 0x22: | |
1865 | case 0x23: | |
1866 | return 1; | |
1867 | break; | |
1868 | default: | |
1869 | return err_sym >> 4; | |
1870 | break; | |
1871 | } | |
1872 | /* x8 symbols */ | |
1873 | else | |
1874 | switch (err_sym) { | |
1875 | /* imaginary bits not in a DIMM */ | |
1876 | case 0x10: | |
1877 | WARN(1, KERN_ERR "Invalid error symbol: 0x%x\n", | |
1878 | err_sym); | |
1879 | return -1; | |
1880 | break; | |
1881 | ||
1882 | case 0x11: | |
1883 | return 0; | |
1884 | break; | |
1885 | case 0x12: | |
1886 | return 1; | |
1887 | break; | |
1888 | default: | |
1889 | return err_sym >> 3; | |
1890 | break; | |
1891 | } | |
1892 | return -1; | |
1893 | } | |
1894 | ||
1895 | static int get_channel_from_ecc_syndrome(struct mem_ctl_info *mci, u16 syndrome) | |
1896 | { | |
1897 | struct amd64_pvt *pvt = mci->pvt_info; | |
ad6a32e9 BP |
1898 | int err_sym = -1; |
1899 | ||
1900 | if (pvt->syn_type == 8) | |
1901 | err_sym = decode_syndrome(syndrome, x8_vectors, | |
1902 | ARRAY_SIZE(x8_vectors), | |
1903 | pvt->syn_type); | |
1904 | else if (pvt->syn_type == 4) | |
1905 | err_sym = decode_syndrome(syndrome, x4_vectors, | |
1906 | ARRAY_SIZE(x4_vectors), | |
1907 | pvt->syn_type); | |
1908 | else { | |
1909 | amd64_printk(KERN_WARNING, "%s: Illegal syndrome type: %u\n", | |
1910 | __func__, pvt->syn_type); | |
1911 | return err_sym; | |
bfc04aec | 1912 | } |
ad6a32e9 BP |
1913 | |
1914 | return map_err_sym_to_channel(err_sym, pvt->syn_type); | |
bfc04aec BP |
1915 | } |
1916 | ||
d27bf6fa DT |
1917 | /* |
1918 | * Handle any Correctable Errors (CEs) that have occurred. Check for valid ERROR | |
1919 | * ADDRESS and process. | |
1920 | */ | |
1921 | static void amd64_handle_ce(struct mem_ctl_info *mci, | |
ef44cc4c | 1922 | struct err_regs *info) |
d27bf6fa DT |
1923 | { |
1924 | struct amd64_pvt *pvt = mci->pvt_info; | |
44e9e2ee | 1925 | u64 sys_addr; |
d27bf6fa DT |
1926 | |
1927 | /* Ensure that the Error Address is VALID */ | |
1928 | if ((info->nbsh & K8_NBSH_VALID_ERROR_ADDR) == 0) { | |
1929 | amd64_mc_printk(mci, KERN_ERR, | |
1930 | "HW has no ERROR_ADDRESS available\n"); | |
1931 | edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR); | |
1932 | return; | |
1933 | } | |
1934 | ||
1f6bcee7 | 1935 | sys_addr = pvt->ops->get_error_address(mci, info); |
d27bf6fa DT |
1936 | |
1937 | amd64_mc_printk(mci, KERN_ERR, | |
44e9e2ee | 1938 | "CE ERROR_ADDRESS= 0x%llx\n", sys_addr); |
d27bf6fa | 1939 | |
44e9e2ee | 1940 | pvt->ops->map_sysaddr_to_csrow(mci, info, sys_addr); |
d27bf6fa DT |
1941 | } |
1942 | ||
1943 | /* Handle any Un-correctable Errors (UEs) */ | |
1944 | static void amd64_handle_ue(struct mem_ctl_info *mci, | |
ef44cc4c | 1945 | struct err_regs *info) |
d27bf6fa | 1946 | { |
1f6bcee7 BP |
1947 | struct amd64_pvt *pvt = mci->pvt_info; |
1948 | struct mem_ctl_info *log_mci, *src_mci = NULL; | |
d27bf6fa | 1949 | int csrow; |
44e9e2ee | 1950 | u64 sys_addr; |
d27bf6fa | 1951 | u32 page, offset; |
d27bf6fa DT |
1952 | |
1953 | log_mci = mci; | |
1954 | ||
1955 | if ((info->nbsh & K8_NBSH_VALID_ERROR_ADDR) == 0) { | |
1956 | amd64_mc_printk(mci, KERN_CRIT, | |
1957 | "HW has no ERROR_ADDRESS available\n"); | |
1958 | edac_mc_handle_ue_no_info(log_mci, EDAC_MOD_STR); | |
1959 | return; | |
1960 | } | |
1961 | ||
1f6bcee7 | 1962 | sys_addr = pvt->ops->get_error_address(mci, info); |
d27bf6fa DT |
1963 | |
1964 | /* | |
1965 | * Find out which node the error address belongs to. This may be | |
1966 | * different from the node that detected the error. | |
1967 | */ | |
44e9e2ee | 1968 | src_mci = find_mc_by_sys_addr(mci, sys_addr); |
d27bf6fa DT |
1969 | if (!src_mci) { |
1970 | amd64_mc_printk(mci, KERN_CRIT, | |
1971 | "ERROR ADDRESS (0x%lx) value NOT mapped to a MC\n", | |
44e9e2ee | 1972 | (unsigned long)sys_addr); |
d27bf6fa DT |
1973 | edac_mc_handle_ue_no_info(log_mci, EDAC_MOD_STR); |
1974 | return; | |
1975 | } | |
1976 | ||
1977 | log_mci = src_mci; | |
1978 | ||
44e9e2ee | 1979 | csrow = sys_addr_to_csrow(log_mci, sys_addr); |
d27bf6fa DT |
1980 | if (csrow < 0) { |
1981 | amd64_mc_printk(mci, KERN_CRIT, | |
1982 | "ERROR_ADDRESS (0x%lx) value NOT mapped to 'csrow'\n", | |
44e9e2ee | 1983 | (unsigned long)sys_addr); |
d27bf6fa DT |
1984 | edac_mc_handle_ue_no_info(log_mci, EDAC_MOD_STR); |
1985 | } else { | |
44e9e2ee | 1986 | error_address_to_page_and_offset(sys_addr, &page, &offset); |
d27bf6fa DT |
1987 | edac_mc_handle_ue(log_mci, page, offset, csrow, EDAC_MOD_STR); |
1988 | } | |
1989 | } | |
1990 | ||
549d042d | 1991 | static inline void __amd64_decode_bus_error(struct mem_ctl_info *mci, |
b69b29de | 1992 | struct err_regs *info) |
d27bf6fa | 1993 | { |
b70ef010 BP |
1994 | u32 ec = ERROR_CODE(info->nbsl); |
1995 | u32 xec = EXT_ERROR_CODE(info->nbsl); | |
17adea01 | 1996 | int ecc_type = (info->nbsh >> 13) & 0x3; |
d27bf6fa | 1997 | |
b70ef010 BP |
1998 | /* Bail early out if this was an 'observed' error */ |
1999 | if (PP(ec) == K8_NBSL_PP_OBS) | |
2000 | return; | |
d27bf6fa | 2001 | |
ecaf5606 BP |
2002 | /* Do only ECC errors */ |
2003 | if (xec && xec != F10_NBSL_EXT_ERR_ECC) | |
d27bf6fa | 2004 | return; |
d27bf6fa | 2005 | |
ecaf5606 | 2006 | if (ecc_type == 2) |
d27bf6fa | 2007 | amd64_handle_ce(mci, info); |
ecaf5606 | 2008 | else if (ecc_type == 1) |
d27bf6fa | 2009 | amd64_handle_ue(mci, info); |
d27bf6fa DT |
2010 | } |
2011 | ||
7cfd4a87 | 2012 | void amd64_decode_bus_error(int node_id, struct mce *m, u32 nbcfg) |
d27bf6fa | 2013 | { |
549d042d | 2014 | struct mem_ctl_info *mci = mci_lookup[node_id]; |
7cfd4a87 | 2015 | struct err_regs regs; |
d27bf6fa | 2016 | |
7cfd4a87 BP |
2017 | regs.nbsl = (u32) m->status; |
2018 | regs.nbsh = (u32)(m->status >> 32); | |
2019 | regs.nbeal = (u32) m->addr; | |
2020 | regs.nbeah = (u32)(m->addr >> 32); | |
2021 | regs.nbcfg = nbcfg; | |
2022 | ||
2023 | __amd64_decode_bus_error(mci, ®s); | |
d27bf6fa | 2024 | |
d27bf6fa DT |
2025 | /* |
2026 | * Check the UE bit of the NB status high register, if set generate some | |
2027 | * logs. If NOT a GART error, then process the event as a NO-INFO event. | |
2028 | * If it was a GART error, skip that process. | |
549d042d BP |
2029 | * |
2030 | * FIXME: this should go somewhere else, if at all. | |
d27bf6fa | 2031 | */ |
7cfd4a87 | 2032 | if (regs.nbsh & K8_NBSH_UC_ERR && !report_gart_errors) |
5110dbde | 2033 | edac_mc_handle_ue_no_info(mci, "UE bit is set"); |
549d042d | 2034 | |
d27bf6fa | 2035 | } |
d27bf6fa | 2036 | |
0ec449ee | 2037 | /* |
bbd0c1f6 BP |
2038 | * Use pvt->dram_f2_ctl which contains the F2 CPU PCI device to get the related |
2039 | * F1 (AddrMap) and F3 (Misc) devices. Return negative value on error. | |
0ec449ee | 2040 | */ |
bbd0c1f6 BP |
2041 | static int amd64_reserve_mc_sibling_devices(struct amd64_pvt *pvt, u16 f1_id, |
2042 | u16 f3_id) | |
0ec449ee | 2043 | { |
0ec449ee DT |
2044 | /* Reserve the ADDRESS MAP Device */ |
2045 | pvt->addr_f1_ctl = pci_get_related_function(pvt->dram_f2_ctl->vendor, | |
bbd0c1f6 | 2046 | f1_id, |
0ec449ee DT |
2047 | pvt->dram_f2_ctl); |
2048 | ||
2049 | if (!pvt->addr_f1_ctl) { | |
2050 | amd64_printk(KERN_ERR, "error address map device not found: " | |
2051 | "vendor %x device 0x%x (broken BIOS?)\n", | |
bbd0c1f6 BP |
2052 | PCI_VENDOR_ID_AMD, f1_id); |
2053 | return -ENODEV; | |
0ec449ee DT |
2054 | } |
2055 | ||
2056 | /* Reserve the MISC Device */ | |
2057 | pvt->misc_f3_ctl = pci_get_related_function(pvt->dram_f2_ctl->vendor, | |
bbd0c1f6 | 2058 | f3_id, |
0ec449ee DT |
2059 | pvt->dram_f2_ctl); |
2060 | ||
2061 | if (!pvt->misc_f3_ctl) { | |
2062 | pci_dev_put(pvt->addr_f1_ctl); | |
2063 | pvt->addr_f1_ctl = NULL; | |
2064 | ||
2065 | amd64_printk(KERN_ERR, "error miscellaneous device not found: " | |
2066 | "vendor %x device 0x%x (broken BIOS?)\n", | |
bbd0c1f6 BP |
2067 | PCI_VENDOR_ID_AMD, f3_id); |
2068 | return -ENODEV; | |
0ec449ee DT |
2069 | } |
2070 | ||
2071 | debugf1(" Addr Map device PCI Bus ID:\t%s\n", | |
2072 | pci_name(pvt->addr_f1_ctl)); | |
2073 | debugf1(" DRAM MEM-CTL PCI Bus ID:\t%s\n", | |
2074 | pci_name(pvt->dram_f2_ctl)); | |
2075 | debugf1(" Misc device PCI Bus ID:\t%s\n", | |
2076 | pci_name(pvt->misc_f3_ctl)); | |
2077 | ||
2078 | return 0; | |
2079 | } | |
2080 | ||
2081 | static void amd64_free_mc_sibling_devices(struct amd64_pvt *pvt) | |
2082 | { | |
2083 | pci_dev_put(pvt->addr_f1_ctl); | |
2084 | pci_dev_put(pvt->misc_f3_ctl); | |
2085 | } | |
2086 | ||
2087 | /* | |
2088 | * Retrieve the hardware registers of the memory controller (this includes the | |
2089 | * 'Address Map' and 'Misc' device regs) | |
2090 | */ | |
2091 | static void amd64_read_mc_registers(struct amd64_pvt *pvt) | |
2092 | { | |
2093 | u64 msr_val; | |
ad6a32e9 | 2094 | u32 tmp; |
6ba5dcdc | 2095 | int dram; |
0ec449ee DT |
2096 | |
2097 | /* | |
2098 | * Retrieve TOP_MEM and TOP_MEM2; no masking off of reserved bits since | |
2099 | * those are Read-As-Zero | |
2100 | */ | |
e97f8bb8 BP |
2101 | rdmsrl(MSR_K8_TOP_MEM1, pvt->top_mem); |
2102 | debugf0(" TOP_MEM: 0x%016llx\n", pvt->top_mem); | |
0ec449ee DT |
2103 | |
2104 | /* check first whether TOP_MEM2 is enabled */ | |
2105 | rdmsrl(MSR_K8_SYSCFG, msr_val); | |
2106 | if (msr_val & (1U << 21)) { | |
e97f8bb8 BP |
2107 | rdmsrl(MSR_K8_TOP_MEM2, pvt->top_mem2); |
2108 | debugf0(" TOP_MEM2: 0x%016llx\n", pvt->top_mem2); | |
0ec449ee DT |
2109 | } else |
2110 | debugf0(" TOP_MEM2 disabled.\n"); | |
2111 | ||
6ba5dcdc | 2112 | amd64_read_pci_cfg(pvt->misc_f3_ctl, K8_NBCAP, &pvt->nbcap); |
0ec449ee DT |
2113 | |
2114 | if (pvt->ops->read_dram_ctl_register) | |
2115 | pvt->ops->read_dram_ctl_register(pvt); | |
2116 | ||
2117 | for (dram = 0; dram < DRAM_REG_COUNT; dram++) { | |
2118 | /* | |
2119 | * Call CPU specific READ function to get the DRAM Base and | |
2120 | * Limit values from the DCT. | |
2121 | */ | |
2122 | pvt->ops->read_dram_base_limit(pvt, dram); | |
2123 | ||
2124 | /* | |
2125 | * Only print out debug info on rows with both R and W Enabled. | |
2126 | * Normal processing, compiler should optimize this whole 'if' | |
2127 | * debug output block away. | |
2128 | */ | |
2129 | if (pvt->dram_rw_en[dram] != 0) { | |
e97f8bb8 BP |
2130 | debugf1(" DRAM-BASE[%d]: 0x%016llx " |
2131 | "DRAM-LIMIT: 0x%016llx\n", | |
0ec449ee | 2132 | dram, |
e97f8bb8 BP |
2133 | pvt->dram_base[dram], |
2134 | pvt->dram_limit[dram]); | |
2135 | ||
0ec449ee DT |
2136 | debugf1(" IntlvEn=%s %s %s " |
2137 | "IntlvSel=%d DstNode=%d\n", | |
2138 | pvt->dram_IntlvEn[dram] ? | |
2139 | "Enabled" : "Disabled", | |
2140 | (pvt->dram_rw_en[dram] & 0x2) ? "W" : "!W", | |
2141 | (pvt->dram_rw_en[dram] & 0x1) ? "R" : "!R", | |
2142 | pvt->dram_IntlvSel[dram], | |
2143 | pvt->dram_DstNode[dram]); | |
2144 | } | |
2145 | } | |
2146 | ||
2147 | amd64_read_dct_base_mask(pvt); | |
2148 | ||
6ba5dcdc | 2149 | amd64_read_pci_cfg(pvt->addr_f1_ctl, K8_DHAR, &pvt->dhar); |
0ec449ee DT |
2150 | amd64_read_dbam_reg(pvt); |
2151 | ||
6ba5dcdc BP |
2152 | amd64_read_pci_cfg(pvt->misc_f3_ctl, |
2153 | F10_ONLINE_SPARE, &pvt->online_spare); | |
0ec449ee | 2154 | |
6ba5dcdc BP |
2155 | amd64_read_pci_cfg(pvt->dram_f2_ctl, F10_DCLR_0, &pvt->dclr0); |
2156 | amd64_read_pci_cfg(pvt->dram_f2_ctl, F10_DCHR_0, &pvt->dchr0); | |
0ec449ee | 2157 | |
ad6a32e9 BP |
2158 | if (boot_cpu_data.x86 >= 0x10) { |
2159 | if (!dct_ganging_enabled(pvt)) { | |
2160 | amd64_read_pci_cfg(pvt->dram_f2_ctl, F10_DCLR_1, &pvt->dclr1); | |
2161 | amd64_read_pci_cfg(pvt->dram_f2_ctl, F10_DCHR_1, &pvt->dchr1); | |
2162 | } | |
2163 | amd64_read_pci_cfg(pvt->misc_f3_ctl, EXT_NB_MCA_CFG, &tmp); | |
0ec449ee | 2164 | } |
ad6a32e9 BP |
2165 | |
2166 | if (boot_cpu_data.x86 == 0x10 && | |
2167 | boot_cpu_data.x86_model > 7 && | |
2168 | /* F3x180[EccSymbolSize]=1 => x8 symbols */ | |
2169 | tmp & BIT(25)) | |
2170 | pvt->syn_type = 8; | |
2171 | else | |
2172 | pvt->syn_type = 4; | |
2173 | ||
0ec449ee | 2174 | amd64_dump_misc_regs(pvt); |
0ec449ee DT |
2175 | } |
2176 | ||
2177 | /* | |
2178 | * NOTE: CPU Revision Dependent code | |
2179 | * | |
2180 | * Input: | |
9d858bb1 | 2181 | * @csrow_nr ChipSelect Row Number (0..pvt->cs_count-1) |
0ec449ee DT |
2182 | * k8 private pointer to --> |
2183 | * DRAM Bank Address mapping register | |
2184 | * node_id | |
2185 | * DCL register where dual_channel_active is | |
2186 | * | |
2187 | * The DBAM register consists of 4 sets of 4 bits each definitions: | |
2188 | * | |
2189 | * Bits: CSROWs | |
2190 | * 0-3 CSROWs 0 and 1 | |
2191 | * 4-7 CSROWs 2 and 3 | |
2192 | * 8-11 CSROWs 4 and 5 | |
2193 | * 12-15 CSROWs 6 and 7 | |
2194 | * | |
2195 | * Values range from: 0 to 15 | |
2196 | * The meaning of the values depends on CPU revision and dual-channel state, | |
2197 | * see relevant BKDG more info. | |
2198 | * | |
2199 | * The memory controller provides for total of only 8 CSROWs in its current | |
2200 | * architecture. Each "pair" of CSROWs normally represents just one DIMM in | |
2201 | * single channel or two (2) DIMMs in dual channel mode. | |
2202 | * | |
2203 | * The following code logic collapses the various tables for CSROW based on CPU | |
2204 | * revision. | |
2205 | * | |
2206 | * Returns: | |
2207 | * The number of PAGE_SIZE pages on the specified CSROW number it | |
2208 | * encompasses | |
2209 | * | |
2210 | */ | |
2211 | static u32 amd64_csrow_nr_pages(int csrow_nr, struct amd64_pvt *pvt) | |
2212 | { | |
1433eb99 | 2213 | u32 cs_mode, nr_pages; |
0ec449ee DT |
2214 | |
2215 | /* | |
2216 | * The math on this doesn't look right on the surface because x/2*4 can | |
2217 | * be simplified to x*2 but this expression makes use of the fact that | |
2218 | * it is integral math where 1/2=0. This intermediate value becomes the | |
2219 | * number of bits to shift the DBAM register to extract the proper CSROW | |
2220 | * field. | |
2221 | */ | |
1433eb99 | 2222 | cs_mode = (pvt->dbam0 >> ((csrow_nr / 2) * 4)) & 0xF; |
0ec449ee | 2223 | |
1433eb99 | 2224 | nr_pages = pvt->ops->dbam_to_cs(pvt, cs_mode) << (20 - PAGE_SHIFT); |
0ec449ee DT |
2225 | |
2226 | /* | |
2227 | * If dual channel then double the memory size of single channel. | |
2228 | * Channel count is 1 or 2 | |
2229 | */ | |
2230 | nr_pages <<= (pvt->channel_count - 1); | |
2231 | ||
1433eb99 | 2232 | debugf0(" (csrow=%d) DBAM map index= %d\n", csrow_nr, cs_mode); |
0ec449ee DT |
2233 | debugf0(" nr_pages= %u channel-count = %d\n", |
2234 | nr_pages, pvt->channel_count); | |
2235 | ||
2236 | return nr_pages; | |
2237 | } | |
2238 | ||
2239 | /* | |
2240 | * Initialize the array of csrow attribute instances, based on the values | |
2241 | * from pci config hardware registers. | |
2242 | */ | |
2243 | static int amd64_init_csrows(struct mem_ctl_info *mci) | |
2244 | { | |
2245 | struct csrow_info *csrow; | |
2246 | struct amd64_pvt *pvt; | |
2247 | u64 input_addr_min, input_addr_max, sys_addr; | |
6ba5dcdc | 2248 | int i, empty = 1; |
0ec449ee DT |
2249 | |
2250 | pvt = mci->pvt_info; | |
2251 | ||
6ba5dcdc | 2252 | amd64_read_pci_cfg(pvt->misc_f3_ctl, K8_NBCFG, &pvt->nbcfg); |
0ec449ee DT |
2253 | |
2254 | debugf0("NBCFG= 0x%x CHIPKILL= %s DRAM ECC= %s\n", pvt->nbcfg, | |
2255 | (pvt->nbcfg & K8_NBCFG_CHIPKILL) ? "Enabled" : "Disabled", | |
2256 | (pvt->nbcfg & K8_NBCFG_ECC_ENABLE) ? "Enabled" : "Disabled" | |
2257 | ); | |
2258 | ||
9d858bb1 | 2259 | for (i = 0; i < pvt->cs_count; i++) { |
0ec449ee DT |
2260 | csrow = &mci->csrows[i]; |
2261 | ||
2262 | if ((pvt->dcsb0[i] & K8_DCSB_CS_ENABLE) == 0) { | |
2263 | debugf1("----CSROW %d EMPTY for node %d\n", i, | |
2264 | pvt->mc_node_id); | |
2265 | continue; | |
2266 | } | |
2267 | ||
2268 | debugf1("----CSROW %d VALID for MC node %d\n", | |
2269 | i, pvt->mc_node_id); | |
2270 | ||
2271 | empty = 0; | |
2272 | csrow->nr_pages = amd64_csrow_nr_pages(i, pvt); | |
2273 | find_csrow_limits(mci, i, &input_addr_min, &input_addr_max); | |
2274 | sys_addr = input_addr_to_sys_addr(mci, input_addr_min); | |
2275 | csrow->first_page = (u32) (sys_addr >> PAGE_SHIFT); | |
2276 | sys_addr = input_addr_to_sys_addr(mci, input_addr_max); | |
2277 | csrow->last_page = (u32) (sys_addr >> PAGE_SHIFT); | |
2278 | csrow->page_mask = ~mask_from_dct_mask(pvt, i); | |
2279 | /* 8 bytes of resolution */ | |
2280 | ||
2281 | csrow->mtype = amd64_determine_memory_type(pvt); | |
2282 | ||
2283 | debugf1(" for MC node %d csrow %d:\n", pvt->mc_node_id, i); | |
2284 | debugf1(" input_addr_min: 0x%lx input_addr_max: 0x%lx\n", | |
2285 | (unsigned long)input_addr_min, | |
2286 | (unsigned long)input_addr_max); | |
2287 | debugf1(" sys_addr: 0x%lx page_mask: 0x%lx\n", | |
2288 | (unsigned long)sys_addr, csrow->page_mask); | |
2289 | debugf1(" nr_pages: %u first_page: 0x%lx " | |
2290 | "last_page: 0x%lx\n", | |
2291 | (unsigned)csrow->nr_pages, | |
2292 | csrow->first_page, csrow->last_page); | |
2293 | ||
2294 | /* | |
2295 | * determine whether CHIPKILL or JUST ECC or NO ECC is operating | |
2296 | */ | |
2297 | if (pvt->nbcfg & K8_NBCFG_ECC_ENABLE) | |
2298 | csrow->edac_mode = | |
2299 | (pvt->nbcfg & K8_NBCFG_CHIPKILL) ? | |
2300 | EDAC_S4ECD4ED : EDAC_SECDED; | |
2301 | else | |
2302 | csrow->edac_mode = EDAC_NONE; | |
2303 | } | |
2304 | ||
2305 | return empty; | |
2306 | } | |
d27bf6fa | 2307 | |
f6d6ae96 BP |
2308 | /* get all cores on this DCT */ |
2309 | static void get_cpus_on_this_dct_cpumask(struct cpumask *mask, int nid) | |
2310 | { | |
2311 | int cpu; | |
2312 | ||
2313 | for_each_online_cpu(cpu) | |
2314 | if (amd_get_nb_id(cpu) == nid) | |
2315 | cpumask_set_cpu(cpu, mask); | |
2316 | } | |
2317 | ||
2318 | /* check MCG_CTL on all the cpus on this node */ | |
2319 | static bool amd64_nb_mce_bank_enabled_on_node(int nid) | |
2320 | { | |
2321 | cpumask_var_t mask; | |
50542251 | 2322 | int cpu, nbe; |
f6d6ae96 BP |
2323 | bool ret = false; |
2324 | ||
2325 | if (!zalloc_cpumask_var(&mask, GFP_KERNEL)) { | |
2326 | amd64_printk(KERN_WARNING, "%s: error allocating mask\n", | |
2327 | __func__); | |
2328 | return false; | |
2329 | } | |
2330 | ||
2331 | get_cpus_on_this_dct_cpumask(mask, nid); | |
2332 | ||
f6d6ae96 BP |
2333 | rdmsr_on_cpus(mask, MSR_IA32_MCG_CTL, msrs); |
2334 | ||
2335 | for_each_cpu(cpu, mask) { | |
50542251 BP |
2336 | struct msr *reg = per_cpu_ptr(msrs, cpu); |
2337 | nbe = reg->l & K8_MSR_MCGCTL_NBE; | |
f6d6ae96 BP |
2338 | |
2339 | debugf0("core: %u, MCG_CTL: 0x%llx, NB MSR is %s\n", | |
50542251 | 2340 | cpu, reg->q, |
f6d6ae96 BP |
2341 | (nbe ? "enabled" : "disabled")); |
2342 | ||
2343 | if (!nbe) | |
2344 | goto out; | |
f6d6ae96 BP |
2345 | } |
2346 | ret = true; | |
2347 | ||
2348 | out: | |
f6d6ae96 BP |
2349 | free_cpumask_var(mask); |
2350 | return ret; | |
2351 | } | |
2352 | ||
2353 | static int amd64_toggle_ecc_err_reporting(struct amd64_pvt *pvt, bool on) | |
2354 | { | |
2355 | cpumask_var_t cmask; | |
50542251 | 2356 | int cpu; |
f6d6ae96 BP |
2357 | |
2358 | if (!zalloc_cpumask_var(&cmask, GFP_KERNEL)) { | |
2359 | amd64_printk(KERN_WARNING, "%s: error allocating mask\n", | |
2360 | __func__); | |
2361 | return false; | |
2362 | } | |
2363 | ||
2364 | get_cpus_on_this_dct_cpumask(cmask, pvt->mc_node_id); | |
2365 | ||
f6d6ae96 BP |
2366 | rdmsr_on_cpus(cmask, MSR_IA32_MCG_CTL, msrs); |
2367 | ||
2368 | for_each_cpu(cpu, cmask) { | |
2369 | ||
50542251 BP |
2370 | struct msr *reg = per_cpu_ptr(msrs, cpu); |
2371 | ||
f6d6ae96 | 2372 | if (on) { |
50542251 | 2373 | if (reg->l & K8_MSR_MCGCTL_NBE) |
d95cf4de | 2374 | pvt->flags.nb_mce_enable = 1; |
f6d6ae96 | 2375 | |
50542251 | 2376 | reg->l |= K8_MSR_MCGCTL_NBE; |
f6d6ae96 BP |
2377 | } else { |
2378 | /* | |
d95cf4de | 2379 | * Turn off NB MCE reporting only when it was off before |
f6d6ae96 | 2380 | */ |
d95cf4de | 2381 | if (!pvt->flags.nb_mce_enable) |
50542251 | 2382 | reg->l &= ~K8_MSR_MCGCTL_NBE; |
f6d6ae96 | 2383 | } |
f6d6ae96 BP |
2384 | } |
2385 | wrmsr_on_cpus(cmask, MSR_IA32_MCG_CTL, msrs); | |
2386 | ||
f6d6ae96 BP |
2387 | free_cpumask_var(cmask); |
2388 | ||
2389 | return 0; | |
2390 | } | |
2391 | ||
f9431992 DT |
2392 | static void amd64_enable_ecc_error_reporting(struct mem_ctl_info *mci) |
2393 | { | |
2394 | struct amd64_pvt *pvt = mci->pvt_info; | |
f6d6ae96 | 2395 | u32 value, mask = K8_NBCTL_CECCEn | K8_NBCTL_UECCEn; |
f9431992 | 2396 | |
6ba5dcdc | 2397 | amd64_read_pci_cfg(pvt->misc_f3_ctl, K8_NBCTL, &value); |
f9431992 DT |
2398 | |
2399 | /* turn on UECCn and CECCEn bits */ | |
2400 | pvt->old_nbctl = value & mask; | |
2401 | pvt->nbctl_mcgctl_saved = 1; | |
2402 | ||
2403 | value |= mask; | |
2404 | pci_write_config_dword(pvt->misc_f3_ctl, K8_NBCTL, value); | |
2405 | ||
f6d6ae96 BP |
2406 | if (amd64_toggle_ecc_err_reporting(pvt, ON)) |
2407 | amd64_printk(KERN_WARNING, "Error enabling ECC reporting over " | |
2408 | "MCGCTL!\n"); | |
f9431992 | 2409 | |
6ba5dcdc | 2410 | amd64_read_pci_cfg(pvt->misc_f3_ctl, K8_NBCFG, &value); |
f9431992 DT |
2411 | |
2412 | debugf0("NBCFG(1)= 0x%x CHIPKILL= %s ECC_ENABLE= %s\n", value, | |
2413 | (value & K8_NBCFG_CHIPKILL) ? "Enabled" : "Disabled", | |
2414 | (value & K8_NBCFG_ECC_ENABLE) ? "Enabled" : "Disabled"); | |
2415 | ||
2416 | if (!(value & K8_NBCFG_ECC_ENABLE)) { | |
2417 | amd64_printk(KERN_WARNING, | |
2418 | "This node reports that DRAM ECC is " | |
2419 | "currently Disabled; ENABLING now\n"); | |
2420 | ||
d95cf4de BP |
2421 | pvt->flags.nb_ecc_prev = 0; |
2422 | ||
f9431992 DT |
2423 | /* Attempt to turn on DRAM ECC Enable */ |
2424 | value |= K8_NBCFG_ECC_ENABLE; | |
2425 | pci_write_config_dword(pvt->misc_f3_ctl, K8_NBCFG, value); | |
2426 | ||
6ba5dcdc | 2427 | amd64_read_pci_cfg(pvt->misc_f3_ctl, K8_NBCFG, &value); |
f9431992 DT |
2428 | |
2429 | if (!(value & K8_NBCFG_ECC_ENABLE)) { | |
2430 | amd64_printk(KERN_WARNING, | |
2431 | "Hardware rejects Enabling DRAM ECC checking\n" | |
2432 | "Check memory DIMM configuration\n"); | |
2433 | } else { | |
2434 | amd64_printk(KERN_DEBUG, | |
2435 | "Hardware accepted DRAM ECC Enable\n"); | |
2436 | } | |
d95cf4de BP |
2437 | } else { |
2438 | pvt->flags.nb_ecc_prev = 1; | |
f9431992 | 2439 | } |
d95cf4de | 2440 | |
f9431992 DT |
2441 | debugf0("NBCFG(2)= 0x%x CHIPKILL= %s ECC_ENABLE= %s\n", value, |
2442 | (value & K8_NBCFG_CHIPKILL) ? "Enabled" : "Disabled", | |
2443 | (value & K8_NBCFG_ECC_ENABLE) ? "Enabled" : "Disabled"); | |
2444 | ||
2445 | pvt->ctl_error_info.nbcfg = value; | |
2446 | } | |
2447 | ||
2448 | static void amd64_restore_ecc_error_reporting(struct amd64_pvt *pvt) | |
2449 | { | |
f6d6ae96 | 2450 | u32 value, mask = K8_NBCTL_CECCEn | K8_NBCTL_UECCEn; |
f9431992 DT |
2451 | |
2452 | if (!pvt->nbctl_mcgctl_saved) | |
2453 | return; | |
2454 | ||
6ba5dcdc | 2455 | amd64_read_pci_cfg(pvt->misc_f3_ctl, K8_NBCTL, &value); |
f9431992 DT |
2456 | value &= ~mask; |
2457 | value |= pvt->old_nbctl; | |
2458 | ||
f9431992 DT |
2459 | pci_write_config_dword(pvt->misc_f3_ctl, K8_NBCTL, value); |
2460 | ||
d95cf4de BP |
2461 | /* restore previous BIOS DRAM ECC "off" setting which we force-enabled */ |
2462 | if (!pvt->flags.nb_ecc_prev) { | |
2463 | amd64_read_pci_cfg(pvt->misc_f3_ctl, K8_NBCFG, &value); | |
2464 | value &= ~K8_NBCFG_ECC_ENABLE; | |
2465 | pci_write_config_dword(pvt->misc_f3_ctl, K8_NBCFG, value); | |
2466 | } | |
2467 | ||
2468 | /* restore the NB Enable MCGCTL bit */ | |
f6d6ae96 | 2469 | if (amd64_toggle_ecc_err_reporting(pvt, OFF)) |
d95cf4de | 2470 | amd64_printk(KERN_WARNING, "Error restoring NB MCGCTL settings!\n"); |
f9431992 DT |
2471 | } |
2472 | ||
2473 | /* | |
2474 | * EDAC requires that the BIOS have ECC enabled before taking over the | |
2475 | * processing of ECC errors. This is because the BIOS can properly initialize | |
2476 | * the memory system completely. A command line option allows to force-enable | |
2477 | * hardware ECC later in amd64_enable_ecc_error_reporting(). | |
2478 | */ | |
cab4d277 BP |
2479 | static const char *ecc_msg = |
2480 | "ECC disabled in the BIOS or no ECC capability, module will not load.\n" | |
2481 | " Either enable ECC checking or force module loading by setting " | |
2482 | "'ecc_enable_override'.\n" | |
2483 | " (Note that use of the override may cause unknown side effects.)\n"; | |
be3468e8 | 2484 | |
f9431992 DT |
2485 | static int amd64_check_ecc_enabled(struct amd64_pvt *pvt) |
2486 | { | |
2487 | u32 value; | |
06724535 BP |
2488 | u8 ecc_enabled = 0; |
2489 | bool nb_mce_en = false; | |
f9431992 | 2490 | |
6ba5dcdc | 2491 | amd64_read_pci_cfg(pvt->misc_f3_ctl, K8_NBCFG, &value); |
f9431992 DT |
2492 | |
2493 | ecc_enabled = !!(value & K8_NBCFG_ECC_ENABLE); | |
be3468e8 | 2494 | if (!ecc_enabled) |
cab4d277 | 2495 | amd64_printk(KERN_NOTICE, "This node reports that Memory ECC " |
be3468e8 BP |
2496 | "is currently disabled, set F3x%x[22] (%s).\n", |
2497 | K8_NBCFG, pci_name(pvt->misc_f3_ctl)); | |
2498 | else | |
2499 | amd64_printk(KERN_INFO, "ECC is enabled by BIOS.\n"); | |
f9431992 | 2500 | |
06724535 BP |
2501 | nb_mce_en = amd64_nb_mce_bank_enabled_on_node(pvt->mc_node_id); |
2502 | if (!nb_mce_en) | |
cab4d277 | 2503 | amd64_printk(KERN_NOTICE, "NB MCE bank disabled, set MSR " |
be3468e8 BP |
2504 | "0x%08x[4] on node %d to enable.\n", |
2505 | MSR_IA32_MCG_CTL, pvt->mc_node_id); | |
f9431992 | 2506 | |
06724535 | 2507 | if (!ecc_enabled || !nb_mce_en) { |
f9431992 | 2508 | if (!ecc_enable_override) { |
cab4d277 | 2509 | amd64_printk(KERN_NOTICE, "%s", ecc_msg); |
be3468e8 | 2510 | return -ENODEV; |
d95cf4de BP |
2511 | } else { |
2512 | amd64_printk(KERN_WARNING, "Forcing ECC checking on!\n"); | |
be3468e8 | 2513 | } |
43f5e687 | 2514 | } |
f9431992 | 2515 | |
be3468e8 | 2516 | return 0; |
f9431992 DT |
2517 | } |
2518 | ||
7d6034d3 DT |
2519 | struct mcidev_sysfs_attribute sysfs_attrs[ARRAY_SIZE(amd64_dbg_attrs) + |
2520 | ARRAY_SIZE(amd64_inj_attrs) + | |
2521 | 1]; | |
2522 | ||
2523 | struct mcidev_sysfs_attribute terminator = { .attr = { .name = NULL } }; | |
2524 | ||
2525 | static void amd64_set_mc_sysfs_attributes(struct mem_ctl_info *mci) | |
2526 | { | |
2527 | unsigned int i = 0, j = 0; | |
2528 | ||
2529 | for (; i < ARRAY_SIZE(amd64_dbg_attrs); i++) | |
2530 | sysfs_attrs[i] = amd64_dbg_attrs[i]; | |
2531 | ||
2532 | for (j = 0; j < ARRAY_SIZE(amd64_inj_attrs); j++, i++) | |
2533 | sysfs_attrs[i] = amd64_inj_attrs[j]; | |
2534 | ||
2535 | sysfs_attrs[i] = terminator; | |
2536 | ||
2537 | mci->mc_driver_sysfs_attributes = sysfs_attrs; | |
2538 | } | |
2539 | ||
2540 | static void amd64_setup_mci_misc_attributes(struct mem_ctl_info *mci) | |
2541 | { | |
2542 | struct amd64_pvt *pvt = mci->pvt_info; | |
2543 | ||
2544 | mci->mtype_cap = MEM_FLAG_DDR2 | MEM_FLAG_RDDR2; | |
2545 | mci->edac_ctl_cap = EDAC_FLAG_NONE; | |
7d6034d3 DT |
2546 | |
2547 | if (pvt->nbcap & K8_NBCAP_SECDED) | |
2548 | mci->edac_ctl_cap |= EDAC_FLAG_SECDED; | |
2549 | ||
2550 | if (pvt->nbcap & K8_NBCAP_CHIPKILL) | |
2551 | mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED; | |
2552 | ||
2553 | mci->edac_cap = amd64_determine_edac_cap(pvt); | |
2554 | mci->mod_name = EDAC_MOD_STR; | |
2555 | mci->mod_ver = EDAC_AMD64_VERSION; | |
0092b20d | 2556 | mci->ctl_name = pvt->ctl_name; |
7d6034d3 DT |
2557 | mci->dev_name = pci_name(pvt->dram_f2_ctl); |
2558 | mci->ctl_page_to_phys = NULL; | |
2559 | ||
7d6034d3 DT |
2560 | /* memory scrubber interface */ |
2561 | mci->set_sdram_scrub_rate = amd64_set_scrub_rate; | |
2562 | mci->get_sdram_scrub_rate = amd64_get_scrub_rate; | |
2563 | } | |
2564 | ||
0092b20d BP |
2565 | /* |
2566 | * returns a pointer to the family descriptor on success, NULL otherwise. | |
2567 | */ | |
2568 | static struct amd64_family_type *amd64_per_family_init(struct amd64_pvt *pvt) | |
395ae783 | 2569 | { |
0092b20d BP |
2570 | u8 fam = boot_cpu_data.x86; |
2571 | struct amd64_family_type *fam_type = NULL; | |
2572 | ||
2573 | switch (fam) { | |
395ae783 | 2574 | case 0xf: |
0092b20d | 2575 | fam_type = &amd64_family_types[K8_CPUS]; |
b8cfa02f | 2576 | pvt->ops = &amd64_family_types[K8_CPUS].ops; |
0092b20d BP |
2577 | pvt->ctl_name = fam_type->ctl_name; |
2578 | pvt->min_scrubrate = K8_MIN_SCRUB_RATE_BITS; | |
395ae783 BP |
2579 | break; |
2580 | case 0x10: | |
0092b20d | 2581 | fam_type = &amd64_family_types[F10_CPUS]; |
b8cfa02f | 2582 | pvt->ops = &amd64_family_types[F10_CPUS].ops; |
0092b20d BP |
2583 | pvt->ctl_name = fam_type->ctl_name; |
2584 | pvt->min_scrubrate = F10_MIN_SCRUB_RATE_BITS; | |
395ae783 BP |
2585 | break; |
2586 | ||
2587 | default: | |
2588 | amd64_printk(KERN_ERR, "Unsupported family!\n"); | |
0092b20d | 2589 | return NULL; |
395ae783 | 2590 | } |
0092b20d | 2591 | |
b8cfa02f BP |
2592 | pvt->ext_model = boot_cpu_data.x86_model >> 4; |
2593 | ||
0092b20d BP |
2594 | amd64_printk(KERN_INFO, "%s %s detected.\n", pvt->ctl_name, |
2595 | (fam == 0xf ? | |
2596 | (pvt->ext_model >= K8_REV_F ? "revF or later" | |
2597 | : "revE or earlier") | |
2598 | : "")); | |
2599 | return fam_type; | |
395ae783 BP |
2600 | } |
2601 | ||
7d6034d3 DT |
2602 | /* |
2603 | * Init stuff for this DRAM Controller device. | |
2604 | * | |
2605 | * Due to a hardware feature on Fam10h CPUs, the Enable Extended Configuration | |
2606 | * Space feature MUST be enabled on ALL Processors prior to actually reading | |
2607 | * from the ECS registers. Since the loading of the module can occur on any | |
2608 | * 'core', and cores don't 'see' all the other processors ECS data when the | |
2609 | * others are NOT enabled. Our solution is to first enable ECS access in this | |
2610 | * routine on all processors, gather some data in a amd64_pvt structure and | |
2611 | * later come back in a finish-setup function to perform that final | |
2612 | * initialization. See also amd64_init_2nd_stage() for that. | |
2613 | */ | |
b8cfa02f | 2614 | static int amd64_probe_one_instance(struct pci_dev *dram_f2_ctl) |
7d6034d3 DT |
2615 | { |
2616 | struct amd64_pvt *pvt = NULL; | |
0092b20d | 2617 | struct amd64_family_type *fam_type = NULL; |
7d6034d3 DT |
2618 | int err = 0, ret; |
2619 | ||
2620 | ret = -ENOMEM; | |
2621 | pvt = kzalloc(sizeof(struct amd64_pvt), GFP_KERNEL); | |
2622 | if (!pvt) | |
2623 | goto err_exit; | |
2624 | ||
b8cfa02f BP |
2625 | pvt->mc_node_id = get_node_id(dram_f2_ctl); |
2626 | pvt->dram_f2_ctl = dram_f2_ctl; | |
7d6034d3 | 2627 | |
395ae783 | 2628 | ret = -EINVAL; |
0092b20d BP |
2629 | fam_type = amd64_per_family_init(pvt); |
2630 | if (!fam_type) | |
395ae783 BP |
2631 | goto err_free; |
2632 | ||
7d6034d3 | 2633 | ret = -ENODEV; |
bbd0c1f6 BP |
2634 | err = amd64_reserve_mc_sibling_devices(pvt, fam_type->addr_f1_ctl, |
2635 | fam_type->misc_f3_ctl); | |
7d6034d3 DT |
2636 | if (err) |
2637 | goto err_free; | |
2638 | ||
2639 | ret = -EINVAL; | |
2640 | err = amd64_check_ecc_enabled(pvt); | |
2641 | if (err) | |
2642 | goto err_put; | |
2643 | ||
2644 | /* | |
2645 | * Key operation here: setup of HW prior to performing ops on it. Some | |
2646 | * setup is required to access ECS data. After this is performed, the | |
2647 | * 'teardown' function must be called upon error and normal exit paths. | |
2648 | */ | |
2649 | if (boot_cpu_data.x86 >= 0x10) | |
2650 | amd64_setup(pvt); | |
2651 | ||
2652 | /* | |
2653 | * Save the pointer to the private data for use in 2nd initialization | |
2654 | * stage | |
2655 | */ | |
2656 | pvt_lookup[pvt->mc_node_id] = pvt; | |
2657 | ||
2658 | return 0; | |
2659 | ||
2660 | err_put: | |
2661 | amd64_free_mc_sibling_devices(pvt); | |
2662 | ||
2663 | err_free: | |
2664 | kfree(pvt); | |
2665 | ||
2666 | err_exit: | |
2667 | return ret; | |
2668 | } | |
2669 | ||
2670 | /* | |
2671 | * This is the finishing stage of the init code. Needs to be performed after all | |
2672 | * MCs' hardware have been prepped for accessing extended config space. | |
2673 | */ | |
2674 | static int amd64_init_2nd_stage(struct amd64_pvt *pvt) | |
2675 | { | |
2676 | int node_id = pvt->mc_node_id; | |
2677 | struct mem_ctl_info *mci; | |
18ba54ac | 2678 | int ret = -ENODEV; |
7d6034d3 DT |
2679 | |
2680 | amd64_read_mc_registers(pvt); | |
2681 | ||
7d6034d3 DT |
2682 | /* |
2683 | * We need to determine how many memory channels there are. Then use | |
2684 | * that information for calculating the size of the dynamic instance | |
2685 | * tables in the 'mci' structure | |
2686 | */ | |
2687 | pvt->channel_count = pvt->ops->early_channel_count(pvt); | |
2688 | if (pvt->channel_count < 0) | |
2689 | goto err_exit; | |
2690 | ||
2691 | ret = -ENOMEM; | |
9d858bb1 | 2692 | mci = edac_mc_alloc(0, pvt->cs_count, pvt->channel_count, node_id); |
7d6034d3 DT |
2693 | if (!mci) |
2694 | goto err_exit; | |
2695 | ||
2696 | mci->pvt_info = pvt; | |
2697 | ||
2698 | mci->dev = &pvt->dram_f2_ctl->dev; | |
2699 | amd64_setup_mci_misc_attributes(mci); | |
2700 | ||
2701 | if (amd64_init_csrows(mci)) | |
2702 | mci->edac_cap = EDAC_FLAG_NONE; | |
2703 | ||
2704 | amd64_enable_ecc_error_reporting(mci); | |
2705 | amd64_set_mc_sysfs_attributes(mci); | |
2706 | ||
2707 | ret = -ENODEV; | |
2708 | if (edac_mc_add_mc(mci)) { | |
2709 | debugf1("failed edac_mc_add_mc()\n"); | |
2710 | goto err_add_mc; | |
2711 | } | |
2712 | ||
2713 | mci_lookup[node_id] = mci; | |
2714 | pvt_lookup[node_id] = NULL; | |
549d042d BP |
2715 | |
2716 | /* register stuff with EDAC MCE */ | |
2717 | if (report_gart_errors) | |
2718 | amd_report_gart_errors(true); | |
2719 | ||
2720 | amd_register_ecc_decoder(amd64_decode_bus_error); | |
2721 | ||
7d6034d3 DT |
2722 | return 0; |
2723 | ||
2724 | err_add_mc: | |
2725 | edac_mc_free(mci); | |
2726 | ||
2727 | err_exit: | |
2728 | debugf0("failure to init 2nd stage: ret=%d\n", ret); | |
2729 | ||
2730 | amd64_restore_ecc_error_reporting(pvt); | |
2731 | ||
2732 | if (boot_cpu_data.x86 > 0xf) | |
2733 | amd64_teardown(pvt); | |
2734 | ||
2735 | amd64_free_mc_sibling_devices(pvt); | |
2736 | ||
2737 | kfree(pvt_lookup[pvt->mc_node_id]); | |
2738 | pvt_lookup[node_id] = NULL; | |
2739 | ||
2740 | return ret; | |
2741 | } | |
2742 | ||
2743 | ||
2744 | static int __devinit amd64_init_one_instance(struct pci_dev *pdev, | |
b8cfa02f | 2745 | const struct pci_device_id *mc_type) |
7d6034d3 DT |
2746 | { |
2747 | int ret = 0; | |
2748 | ||
0092b20d | 2749 | debugf0("(MC node=%d)\n", get_node_id(pdev)); |
7d6034d3 DT |
2750 | |
2751 | ret = pci_enable_device(pdev); | |
b8cfa02f BP |
2752 | if (ret < 0) { |
2753 | debugf0("ret=%d\n", ret); | |
2754 | return -EIO; | |
2755 | } | |
7d6034d3 | 2756 | |
b8cfa02f | 2757 | ret = amd64_probe_one_instance(pdev); |
7d6034d3 | 2758 | if (ret < 0) |
b8cfa02f BP |
2759 | amd64_printk(KERN_ERR, "Error probing instance: %d\n", |
2760 | get_node_id(pdev)); | |
7d6034d3 DT |
2761 | |
2762 | return ret; | |
2763 | } | |
2764 | ||
2765 | static void __devexit amd64_remove_one_instance(struct pci_dev *pdev) | |
2766 | { | |
2767 | struct mem_ctl_info *mci; | |
2768 | struct amd64_pvt *pvt; | |
2769 | ||
2770 | /* Remove from EDAC CORE tracking list */ | |
2771 | mci = edac_mc_del_mc(&pdev->dev); | |
2772 | if (!mci) | |
2773 | return; | |
2774 | ||
2775 | pvt = mci->pvt_info; | |
2776 | ||
2777 | amd64_restore_ecc_error_reporting(pvt); | |
2778 | ||
2779 | if (boot_cpu_data.x86 > 0xf) | |
2780 | amd64_teardown(pvt); | |
2781 | ||
2782 | amd64_free_mc_sibling_devices(pvt); | |
2783 | ||
549d042d BP |
2784 | /* unregister from EDAC MCE */ |
2785 | amd_report_gart_errors(false); | |
2786 | amd_unregister_ecc_decoder(amd64_decode_bus_error); | |
2787 | ||
7d6034d3 | 2788 | /* Free the EDAC CORE resources */ |
8f68ed97 BP |
2789 | mci->pvt_info = NULL; |
2790 | mci_lookup[pvt->mc_node_id] = NULL; | |
2791 | ||
2792 | kfree(pvt); | |
7d6034d3 DT |
2793 | edac_mc_free(mci); |
2794 | } | |
2795 | ||
2796 | /* | |
2797 | * This table is part of the interface for loading drivers for PCI devices. The | |
2798 | * PCI core identifies what devices are on a system during boot, and then | |
2799 | * inquiry this table to see if this driver is for a given device found. | |
2800 | */ | |
2801 | static const struct pci_device_id amd64_pci_table[] __devinitdata = { | |
2802 | { | |
2803 | .vendor = PCI_VENDOR_ID_AMD, | |
2804 | .device = PCI_DEVICE_ID_AMD_K8_NB_MEMCTL, | |
2805 | .subvendor = PCI_ANY_ID, | |
2806 | .subdevice = PCI_ANY_ID, | |
2807 | .class = 0, | |
2808 | .class_mask = 0, | |
7d6034d3 DT |
2809 | }, |
2810 | { | |
2811 | .vendor = PCI_VENDOR_ID_AMD, | |
2812 | .device = PCI_DEVICE_ID_AMD_10H_NB_DRAM, | |
2813 | .subvendor = PCI_ANY_ID, | |
2814 | .subdevice = PCI_ANY_ID, | |
2815 | .class = 0, | |
2816 | .class_mask = 0, | |
7d6034d3 | 2817 | }, |
7d6034d3 DT |
2818 | {0, } |
2819 | }; | |
2820 | MODULE_DEVICE_TABLE(pci, amd64_pci_table); | |
2821 | ||
2822 | static struct pci_driver amd64_pci_driver = { | |
2823 | .name = EDAC_MOD_STR, | |
2824 | .probe = amd64_init_one_instance, | |
2825 | .remove = __devexit_p(amd64_remove_one_instance), | |
2826 | .id_table = amd64_pci_table, | |
2827 | }; | |
2828 | ||
2829 | static void amd64_setup_pci_device(void) | |
2830 | { | |
2831 | struct mem_ctl_info *mci; | |
2832 | struct amd64_pvt *pvt; | |
2833 | ||
2834 | if (amd64_ctl_pci) | |
2835 | return; | |
2836 | ||
2837 | mci = mci_lookup[0]; | |
2838 | if (mci) { | |
2839 | ||
2840 | pvt = mci->pvt_info; | |
2841 | amd64_ctl_pci = | |
2842 | edac_pci_create_generic_ctl(&pvt->dram_f2_ctl->dev, | |
2843 | EDAC_MOD_STR); | |
2844 | ||
2845 | if (!amd64_ctl_pci) { | |
2846 | pr_warning("%s(): Unable to create PCI control\n", | |
2847 | __func__); | |
2848 | ||
2849 | pr_warning("%s(): PCI error report via EDAC not set\n", | |
2850 | __func__); | |
2851 | } | |
2852 | } | |
2853 | } | |
2854 | ||
2855 | static int __init amd64_edac_init(void) | |
2856 | { | |
2857 | int nb, err = -ENODEV; | |
56b34b91 | 2858 | bool load_ok = false; |
7d6034d3 DT |
2859 | |
2860 | edac_printk(KERN_INFO, EDAC_MOD_STR, EDAC_AMD64_VERSION "\n"); | |
2861 | ||
2862 | opstate_init(); | |
2863 | ||
9653a5c7 | 2864 | if (amd_cache_northbridges() < 0) |
56b34b91 | 2865 | goto err_ret; |
7d6034d3 | 2866 | |
50542251 | 2867 | msrs = msrs_alloc(); |
56b34b91 BP |
2868 | if (!msrs) |
2869 | goto err_ret; | |
50542251 | 2870 | |
7d6034d3 DT |
2871 | err = pci_register_driver(&amd64_pci_driver); |
2872 | if (err) | |
56b34b91 | 2873 | goto err_pci; |
7d6034d3 DT |
2874 | |
2875 | /* | |
2876 | * At this point, the array 'pvt_lookup[]' contains pointers to alloc'd | |
2877 | * amd64_pvt structs. These will be used in the 2nd stage init function | |
2878 | * to finish initialization of the MC instances. | |
2879 | */ | |
56b34b91 | 2880 | err = -ENODEV; |
9653a5c7 | 2881 | for (nb = 0; nb < amd_nb_num(); nb++) { |
7d6034d3 DT |
2882 | if (!pvt_lookup[nb]) |
2883 | continue; | |
2884 | ||
2885 | err = amd64_init_2nd_stage(pvt_lookup[nb]); | |
2886 | if (err) | |
37da0450 | 2887 | goto err_2nd_stage; |
7d6034d3 | 2888 | |
56b34b91 BP |
2889 | load_ok = true; |
2890 | } | |
7d6034d3 | 2891 | |
56b34b91 BP |
2892 | if (load_ok) { |
2893 | amd64_setup_pci_device(); | |
2894 | return 0; | |
2895 | } | |
7d6034d3 | 2896 | |
37da0450 | 2897 | err_2nd_stage: |
7d6034d3 | 2898 | pci_unregister_driver(&amd64_pci_driver); |
56b34b91 BP |
2899 | err_pci: |
2900 | msrs_free(msrs); | |
2901 | msrs = NULL; | |
2902 | err_ret: | |
7d6034d3 DT |
2903 | return err; |
2904 | } | |
2905 | ||
2906 | static void __exit amd64_edac_exit(void) | |
2907 | { | |
2908 | if (amd64_ctl_pci) | |
2909 | edac_pci_release_generic_ctl(amd64_ctl_pci); | |
2910 | ||
2911 | pci_unregister_driver(&amd64_pci_driver); | |
50542251 BP |
2912 | |
2913 | msrs_free(msrs); | |
2914 | msrs = NULL; | |
7d6034d3 DT |
2915 | } |
2916 | ||
2917 | module_init(amd64_edac_init); | |
2918 | module_exit(amd64_edac_exit); | |
2919 | ||
2920 | MODULE_LICENSE("GPL"); | |
2921 | MODULE_AUTHOR("SoftwareBitMaker: Doug Thompson, " | |
2922 | "Dave Peterson, Thayne Harbaugh"); | |
2923 | MODULE_DESCRIPTION("MC support for AMD64 memory controllers - " | |
2924 | EDAC_AMD64_VERSION); | |
2925 | ||
2926 | module_param(edac_op_state, int, 0444); | |
2927 | MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); |