Commit | Line | Data |
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2bc65418 DT |
1 | #include "amd64_edac.h" |
2 | ||
3 | static struct edac_pci_ctl_info *amd64_ctl_pci; | |
4 | ||
5 | static int report_gart_errors; | |
6 | module_param(report_gart_errors, int, 0644); | |
7 | ||
8 | /* | |
9 | * Set by command line parameter. If BIOS has enabled the ECC, this override is | |
10 | * cleared to prevent re-enabling the hardware by this driver. | |
11 | */ | |
12 | static int ecc_enable_override; | |
13 | module_param(ecc_enable_override, int, 0644); | |
14 | ||
15 | /* Lookup table for all possible MC control instances */ | |
16 | struct amd64_pvt; | |
17 | static struct mem_ctl_info *mci_lookup[MAX_NUMNODES]; | |
18 | static struct amd64_pvt *pvt_lookup[MAX_NUMNODES]; | |
19 | ||
20 | /* | |
21 | * Memory scrubber control interface. For K8, memory scrubbing is handled by | |
22 | * hardware and can involve L2 cache, dcache as well as the main memory. With | |
23 | * F10, this is extended to L3 cache scrubbing on CPU models sporting that | |
24 | * functionality. | |
25 | * | |
26 | * This causes the "units" for the scrubbing speed to vary from 64 byte blocks | |
27 | * (dram) over to cache lines. This is nasty, so we will use bandwidth in | |
28 | * bytes/sec for the setting. | |
29 | * | |
30 | * Currently, we only do dram scrubbing. If the scrubbing is done in software on | |
31 | * other archs, we might not have access to the caches directly. | |
32 | */ | |
33 | ||
34 | /* | |
35 | * scan the scrub rate mapping table for a close or matching bandwidth value to | |
36 | * issue. If requested is too big, then use last maximum value found. | |
37 | */ | |
38 | static int amd64_search_set_scrub_rate(struct pci_dev *ctl, u32 new_bw, | |
39 | u32 min_scrubrate) | |
40 | { | |
41 | u32 scrubval; | |
42 | int i; | |
43 | ||
44 | /* | |
45 | * map the configured rate (new_bw) to a value specific to the AMD64 | |
46 | * memory controller and apply to register. Search for the first | |
47 | * bandwidth entry that is greater or equal than the setting requested | |
48 | * and program that. If at last entry, turn off DRAM scrubbing. | |
49 | */ | |
50 | for (i = 0; i < ARRAY_SIZE(scrubrates); i++) { | |
51 | /* | |
52 | * skip scrub rates which aren't recommended | |
53 | * (see F10 BKDG, F3x58) | |
54 | */ | |
55 | if (scrubrates[i].scrubval < min_scrubrate) | |
56 | continue; | |
57 | ||
58 | if (scrubrates[i].bandwidth <= new_bw) | |
59 | break; | |
60 | ||
61 | /* | |
62 | * if no suitable bandwidth found, turn off DRAM scrubbing | |
63 | * entirely by falling back to the last element in the | |
64 | * scrubrates array. | |
65 | */ | |
66 | } | |
67 | ||
68 | scrubval = scrubrates[i].scrubval; | |
69 | if (scrubval) | |
70 | edac_printk(KERN_DEBUG, EDAC_MC, | |
71 | "Setting scrub rate bandwidth: %u\n", | |
72 | scrubrates[i].bandwidth); | |
73 | else | |
74 | edac_printk(KERN_DEBUG, EDAC_MC, "Turning scrubbing off.\n"); | |
75 | ||
76 | pci_write_bits32(ctl, K8_SCRCTRL, scrubval, 0x001F); | |
77 | ||
78 | return 0; | |
79 | } | |
80 | ||
81 | static int amd64_set_scrub_rate(struct mem_ctl_info *mci, u32 *bandwidth) | |
82 | { | |
83 | struct amd64_pvt *pvt = mci->pvt_info; | |
84 | u32 min_scrubrate = 0x0; | |
85 | ||
86 | switch (boot_cpu_data.x86) { | |
87 | case 0xf: | |
88 | min_scrubrate = K8_MIN_SCRUB_RATE_BITS; | |
89 | break; | |
90 | case 0x10: | |
91 | min_scrubrate = F10_MIN_SCRUB_RATE_BITS; | |
92 | break; | |
93 | case 0x11: | |
94 | min_scrubrate = F11_MIN_SCRUB_RATE_BITS; | |
95 | break; | |
96 | ||
97 | default: | |
98 | amd64_printk(KERN_ERR, "Unsupported family!\n"); | |
99 | break; | |
100 | } | |
101 | return amd64_search_set_scrub_rate(pvt->misc_f3_ctl, *bandwidth, | |
102 | min_scrubrate); | |
103 | } | |
104 | ||
105 | static int amd64_get_scrub_rate(struct mem_ctl_info *mci, u32 *bw) | |
106 | { | |
107 | struct amd64_pvt *pvt = mci->pvt_info; | |
108 | u32 scrubval = 0; | |
109 | int status = -1, i, ret = 0; | |
110 | ||
111 | ret = pci_read_config_dword(pvt->misc_f3_ctl, K8_SCRCTRL, &scrubval); | |
112 | if (ret) | |
113 | debugf0("Reading K8_SCRCTRL failed\n"); | |
114 | ||
115 | scrubval = scrubval & 0x001F; | |
116 | ||
117 | edac_printk(KERN_DEBUG, EDAC_MC, | |
118 | "pci-read, sdram scrub control value: %d \n", scrubval); | |
119 | ||
120 | for (i = 0; ARRAY_SIZE(scrubrates); i++) { | |
121 | if (scrubrates[i].scrubval == scrubval) { | |
122 | *bw = scrubrates[i].bandwidth; | |
123 | status = 0; | |
124 | break; | |
125 | } | |
126 | } | |
127 | ||
128 | return status; | |
129 | } | |
130 | ||
6775763a DT |
131 | /* Map from a CSROW entry to the mask entry that operates on it */ |
132 | static inline u32 amd64_map_to_dcs_mask(struct amd64_pvt *pvt, int csrow) | |
133 | { | |
134 | return csrow >> (pvt->num_dcsm >> 3); | |
135 | } | |
136 | ||
137 | /* return the 'base' address the i'th CS entry of the 'dct' DRAM controller */ | |
138 | static u32 amd64_get_dct_base(struct amd64_pvt *pvt, int dct, int csrow) | |
139 | { | |
140 | if (dct == 0) | |
141 | return pvt->dcsb0[csrow]; | |
142 | else | |
143 | return pvt->dcsb1[csrow]; | |
144 | } | |
145 | ||
146 | /* | |
147 | * Return the 'mask' address the i'th CS entry. This function is needed because | |
148 | * there number of DCSM registers on Rev E and prior vs Rev F and later is | |
149 | * different. | |
150 | */ | |
151 | static u32 amd64_get_dct_mask(struct amd64_pvt *pvt, int dct, int csrow) | |
152 | { | |
153 | if (dct == 0) | |
154 | return pvt->dcsm0[amd64_map_to_dcs_mask(pvt, csrow)]; | |
155 | else | |
156 | return pvt->dcsm1[amd64_map_to_dcs_mask(pvt, csrow)]; | |
157 | } | |
158 | ||
159 | ||
160 | /* | |
161 | * In *base and *limit, pass back the full 40-bit base and limit physical | |
162 | * addresses for the node given by node_id. This information is obtained from | |
163 | * DRAM Base (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers. The | |
164 | * base and limit addresses are of type SysAddr, as defined at the start of | |
165 | * section 3.4.4 (p. 70). They are the lowest and highest physical addresses | |
166 | * in the address range they represent. | |
167 | */ | |
168 | static void amd64_get_base_and_limit(struct amd64_pvt *pvt, int node_id, | |
169 | u64 *base, u64 *limit) | |
170 | { | |
171 | *base = pvt->dram_base[node_id]; | |
172 | *limit = pvt->dram_limit[node_id]; | |
173 | } | |
174 | ||
175 | /* | |
176 | * Return 1 if the SysAddr given by sys_addr matches the base/limit associated | |
177 | * with node_id | |
178 | */ | |
179 | static int amd64_base_limit_match(struct amd64_pvt *pvt, | |
180 | u64 sys_addr, int node_id) | |
181 | { | |
182 | u64 base, limit, addr; | |
183 | ||
184 | amd64_get_base_and_limit(pvt, node_id, &base, &limit); | |
185 | ||
186 | /* The K8 treats this as a 40-bit value. However, bits 63-40 will be | |
187 | * all ones if the most significant implemented address bit is 1. | |
188 | * Here we discard bits 63-40. See section 3.4.2 of AMD publication | |
189 | * 24592: AMD x86-64 Architecture Programmer's Manual Volume 1 | |
190 | * Application Programming. | |
191 | */ | |
192 | addr = sys_addr & 0x000000ffffffffffull; | |
193 | ||
194 | return (addr >= base) && (addr <= limit); | |
195 | } | |
196 | ||
197 | /* | |
198 | * Attempt to map a SysAddr to a node. On success, return a pointer to the | |
199 | * mem_ctl_info structure for the node that the SysAddr maps to. | |
200 | * | |
201 | * On failure, return NULL. | |
202 | */ | |
203 | static struct mem_ctl_info *find_mc_by_sys_addr(struct mem_ctl_info *mci, | |
204 | u64 sys_addr) | |
205 | { | |
206 | struct amd64_pvt *pvt; | |
207 | int node_id; | |
208 | u32 intlv_en, bits; | |
209 | ||
210 | /* | |
211 | * Here we use the DRAM Base (section 3.4.4.1) and DRAM Limit (section | |
212 | * 3.4.4.2) registers to map the SysAddr to a node ID. | |
213 | */ | |
214 | pvt = mci->pvt_info; | |
215 | ||
216 | /* | |
217 | * The value of this field should be the same for all DRAM Base | |
218 | * registers. Therefore we arbitrarily choose to read it from the | |
219 | * register for node 0. | |
220 | */ | |
221 | intlv_en = pvt->dram_IntlvEn[0]; | |
222 | ||
223 | if (intlv_en == 0) { | |
224 | for (node_id = 0; ; ) { | |
225 | if (amd64_base_limit_match(pvt, sys_addr, node_id)) | |
226 | break; | |
227 | ||
228 | if (++node_id >= DRAM_REG_COUNT) | |
229 | goto err_no_match; | |
230 | } | |
231 | goto found; | |
232 | } | |
233 | ||
234 | if (unlikely((intlv_en != (0x01 << 8)) && | |
235 | (intlv_en != (0x03 << 8)) && | |
236 | (intlv_en != (0x07 << 8)))) { | |
237 | amd64_printk(KERN_WARNING, "junk value of 0x%x extracted from " | |
238 | "IntlvEn field of DRAM Base Register for node 0: " | |
239 | "This probably indicates a BIOS bug.\n", intlv_en); | |
240 | return NULL; | |
241 | } | |
242 | ||
243 | bits = (((u32) sys_addr) >> 12) & intlv_en; | |
244 | ||
245 | for (node_id = 0; ; ) { | |
246 | if ((pvt->dram_limit[node_id] & intlv_en) == bits) | |
247 | break; /* intlv_sel field matches */ | |
248 | ||
249 | if (++node_id >= DRAM_REG_COUNT) | |
250 | goto err_no_match; | |
251 | } | |
252 | ||
253 | /* sanity test for sys_addr */ | |
254 | if (unlikely(!amd64_base_limit_match(pvt, sys_addr, node_id))) { | |
255 | amd64_printk(KERN_WARNING, | |
256 | "%s(): sys_addr 0x%lx falls outside base/limit " | |
257 | "address range for node %d with node interleaving " | |
258 | "enabled.\n", __func__, (unsigned long)sys_addr, | |
259 | node_id); | |
260 | return NULL; | |
261 | } | |
262 | ||
263 | found: | |
264 | return edac_mc_find(node_id); | |
265 | ||
266 | err_no_match: | |
267 | debugf2("sys_addr 0x%lx doesn't match any node\n", | |
268 | (unsigned long)sys_addr); | |
269 | ||
270 | return NULL; | |
271 | } | |
e2ce7255 DT |
272 | |
273 | /* | |
274 | * Extract the DRAM CS base address from selected csrow register. | |
275 | */ | |
276 | static u64 base_from_dct_base(struct amd64_pvt *pvt, int csrow) | |
277 | { | |
278 | return ((u64) (amd64_get_dct_base(pvt, 0, csrow) & pvt->dcsb_base)) << | |
279 | pvt->dcs_shift; | |
280 | } | |
281 | ||
282 | /* | |
283 | * Extract the mask from the dcsb0[csrow] entry in a CPU revision-specific way. | |
284 | */ | |
285 | static u64 mask_from_dct_mask(struct amd64_pvt *pvt, int csrow) | |
286 | { | |
287 | u64 dcsm_bits, other_bits; | |
288 | u64 mask; | |
289 | ||
290 | /* Extract bits from DRAM CS Mask. */ | |
291 | dcsm_bits = amd64_get_dct_mask(pvt, 0, csrow) & pvt->dcsm_mask; | |
292 | ||
293 | other_bits = pvt->dcsm_mask; | |
294 | other_bits = ~(other_bits << pvt->dcs_shift); | |
295 | ||
296 | /* | |
297 | * The extracted bits from DCSM belong in the spaces represented by | |
298 | * the cleared bits in other_bits. | |
299 | */ | |
300 | mask = (dcsm_bits << pvt->dcs_shift) | other_bits; | |
301 | ||
302 | return mask; | |
303 | } | |
304 | ||
305 | /* | |
306 | * @input_addr is an InputAddr associated with the node given by mci. Return the | |
307 | * csrow that input_addr maps to, or -1 on failure (no csrow claims input_addr). | |
308 | */ | |
309 | static int input_addr_to_csrow(struct mem_ctl_info *mci, u64 input_addr) | |
310 | { | |
311 | struct amd64_pvt *pvt; | |
312 | int csrow; | |
313 | u64 base, mask; | |
314 | ||
315 | pvt = mci->pvt_info; | |
316 | ||
317 | /* | |
318 | * Here we use the DRAM CS Base and DRAM CS Mask registers. For each CS | |
319 | * base/mask register pair, test the condition shown near the start of | |
320 | * section 3.5.4 (p. 84, BKDG #26094, K8, revA-E). | |
321 | */ | |
322 | for (csrow = 0; csrow < CHIPSELECT_COUNT; csrow++) { | |
323 | ||
324 | /* This DRAM chip select is disabled on this node */ | |
325 | if ((pvt->dcsb0[csrow] & K8_DCSB_CS_ENABLE) == 0) | |
326 | continue; | |
327 | ||
328 | base = base_from_dct_base(pvt, csrow); | |
329 | mask = ~mask_from_dct_mask(pvt, csrow); | |
330 | ||
331 | if ((input_addr & mask) == (base & mask)) { | |
332 | debugf2("InputAddr 0x%lx matches csrow %d (node %d)\n", | |
333 | (unsigned long)input_addr, csrow, | |
334 | pvt->mc_node_id); | |
335 | ||
336 | return csrow; | |
337 | } | |
338 | } | |
339 | ||
340 | debugf2("no matching csrow for InputAddr 0x%lx (MC node %d)\n", | |
341 | (unsigned long)input_addr, pvt->mc_node_id); | |
342 | ||
343 | return -1; | |
344 | } | |
345 | ||
346 | /* | |
347 | * Return the base value defined by the DRAM Base register for the node | |
348 | * represented by mci. This function returns the full 40-bit value despite the | |
349 | * fact that the register only stores bits 39-24 of the value. See section | |
350 | * 3.4.4.1 (BKDG #26094, K8, revA-E) | |
351 | */ | |
352 | static inline u64 get_dram_base(struct mem_ctl_info *mci) | |
353 | { | |
354 | struct amd64_pvt *pvt = mci->pvt_info; | |
355 | ||
356 | return pvt->dram_base[pvt->mc_node_id]; | |
357 | } | |
358 | ||
359 | /* | |
360 | * Obtain info from the DRAM Hole Address Register (section 3.4.8, pub #26094) | |
361 | * for the node represented by mci. Info is passed back in *hole_base, | |
362 | * *hole_offset, and *hole_size. Function returns 0 if info is valid or 1 if | |
363 | * info is invalid. Info may be invalid for either of the following reasons: | |
364 | * | |
365 | * - The revision of the node is not E or greater. In this case, the DRAM Hole | |
366 | * Address Register does not exist. | |
367 | * | |
368 | * - The DramHoleValid bit is cleared in the DRAM Hole Address Register, | |
369 | * indicating that its contents are not valid. | |
370 | * | |
371 | * The values passed back in *hole_base, *hole_offset, and *hole_size are | |
372 | * complete 32-bit values despite the fact that the bitfields in the DHAR | |
373 | * only represent bits 31-24 of the base and offset values. | |
374 | */ | |
375 | int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base, | |
376 | u64 *hole_offset, u64 *hole_size) | |
377 | { | |
378 | struct amd64_pvt *pvt = mci->pvt_info; | |
379 | u64 base; | |
380 | ||
381 | /* only revE and later have the DRAM Hole Address Register */ | |
382 | if (boot_cpu_data.x86 == 0xf && pvt->ext_model < OPTERON_CPU_REV_E) { | |
383 | debugf1(" revision %d for node %d does not support DHAR\n", | |
384 | pvt->ext_model, pvt->mc_node_id); | |
385 | return 1; | |
386 | } | |
387 | ||
388 | /* only valid for Fam10h */ | |
389 | if (boot_cpu_data.x86 == 0x10 && | |
390 | (pvt->dhar & F10_DRAM_MEM_HOIST_VALID) == 0) { | |
391 | debugf1(" Dram Memory Hoisting is DISABLED on this system\n"); | |
392 | return 1; | |
393 | } | |
394 | ||
395 | if ((pvt->dhar & DHAR_VALID) == 0) { | |
396 | debugf1(" Dram Memory Hoisting is DISABLED on this node %d\n", | |
397 | pvt->mc_node_id); | |
398 | return 1; | |
399 | } | |
400 | ||
401 | /* This node has Memory Hoisting */ | |
402 | ||
403 | /* +------------------+--------------------+--------------------+----- | |
404 | * | memory | DRAM hole | relocated | | |
405 | * | [0, (x - 1)] | [x, 0xffffffff] | addresses from | | |
406 | * | | | DRAM hole | | |
407 | * | | | [0x100000000, | | |
408 | * | | | (0x100000000+ | | |
409 | * | | | (0xffffffff-x))] | | |
410 | * +------------------+--------------------+--------------------+----- | |
411 | * | |
412 | * Above is a diagram of physical memory showing the DRAM hole and the | |
413 | * relocated addresses from the DRAM hole. As shown, the DRAM hole | |
414 | * starts at address x (the base address) and extends through address | |
415 | * 0xffffffff. The DRAM Hole Address Register (DHAR) relocates the | |
416 | * addresses in the hole so that they start at 0x100000000. | |
417 | */ | |
418 | ||
419 | base = dhar_base(pvt->dhar); | |
420 | ||
421 | *hole_base = base; | |
422 | *hole_size = (0x1ull << 32) - base; | |
423 | ||
424 | if (boot_cpu_data.x86 > 0xf) | |
425 | *hole_offset = f10_dhar_offset(pvt->dhar); | |
426 | else | |
427 | *hole_offset = k8_dhar_offset(pvt->dhar); | |
428 | ||
429 | debugf1(" DHAR info for node %d base 0x%lx offset 0x%lx size 0x%lx\n", | |
430 | pvt->mc_node_id, (unsigned long)*hole_base, | |
431 | (unsigned long)*hole_offset, (unsigned long)*hole_size); | |
432 | ||
433 | return 0; | |
434 | } | |
435 | EXPORT_SYMBOL_GPL(amd64_get_dram_hole_info); | |
436 | ||
93c2df58 DT |
437 | /* |
438 | * Return the DramAddr that the SysAddr given by @sys_addr maps to. It is | |
439 | * assumed that sys_addr maps to the node given by mci. | |
440 | * | |
441 | * The first part of section 3.4.4 (p. 70) shows how the DRAM Base (section | |
442 | * 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers are used to translate a | |
443 | * SysAddr to a DramAddr. If the DRAM Hole Address Register (DHAR) is enabled, | |
444 | * then it is also involved in translating a SysAddr to a DramAddr. Sections | |
445 | * 3.4.8 and 3.5.8.2 describe the DHAR and how it is used for memory hoisting. | |
446 | * These parts of the documentation are unclear. I interpret them as follows: | |
447 | * | |
448 | * When node n receives a SysAddr, it processes the SysAddr as follows: | |
449 | * | |
450 | * 1. It extracts the DRAMBase and DRAMLimit values from the DRAM Base and DRAM | |
451 | * Limit registers for node n. If the SysAddr is not within the range | |
452 | * specified by the base and limit values, then node n ignores the Sysaddr | |
453 | * (since it does not map to node n). Otherwise continue to step 2 below. | |
454 | * | |
455 | * 2. If the DramHoleValid bit of the DHAR for node n is clear, the DHAR is | |
456 | * disabled so skip to step 3 below. Otherwise see if the SysAddr is within | |
457 | * the range of relocated addresses (starting at 0x100000000) from the DRAM | |
458 | * hole. If not, skip to step 3 below. Else get the value of the | |
459 | * DramHoleOffset field from the DHAR. To obtain the DramAddr, subtract the | |
460 | * offset defined by this value from the SysAddr. | |
461 | * | |
462 | * 3. Obtain the base address for node n from the DRAMBase field of the DRAM | |
463 | * Base register for node n. To obtain the DramAddr, subtract the base | |
464 | * address from the SysAddr, as shown near the start of section 3.4.4 (p.70). | |
465 | */ | |
466 | static u64 sys_addr_to_dram_addr(struct mem_ctl_info *mci, u64 sys_addr) | |
467 | { | |
468 | u64 dram_base, hole_base, hole_offset, hole_size, dram_addr; | |
469 | int ret = 0; | |
470 | ||
471 | dram_base = get_dram_base(mci); | |
472 | ||
473 | ret = amd64_get_dram_hole_info(mci, &hole_base, &hole_offset, | |
474 | &hole_size); | |
475 | if (!ret) { | |
476 | if ((sys_addr >= (1ull << 32)) && | |
477 | (sys_addr < ((1ull << 32) + hole_size))) { | |
478 | /* use DHAR to translate SysAddr to DramAddr */ | |
479 | dram_addr = sys_addr - hole_offset; | |
480 | ||
481 | debugf2("using DHAR to translate SysAddr 0x%lx to " | |
482 | "DramAddr 0x%lx\n", | |
483 | (unsigned long)sys_addr, | |
484 | (unsigned long)dram_addr); | |
485 | ||
486 | return dram_addr; | |
487 | } | |
488 | } | |
489 | ||
490 | /* | |
491 | * Translate the SysAddr to a DramAddr as shown near the start of | |
492 | * section 3.4.4 (p. 70). Although sys_addr is a 64-bit value, the k8 | |
493 | * only deals with 40-bit values. Therefore we discard bits 63-40 of | |
494 | * sys_addr below. If bit 39 of sys_addr is 1 then the bits we | |
495 | * discard are all 1s. Otherwise the bits we discard are all 0s. See | |
496 | * section 3.4.2 of AMD publication 24592: AMD x86-64 Architecture | |
497 | * Programmer's Manual Volume 1 Application Programming. | |
498 | */ | |
499 | dram_addr = (sys_addr & 0xffffffffffull) - dram_base; | |
500 | ||
501 | debugf2("using DRAM Base register to translate SysAddr 0x%lx to " | |
502 | "DramAddr 0x%lx\n", (unsigned long)sys_addr, | |
503 | (unsigned long)dram_addr); | |
504 | return dram_addr; | |
505 | } | |
506 | ||
507 | /* | |
508 | * @intlv_en is the value of the IntlvEn field from a DRAM Base register | |
509 | * (section 3.4.4.1). Return the number of bits from a SysAddr that are used | |
510 | * for node interleaving. | |
511 | */ | |
512 | static int num_node_interleave_bits(unsigned intlv_en) | |
513 | { | |
514 | static const int intlv_shift_table[] = { 0, 1, 0, 2, 0, 0, 0, 3 }; | |
515 | int n; | |
516 | ||
517 | BUG_ON(intlv_en > 7); | |
518 | n = intlv_shift_table[intlv_en]; | |
519 | return n; | |
520 | } | |
521 | ||
522 | /* Translate the DramAddr given by @dram_addr to an InputAddr. */ | |
523 | static u64 dram_addr_to_input_addr(struct mem_ctl_info *mci, u64 dram_addr) | |
524 | { | |
525 | struct amd64_pvt *pvt; | |
526 | int intlv_shift; | |
527 | u64 input_addr; | |
528 | ||
529 | pvt = mci->pvt_info; | |
530 | ||
531 | /* | |
532 | * See the start of section 3.4.4 (p. 70, BKDG #26094, K8, revA-E) | |
533 | * concerning translating a DramAddr to an InputAddr. | |
534 | */ | |
535 | intlv_shift = num_node_interleave_bits(pvt->dram_IntlvEn[0]); | |
536 | input_addr = ((dram_addr >> intlv_shift) & 0xffffff000ull) + | |
537 | (dram_addr & 0xfff); | |
538 | ||
539 | debugf2(" Intlv Shift=%d DramAddr=0x%lx maps to InputAddr=0x%lx\n", | |
540 | intlv_shift, (unsigned long)dram_addr, | |
541 | (unsigned long)input_addr); | |
542 | ||
543 | return input_addr; | |
544 | } | |
545 | ||
546 | /* | |
547 | * Translate the SysAddr represented by @sys_addr to an InputAddr. It is | |
548 | * assumed that @sys_addr maps to the node given by mci. | |
549 | */ | |
550 | static u64 sys_addr_to_input_addr(struct mem_ctl_info *mci, u64 sys_addr) | |
551 | { | |
552 | u64 input_addr; | |
553 | ||
554 | input_addr = | |
555 | dram_addr_to_input_addr(mci, sys_addr_to_dram_addr(mci, sys_addr)); | |
556 | ||
557 | debugf2("SysAdddr 0x%lx translates to InputAddr 0x%lx\n", | |
558 | (unsigned long)sys_addr, (unsigned long)input_addr); | |
559 | ||
560 | return input_addr; | |
561 | } | |
562 | ||
563 | ||
564 | /* | |
565 | * @input_addr is an InputAddr associated with the node represented by mci. | |
566 | * Translate @input_addr to a DramAddr and return the result. | |
567 | */ | |
568 | static u64 input_addr_to_dram_addr(struct mem_ctl_info *mci, u64 input_addr) | |
569 | { | |
570 | struct amd64_pvt *pvt; | |
571 | int node_id, intlv_shift; | |
572 | u64 bits, dram_addr; | |
573 | u32 intlv_sel; | |
574 | ||
575 | /* | |
576 | * Near the start of section 3.4.4 (p. 70, BKDG #26094, K8, revA-E) | |
577 | * shows how to translate a DramAddr to an InputAddr. Here we reverse | |
578 | * this procedure. When translating from a DramAddr to an InputAddr, the | |
579 | * bits used for node interleaving are discarded. Here we recover these | |
580 | * bits from the IntlvSel field of the DRAM Limit register (section | |
581 | * 3.4.4.2) for the node that input_addr is associated with. | |
582 | */ | |
583 | pvt = mci->pvt_info; | |
584 | node_id = pvt->mc_node_id; | |
585 | BUG_ON((node_id < 0) || (node_id > 7)); | |
586 | ||
587 | intlv_shift = num_node_interleave_bits(pvt->dram_IntlvEn[0]); | |
588 | ||
589 | if (intlv_shift == 0) { | |
590 | debugf1(" InputAddr 0x%lx translates to DramAddr of " | |
591 | "same value\n", (unsigned long)input_addr); | |
592 | ||
593 | return input_addr; | |
594 | } | |
595 | ||
596 | bits = ((input_addr & 0xffffff000ull) << intlv_shift) + | |
597 | (input_addr & 0xfff); | |
598 | ||
599 | intlv_sel = pvt->dram_IntlvSel[node_id] & ((1 << intlv_shift) - 1); | |
600 | dram_addr = bits + (intlv_sel << 12); | |
601 | ||
602 | debugf1("InputAddr 0x%lx translates to DramAddr 0x%lx " | |
603 | "(%d node interleave bits)\n", (unsigned long)input_addr, | |
604 | (unsigned long)dram_addr, intlv_shift); | |
605 | ||
606 | return dram_addr; | |
607 | } | |
608 | ||
609 | /* | |
610 | * @dram_addr is a DramAddr that maps to the node represented by mci. Convert | |
611 | * @dram_addr to a SysAddr. | |
612 | */ | |
613 | static u64 dram_addr_to_sys_addr(struct mem_ctl_info *mci, u64 dram_addr) | |
614 | { | |
615 | struct amd64_pvt *pvt = mci->pvt_info; | |
616 | u64 hole_base, hole_offset, hole_size, base, limit, sys_addr; | |
617 | int ret = 0; | |
618 | ||
619 | ret = amd64_get_dram_hole_info(mci, &hole_base, &hole_offset, | |
620 | &hole_size); | |
621 | if (!ret) { | |
622 | if ((dram_addr >= hole_base) && | |
623 | (dram_addr < (hole_base + hole_size))) { | |
624 | sys_addr = dram_addr + hole_offset; | |
625 | ||
626 | debugf1("using DHAR to translate DramAddr 0x%lx to " | |
627 | "SysAddr 0x%lx\n", (unsigned long)dram_addr, | |
628 | (unsigned long)sys_addr); | |
629 | ||
630 | return sys_addr; | |
631 | } | |
632 | } | |
633 | ||
634 | amd64_get_base_and_limit(pvt, pvt->mc_node_id, &base, &limit); | |
635 | sys_addr = dram_addr + base; | |
636 | ||
637 | /* | |
638 | * The sys_addr we have computed up to this point is a 40-bit value | |
639 | * because the k8 deals with 40-bit values. However, the value we are | |
640 | * supposed to return is a full 64-bit physical address. The AMD | |
641 | * x86-64 architecture specifies that the most significant implemented | |
642 | * address bit through bit 63 of a physical address must be either all | |
643 | * 0s or all 1s. Therefore we sign-extend the 40-bit sys_addr to a | |
644 | * 64-bit value below. See section 3.4.2 of AMD publication 24592: | |
645 | * AMD x86-64 Architecture Programmer's Manual Volume 1 Application | |
646 | * Programming. | |
647 | */ | |
648 | sys_addr |= ~((sys_addr & (1ull << 39)) - 1); | |
649 | ||
650 | debugf1(" Node %d, DramAddr 0x%lx to SysAddr 0x%lx\n", | |
651 | pvt->mc_node_id, (unsigned long)dram_addr, | |
652 | (unsigned long)sys_addr); | |
653 | ||
654 | return sys_addr; | |
655 | } | |
656 | ||
657 | /* | |
658 | * @input_addr is an InputAddr associated with the node given by mci. Translate | |
659 | * @input_addr to a SysAddr. | |
660 | */ | |
661 | static inline u64 input_addr_to_sys_addr(struct mem_ctl_info *mci, | |
662 | u64 input_addr) | |
663 | { | |
664 | return dram_addr_to_sys_addr(mci, | |
665 | input_addr_to_dram_addr(mci, input_addr)); | |
666 | } | |
667 | ||
668 | /* | |
669 | * Find the minimum and maximum InputAddr values that map to the given @csrow. | |
670 | * Pass back these values in *input_addr_min and *input_addr_max. | |
671 | */ | |
672 | static void find_csrow_limits(struct mem_ctl_info *mci, int csrow, | |
673 | u64 *input_addr_min, u64 *input_addr_max) | |
674 | { | |
675 | struct amd64_pvt *pvt; | |
676 | u64 base, mask; | |
677 | ||
678 | pvt = mci->pvt_info; | |
679 | BUG_ON((csrow < 0) || (csrow >= CHIPSELECT_COUNT)); | |
680 | ||
681 | base = base_from_dct_base(pvt, csrow); | |
682 | mask = mask_from_dct_mask(pvt, csrow); | |
683 | ||
684 | *input_addr_min = base & ~mask; | |
685 | *input_addr_max = base | mask | pvt->dcs_mask_notused; | |
686 | } | |
687 | ||
688 | /* | |
689 | * Extract error address from MCA NB Address Low (section 3.6.4.5) and MCA NB | |
690 | * Address High (section 3.6.4.6) register values and return the result. Address | |
691 | * is located in the info structure (nbeah and nbeal), the encoding is device | |
692 | * specific. | |
693 | */ | |
694 | static u64 extract_error_address(struct mem_ctl_info *mci, | |
695 | struct amd64_error_info_regs *info) | |
696 | { | |
697 | struct amd64_pvt *pvt = mci->pvt_info; | |
698 | ||
699 | return pvt->ops->get_error_address(mci, info); | |
700 | } | |
701 | ||
702 | ||
703 | /* Map the Error address to a PAGE and PAGE OFFSET. */ | |
704 | static inline void error_address_to_page_and_offset(u64 error_address, | |
705 | u32 *page, u32 *offset) | |
706 | { | |
707 | *page = (u32) (error_address >> PAGE_SHIFT); | |
708 | *offset = ((u32) error_address) & ~PAGE_MASK; | |
709 | } | |
710 | ||
711 | /* | |
712 | * @sys_addr is an error address (a SysAddr) extracted from the MCA NB Address | |
713 | * Low (section 3.6.4.5) and MCA NB Address High (section 3.6.4.6) registers | |
714 | * of a node that detected an ECC memory error. mci represents the node that | |
715 | * the error address maps to (possibly different from the node that detected | |
716 | * the error). Return the number of the csrow that sys_addr maps to, or -1 on | |
717 | * error. | |
718 | */ | |
719 | static int sys_addr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr) | |
720 | { | |
721 | int csrow; | |
722 | ||
723 | csrow = input_addr_to_csrow(mci, sys_addr_to_input_addr(mci, sys_addr)); | |
724 | ||
725 | if (csrow == -1) | |
726 | amd64_mc_printk(mci, KERN_ERR, | |
727 | "Failed to translate InputAddr to csrow for " | |
728 | "address 0x%lx\n", (unsigned long)sys_addr); | |
729 | return csrow; | |
730 | } | |
e2ce7255 | 731 | |
2da11654 DT |
732 | static int get_channel_from_ecc_syndrome(unsigned short syndrome); |
733 | ||
734 | static void amd64_cpu_display_info(struct amd64_pvt *pvt) | |
735 | { | |
736 | if (boot_cpu_data.x86 == 0x11) | |
737 | edac_printk(KERN_DEBUG, EDAC_MC, "F11h CPU detected\n"); | |
738 | else if (boot_cpu_data.x86 == 0x10) | |
739 | edac_printk(KERN_DEBUG, EDAC_MC, "F10h CPU detected\n"); | |
740 | else if (boot_cpu_data.x86 == 0xf) | |
741 | edac_printk(KERN_DEBUG, EDAC_MC, "%s detected\n", | |
742 | (pvt->ext_model >= OPTERON_CPU_REV_F) ? | |
743 | "Rev F or later" : "Rev E or earlier"); | |
744 | else | |
745 | /* we'll hardly ever ever get here */ | |
746 | edac_printk(KERN_ERR, EDAC_MC, "Unknown cpu!\n"); | |
747 | } | |
748 | ||
749 | /* | |
750 | * Determine if the DIMMs have ECC enabled. ECC is enabled ONLY if all the DIMMs | |
751 | * are ECC capable. | |
752 | */ | |
753 | static enum edac_type amd64_determine_edac_cap(struct amd64_pvt *pvt) | |
754 | { | |
755 | int bit; | |
756 | enum dev_type edac_cap = EDAC_NONE; | |
757 | ||
758 | bit = (boot_cpu_data.x86 > 0xf || pvt->ext_model >= OPTERON_CPU_REV_F) | |
759 | ? 19 | |
760 | : 17; | |
761 | ||
762 | if (pvt->dclr0 >> BIT(bit)) | |
763 | edac_cap = EDAC_FLAG_SECDED; | |
764 | ||
765 | return edac_cap; | |
766 | } | |
767 | ||
768 | ||
769 | static void f10_debug_display_dimm_sizes(int ctrl, struct amd64_pvt *pvt, | |
770 | int ganged); | |
771 | ||
772 | /* Display and decode various NB registers for debug purposes. */ | |
773 | static void amd64_dump_misc_regs(struct amd64_pvt *pvt) | |
774 | { | |
775 | int ganged; | |
776 | ||
777 | debugf1(" nbcap:0x%8.08x DctDualCap=%s DualNode=%s 8-Node=%s\n", | |
778 | pvt->nbcap, | |
779 | (pvt->nbcap & K8_NBCAP_DCT_DUAL) ? "True" : "False", | |
780 | (pvt->nbcap & K8_NBCAP_DUAL_NODE) ? "True" : "False", | |
781 | (pvt->nbcap & K8_NBCAP_8_NODE) ? "True" : "False"); | |
782 | debugf1(" ECC Capable=%s ChipKill Capable=%s\n", | |
783 | (pvt->nbcap & K8_NBCAP_SECDED) ? "True" : "False", | |
784 | (pvt->nbcap & K8_NBCAP_CHIPKILL) ? "True" : "False"); | |
785 | debugf1(" DramCfg0-low=0x%08x DIMM-ECC=%s Parity=%s Width=%s\n", | |
786 | pvt->dclr0, | |
787 | (pvt->dclr0 & BIT(19)) ? "Enabled" : "Disabled", | |
788 | (pvt->dclr0 & BIT(8)) ? "Enabled" : "Disabled", | |
789 | (pvt->dclr0 & BIT(11)) ? "128b" : "64b"); | |
790 | debugf1(" DIMM x4 Present: L0=%s L1=%s L2=%s L3=%s DIMM Type=%s\n", | |
791 | (pvt->dclr0 & BIT(12)) ? "Y" : "N", | |
792 | (pvt->dclr0 & BIT(13)) ? "Y" : "N", | |
793 | (pvt->dclr0 & BIT(14)) ? "Y" : "N", | |
794 | (pvt->dclr0 & BIT(15)) ? "Y" : "N", | |
795 | (pvt->dclr0 & BIT(16)) ? "UN-Buffered" : "Buffered"); | |
796 | ||
797 | ||
798 | debugf1(" online-spare: 0x%8.08x\n", pvt->online_spare); | |
799 | ||
800 | if (boot_cpu_data.x86 == 0xf) { | |
801 | debugf1(" dhar: 0x%8.08x Base=0x%08x Offset=0x%08x\n", | |
802 | pvt->dhar, dhar_base(pvt->dhar), | |
803 | k8_dhar_offset(pvt->dhar)); | |
804 | debugf1(" DramHoleValid=%s\n", | |
805 | (pvt->dhar & DHAR_VALID) ? "True" : "False"); | |
806 | ||
807 | debugf1(" dbam-dkt: 0x%8.08x\n", pvt->dbam0); | |
808 | ||
809 | /* everything below this point is Fam10h and above */ | |
810 | return; | |
811 | ||
812 | } else { | |
813 | debugf1(" dhar: 0x%8.08x Base=0x%08x Offset=0x%08x\n", | |
814 | pvt->dhar, dhar_base(pvt->dhar), | |
815 | f10_dhar_offset(pvt->dhar)); | |
816 | debugf1(" DramMemHoistValid=%s DramHoleValid=%s\n", | |
817 | (pvt->dhar & F10_DRAM_MEM_HOIST_VALID) ? | |
818 | "True" : "False", | |
819 | (pvt->dhar & DHAR_VALID) ? | |
820 | "True" : "False"); | |
821 | } | |
822 | ||
823 | /* Only if NOT ganged does dcl1 have valid info */ | |
824 | if (!dct_ganging_enabled(pvt)) { | |
825 | debugf1(" DramCfg1-low=0x%08x DIMM-ECC=%s Parity=%s " | |
826 | "Width=%s\n", pvt->dclr1, | |
827 | (pvt->dclr1 & BIT(19)) ? "Enabled" : "Disabled", | |
828 | (pvt->dclr1 & BIT(8)) ? "Enabled" : "Disabled", | |
829 | (pvt->dclr1 & BIT(11)) ? "128b" : "64b"); | |
830 | debugf1(" DIMM x4 Present: L0=%s L1=%s L2=%s L3=%s " | |
831 | "DIMM Type=%s\n", | |
832 | (pvt->dclr1 & BIT(12)) ? "Y" : "N", | |
833 | (pvt->dclr1 & BIT(13)) ? "Y" : "N", | |
834 | (pvt->dclr1 & BIT(14)) ? "Y" : "N", | |
835 | (pvt->dclr1 & BIT(15)) ? "Y" : "N", | |
836 | (pvt->dclr1 & BIT(16)) ? "UN-Buffered" : "Buffered"); | |
837 | } | |
838 | ||
839 | /* | |
840 | * Determine if ganged and then dump memory sizes for first controller, | |
841 | * and if NOT ganged dump info for 2nd controller. | |
842 | */ | |
843 | ganged = dct_ganging_enabled(pvt); | |
844 | ||
845 | f10_debug_display_dimm_sizes(0, pvt, ganged); | |
846 | ||
847 | if (!ganged) | |
848 | f10_debug_display_dimm_sizes(1, pvt, ganged); | |
849 | } | |
850 | ||
851 | /* Read in both of DBAM registers */ | |
852 | static void amd64_read_dbam_reg(struct amd64_pvt *pvt) | |
853 | { | |
854 | int err = 0; | |
855 | unsigned int reg; | |
856 | ||
857 | reg = DBAM0; | |
858 | err = pci_read_config_dword(pvt->dram_f2_ctl, reg, &pvt->dbam0); | |
859 | if (err) | |
860 | goto err_reg; | |
861 | ||
862 | if (boot_cpu_data.x86 >= 0x10) { | |
863 | reg = DBAM1; | |
864 | err = pci_read_config_dword(pvt->dram_f2_ctl, reg, &pvt->dbam1); | |
865 | ||
866 | if (err) | |
867 | goto err_reg; | |
868 | } | |
869 | ||
870 | err_reg: | |
871 | debugf0("Error reading F2x%03x.\n", reg); | |
872 | } | |
873 | ||
94be4bff DT |
874 | /* |
875 | * NOTE: CPU Revision Dependent code: Rev E and Rev F | |
876 | * | |
877 | * Set the DCSB and DCSM mask values depending on the CPU revision value. Also | |
878 | * set the shift factor for the DCSB and DCSM values. | |
879 | * | |
880 | * ->dcs_mask_notused, RevE: | |
881 | * | |
882 | * To find the max InputAddr for the csrow, start with the base address and set | |
883 | * all bits that are "don't care" bits in the test at the start of section | |
884 | * 3.5.4 (p. 84). | |
885 | * | |
886 | * The "don't care" bits are all set bits in the mask and all bits in the gaps | |
887 | * between bit ranges [35:25] and [19:13]. The value REV_E_DCS_NOTUSED_BITS | |
888 | * represents bits [24:20] and [12:0], which are all bits in the above-mentioned | |
889 | * gaps. | |
890 | * | |
891 | * ->dcs_mask_notused, RevF and later: | |
892 | * | |
893 | * To find the max InputAddr for the csrow, start with the base address and set | |
894 | * all bits that are "don't care" bits in the test at the start of NPT section | |
895 | * 4.5.4 (p. 87). | |
896 | * | |
897 | * The "don't care" bits are all set bits in the mask and all bits in the gaps | |
898 | * between bit ranges [36:27] and [21:13]. | |
899 | * | |
900 | * The value REV_F_F1Xh_DCS_NOTUSED_BITS represents bits [26:22] and [12:0], | |
901 | * which are all bits in the above-mentioned gaps. | |
902 | */ | |
903 | static void amd64_set_dct_base_and_mask(struct amd64_pvt *pvt) | |
904 | { | |
905 | if (pvt->ext_model >= OPTERON_CPU_REV_F) { | |
906 | pvt->dcsb_base = REV_F_F1Xh_DCSB_BASE_BITS; | |
907 | pvt->dcsm_mask = REV_F_F1Xh_DCSM_MASK_BITS; | |
908 | pvt->dcs_mask_notused = REV_F_F1Xh_DCS_NOTUSED_BITS; | |
909 | pvt->dcs_shift = REV_F_F1Xh_DCS_SHIFT; | |
910 | ||
911 | switch (boot_cpu_data.x86) { | |
912 | case 0xf: | |
913 | pvt->num_dcsm = REV_F_DCSM_COUNT; | |
914 | break; | |
915 | ||
916 | case 0x10: | |
917 | pvt->num_dcsm = F10_DCSM_COUNT; | |
918 | break; | |
919 | ||
920 | case 0x11: | |
921 | pvt->num_dcsm = F11_DCSM_COUNT; | |
922 | break; | |
923 | ||
924 | default: | |
925 | amd64_printk(KERN_ERR, "Unsupported family!\n"); | |
926 | break; | |
927 | } | |
928 | } else { | |
929 | pvt->dcsb_base = REV_E_DCSB_BASE_BITS; | |
930 | pvt->dcsm_mask = REV_E_DCSM_MASK_BITS; | |
931 | pvt->dcs_mask_notused = REV_E_DCS_NOTUSED_BITS; | |
932 | pvt->dcs_shift = REV_E_DCS_SHIFT; | |
933 | pvt->num_dcsm = REV_E_DCSM_COUNT; | |
934 | } | |
935 | } | |
936 | ||
937 | /* | |
938 | * Function 2 Offset F10_DCSB0; read in the DCS Base and DCS Mask hw registers | |
939 | */ | |
940 | static void amd64_read_dct_base_mask(struct amd64_pvt *pvt) | |
941 | { | |
942 | int cs, reg, err = 0; | |
943 | ||
944 | amd64_set_dct_base_and_mask(pvt); | |
945 | ||
946 | for (cs = 0; cs < CHIPSELECT_COUNT; cs++) { | |
947 | reg = K8_DCSB0 + (cs * 4); | |
948 | err = pci_read_config_dword(pvt->dram_f2_ctl, reg, | |
949 | &pvt->dcsb0[cs]); | |
950 | if (unlikely(err)) | |
951 | debugf0("Reading K8_DCSB0[%d] failed\n", cs); | |
952 | else | |
953 | debugf0(" DCSB0[%d]=0x%08x reg: F2x%x\n", | |
954 | cs, pvt->dcsb0[cs], reg); | |
955 | ||
956 | /* If DCT are NOT ganged, then read in DCT1's base */ | |
957 | if (boot_cpu_data.x86 >= 0x10 && !dct_ganging_enabled(pvt)) { | |
958 | reg = F10_DCSB1 + (cs * 4); | |
959 | err = pci_read_config_dword(pvt->dram_f2_ctl, reg, | |
960 | &pvt->dcsb1[cs]); | |
961 | if (unlikely(err)) | |
962 | debugf0("Reading F10_DCSB1[%d] failed\n", cs); | |
963 | else | |
964 | debugf0(" DCSB1[%d]=0x%08x reg: F2x%x\n", | |
965 | cs, pvt->dcsb1[cs], reg); | |
966 | } else { | |
967 | pvt->dcsb1[cs] = 0; | |
968 | } | |
969 | } | |
970 | ||
971 | for (cs = 0; cs < pvt->num_dcsm; cs++) { | |
972 | reg = K8_DCSB0 + (cs * 4); | |
973 | err = pci_read_config_dword(pvt->dram_f2_ctl, reg, | |
974 | &pvt->dcsm0[cs]); | |
975 | if (unlikely(err)) | |
976 | debugf0("Reading K8_DCSM0 failed\n"); | |
977 | else | |
978 | debugf0(" DCSM0[%d]=0x%08x reg: F2x%x\n", | |
979 | cs, pvt->dcsm0[cs], reg); | |
980 | ||
981 | /* If DCT are NOT ganged, then read in DCT1's mask */ | |
982 | if (boot_cpu_data.x86 >= 0x10 && !dct_ganging_enabled(pvt)) { | |
983 | reg = F10_DCSM1 + (cs * 4); | |
984 | err = pci_read_config_dword(pvt->dram_f2_ctl, reg, | |
985 | &pvt->dcsm1[cs]); | |
986 | if (unlikely(err)) | |
987 | debugf0("Reading F10_DCSM1[%d] failed\n", cs); | |
988 | else | |
989 | debugf0(" DCSM1[%d]=0x%08x reg: F2x%x\n", | |
990 | cs, pvt->dcsm1[cs], reg); | |
991 | } else | |
992 | pvt->dcsm1[cs] = 0; | |
993 | } | |
994 | } | |
995 | ||
996 | static enum mem_type amd64_determine_memory_type(struct amd64_pvt *pvt) | |
997 | { | |
998 | enum mem_type type; | |
999 | ||
1000 | if (boot_cpu_data.x86 >= 0x10 || pvt->ext_model >= OPTERON_CPU_REV_F) { | |
1001 | /* Rev F and later */ | |
1002 | type = (pvt->dclr0 & BIT(16)) ? MEM_DDR2 : MEM_RDDR2; | |
1003 | } else { | |
1004 | /* Rev E and earlier */ | |
1005 | type = (pvt->dclr0 & BIT(18)) ? MEM_DDR : MEM_RDDR; | |
1006 | } | |
1007 | ||
1008 | debugf1(" Memory type is: %s\n", | |
1009 | (type == MEM_DDR2) ? "MEM_DDR2" : | |
1010 | (type == MEM_RDDR2) ? "MEM_RDDR2" : | |
1011 | (type == MEM_DDR) ? "MEM_DDR" : "MEM_RDDR"); | |
1012 | ||
1013 | return type; | |
1014 | } | |
1015 | ||
ddff876d DT |
1016 | /* |
1017 | * Read the DRAM Configuration Low register. It differs between CG, D & E revs | |
1018 | * and the later RevF memory controllers (DDR vs DDR2) | |
1019 | * | |
1020 | * Return: | |
1021 | * number of memory channels in operation | |
1022 | * Pass back: | |
1023 | * contents of the DCL0_LOW register | |
1024 | */ | |
1025 | static int k8_early_channel_count(struct amd64_pvt *pvt) | |
1026 | { | |
1027 | int flag, err = 0; | |
1028 | ||
1029 | err = pci_read_config_dword(pvt->dram_f2_ctl, F10_DCLR_0, &pvt->dclr0); | |
1030 | if (err) | |
1031 | return err; | |
1032 | ||
1033 | if ((boot_cpu_data.x86_model >> 4) >= OPTERON_CPU_REV_F) { | |
1034 | /* RevF (NPT) and later */ | |
1035 | flag = pvt->dclr0 & F10_WIDTH_128; | |
1036 | } else { | |
1037 | /* RevE and earlier */ | |
1038 | flag = pvt->dclr0 & REVE_WIDTH_128; | |
1039 | } | |
1040 | ||
1041 | /* not used */ | |
1042 | pvt->dclr1 = 0; | |
1043 | ||
1044 | return (flag) ? 2 : 1; | |
1045 | } | |
1046 | ||
1047 | /* extract the ERROR ADDRESS for the K8 CPUs */ | |
1048 | static u64 k8_get_error_address(struct mem_ctl_info *mci, | |
1049 | struct amd64_error_info_regs *info) | |
1050 | { | |
1051 | return (((u64) (info->nbeah & 0xff)) << 32) + | |
1052 | (info->nbeal & ~0x03); | |
1053 | } | |
1054 | ||
1055 | /* | |
1056 | * Read the Base and Limit registers for K8 based Memory controllers; extract | |
1057 | * fields from the 'raw' reg into separate data fields | |
1058 | * | |
1059 | * Isolates: BASE, LIMIT, IntlvEn, IntlvSel, RW_EN | |
1060 | */ | |
1061 | static void k8_read_dram_base_limit(struct amd64_pvt *pvt, int dram) | |
1062 | { | |
1063 | u32 low; | |
1064 | u32 off = dram << 3; /* 8 bytes between DRAM entries */ | |
1065 | int err; | |
1066 | ||
1067 | err = pci_read_config_dword(pvt->addr_f1_ctl, | |
1068 | K8_DRAM_BASE_LOW + off, &low); | |
1069 | if (err) | |
1070 | debugf0("Reading K8_DRAM_BASE_LOW failed\n"); | |
1071 | ||
1072 | /* Extract parts into separate data entries */ | |
1073 | pvt->dram_base[dram] = ((u64) low & 0xFFFF0000) << 8; | |
1074 | pvt->dram_IntlvEn[dram] = (low >> 8) & 0x7; | |
1075 | pvt->dram_rw_en[dram] = (low & 0x3); | |
1076 | ||
1077 | err = pci_read_config_dword(pvt->addr_f1_ctl, | |
1078 | K8_DRAM_LIMIT_LOW + off, &low); | |
1079 | if (err) | |
1080 | debugf0("Reading K8_DRAM_LIMIT_LOW failed\n"); | |
1081 | ||
1082 | /* | |
1083 | * Extract parts into separate data entries. Limit is the HIGHEST memory | |
1084 | * location of the region, so lower 24 bits need to be all ones | |
1085 | */ | |
1086 | pvt->dram_limit[dram] = (((u64) low & 0xFFFF0000) << 8) | 0x00FFFFFF; | |
1087 | pvt->dram_IntlvSel[dram] = (low >> 8) & 0x7; | |
1088 | pvt->dram_DstNode[dram] = (low & 0x7); | |
1089 | } | |
1090 | ||
1091 | static void k8_map_sysaddr_to_csrow(struct mem_ctl_info *mci, | |
1092 | struct amd64_error_info_regs *info, | |
1093 | u64 SystemAddress) | |
1094 | { | |
1095 | struct mem_ctl_info *src_mci; | |
1096 | unsigned short syndrome; | |
1097 | int channel, csrow; | |
1098 | u32 page, offset; | |
1099 | ||
1100 | /* Extract the syndrome parts and form a 16-bit syndrome */ | |
1101 | syndrome = EXTRACT_HIGH_SYNDROME(info->nbsl) << 8; | |
1102 | syndrome |= EXTRACT_LOW_SYNDROME(info->nbsh); | |
1103 | ||
1104 | /* CHIPKILL enabled */ | |
1105 | if (info->nbcfg & K8_NBCFG_CHIPKILL) { | |
1106 | channel = get_channel_from_ecc_syndrome(syndrome); | |
1107 | if (channel < 0) { | |
1108 | /* | |
1109 | * Syndrome didn't map, so we don't know which of the | |
1110 | * 2 DIMMs is in error. So we need to ID 'both' of them | |
1111 | * as suspect. | |
1112 | */ | |
1113 | amd64_mc_printk(mci, KERN_WARNING, | |
1114 | "unknown syndrome 0x%x - possible error " | |
1115 | "reporting race\n", syndrome); | |
1116 | edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR); | |
1117 | return; | |
1118 | } | |
1119 | } else { | |
1120 | /* | |
1121 | * non-chipkill ecc mode | |
1122 | * | |
1123 | * The k8 documentation is unclear about how to determine the | |
1124 | * channel number when using non-chipkill memory. This method | |
1125 | * was obtained from email communication with someone at AMD. | |
1126 | * (Wish the email was placed in this comment - norsk) | |
1127 | */ | |
1128 | channel = ((SystemAddress & BIT(3)) != 0); | |
1129 | } | |
1130 | ||
1131 | /* | |
1132 | * Find out which node the error address belongs to. This may be | |
1133 | * different from the node that detected the error. | |
1134 | */ | |
1135 | src_mci = find_mc_by_sys_addr(mci, SystemAddress); | |
1136 | if (src_mci) { | |
1137 | amd64_mc_printk(mci, KERN_ERR, | |
1138 | "failed to map error address 0x%lx to a node\n", | |
1139 | (unsigned long)SystemAddress); | |
1140 | edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR); | |
1141 | return; | |
1142 | } | |
1143 | ||
1144 | /* Now map the SystemAddress to a CSROW */ | |
1145 | csrow = sys_addr_to_csrow(src_mci, SystemAddress); | |
1146 | if (csrow < 0) { | |
1147 | edac_mc_handle_ce_no_info(src_mci, EDAC_MOD_STR); | |
1148 | } else { | |
1149 | error_address_to_page_and_offset(SystemAddress, &page, &offset); | |
1150 | ||
1151 | edac_mc_handle_ce(src_mci, page, offset, syndrome, csrow, | |
1152 | channel, EDAC_MOD_STR); | |
1153 | } | |
1154 | } | |
1155 | ||
1156 | /* | |
1157 | * determrine the number of PAGES in for this DIMM's size based on its DRAM | |
1158 | * Address Mapping. | |
1159 | * | |
1160 | * First step is to calc the number of bits to shift a value of 1 left to | |
1161 | * indicate show many pages. Start with the DBAM value as the starting bits, | |
1162 | * then proceed to adjust those shift bits, based on CPU rev and the table. | |
1163 | * See BKDG on the DBAM | |
1164 | */ | |
1165 | static int k8_dbam_map_to_pages(struct amd64_pvt *pvt, int dram_map) | |
1166 | { | |
1167 | int nr_pages; | |
1168 | ||
1169 | if (pvt->ext_model >= OPTERON_CPU_REV_F) { | |
1170 | nr_pages = 1 << (revf_quad_ddr2_shift[dram_map] - PAGE_SHIFT); | |
1171 | } else { | |
1172 | /* | |
1173 | * RevE and less section; this line is tricky. It collapses the | |
1174 | * table used by RevD and later to one that matches revisions CG | |
1175 | * and earlier. | |
1176 | */ | |
1177 | dram_map -= (pvt->ext_model >= OPTERON_CPU_REV_D) ? | |
1178 | (dram_map > 8 ? 4 : (dram_map > 5 ? | |
1179 | 3 : (dram_map > 2 ? 1 : 0))) : 0; | |
1180 | ||
1181 | /* 25 shift is 32MiB minimum DIMM size in RevE and prior */ | |
1182 | nr_pages = 1 << (dram_map + 25 - PAGE_SHIFT); | |
1183 | } | |
1184 | ||
1185 | return nr_pages; | |
1186 | } | |
1187 | ||
1afd3c98 DT |
1188 | /* |
1189 | * Get the number of DCT channels in use. | |
1190 | * | |
1191 | * Return: | |
1192 | * number of Memory Channels in operation | |
1193 | * Pass back: | |
1194 | * contents of the DCL0_LOW register | |
1195 | */ | |
1196 | static int f10_early_channel_count(struct amd64_pvt *pvt) | |
1197 | { | |
1198 | int err = 0, channels = 0; | |
1199 | u32 dbam; | |
1200 | ||
1201 | err = pci_read_config_dword(pvt->dram_f2_ctl, F10_DCLR_0, &pvt->dclr0); | |
1202 | if (err) | |
1203 | goto err_reg; | |
1204 | ||
1205 | err = pci_read_config_dword(pvt->dram_f2_ctl, F10_DCLR_1, &pvt->dclr1); | |
1206 | if (err) | |
1207 | goto err_reg; | |
1208 | ||
1209 | /* If we are in 128 bit mode, then we are using 2 channels */ | |
1210 | if (pvt->dclr0 & F10_WIDTH_128) { | |
1211 | debugf0("Data WIDTH is 128 bits - 2 channels\n"); | |
1212 | channels = 2; | |
1213 | return channels; | |
1214 | } | |
1215 | ||
1216 | /* | |
1217 | * Need to check if in UN-ganged mode: In such, there are 2 channels, | |
1218 | * but they are NOT in 128 bit mode and thus the above 'dcl0' status bit | |
1219 | * will be OFF. | |
1220 | * | |
1221 | * Need to check DCT0[0] and DCT1[0] to see if only one of them has | |
1222 | * their CSEnable bit on. If so, then SINGLE DIMM case. | |
1223 | */ | |
1224 | debugf0("Data WIDTH is NOT 128 bits - need more decoding\n"); | |
ddff876d | 1225 | |
1afd3c98 DT |
1226 | /* |
1227 | * Check DRAM Bank Address Mapping values for each DIMM to see if there | |
1228 | * is more than just one DIMM present in unganged mode. Need to check | |
1229 | * both controllers since DIMMs can be placed in either one. | |
1230 | */ | |
1231 | channels = 0; | |
1232 | err = pci_read_config_dword(pvt->dram_f2_ctl, DBAM0, &dbam); | |
1233 | if (err) | |
1234 | goto err_reg; | |
1235 | ||
1236 | if (DBAM_DIMM(0, dbam) > 0) | |
1237 | channels++; | |
1238 | if (DBAM_DIMM(1, dbam) > 0) | |
1239 | channels++; | |
1240 | if (DBAM_DIMM(2, dbam) > 0) | |
1241 | channels++; | |
1242 | if (DBAM_DIMM(3, dbam) > 0) | |
1243 | channels++; | |
1244 | ||
1245 | /* If more than 2 DIMMs are present, then we have 2 channels */ | |
1246 | if (channels > 2) | |
1247 | channels = 2; | |
1248 | else if (channels == 0) { | |
1249 | /* No DIMMs on DCT0, so look at DCT1 */ | |
1250 | err = pci_read_config_dword(pvt->dram_f2_ctl, DBAM1, &dbam); | |
1251 | if (err) | |
1252 | goto err_reg; | |
1253 | ||
1254 | if (DBAM_DIMM(0, dbam) > 0) | |
1255 | channels++; | |
1256 | if (DBAM_DIMM(1, dbam) > 0) | |
1257 | channels++; | |
1258 | if (DBAM_DIMM(2, dbam) > 0) | |
1259 | channels++; | |
1260 | if (DBAM_DIMM(3, dbam) > 0) | |
1261 | channels++; | |
1262 | ||
1263 | if (channels > 2) | |
1264 | channels = 2; | |
1265 | } | |
1266 | ||
1267 | /* If we found ALL 0 values, then assume just ONE DIMM-ONE Channel */ | |
1268 | if (channels == 0) | |
1269 | channels = 1; | |
1270 | ||
1271 | debugf0("DIMM count= %d\n", channels); | |
1272 | ||
1273 | return channels; | |
1274 | ||
1275 | err_reg: | |
1276 | return -1; | |
1277 | ||
1278 | } | |
1279 | ||
1280 | static int f10_dbam_map_to_pages(struct amd64_pvt *pvt, int dram_map) | |
1281 | { | |
1282 | return 1 << (revf_quad_ddr2_shift[dram_map] - PAGE_SHIFT); | |
1283 | } | |
1284 | ||
1285 | /* Enable extended configuration access via 0xCF8 feature */ | |
1286 | static void amd64_setup(struct amd64_pvt *pvt) | |
1287 | { | |
1288 | u32 reg; | |
1289 | ||
1290 | pci_read_config_dword(pvt->misc_f3_ctl, F10_NB_CFG_HIGH, ®); | |
1291 | ||
1292 | pvt->flags.cf8_extcfg = !!(reg & F10_NB_CFG_LOW_ENABLE_EXT_CFG); | |
1293 | reg |= F10_NB_CFG_LOW_ENABLE_EXT_CFG; | |
1294 | pci_write_config_dword(pvt->misc_f3_ctl, F10_NB_CFG_HIGH, reg); | |
1295 | } | |
1296 | ||
1297 | /* Restore the extended configuration access via 0xCF8 feature */ | |
1298 | static void amd64_teardown(struct amd64_pvt *pvt) | |
1299 | { | |
1300 | u32 reg; | |
1301 | ||
1302 | pci_read_config_dword(pvt->misc_f3_ctl, F10_NB_CFG_HIGH, ®); | |
1303 | ||
1304 | reg &= ~F10_NB_CFG_LOW_ENABLE_EXT_CFG; | |
1305 | if (pvt->flags.cf8_extcfg) | |
1306 | reg |= F10_NB_CFG_LOW_ENABLE_EXT_CFG; | |
1307 | pci_write_config_dword(pvt->misc_f3_ctl, F10_NB_CFG_HIGH, reg); | |
1308 | } | |
1309 | ||
1310 | static u64 f10_get_error_address(struct mem_ctl_info *mci, | |
1311 | struct amd64_error_info_regs *info) | |
1312 | { | |
1313 | return (((u64) (info->nbeah & 0xffff)) << 32) + | |
1314 | (info->nbeal & ~0x01); | |
1315 | } | |
1316 | ||
1317 | /* | |
1318 | * Read the Base and Limit registers for F10 based Memory controllers. Extract | |
1319 | * fields from the 'raw' reg into separate data fields. | |
1320 | * | |
1321 | * Isolates: BASE, LIMIT, IntlvEn, IntlvSel, RW_EN. | |
1322 | */ | |
1323 | static void f10_read_dram_base_limit(struct amd64_pvt *pvt, int dram) | |
1324 | { | |
1325 | u32 high_offset, low_offset, high_base, low_base, high_limit, low_limit; | |
1326 | ||
1327 | low_offset = K8_DRAM_BASE_LOW + (dram << 3); | |
1328 | high_offset = F10_DRAM_BASE_HIGH + (dram << 3); | |
1329 | ||
1330 | /* read the 'raw' DRAM BASE Address register */ | |
1331 | pci_read_config_dword(pvt->addr_f1_ctl, low_offset, &low_base); | |
1332 | ||
1333 | /* Read from the ECS data register */ | |
1334 | pci_read_config_dword(pvt->addr_f1_ctl, high_offset, &high_base); | |
1335 | ||
1336 | /* Extract parts into separate data entries */ | |
1337 | pvt->dram_rw_en[dram] = (low_base & 0x3); | |
1338 | ||
1339 | if (pvt->dram_rw_en[dram] == 0) | |
1340 | return; | |
1341 | ||
1342 | pvt->dram_IntlvEn[dram] = (low_base >> 8) & 0x7; | |
1343 | ||
1344 | pvt->dram_base[dram] = (((((u64) high_base & 0x000000FF) << 32) | | |
1345 | ((u64) low_base & 0xFFFF0000))) << 8; | |
1346 | ||
1347 | low_offset = K8_DRAM_LIMIT_LOW + (dram << 3); | |
1348 | high_offset = F10_DRAM_LIMIT_HIGH + (dram << 3); | |
1349 | ||
1350 | /* read the 'raw' LIMIT registers */ | |
1351 | pci_read_config_dword(pvt->addr_f1_ctl, low_offset, &low_limit); | |
1352 | ||
1353 | /* Read from the ECS data register for the HIGH portion */ | |
1354 | pci_read_config_dword(pvt->addr_f1_ctl, high_offset, &high_limit); | |
1355 | ||
1356 | debugf0(" HW Regs: BASE=0x%08x-%08x LIMIT= 0x%08x-%08x\n", | |
1357 | high_base, low_base, high_limit, low_limit); | |
1358 | ||
1359 | pvt->dram_DstNode[dram] = (low_limit & 0x7); | |
1360 | pvt->dram_IntlvSel[dram] = (low_limit >> 8) & 0x7; | |
1361 | ||
1362 | /* | |
1363 | * Extract address values and form a LIMIT address. Limit is the HIGHEST | |
1364 | * memory location of the region, so low 24 bits need to be all ones. | |
1365 | */ | |
1366 | low_limit |= 0x0000FFFF; | |
1367 | pvt->dram_limit[dram] = | |
1368 | ((((u64) high_limit << 32) + (u64) low_limit) << 8) | (0xFF); | |
1369 | } | |
6163b5d4 DT |
1370 | |
1371 | static void f10_read_dram_ctl_register(struct amd64_pvt *pvt) | |
1372 | { | |
1373 | int err = 0; | |
1374 | ||
1375 | err = pci_read_config_dword(pvt->dram_f2_ctl, F10_DCTL_SEL_LOW, | |
1376 | &pvt->dram_ctl_select_low); | |
1377 | if (err) { | |
1378 | debugf0("Reading F10_DCTL_SEL_LOW failed\n"); | |
1379 | } else { | |
1380 | debugf0("DRAM_DCTL_SEL_LOW=0x%x DctSelBaseAddr=0x%x\n", | |
1381 | pvt->dram_ctl_select_low, dct_sel_baseaddr(pvt)); | |
1382 | ||
1383 | debugf0(" DRAM DCTs are=%s DRAM Is=%s DRAM-Ctl-" | |
1384 | "sel-hi-range=%s\n", | |
1385 | (dct_ganging_enabled(pvt) ? "GANGED" : "NOT GANGED"), | |
1386 | (dct_dram_enabled(pvt) ? "Enabled" : "Disabled"), | |
1387 | (dct_high_range_enabled(pvt) ? "Enabled" : "Disabled")); | |
1388 | ||
1389 | debugf0(" DctDatIntLv=%s MemCleared=%s DctSelIntLvAddr=0x%x\n", | |
1390 | (dct_data_intlv_enabled(pvt) ? "Enabled" : "Disabled"), | |
1391 | (dct_memory_cleared(pvt) ? "True " : "False "), | |
1392 | dct_sel_interleave_addr(pvt)); | |
1393 | } | |
1394 | ||
1395 | err = pci_read_config_dword(pvt->dram_f2_ctl, F10_DCTL_SEL_HIGH, | |
1396 | &pvt->dram_ctl_select_high); | |
1397 | if (err) | |
1398 | debugf0("Reading F10_DCTL_SEL_HIGH failed\n"); | |
1399 | } | |
1400 | ||
f71d0a05 DT |
1401 | /* |
1402 | * determine channel based on the interleaving mode: F10h BKDG, 2.8.9 Memory | |
1403 | * Interleaving Modes. | |
1404 | */ | |
6163b5d4 DT |
1405 | static u32 f10_determine_channel(struct amd64_pvt *pvt, u64 sys_addr, |
1406 | int hi_range_sel, u32 intlv_en) | |
1407 | { | |
1408 | u32 cs, temp, dct_sel_high = (pvt->dram_ctl_select_low >> 1) & 1; | |
1409 | ||
1410 | if (dct_ganging_enabled(pvt)) | |
1411 | cs = 0; | |
1412 | else if (hi_range_sel) | |
1413 | cs = dct_sel_high; | |
1414 | else if (dct_interleave_enabled(pvt)) { | |
f71d0a05 DT |
1415 | /* |
1416 | * see F2x110[DctSelIntLvAddr] - channel interleave mode | |
1417 | */ | |
6163b5d4 DT |
1418 | if (dct_sel_interleave_addr(pvt) == 0) |
1419 | cs = sys_addr >> 6 & 1; | |
1420 | else if ((dct_sel_interleave_addr(pvt) >> 1) & 1) { | |
1421 | temp = hweight_long((u32) ((sys_addr >> 16) & 0x1F)) % 2; | |
1422 | ||
1423 | if (dct_sel_interleave_addr(pvt) & 1) | |
1424 | cs = (sys_addr >> 9 & 1) ^ temp; | |
1425 | else | |
1426 | cs = (sys_addr >> 6 & 1) ^ temp; | |
1427 | } else if (intlv_en & 4) | |
1428 | cs = sys_addr >> 15 & 1; | |
1429 | else if (intlv_en & 2) | |
1430 | cs = sys_addr >> 14 & 1; | |
1431 | else if (intlv_en & 1) | |
1432 | cs = sys_addr >> 13 & 1; | |
1433 | else | |
1434 | cs = sys_addr >> 12 & 1; | |
1435 | } else if (dct_high_range_enabled(pvt) && !dct_ganging_enabled(pvt)) | |
1436 | cs = ~dct_sel_high & 1; | |
1437 | else | |
1438 | cs = 0; | |
1439 | ||
1440 | return cs; | |
1441 | } | |
1442 | ||
1443 | static inline u32 f10_map_intlv_en_to_shift(u32 intlv_en) | |
1444 | { | |
1445 | if (intlv_en == 1) | |
1446 | return 1; | |
1447 | else if (intlv_en == 3) | |
1448 | return 2; | |
1449 | else if (intlv_en == 7) | |
1450 | return 3; | |
1451 | ||
1452 | return 0; | |
1453 | } | |
1454 | ||
f71d0a05 DT |
1455 | /* See F10h BKDG, 2.8.10.2 DctSelBaseOffset Programming */ |
1456 | static inline u64 f10_get_base_addr_offset(u64 sys_addr, int hi_range_sel, | |
6163b5d4 DT |
1457 | u32 dct_sel_base_addr, |
1458 | u64 dct_sel_base_off, | |
f71d0a05 | 1459 | u32 hole_valid, u32 hole_off, |
6163b5d4 DT |
1460 | u64 dram_base) |
1461 | { | |
1462 | u64 chan_off; | |
1463 | ||
1464 | if (hi_range_sel) { | |
1465 | if (!(dct_sel_base_addr & 0xFFFFF800) && | |
f71d0a05 | 1466 | hole_valid && (sys_addr >= 0x100000000ULL)) |
6163b5d4 DT |
1467 | chan_off = hole_off << 16; |
1468 | else | |
1469 | chan_off = dct_sel_base_off; | |
1470 | } else { | |
f71d0a05 | 1471 | if (hole_valid && (sys_addr >= 0x100000000ULL)) |
6163b5d4 DT |
1472 | chan_off = hole_off << 16; |
1473 | else | |
1474 | chan_off = dram_base & 0xFFFFF8000000ULL; | |
1475 | } | |
1476 | ||
1477 | return (sys_addr & 0x0000FFFFFFFFFFC0ULL) - | |
1478 | (chan_off & 0x0000FFFFFF800000ULL); | |
1479 | } | |
1480 | ||
1481 | /* Hack for the time being - Can we get this from BIOS?? */ | |
1482 | #define CH0SPARE_RANK 0 | |
1483 | #define CH1SPARE_RANK 1 | |
1484 | ||
1485 | /* | |
1486 | * checks if the csrow passed in is marked as SPARED, if so returns the new | |
1487 | * spare row | |
1488 | */ | |
1489 | static inline int f10_process_possible_spare(int csrow, | |
1490 | u32 cs, struct amd64_pvt *pvt) | |
1491 | { | |
1492 | u32 swap_done; | |
1493 | u32 bad_dram_cs; | |
1494 | ||
1495 | /* Depending on channel, isolate respective SPARING info */ | |
1496 | if (cs) { | |
1497 | swap_done = F10_ONLINE_SPARE_SWAPDONE1(pvt->online_spare); | |
1498 | bad_dram_cs = F10_ONLINE_SPARE_BADDRAM_CS1(pvt->online_spare); | |
1499 | if (swap_done && (csrow == bad_dram_cs)) | |
1500 | csrow = CH1SPARE_RANK; | |
1501 | } else { | |
1502 | swap_done = F10_ONLINE_SPARE_SWAPDONE0(pvt->online_spare); | |
1503 | bad_dram_cs = F10_ONLINE_SPARE_BADDRAM_CS0(pvt->online_spare); | |
1504 | if (swap_done && (csrow == bad_dram_cs)) | |
1505 | csrow = CH0SPARE_RANK; | |
1506 | } | |
1507 | return csrow; | |
1508 | } | |
1509 | ||
1510 | /* | |
1511 | * Iterate over the DRAM DCT "base" and "mask" registers looking for a | |
1512 | * SystemAddr match on the specified 'ChannelSelect' and 'NodeID' | |
1513 | * | |
1514 | * Return: | |
1515 | * -EINVAL: NOT FOUND | |
1516 | * 0..csrow = Chip-Select Row | |
1517 | */ | |
1518 | static int f10_lookup_addr_in_dct(u32 in_addr, u32 nid, u32 cs) | |
1519 | { | |
1520 | struct mem_ctl_info *mci; | |
1521 | struct amd64_pvt *pvt; | |
1522 | u32 cs_base, cs_mask; | |
1523 | int cs_found = -EINVAL; | |
1524 | int csrow; | |
1525 | ||
1526 | mci = mci_lookup[nid]; | |
1527 | if (!mci) | |
1528 | return cs_found; | |
1529 | ||
1530 | pvt = mci->pvt_info; | |
1531 | ||
1532 | debugf1("InputAddr=0x%x channelselect=%d\n", in_addr, cs); | |
1533 | ||
1534 | for (csrow = 0; csrow < CHIPSELECT_COUNT; csrow++) { | |
1535 | ||
1536 | cs_base = amd64_get_dct_base(pvt, cs, csrow); | |
1537 | if (!(cs_base & K8_DCSB_CS_ENABLE)) | |
1538 | continue; | |
1539 | ||
1540 | /* | |
1541 | * We have an ENABLED CSROW, Isolate just the MASK bits of the | |
1542 | * target: [28:19] and [13:5], which map to [36:27] and [21:13] | |
1543 | * of the actual address. | |
1544 | */ | |
1545 | cs_base &= REV_F_F1Xh_DCSB_BASE_BITS; | |
1546 | ||
1547 | /* | |
1548 | * Get the DCT Mask, and ENABLE the reserved bits: [18:16] and | |
1549 | * [4:0] to become ON. Then mask off bits [28:0] ([36:8]) | |
1550 | */ | |
1551 | cs_mask = amd64_get_dct_mask(pvt, cs, csrow); | |
1552 | ||
1553 | debugf1(" CSROW=%d CSBase=0x%x RAW CSMask=0x%x\n", | |
1554 | csrow, cs_base, cs_mask); | |
1555 | ||
1556 | cs_mask = (cs_mask | 0x0007C01F) & 0x1FFFFFFF; | |
1557 | ||
1558 | debugf1(" Final CSMask=0x%x\n", cs_mask); | |
1559 | debugf1(" (InputAddr & ~CSMask)=0x%x " | |
1560 | "(CSBase & ~CSMask)=0x%x\n", | |
1561 | (in_addr & ~cs_mask), (cs_base & ~cs_mask)); | |
1562 | ||
1563 | if ((in_addr & ~cs_mask) == (cs_base & ~cs_mask)) { | |
1564 | cs_found = f10_process_possible_spare(csrow, cs, pvt); | |
1565 | ||
1566 | debugf1(" MATCH csrow=%d\n", cs_found); | |
1567 | break; | |
1568 | } | |
1569 | } | |
1570 | return cs_found; | |
1571 | } | |
1572 | ||
f71d0a05 DT |
1573 | /* For a given @dram_range, check if @sys_addr falls within it. */ |
1574 | static int f10_match_to_this_node(struct amd64_pvt *pvt, int dram_range, | |
1575 | u64 sys_addr, int *nid, int *chan_sel) | |
1576 | { | |
1577 | int node_id, cs_found = -EINVAL, high_range = 0; | |
1578 | u32 intlv_en, intlv_sel, intlv_shift, hole_off; | |
1579 | u32 hole_valid, tmp, dct_sel_base, channel; | |
1580 | u64 dram_base, chan_addr, dct_sel_base_off; | |
1581 | ||
1582 | dram_base = pvt->dram_base[dram_range]; | |
1583 | intlv_en = pvt->dram_IntlvEn[dram_range]; | |
1584 | ||
1585 | node_id = pvt->dram_DstNode[dram_range]; | |
1586 | intlv_sel = pvt->dram_IntlvSel[dram_range]; | |
1587 | ||
1588 | debugf1("(dram=%d) Base=0x%llx SystemAddr= 0x%llx Limit=0x%llx\n", | |
1589 | dram_range, dram_base, sys_addr, pvt->dram_limit[dram_range]); | |
1590 | ||
1591 | /* | |
1592 | * This assumes that one node's DHAR is the same as all the other | |
1593 | * nodes' DHAR. | |
1594 | */ | |
1595 | hole_off = (pvt->dhar & 0x0000FF80); | |
1596 | hole_valid = (pvt->dhar & 0x1); | |
1597 | dct_sel_base_off = (pvt->dram_ctl_select_high & 0xFFFFFC00) << 16; | |
1598 | ||
1599 | debugf1(" HoleOffset=0x%x HoleValid=0x%x IntlvSel=0x%x\n", | |
1600 | hole_off, hole_valid, intlv_sel); | |
1601 | ||
1602 | if (intlv_en || | |
1603 | (intlv_sel != ((sys_addr >> 12) & intlv_en))) | |
1604 | return -EINVAL; | |
1605 | ||
1606 | dct_sel_base = dct_sel_baseaddr(pvt); | |
1607 | ||
1608 | /* | |
1609 | * check whether addresses >= DctSelBaseAddr[47:27] are to be used to | |
1610 | * select between DCT0 and DCT1. | |
1611 | */ | |
1612 | if (dct_high_range_enabled(pvt) && | |
1613 | !dct_ganging_enabled(pvt) && | |
1614 | ((sys_addr >> 27) >= (dct_sel_base >> 11))) | |
1615 | high_range = 1; | |
1616 | ||
1617 | channel = f10_determine_channel(pvt, sys_addr, high_range, intlv_en); | |
1618 | ||
1619 | chan_addr = f10_get_base_addr_offset(sys_addr, high_range, dct_sel_base, | |
1620 | dct_sel_base_off, hole_valid, | |
1621 | hole_off, dram_base); | |
1622 | ||
1623 | intlv_shift = f10_map_intlv_en_to_shift(intlv_en); | |
1624 | ||
1625 | /* remove Node ID (in case of memory interleaving) */ | |
1626 | tmp = chan_addr & 0xFC0; | |
1627 | ||
1628 | chan_addr = ((chan_addr >> intlv_shift) & 0xFFFFFFFFF000ULL) | tmp; | |
1629 | ||
1630 | /* remove channel interleave and hash */ | |
1631 | if (dct_interleave_enabled(pvt) && | |
1632 | !dct_high_range_enabled(pvt) && | |
1633 | !dct_ganging_enabled(pvt)) { | |
1634 | if (dct_sel_interleave_addr(pvt) != 1) | |
1635 | chan_addr = (chan_addr >> 1) & 0xFFFFFFFFFFFFFFC0ULL; | |
1636 | else { | |
1637 | tmp = chan_addr & 0xFC0; | |
1638 | chan_addr = ((chan_addr & 0xFFFFFFFFFFFFC000ULL) >> 1) | |
1639 | | tmp; | |
1640 | } | |
1641 | } | |
1642 | ||
1643 | debugf1(" (ChannelAddrLong=0x%llx) >> 8 becomes InputAddr=0x%x\n", | |
1644 | chan_addr, (u32)(chan_addr >> 8)); | |
1645 | ||
1646 | cs_found = f10_lookup_addr_in_dct(chan_addr >> 8, node_id, channel); | |
1647 | ||
1648 | if (cs_found >= 0) { | |
1649 | *nid = node_id; | |
1650 | *chan_sel = channel; | |
1651 | } | |
1652 | return cs_found; | |
1653 | } | |
1654 | ||
1655 | static int f10_translate_sysaddr_to_cs(struct amd64_pvt *pvt, u64 sys_addr, | |
1656 | int *node, int *chan_sel) | |
1657 | { | |
1658 | int dram_range, cs_found = -EINVAL; | |
1659 | u64 dram_base, dram_limit; | |
1660 | ||
1661 | for (dram_range = 0; dram_range < DRAM_REG_COUNT; dram_range++) { | |
1662 | ||
1663 | if (!pvt->dram_rw_en[dram_range]) | |
1664 | continue; | |
1665 | ||
1666 | dram_base = pvt->dram_base[dram_range]; | |
1667 | dram_limit = pvt->dram_limit[dram_range]; | |
1668 | ||
1669 | if ((dram_base <= sys_addr) && (sys_addr <= dram_limit)) { | |
1670 | ||
1671 | cs_found = f10_match_to_this_node(pvt, dram_range, | |
1672 | sys_addr, node, | |
1673 | chan_sel); | |
1674 | if (cs_found >= 0) | |
1675 | break; | |
1676 | } | |
1677 | } | |
1678 | return cs_found; | |
1679 | } | |
1680 | ||
1681 | /* | |
1682 | * This the F10h reference code from AMD to map a @sys_addr to NodeID, | |
1683 | * CSROW, Channel. | |
1684 | * | |
1685 | * The @sys_addr is usually an error address received from the hardware. | |
1686 | */ | |
1687 | static void f10_map_sysaddr_to_csrow(struct mem_ctl_info *mci, | |
1688 | struct amd64_error_info_regs *info, | |
1689 | u64 sys_addr) | |
1690 | { | |
1691 | struct amd64_pvt *pvt = mci->pvt_info; | |
1692 | u32 page, offset; | |
1693 | unsigned short syndrome; | |
1694 | int nid, csrow, chan = 0; | |
1695 | ||
1696 | csrow = f10_translate_sysaddr_to_cs(pvt, sys_addr, &nid, &chan); | |
1697 | ||
1698 | if (csrow >= 0) { | |
1699 | error_address_to_page_and_offset(sys_addr, &page, &offset); | |
1700 | ||
1701 | syndrome = EXTRACT_HIGH_SYNDROME(info->nbsl) << 8; | |
1702 | syndrome |= EXTRACT_LOW_SYNDROME(info->nbsh); | |
1703 | ||
1704 | /* | |
1705 | * Is CHIPKILL on? If so, then we can attempt to use the | |
1706 | * syndrome to isolate which channel the error was on. | |
1707 | */ | |
1708 | if (pvt->nbcfg & K8_NBCFG_CHIPKILL) | |
1709 | chan = get_channel_from_ecc_syndrome(syndrome); | |
1710 | ||
1711 | if (chan >= 0) { | |
1712 | edac_mc_handle_ce(mci, page, offset, syndrome, | |
1713 | csrow, chan, EDAC_MOD_STR); | |
1714 | } else { | |
1715 | /* | |
1716 | * Channel unknown, report all channels on this | |
1717 | * CSROW as failed. | |
1718 | */ | |
1719 | for (chan = 0; chan < mci->csrows[csrow].nr_channels; | |
1720 | chan++) { | |
1721 | edac_mc_handle_ce(mci, page, offset, | |
1722 | syndrome, | |
1723 | csrow, chan, | |
1724 | EDAC_MOD_STR); | |
1725 | } | |
1726 | } | |
1727 | ||
1728 | } else { | |
1729 | edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR); | |
1730 | } | |
1731 | } | |
1732 | ||
1733 | /* | |
1734 | * Input (@index) is the DBAM DIMM value (1 of 4) used as an index into a shift | |
1735 | * table (revf_quad_ddr2_shift) which starts at 128MB DIMM size. Index of 0 | |
1736 | * indicates an empty DIMM slot, as reported by Hardware on empty slots. | |
1737 | * | |
1738 | * Normalize to 128MB by subracting 27 bit shift. | |
1739 | */ | |
1740 | static int map_dbam_to_csrow_size(int index) | |
1741 | { | |
1742 | int mega_bytes = 0; | |
1743 | ||
1744 | if (index > 0 && index <= DBAM_MAX_VALUE) | |
1745 | mega_bytes = ((128 << (revf_quad_ddr2_shift[index]-27))); | |
1746 | ||
1747 | return mega_bytes; | |
1748 | } | |
1749 | ||
1750 | /* | |
1751 | * debug routine to display the memory sizes of a DIMM (ganged or not) and it | |
1752 | * CSROWs as well | |
1753 | */ | |
1754 | static void f10_debug_display_dimm_sizes(int ctrl, struct amd64_pvt *pvt, | |
1755 | int ganged) | |
1756 | { | |
1757 | int dimm, size0, size1; | |
1758 | u32 dbam; | |
1759 | u32 *dcsb; | |
1760 | ||
1761 | debugf1(" dbam%d: 0x%8.08x CSROW is %s\n", ctrl, | |
1762 | ctrl ? pvt->dbam1 : pvt->dbam0, | |
1763 | ganged ? "GANGED - dbam1 not used" : "NON-GANGED"); | |
1764 | ||
1765 | dbam = ctrl ? pvt->dbam1 : pvt->dbam0; | |
1766 | dcsb = ctrl ? pvt->dcsb1 : pvt->dcsb0; | |
1767 | ||
1768 | /* Dump memory sizes for DIMM and its CSROWs */ | |
1769 | for (dimm = 0; dimm < 4; dimm++) { | |
1770 | ||
1771 | size0 = 0; | |
1772 | if (dcsb[dimm*2] & K8_DCSB_CS_ENABLE) | |
1773 | size0 = map_dbam_to_csrow_size(DBAM_DIMM(dimm, dbam)); | |
1774 | ||
1775 | size1 = 0; | |
1776 | if (dcsb[dimm*2 + 1] & K8_DCSB_CS_ENABLE) | |
1777 | size1 = map_dbam_to_csrow_size(DBAM_DIMM(dimm, dbam)); | |
1778 | ||
1779 | debugf1(" CTRL-%d DIMM-%d=%5dMB CSROW-%d=%5dMB " | |
1780 | "CSROW-%d=%5dMB\n", | |
1781 | ctrl, | |
1782 | dimm, | |
1783 | size0 + size1, | |
1784 | dimm * 2, | |
1785 | size0, | |
1786 | dimm * 2 + 1, | |
1787 | size1); | |
1788 | } | |
1789 | } | |
1790 | ||
1791 | /* | |
1792 | * Very early hardware probe on pci_probe thread to determine if this module | |
1793 | * supports the hardware. | |
1794 | * | |
1795 | * Return: | |
1796 | * 0 for OK | |
1797 | * 1 for error | |
1798 | */ | |
1799 | static int f10_probe_valid_hardware(struct amd64_pvt *pvt) | |
1800 | { | |
1801 | int ret = 0; | |
1802 | ||
1803 | /* | |
1804 | * If we are on a DDR3 machine, we don't know yet if | |
1805 | * we support that properly at this time | |
1806 | */ | |
1807 | if ((pvt->dchr0 & F10_DCHR_Ddr3Mode) || | |
1808 | (pvt->dchr1 & F10_DCHR_Ddr3Mode)) { | |
1809 | ||
1810 | amd64_printk(KERN_WARNING, | |
1811 | "%s() This machine is running with DDR3 memory. " | |
1812 | "This is not currently supported. " | |
1813 | "DCHR0=0x%x DCHR1=0x%x\n", | |
1814 | __func__, pvt->dchr0, pvt->dchr1); | |
1815 | ||
1816 | amd64_printk(KERN_WARNING, | |
1817 | " Contact '%s' module MAINTAINER to help add" | |
1818 | " support.\n", | |
1819 | EDAC_MOD_STR); | |
1820 | ||
1821 | ret = 1; | |
1822 | ||
1823 | } | |
1824 | return ret; | |
1825 | } | |
6163b5d4 | 1826 | |
4d37607a DT |
1827 | /* |
1828 | * There currently are 3 types type of MC devices for AMD Athlon/Opterons | |
1829 | * (as per PCI DEVICE_IDs): | |
1830 | * | |
1831 | * Family K8: That is the Athlon64 and Opteron CPUs. They all have the same PCI | |
1832 | * DEVICE ID, even though there is differences between the different Revisions | |
1833 | * (CG,D,E,F). | |
1834 | * | |
1835 | * Family F10h and F11h. | |
1836 | * | |
1837 | */ | |
1838 | static struct amd64_family_type amd64_family_types[] = { | |
1839 | [K8_CPUS] = { | |
1840 | .ctl_name = "RevF", | |
1841 | .addr_f1_ctl = PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP, | |
1842 | .misc_f3_ctl = PCI_DEVICE_ID_AMD_K8_NB_MISC, | |
1843 | .ops = { | |
1844 | .early_channel_count = k8_early_channel_count, | |
1845 | .get_error_address = k8_get_error_address, | |
1846 | .read_dram_base_limit = k8_read_dram_base_limit, | |
1847 | .map_sysaddr_to_csrow = k8_map_sysaddr_to_csrow, | |
1848 | .dbam_map_to_pages = k8_dbam_map_to_pages, | |
1849 | } | |
1850 | }, | |
1851 | [F10_CPUS] = { | |
1852 | .ctl_name = "Family 10h", | |
1853 | .addr_f1_ctl = PCI_DEVICE_ID_AMD_10H_NB_MAP, | |
1854 | .misc_f3_ctl = PCI_DEVICE_ID_AMD_10H_NB_MISC, | |
1855 | .ops = { | |
1856 | .probe_valid_hardware = f10_probe_valid_hardware, | |
1857 | .early_channel_count = f10_early_channel_count, | |
1858 | .get_error_address = f10_get_error_address, | |
1859 | .read_dram_base_limit = f10_read_dram_base_limit, | |
1860 | .read_dram_ctl_register = f10_read_dram_ctl_register, | |
1861 | .map_sysaddr_to_csrow = f10_map_sysaddr_to_csrow, | |
1862 | .dbam_map_to_pages = f10_dbam_map_to_pages, | |
1863 | } | |
1864 | }, | |
1865 | [F11_CPUS] = { | |
1866 | .ctl_name = "Family 11h", | |
1867 | .addr_f1_ctl = PCI_DEVICE_ID_AMD_11H_NB_MAP, | |
1868 | .misc_f3_ctl = PCI_DEVICE_ID_AMD_11H_NB_MISC, | |
1869 | .ops = { | |
1870 | .probe_valid_hardware = f10_probe_valid_hardware, | |
1871 | .early_channel_count = f10_early_channel_count, | |
1872 | .get_error_address = f10_get_error_address, | |
1873 | .read_dram_base_limit = f10_read_dram_base_limit, | |
1874 | .read_dram_ctl_register = f10_read_dram_ctl_register, | |
1875 | .map_sysaddr_to_csrow = f10_map_sysaddr_to_csrow, | |
1876 | .dbam_map_to_pages = f10_dbam_map_to_pages, | |
1877 | } | |
1878 | }, | |
1879 | }; | |
1880 | ||
1881 | static struct pci_dev *pci_get_related_function(unsigned int vendor, | |
1882 | unsigned int device, | |
1883 | struct pci_dev *related) | |
1884 | { | |
1885 | struct pci_dev *dev = NULL; | |
1886 | ||
1887 | dev = pci_get_device(vendor, device, dev); | |
1888 | while (dev) { | |
1889 | if ((dev->bus->number == related->bus->number) && | |
1890 | (PCI_SLOT(dev->devfn) == PCI_SLOT(related->devfn))) | |
1891 | break; | |
1892 | dev = pci_get_device(vendor, device, dev); | |
1893 | } | |
1894 | ||
1895 | return dev; | |
1896 | } | |
1897 | ||
b1289d6f DT |
1898 | /* |
1899 | * syndrome mapping table for ECC ChipKill devices | |
1900 | * | |
1901 | * The comment in each row is the token (nibble) number that is in error. | |
1902 | * The least significant nibble of the syndrome is the mask for the bits | |
1903 | * that are in error (need to be toggled) for the particular nibble. | |
1904 | * | |
1905 | * Each row contains 16 entries. | |
1906 | * The first entry (0th) is the channel number for that row of syndromes. | |
1907 | * The remaining 15 entries are the syndromes for the respective Error | |
1908 | * bit mask index. | |
1909 | * | |
1910 | * 1st index entry is 0x0001 mask, indicating that the rightmost bit is the | |
1911 | * bit in error. | |
1912 | * The 2nd index entry is 0x0010 that the second bit is damaged. | |
1913 | * The 3rd index entry is 0x0011 indicating that the rightmost 2 bits | |
1914 | * are damaged. | |
1915 | * Thus so on until index 15, 0x1111, whose entry has the syndrome | |
1916 | * indicating that all 4 bits are damaged. | |
1917 | * | |
1918 | * A search is performed on this table looking for a given syndrome. | |
1919 | * | |
1920 | * See the AMD documentation for ECC syndromes. This ECC table is valid | |
1921 | * across all the versions of the AMD64 processors. | |
1922 | * | |
1923 | * A fast lookup is to use the LAST four bits of the 16-bit syndrome as a | |
1924 | * COLUMN index, then search all ROWS of that column, looking for a match | |
1925 | * with the input syndrome. The ROW value will be the token number. | |
1926 | * | |
1927 | * The 0'th entry on that row, can be returned as the CHANNEL (0 or 1) of this | |
1928 | * error. | |
1929 | */ | |
1930 | #define NUMBER_ECC_ROWS 36 | |
1931 | static const unsigned short ecc_chipkill_syndromes[NUMBER_ECC_ROWS][16] = { | |
1932 | /* Channel 0 syndromes */ | |
1933 | {/*0*/ 0, 0xe821, 0x7c32, 0x9413, 0xbb44, 0x5365, 0xc776, 0x2f57, | |
1934 | 0xdd88, 0x35a9, 0xa1ba, 0x499b, 0x66cc, 0x8eed, 0x1afe, 0xf2df }, | |
1935 | {/*1*/ 0, 0x5d31, 0xa612, 0xfb23, 0x9584, 0xc8b5, 0x3396, 0x6ea7, | |
1936 | 0xeac8, 0xb7f9, 0x4cda, 0x11eb, 0x7f4c, 0x227d, 0xd95e, 0x846f }, | |
1937 | {/*2*/ 0, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007, | |
1938 | 0x0008, 0x0009, 0x000a, 0x000b, 0x000c, 0x000d, 0x000e, 0x000f }, | |
1939 | {/*3*/ 0, 0x2021, 0x3032, 0x1013, 0x4044, 0x6065, 0x7076, 0x5057, | |
1940 | 0x8088, 0xa0a9, 0xb0ba, 0x909b, 0xc0cc, 0xe0ed, 0xf0fe, 0xd0df }, | |
1941 | {/*4*/ 0, 0x5041, 0xa082, 0xf0c3, 0x9054, 0xc015, 0x30d6, 0x6097, | |
1942 | 0xe0a8, 0xb0e9, 0x402a, 0x106b, 0x70fc, 0x20bd, 0xd07e, 0x803f }, | |
1943 | {/*5*/ 0, 0xbe21, 0xd732, 0x6913, 0x2144, 0x9f65, 0xf676, 0x4857, | |
1944 | 0x3288, 0x8ca9, 0xe5ba, 0x5b9b, 0x13cc, 0xaded, 0xc4fe, 0x7adf }, | |
1945 | {/*6*/ 0, 0x4951, 0x8ea2, 0xc7f3, 0x5394, 0x1ac5, 0xdd36, 0x9467, | |
1946 | 0xa1e8, 0xe8b9, 0x2f4a, 0x661b, 0xf27c, 0xbb2d, 0x7cde, 0x358f }, | |
1947 | {/*7*/ 0, 0x74e1, 0x9872, 0xec93, 0xd6b4, 0xa255, 0x4ec6, 0x3a27, | |
1948 | 0x6bd8, 0x1f39, 0xf3aa, 0x874b, 0xbd6c, 0xc98d, 0x251e, 0x51ff }, | |
1949 | {/*8*/ 0, 0x15c1, 0x2a42, 0x3f83, 0xcef4, 0xdb35, 0xe4b6, 0xf177, | |
1950 | 0x4758, 0x5299, 0x6d1a, 0x78db, 0x89ac, 0x9c6d, 0xa3ee, 0xb62f }, | |
1951 | {/*9*/ 0, 0x3d01, 0x1602, 0x2b03, 0x8504, 0xb805, 0x9306, 0xae07, | |
1952 | 0xca08, 0xf709, 0xdc0a, 0xe10b, 0x4f0c, 0x720d, 0x590e, 0x640f }, | |
1953 | {/*a*/ 0, 0x9801, 0xec02, 0x7403, 0x6b04, 0xf305, 0x8706, 0x1f07, | |
1954 | 0xbd08, 0x2509, 0x510a, 0xc90b, 0xd60c, 0x4e0d, 0x3a0e, 0xa20f }, | |
1955 | {/*b*/ 0, 0xd131, 0x6212, 0xb323, 0x3884, 0xe9b5, 0x5a96, 0x8ba7, | |
1956 | 0x1cc8, 0xcdf9, 0x7eda, 0xafeb, 0x244c, 0xf57d, 0x465e, 0x976f }, | |
1957 | {/*c*/ 0, 0xe1d1, 0x7262, 0x93b3, 0xb834, 0x59e5, 0xca56, 0x2b87, | |
1958 | 0xdc18, 0x3dc9, 0xae7a, 0x4fab, 0x542c, 0x85fd, 0x164e, 0xf79f }, | |
1959 | {/*d*/ 0, 0x6051, 0xb0a2, 0xd0f3, 0x1094, 0x70c5, 0xa036, 0xc067, | |
1960 | 0x20e8, 0x40b9, 0x904a, 0x601b, 0x307c, 0x502d, 0x80de, 0xe08f }, | |
1961 | {/*e*/ 0, 0xa4c1, 0xf842, 0x5c83, 0xe6f4, 0x4235, 0x1eb6, 0xba77, | |
1962 | 0x7b58, 0xdf99, 0x831a, 0x27db, 0x9dac, 0x396d, 0x65ee, 0xc12f }, | |
1963 | {/*f*/ 0, 0x11c1, 0x2242, 0x3383, 0xc8f4, 0xd935, 0xeab6, 0xfb77, | |
1964 | 0x4c58, 0x5d99, 0x6e1a, 0x7fdb, 0x84ac, 0x956d, 0xa6ee, 0xb72f }, | |
1965 | ||
1966 | /* Channel 1 syndromes */ | |
1967 | {/*10*/ 1, 0x45d1, 0x8a62, 0xcfb3, 0x5e34, 0x1be5, 0xd456, 0x9187, | |
1968 | 0xa718, 0xe2c9, 0x2d7a, 0x68ab, 0xf92c, 0xbcfd, 0x734e, 0x369f }, | |
1969 | {/*11*/ 1, 0x63e1, 0xb172, 0xd293, 0x14b4, 0x7755, 0xa5c6, 0xc627, | |
1970 | 0x28d8, 0x4b39, 0x99aa, 0xfa4b, 0x3c6c, 0x5f8d, 0x8d1e, 0xeeff }, | |
1971 | {/*12*/ 1, 0xb741, 0xd982, 0x6ec3, 0x2254, 0x9515, 0xfbd6, 0x4c97, | |
1972 | 0x33a8, 0x84e9, 0xea2a, 0x5d6b, 0x11fc, 0xa6bd, 0xc87e, 0x7f3f }, | |
1973 | {/*13*/ 1, 0xdd41, 0x6682, 0xbbc3, 0x3554, 0xe815, 0x53d6, 0xce97, | |
1974 | 0x1aa8, 0xc7e9, 0x7c2a, 0xa1fb, 0x2ffc, 0xf2bd, 0x497e, 0x943f }, | |
1975 | {/*14*/ 1, 0x2bd1, 0x3d62, 0x16b3, 0x4f34, 0x64e5, 0x7256, 0x5987, | |
1976 | 0x8518, 0xaec9, 0xb87a, 0x93ab, 0xca2c, 0xe1fd, 0xf74e, 0xdc9f }, | |
1977 | {/*15*/ 1, 0x83c1, 0xc142, 0x4283, 0xa4f4, 0x2735, 0x65b6, 0xe677, | |
1978 | 0xf858, 0x7b99, 0x391a, 0xbadb, 0x5cac, 0xdf6d, 0x9dee, 0x1e2f }, | |
1979 | {/*16*/ 1, 0x8fd1, 0xc562, 0x4ab3, 0xa934, 0x26e5, 0x6c56, 0xe387, | |
1980 | 0xfe18, 0x71c9, 0x3b7a, 0xb4ab, 0x572c, 0xd8fd, 0x924e, 0x1d9f }, | |
1981 | {/*17*/ 1, 0x4791, 0x89e2, 0xce73, 0x5264, 0x15f5, 0xdb86, 0x9c17, | |
1982 | 0xa3b8, 0xe429, 0x2a5a, 0x6dcb, 0xf1dc, 0xb64d, 0x783e, 0x3faf }, | |
1983 | {/*18*/ 1, 0x5781, 0xa9c2, 0xfe43, 0x92a4, 0xc525, 0x3b66, 0x6ce7, | |
1984 | 0xe3f8, 0xb479, 0x4a3a, 0x1dbb, 0x715c, 0x26dd, 0xd89e, 0x8f1f }, | |
1985 | {/*19*/ 1, 0xbf41, 0xd582, 0x6ac3, 0x2954, 0x9615, 0xfcd6, 0x4397, | |
1986 | 0x3ea8, 0x81e9, 0xeb2a, 0x546b, 0x17fc, 0xa8bd, 0xc27e, 0x7d3f }, | |
1987 | {/*1a*/ 1, 0x9891, 0xe1e2, 0x7273, 0x6464, 0xf7f5, 0x8586, 0x1617, | |
1988 | 0xb8b8, 0x2b29, 0x595a, 0xcacb, 0xdcdc, 0x4f4d, 0x3d3e, 0xaeaf }, | |
1989 | {/*1b*/ 1, 0xcce1, 0x4472, 0x8893, 0xfdb4, 0x3f55, 0xb9c6, 0x7527, | |
1990 | 0x56d8, 0x9a39, 0x12aa, 0xde4b, 0xab6c, 0x678d, 0xef1e, 0x23ff }, | |
1991 | {/*1c*/ 1, 0xa761, 0xf9b2, 0x5ed3, 0xe214, 0x4575, 0x1ba6, 0xbcc7, | |
1992 | 0x7328, 0xd449, 0x8a9a, 0x2dfb, 0x913c, 0x365d, 0x688e, 0xcfef }, | |
1993 | {/*1d*/ 1, 0xff61, 0x55b2, 0xaad3, 0x7914, 0x8675, 0x2ca6, 0xd3c7, | |
1994 | 0x9e28, 0x6149, 0xcb9a, 0x34fb, 0xe73c, 0x185d, 0xb28e, 0x4def }, | |
1995 | {/*1e*/ 1, 0x5451, 0xa8a2, 0xfcf3, 0x9694, 0xc2c5, 0x3e36, 0x6a67, | |
1996 | 0xebe8, 0xbfb9, 0x434a, 0x171b, 0x7d7c, 0x292d, 0xd5de, 0x818f }, | |
1997 | {/*1f*/ 1, 0x6fc1, 0xb542, 0xda83, 0x19f4, 0x7635, 0xacb6, 0xc377, | |
1998 | 0x2e58, 0x4199, 0x9b1a, 0xf4db, 0x37ac, 0x586d, 0x82ee, 0xed2f }, | |
1999 | ||
2000 | /* ECC bits are also in the set of tokens and they too can go bad | |
2001 | * first 2 cover channel 0, while the second 2 cover channel 1 | |
2002 | */ | |
2003 | {/*20*/ 0, 0xbe01, 0xd702, 0x6903, 0x2104, 0x9f05, 0xf606, 0x4807, | |
2004 | 0x3208, 0x8c09, 0xe50a, 0x5b0b, 0x130c, 0xad0d, 0xc40e, 0x7a0f }, | |
2005 | {/*21*/ 0, 0x4101, 0x8202, 0xc303, 0x5804, 0x1905, 0xda06, 0x9b07, | |
2006 | 0xac08, 0xed09, 0x2e0a, 0x6f0b, 0x640c, 0xb50d, 0x760e, 0x370f }, | |
2007 | {/*22*/ 1, 0xc441, 0x4882, 0x8cc3, 0xf654, 0x3215, 0xbed6, 0x7a97, | |
2008 | 0x5ba8, 0x9fe9, 0x132a, 0xd76b, 0xadfc, 0x69bd, 0xe57e, 0x213f }, | |
2009 | {/*23*/ 1, 0x7621, 0x9b32, 0xed13, 0xda44, 0xac65, 0x4176, 0x3757, | |
2010 | 0x6f88, 0x19a9, 0xf4ba, 0x829b, 0xb5cc, 0xc3ed, 0x2efe, 0x58df } | |
2011 | }; | |
2012 | ||
2013 | /* | |
2014 | * Given the syndrome argument, scan each of the channel tables for a syndrome | |
2015 | * match. Depending on which table it is found, return the channel number. | |
2016 | */ | |
2017 | static int get_channel_from_ecc_syndrome(unsigned short syndrome) | |
2018 | { | |
2019 | int row; | |
2020 | int column; | |
4d37607a | 2021 | |
b1289d6f DT |
2022 | /* Determine column to scan */ |
2023 | column = syndrome & 0xF; | |
2024 | ||
2025 | /* Scan all rows, looking for syndrome, or end of table */ | |
2026 | for (row = 0; row < NUMBER_ECC_ROWS; row++) { | |
2027 | if (ecc_chipkill_syndromes[row][column] == syndrome) | |
2028 | return ecc_chipkill_syndromes[row][0]; | |
2029 | } | |
2030 | ||
2031 | debugf0("syndrome(%x) not found\n", syndrome); | |
2032 | return -1; | |
2033 | } | |
d27bf6fa DT |
2034 | |
2035 | /* | |
2036 | * Check for valid error in the NB Status High register. If so, proceed to read | |
2037 | * NB Status Low, NB Address Low and NB Address High registers and store data | |
2038 | * into error structure. | |
2039 | * | |
2040 | * Returns: | |
2041 | * - 1: if hardware regs contains valid error info | |
2042 | * - 0: if no valid error is indicated | |
2043 | */ | |
2044 | static int amd64_get_error_info_regs(struct mem_ctl_info *mci, | |
2045 | struct amd64_error_info_regs *regs) | |
2046 | { | |
2047 | struct amd64_pvt *pvt; | |
2048 | struct pci_dev *misc_f3_ctl; | |
2049 | int err = 0; | |
2050 | ||
2051 | pvt = mci->pvt_info; | |
2052 | misc_f3_ctl = pvt->misc_f3_ctl; | |
2053 | ||
2054 | err = pci_read_config_dword(misc_f3_ctl, K8_NBSH, ®s->nbsh); | |
2055 | if (err) | |
2056 | goto err_reg; | |
2057 | ||
2058 | if (!(regs->nbsh & K8_NBSH_VALID_BIT)) | |
2059 | return 0; | |
2060 | ||
2061 | /* valid error, read remaining error information registers */ | |
2062 | err = pci_read_config_dword(misc_f3_ctl, K8_NBSL, ®s->nbsl); | |
2063 | if (err) | |
2064 | goto err_reg; | |
2065 | ||
2066 | err = pci_read_config_dword(misc_f3_ctl, K8_NBEAL, ®s->nbeal); | |
2067 | if (err) | |
2068 | goto err_reg; | |
2069 | ||
2070 | err = pci_read_config_dword(misc_f3_ctl, K8_NBEAH, ®s->nbeah); | |
2071 | if (err) | |
2072 | goto err_reg; | |
2073 | ||
2074 | err = pci_read_config_dword(misc_f3_ctl, K8_NBCFG, ®s->nbcfg); | |
2075 | if (err) | |
2076 | goto err_reg; | |
2077 | ||
2078 | return 1; | |
2079 | ||
2080 | err_reg: | |
2081 | debugf0("Reading error info register failed\n"); | |
2082 | return 0; | |
2083 | } | |
2084 | ||
2085 | /* | |
2086 | * This function is called to retrieve the error data from hardware and store it | |
2087 | * in the info structure. | |
2088 | * | |
2089 | * Returns: | |
2090 | * - 1: if a valid error is found | |
2091 | * - 0: if no error is found | |
2092 | */ | |
2093 | static int amd64_get_error_info(struct mem_ctl_info *mci, | |
2094 | struct amd64_error_info_regs *info) | |
2095 | { | |
2096 | struct amd64_pvt *pvt; | |
2097 | struct amd64_error_info_regs regs; | |
2098 | ||
2099 | pvt = mci->pvt_info; | |
2100 | ||
2101 | if (!amd64_get_error_info_regs(mci, info)) | |
2102 | return 0; | |
2103 | ||
2104 | /* | |
2105 | * Here's the problem with the K8's EDAC reporting: There are four | |
2106 | * registers which report pieces of error information. They are shared | |
2107 | * between CEs and UEs. Furthermore, contrary to what is stated in the | |
2108 | * BKDG, the overflow bit is never used! Every error always updates the | |
2109 | * reporting registers. | |
2110 | * | |
2111 | * Can you see the race condition? All four error reporting registers | |
2112 | * must be read before a new error updates them! There is no way to read | |
2113 | * all four registers atomically. The best than can be done is to detect | |
2114 | * that a race has occured and then report the error without any kind of | |
2115 | * precision. | |
2116 | * | |
2117 | * What is still positive is that errors are still reported and thus | |
2118 | * problems can still be detected - just not localized because the | |
2119 | * syndrome and address are spread out across registers. | |
2120 | * | |
2121 | * Grrrrr!!!!! Here's hoping that AMD fixes this in some future K8 rev. | |
2122 | * UEs and CEs should have separate register sets with proper overflow | |
2123 | * bits that are used! At very least the problem can be fixed by | |
2124 | * honoring the ErrValid bit in 'nbsh' and not updating registers - just | |
2125 | * set the overflow bit - unless the current error is CE and the new | |
2126 | * error is UE which would be the only situation for overwriting the | |
2127 | * current values. | |
2128 | */ | |
2129 | ||
2130 | regs = *info; | |
2131 | ||
2132 | /* Use info from the second read - most current */ | |
2133 | if (unlikely(!amd64_get_error_info_regs(mci, info))) | |
2134 | return 0; | |
2135 | ||
2136 | /* clear the error bits in hardware */ | |
2137 | pci_write_bits32(pvt->misc_f3_ctl, K8_NBSH, 0, K8_NBSH_VALID_BIT); | |
2138 | ||
2139 | /* Check for the possible race condition */ | |
2140 | if ((regs.nbsh != info->nbsh) || | |
2141 | (regs.nbsl != info->nbsl) || | |
2142 | (regs.nbeah != info->nbeah) || | |
2143 | (regs.nbeal != info->nbeal)) { | |
2144 | amd64_mc_printk(mci, KERN_WARNING, | |
2145 | "hardware STATUS read access race condition " | |
2146 | "detected!\n"); | |
2147 | return 0; | |
2148 | } | |
2149 | return 1; | |
2150 | } | |
2151 | ||
2152 | static inline void amd64_decode_gart_tlb_error(struct mem_ctl_info *mci, | |
2153 | struct amd64_error_info_regs *info) | |
2154 | { | |
2155 | u32 err_code; | |
2156 | u32 ec_tt; /* error code transaction type (2b) */ | |
2157 | u32 ec_ll; /* error code cache level (2b) */ | |
2158 | ||
2159 | err_code = EXTRACT_ERROR_CODE(info->nbsl); | |
2160 | ec_ll = EXTRACT_LL_CODE(err_code); | |
2161 | ec_tt = EXTRACT_TT_CODE(err_code); | |
2162 | ||
2163 | amd64_mc_printk(mci, KERN_ERR, | |
2164 | "GART TLB event: transaction type(%s), " | |
2165 | "cache level(%s)\n", tt_msgs[ec_tt], ll_msgs[ec_ll]); | |
2166 | } | |
2167 | ||
2168 | static inline void amd64_decode_mem_cache_error(struct mem_ctl_info *mci, | |
2169 | struct amd64_error_info_regs *info) | |
2170 | { | |
2171 | u32 err_code; | |
2172 | u32 ec_rrrr; /* error code memory transaction (4b) */ | |
2173 | u32 ec_tt; /* error code transaction type (2b) */ | |
2174 | u32 ec_ll; /* error code cache level (2b) */ | |
2175 | ||
2176 | err_code = EXTRACT_ERROR_CODE(info->nbsl); | |
2177 | ec_ll = EXTRACT_LL_CODE(err_code); | |
2178 | ec_tt = EXTRACT_TT_CODE(err_code); | |
2179 | ec_rrrr = EXTRACT_RRRR_CODE(err_code); | |
2180 | ||
2181 | amd64_mc_printk(mci, KERN_ERR, | |
2182 | "cache hierarchy error: memory transaction type(%s), " | |
2183 | "transaction type(%s), cache level(%s)\n", | |
2184 | rrrr_msgs[ec_rrrr], tt_msgs[ec_tt], ll_msgs[ec_ll]); | |
2185 | } | |
2186 | ||
2187 | ||
2188 | /* | |
2189 | * Handle any Correctable Errors (CEs) that have occurred. Check for valid ERROR | |
2190 | * ADDRESS and process. | |
2191 | */ | |
2192 | static void amd64_handle_ce(struct mem_ctl_info *mci, | |
2193 | struct amd64_error_info_regs *info) | |
2194 | { | |
2195 | struct amd64_pvt *pvt = mci->pvt_info; | |
2196 | u64 SystemAddress; | |
2197 | ||
2198 | /* Ensure that the Error Address is VALID */ | |
2199 | if ((info->nbsh & K8_NBSH_VALID_ERROR_ADDR) == 0) { | |
2200 | amd64_mc_printk(mci, KERN_ERR, | |
2201 | "HW has no ERROR_ADDRESS available\n"); | |
2202 | edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR); | |
2203 | return; | |
2204 | } | |
2205 | ||
2206 | SystemAddress = extract_error_address(mci, info); | |
2207 | ||
2208 | amd64_mc_printk(mci, KERN_ERR, | |
2209 | "CE ERROR_ADDRESS= 0x%llx\n", SystemAddress); | |
2210 | ||
2211 | pvt->ops->map_sysaddr_to_csrow(mci, info, SystemAddress); | |
2212 | } | |
2213 | ||
2214 | /* Handle any Un-correctable Errors (UEs) */ | |
2215 | static void amd64_handle_ue(struct mem_ctl_info *mci, | |
2216 | struct amd64_error_info_regs *info) | |
2217 | { | |
2218 | int csrow; | |
2219 | u64 SystemAddress; | |
2220 | u32 page, offset; | |
2221 | struct mem_ctl_info *log_mci, *src_mci = NULL; | |
2222 | ||
2223 | log_mci = mci; | |
2224 | ||
2225 | if ((info->nbsh & K8_NBSH_VALID_ERROR_ADDR) == 0) { | |
2226 | amd64_mc_printk(mci, KERN_CRIT, | |
2227 | "HW has no ERROR_ADDRESS available\n"); | |
2228 | edac_mc_handle_ue_no_info(log_mci, EDAC_MOD_STR); | |
2229 | return; | |
2230 | } | |
2231 | ||
2232 | SystemAddress = extract_error_address(mci, info); | |
2233 | ||
2234 | /* | |
2235 | * Find out which node the error address belongs to. This may be | |
2236 | * different from the node that detected the error. | |
2237 | */ | |
2238 | src_mci = find_mc_by_sys_addr(mci, SystemAddress); | |
2239 | if (!src_mci) { | |
2240 | amd64_mc_printk(mci, KERN_CRIT, | |
2241 | "ERROR ADDRESS (0x%lx) value NOT mapped to a MC\n", | |
2242 | (unsigned long)SystemAddress); | |
2243 | edac_mc_handle_ue_no_info(log_mci, EDAC_MOD_STR); | |
2244 | return; | |
2245 | } | |
2246 | ||
2247 | log_mci = src_mci; | |
2248 | ||
2249 | csrow = sys_addr_to_csrow(log_mci, SystemAddress); | |
2250 | if (csrow < 0) { | |
2251 | amd64_mc_printk(mci, KERN_CRIT, | |
2252 | "ERROR_ADDRESS (0x%lx) value NOT mapped to 'csrow'\n", | |
2253 | (unsigned long)SystemAddress); | |
2254 | edac_mc_handle_ue_no_info(log_mci, EDAC_MOD_STR); | |
2255 | } else { | |
2256 | error_address_to_page_and_offset(SystemAddress, &page, &offset); | |
2257 | edac_mc_handle_ue(log_mci, page, offset, csrow, EDAC_MOD_STR); | |
2258 | } | |
2259 | } | |
2260 | ||
2261 | static void amd64_decode_bus_error(struct mem_ctl_info *mci, | |
2262 | struct amd64_error_info_regs *info) | |
2263 | { | |
2264 | u32 err_code, ext_ec; | |
2265 | u32 ec_pp; /* error code participating processor (2p) */ | |
2266 | u32 ec_to; /* error code timed out (1b) */ | |
2267 | u32 ec_rrrr; /* error code memory transaction (4b) */ | |
2268 | u32 ec_ii; /* error code memory or I/O (2b) */ | |
2269 | u32 ec_ll; /* error code cache level (2b) */ | |
2270 | ||
2271 | ext_ec = EXTRACT_EXT_ERROR_CODE(info->nbsl); | |
2272 | err_code = EXTRACT_ERROR_CODE(info->nbsl); | |
2273 | ||
2274 | ec_ll = EXTRACT_LL_CODE(err_code); | |
2275 | ec_ii = EXTRACT_II_CODE(err_code); | |
2276 | ec_rrrr = EXTRACT_RRRR_CODE(err_code); | |
2277 | ec_to = EXTRACT_TO_CODE(err_code); | |
2278 | ec_pp = EXTRACT_PP_CODE(err_code); | |
2279 | ||
2280 | amd64_mc_printk(mci, KERN_ERR, | |
2281 | "BUS ERROR:\n" | |
2282 | " time-out(%s) mem or i/o(%s)\n" | |
2283 | " participating processor(%s)\n" | |
2284 | " memory transaction type(%s)\n" | |
2285 | " cache level(%s) Error Found by: %s\n", | |
2286 | to_msgs[ec_to], | |
2287 | ii_msgs[ec_ii], | |
2288 | pp_msgs[ec_pp], | |
2289 | rrrr_msgs[ec_rrrr], | |
2290 | ll_msgs[ec_ll], | |
2291 | (info->nbsh & K8_NBSH_ERR_SCRUBER) ? | |
2292 | "Scrubber" : "Normal Operation"); | |
2293 | ||
2294 | /* If this was an 'observed' error, early out */ | |
2295 | if (ec_pp == K8_NBSL_PP_OBS) | |
2296 | return; /* We aren't the node involved */ | |
2297 | ||
2298 | /* Parse out the extended error code for ECC events */ | |
2299 | switch (ext_ec) { | |
2300 | /* F10 changed to one Extended ECC error code */ | |
2301 | case F10_NBSL_EXT_ERR_RES: /* Reserved field */ | |
2302 | case F10_NBSL_EXT_ERR_ECC: /* F10 ECC ext err code */ | |
2303 | break; | |
2304 | ||
2305 | default: | |
2306 | amd64_mc_printk(mci, KERN_ERR, "NOT ECC: no special error " | |
2307 | "handling for this error\n"); | |
2308 | return; | |
2309 | } | |
2310 | ||
2311 | if (info->nbsh & K8_NBSH_CECC) | |
2312 | amd64_handle_ce(mci, info); | |
2313 | else if (info->nbsh & K8_NBSH_UECC) | |
2314 | amd64_handle_ue(mci, info); | |
2315 | ||
2316 | /* | |
2317 | * If main error is CE then overflow must be CE. If main error is UE | |
2318 | * then overflow is unknown. We'll call the overflow a CE - if | |
2319 | * panic_on_ue is set then we're already panic'ed and won't arrive | |
2320 | * here. Else, then apparently someone doesn't think that UE's are | |
2321 | * catastrophic. | |
2322 | */ | |
2323 | if (info->nbsh & K8_NBSH_OVERFLOW) | |
2324 | edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR | |
2325 | "Error Overflow set"); | |
2326 | } | |
2327 | ||
2328 | int amd64_process_error_info(struct mem_ctl_info *mci, | |
2329 | struct amd64_error_info_regs *info, | |
2330 | int handle_errors) | |
2331 | { | |
2332 | struct amd64_pvt *pvt; | |
2333 | struct amd64_error_info_regs *regs; | |
2334 | u32 err_code, ext_ec; | |
2335 | int gart_tlb_error = 0; | |
2336 | ||
2337 | pvt = mci->pvt_info; | |
2338 | ||
2339 | /* If caller doesn't want us to process the error, return */ | |
2340 | if (!handle_errors) | |
2341 | return 1; | |
2342 | ||
2343 | regs = info; | |
2344 | ||
2345 | debugf1("NorthBridge ERROR: mci(0x%p)\n", mci); | |
2346 | debugf1(" MC node(%d) Error-Address(0x%.8x-%.8x)\n", | |
2347 | pvt->mc_node_id, regs->nbeah, regs->nbeal); | |
2348 | debugf1(" nbsh(0x%.8x) nbsl(0x%.8x)\n", | |
2349 | regs->nbsh, regs->nbsl); | |
2350 | debugf1(" Valid Error=%s Overflow=%s\n", | |
2351 | (regs->nbsh & K8_NBSH_VALID_BIT) ? "True" : "False", | |
2352 | (regs->nbsh & K8_NBSH_OVERFLOW) ? "True" : "False"); | |
2353 | debugf1(" Err Uncorrected=%s MCA Error Reporting=%s\n", | |
2354 | (regs->nbsh & K8_NBSH_UNCORRECTED_ERR) ? | |
2355 | "True" : "False", | |
2356 | (regs->nbsh & K8_NBSH_ERR_ENABLE) ? | |
2357 | "True" : "False"); | |
2358 | debugf1(" MiscErr Valid=%s ErrAddr Valid=%s PCC=%s\n", | |
2359 | (regs->nbsh & K8_NBSH_MISC_ERR_VALID) ? | |
2360 | "True" : "False", | |
2361 | (regs->nbsh & K8_NBSH_VALID_ERROR_ADDR) ? | |
2362 | "True" : "False", | |
2363 | (regs->nbsh & K8_NBSH_PCC) ? | |
2364 | "True" : "False"); | |
2365 | debugf1(" CECC=%s UECC=%s Found by Scruber=%s\n", | |
2366 | (regs->nbsh & K8_NBSH_CECC) ? | |
2367 | "True" : "False", | |
2368 | (regs->nbsh & K8_NBSH_UECC) ? | |
2369 | "True" : "False", | |
2370 | (regs->nbsh & K8_NBSH_ERR_SCRUBER) ? | |
2371 | "True" : "False"); | |
2372 | debugf1(" CORE0=%s CORE1=%s CORE2=%s CORE3=%s\n", | |
2373 | (regs->nbsh & K8_NBSH_CORE0) ? "True" : "False", | |
2374 | (regs->nbsh & K8_NBSH_CORE1) ? "True" : "False", | |
2375 | (regs->nbsh & K8_NBSH_CORE2) ? "True" : "False", | |
2376 | (regs->nbsh & K8_NBSH_CORE3) ? "True" : "False"); | |
2377 | ||
2378 | ||
2379 | err_code = EXTRACT_ERROR_CODE(regs->nbsl); | |
2380 | ||
2381 | /* Determine which error type: | |
2382 | * 1) GART errors - non-fatal, developmental events | |
2383 | * 2) MEMORY errors | |
2384 | * 3) BUS errors | |
2385 | * 4) Unknown error | |
2386 | */ | |
2387 | if (TEST_TLB_ERROR(err_code)) { | |
2388 | /* | |
2389 | * GART errors are intended to help graphics driver developers | |
2390 | * to detect bad GART PTEs. It is recommended by AMD to disable | |
2391 | * GART table walk error reporting by default[1] (currently | |
2392 | * being disabled in mce_cpu_quirks()) and according to the | |
2393 | * comment in mce_cpu_quirks(), such GART errors can be | |
2394 | * incorrectly triggered. We may see these errors anyway and | |
2395 | * unless requested by the user, they won't be reported. | |
2396 | * | |
2397 | * [1] section 13.10.1 on BIOS and Kernel Developers Guide for | |
2398 | * AMD NPT family 0Fh processors | |
2399 | */ | |
2400 | if (report_gart_errors == 0) | |
2401 | return 1; | |
2402 | ||
2403 | /* | |
2404 | * Only if GART error reporting is requested should we generate | |
2405 | * any logs. | |
2406 | */ | |
2407 | gart_tlb_error = 1; | |
2408 | ||
2409 | debugf1("GART TLB error\n"); | |
2410 | amd64_decode_gart_tlb_error(mci, info); | |
2411 | } else if (TEST_MEM_ERROR(err_code)) { | |
2412 | debugf1("Memory/Cache error\n"); | |
2413 | amd64_decode_mem_cache_error(mci, info); | |
2414 | } else if (TEST_BUS_ERROR(err_code)) { | |
2415 | debugf1("Bus (Link/DRAM) error\n"); | |
2416 | amd64_decode_bus_error(mci, info); | |
2417 | } else { | |
2418 | /* shouldn't reach here! */ | |
2419 | amd64_mc_printk(mci, KERN_WARNING, | |
2420 | "%s(): unknown MCE error 0x%x\n", __func__, | |
2421 | err_code); | |
2422 | } | |
2423 | ||
2424 | ext_ec = EXTRACT_EXT_ERROR_CODE(regs->nbsl); | |
2425 | amd64_mc_printk(mci, KERN_ERR, | |
2426 | "ExtErr=(0x%x) %s\n", ext_ec, ext_msgs[ext_ec]); | |
2427 | ||
2428 | if (((ext_ec >= F10_NBSL_EXT_ERR_CRC && | |
2429 | ext_ec <= F10_NBSL_EXT_ERR_TGT) || | |
2430 | (ext_ec == F10_NBSL_EXT_ERR_RMW)) && | |
2431 | EXTRACT_LDT_LINK(info->nbsh)) { | |
2432 | ||
2433 | amd64_mc_printk(mci, KERN_ERR, | |
2434 | "Error on hypertransport link: %s\n", | |
2435 | htlink_msgs[ | |
2436 | EXTRACT_LDT_LINK(info->nbsh)]); | |
2437 | } | |
2438 | ||
2439 | /* | |
2440 | * Check the UE bit of the NB status high register, if set generate some | |
2441 | * logs. If NOT a GART error, then process the event as a NO-INFO event. | |
2442 | * If it was a GART error, skip that process. | |
2443 | */ | |
2444 | if (regs->nbsh & K8_NBSH_UNCORRECTED_ERR) { | |
2445 | amd64_mc_printk(mci, KERN_CRIT, "uncorrected error\n"); | |
2446 | if (!gart_tlb_error) | |
2447 | edac_mc_handle_ue_no_info(mci, "UE bit is set\n"); | |
2448 | } | |
2449 | ||
2450 | if (regs->nbsh & K8_NBSH_PCC) | |
2451 | amd64_mc_printk(mci, KERN_CRIT, | |
2452 | "PCC (processor context corrupt) set\n"); | |
2453 | ||
2454 | return 1; | |
2455 | } | |
2456 | EXPORT_SYMBOL_GPL(amd64_process_error_info); | |
2457 | ||
0ec449ee DT |
2458 | /* |
2459 | * The main polling 'check' function, called FROM the edac core to perform the | |
2460 | * error checking and if an error is encountered, error processing. | |
2461 | */ | |
2462 | static void amd64_check(struct mem_ctl_info *mci) | |
2463 | { | |
2464 | struct amd64_error_info_regs info; | |
2465 | ||
2466 | if (amd64_get_error_info(mci, &info)) | |
2467 | amd64_process_error_info(mci, &info, 1); | |
2468 | } | |
2469 | ||
2470 | /* | |
2471 | * Input: | |
2472 | * 1) struct amd64_pvt which contains pvt->dram_f2_ctl pointer | |
2473 | * 2) AMD Family index value | |
2474 | * | |
2475 | * Ouput: | |
2476 | * Upon return of 0, the following filled in: | |
2477 | * | |
2478 | * struct pvt->addr_f1_ctl | |
2479 | * struct pvt->misc_f3_ctl | |
2480 | * | |
2481 | * Filled in with related device funcitions of 'dram_f2_ctl' | |
2482 | * These devices are "reserved" via the pci_get_device() | |
2483 | * | |
2484 | * Upon return of 1 (error status): | |
2485 | * | |
2486 | * Nothing reserved | |
2487 | */ | |
2488 | static int amd64_reserve_mc_sibling_devices(struct amd64_pvt *pvt, int mc_idx) | |
2489 | { | |
2490 | const struct amd64_family_type *amd64_dev = &amd64_family_types[mc_idx]; | |
2491 | ||
2492 | /* Reserve the ADDRESS MAP Device */ | |
2493 | pvt->addr_f1_ctl = pci_get_related_function(pvt->dram_f2_ctl->vendor, | |
2494 | amd64_dev->addr_f1_ctl, | |
2495 | pvt->dram_f2_ctl); | |
2496 | ||
2497 | if (!pvt->addr_f1_ctl) { | |
2498 | amd64_printk(KERN_ERR, "error address map device not found: " | |
2499 | "vendor %x device 0x%x (broken BIOS?)\n", | |
2500 | PCI_VENDOR_ID_AMD, amd64_dev->addr_f1_ctl); | |
2501 | return 1; | |
2502 | } | |
2503 | ||
2504 | /* Reserve the MISC Device */ | |
2505 | pvt->misc_f3_ctl = pci_get_related_function(pvt->dram_f2_ctl->vendor, | |
2506 | amd64_dev->misc_f3_ctl, | |
2507 | pvt->dram_f2_ctl); | |
2508 | ||
2509 | if (!pvt->misc_f3_ctl) { | |
2510 | pci_dev_put(pvt->addr_f1_ctl); | |
2511 | pvt->addr_f1_ctl = NULL; | |
2512 | ||
2513 | amd64_printk(KERN_ERR, "error miscellaneous device not found: " | |
2514 | "vendor %x device 0x%x (broken BIOS?)\n", | |
2515 | PCI_VENDOR_ID_AMD, amd64_dev->misc_f3_ctl); | |
2516 | return 1; | |
2517 | } | |
2518 | ||
2519 | debugf1(" Addr Map device PCI Bus ID:\t%s\n", | |
2520 | pci_name(pvt->addr_f1_ctl)); | |
2521 | debugf1(" DRAM MEM-CTL PCI Bus ID:\t%s\n", | |
2522 | pci_name(pvt->dram_f2_ctl)); | |
2523 | debugf1(" Misc device PCI Bus ID:\t%s\n", | |
2524 | pci_name(pvt->misc_f3_ctl)); | |
2525 | ||
2526 | return 0; | |
2527 | } | |
2528 | ||
2529 | static void amd64_free_mc_sibling_devices(struct amd64_pvt *pvt) | |
2530 | { | |
2531 | pci_dev_put(pvt->addr_f1_ctl); | |
2532 | pci_dev_put(pvt->misc_f3_ctl); | |
2533 | } | |
2534 | ||
2535 | /* | |
2536 | * Retrieve the hardware registers of the memory controller (this includes the | |
2537 | * 'Address Map' and 'Misc' device regs) | |
2538 | */ | |
2539 | static void amd64_read_mc_registers(struct amd64_pvt *pvt) | |
2540 | { | |
2541 | u64 msr_val; | |
2542 | int dram, err = 0; | |
2543 | ||
2544 | /* | |
2545 | * Retrieve TOP_MEM and TOP_MEM2; no masking off of reserved bits since | |
2546 | * those are Read-As-Zero | |
2547 | */ | |
2548 | rdmsrl(MSR_K8_TOP_MEM1, msr_val); | |
2549 | pvt->top_mem = msr_val >> 23; | |
2550 | debugf0(" TOP_MEM=0x%08llx\n", pvt->top_mem); | |
2551 | ||
2552 | /* check first whether TOP_MEM2 is enabled */ | |
2553 | rdmsrl(MSR_K8_SYSCFG, msr_val); | |
2554 | if (msr_val & (1U << 21)) { | |
2555 | rdmsrl(MSR_K8_TOP_MEM2, msr_val); | |
2556 | pvt->top_mem2 = msr_val >> 23; | |
2557 | debugf0(" TOP_MEM2=0x%08llx\n", pvt->top_mem2); | |
2558 | } else | |
2559 | debugf0(" TOP_MEM2 disabled.\n"); | |
2560 | ||
2561 | amd64_cpu_display_info(pvt); | |
2562 | ||
2563 | err = pci_read_config_dword(pvt->misc_f3_ctl, K8_NBCAP, &pvt->nbcap); | |
2564 | if (err) | |
2565 | goto err_reg; | |
2566 | ||
2567 | if (pvt->ops->read_dram_ctl_register) | |
2568 | pvt->ops->read_dram_ctl_register(pvt); | |
2569 | ||
2570 | for (dram = 0; dram < DRAM_REG_COUNT; dram++) { | |
2571 | /* | |
2572 | * Call CPU specific READ function to get the DRAM Base and | |
2573 | * Limit values from the DCT. | |
2574 | */ | |
2575 | pvt->ops->read_dram_base_limit(pvt, dram); | |
2576 | ||
2577 | /* | |
2578 | * Only print out debug info on rows with both R and W Enabled. | |
2579 | * Normal processing, compiler should optimize this whole 'if' | |
2580 | * debug output block away. | |
2581 | */ | |
2582 | if (pvt->dram_rw_en[dram] != 0) { | |
2583 | debugf1(" DRAM_BASE[%d]: 0x%8.08x-%8.08x " | |
2584 | "DRAM_LIMIT: 0x%8.08x-%8.08x\n", | |
2585 | dram, | |
2586 | (u32)(pvt->dram_base[dram] >> 32), | |
2587 | (u32)(pvt->dram_base[dram] & 0xFFFFFFFF), | |
2588 | (u32)(pvt->dram_limit[dram] >> 32), | |
2589 | (u32)(pvt->dram_limit[dram] & 0xFFFFFFFF)); | |
2590 | debugf1(" IntlvEn=%s %s %s " | |
2591 | "IntlvSel=%d DstNode=%d\n", | |
2592 | pvt->dram_IntlvEn[dram] ? | |
2593 | "Enabled" : "Disabled", | |
2594 | (pvt->dram_rw_en[dram] & 0x2) ? "W" : "!W", | |
2595 | (pvt->dram_rw_en[dram] & 0x1) ? "R" : "!R", | |
2596 | pvt->dram_IntlvSel[dram], | |
2597 | pvt->dram_DstNode[dram]); | |
2598 | } | |
2599 | } | |
2600 | ||
2601 | amd64_read_dct_base_mask(pvt); | |
2602 | ||
2603 | err = pci_read_config_dword(pvt->addr_f1_ctl, K8_DHAR, &pvt->dhar); | |
2604 | if (err) | |
2605 | goto err_reg; | |
2606 | ||
2607 | amd64_read_dbam_reg(pvt); | |
2608 | ||
2609 | err = pci_read_config_dword(pvt->misc_f3_ctl, | |
2610 | F10_ONLINE_SPARE, &pvt->online_spare); | |
2611 | if (err) | |
2612 | goto err_reg; | |
2613 | ||
2614 | err = pci_read_config_dword(pvt->dram_f2_ctl, F10_DCLR_0, &pvt->dclr0); | |
2615 | if (err) | |
2616 | goto err_reg; | |
2617 | ||
2618 | err = pci_read_config_dword(pvt->dram_f2_ctl, F10_DCHR_0, &pvt->dchr0); | |
2619 | if (err) | |
2620 | goto err_reg; | |
2621 | ||
2622 | if (!dct_ganging_enabled(pvt)) { | |
2623 | err = pci_read_config_dword(pvt->dram_f2_ctl, F10_DCLR_1, | |
2624 | &pvt->dclr1); | |
2625 | if (err) | |
2626 | goto err_reg; | |
2627 | ||
2628 | err = pci_read_config_dword(pvt->dram_f2_ctl, F10_DCHR_1, | |
2629 | &pvt->dchr1); | |
2630 | if (err) | |
2631 | goto err_reg; | |
2632 | } | |
2633 | ||
2634 | amd64_dump_misc_regs(pvt); | |
2635 | ||
2636 | err_reg: | |
2637 | debugf0("Reading an MC register failed\n"); | |
2638 | ||
2639 | } | |
2640 | ||
2641 | /* | |
2642 | * NOTE: CPU Revision Dependent code | |
2643 | * | |
2644 | * Input: | |
2645 | * @csrow_nr ChipSelect Row Number (0..CHIPSELECT_COUNT-1) | |
2646 | * k8 private pointer to --> | |
2647 | * DRAM Bank Address mapping register | |
2648 | * node_id | |
2649 | * DCL register where dual_channel_active is | |
2650 | * | |
2651 | * The DBAM register consists of 4 sets of 4 bits each definitions: | |
2652 | * | |
2653 | * Bits: CSROWs | |
2654 | * 0-3 CSROWs 0 and 1 | |
2655 | * 4-7 CSROWs 2 and 3 | |
2656 | * 8-11 CSROWs 4 and 5 | |
2657 | * 12-15 CSROWs 6 and 7 | |
2658 | * | |
2659 | * Values range from: 0 to 15 | |
2660 | * The meaning of the values depends on CPU revision and dual-channel state, | |
2661 | * see relevant BKDG more info. | |
2662 | * | |
2663 | * The memory controller provides for total of only 8 CSROWs in its current | |
2664 | * architecture. Each "pair" of CSROWs normally represents just one DIMM in | |
2665 | * single channel or two (2) DIMMs in dual channel mode. | |
2666 | * | |
2667 | * The following code logic collapses the various tables for CSROW based on CPU | |
2668 | * revision. | |
2669 | * | |
2670 | * Returns: | |
2671 | * The number of PAGE_SIZE pages on the specified CSROW number it | |
2672 | * encompasses | |
2673 | * | |
2674 | */ | |
2675 | static u32 amd64_csrow_nr_pages(int csrow_nr, struct amd64_pvt *pvt) | |
2676 | { | |
2677 | u32 dram_map, nr_pages; | |
2678 | ||
2679 | /* | |
2680 | * The math on this doesn't look right on the surface because x/2*4 can | |
2681 | * be simplified to x*2 but this expression makes use of the fact that | |
2682 | * it is integral math where 1/2=0. This intermediate value becomes the | |
2683 | * number of bits to shift the DBAM register to extract the proper CSROW | |
2684 | * field. | |
2685 | */ | |
2686 | dram_map = (pvt->dbam0 >> ((csrow_nr / 2) * 4)) & 0xF; | |
2687 | ||
2688 | nr_pages = pvt->ops->dbam_map_to_pages(pvt, dram_map); | |
2689 | ||
2690 | /* | |
2691 | * If dual channel then double the memory size of single channel. | |
2692 | * Channel count is 1 or 2 | |
2693 | */ | |
2694 | nr_pages <<= (pvt->channel_count - 1); | |
2695 | ||
2696 | debugf0(" (csrow=%d) DBAM map index= %d\n", csrow_nr, dram_map); | |
2697 | debugf0(" nr_pages= %u channel-count = %d\n", | |
2698 | nr_pages, pvt->channel_count); | |
2699 | ||
2700 | return nr_pages; | |
2701 | } | |
2702 | ||
2703 | /* | |
2704 | * Initialize the array of csrow attribute instances, based on the values | |
2705 | * from pci config hardware registers. | |
2706 | */ | |
2707 | static int amd64_init_csrows(struct mem_ctl_info *mci) | |
2708 | { | |
2709 | struct csrow_info *csrow; | |
2710 | struct amd64_pvt *pvt; | |
2711 | u64 input_addr_min, input_addr_max, sys_addr; | |
2712 | int i, err = 0, empty = 1; | |
2713 | ||
2714 | pvt = mci->pvt_info; | |
2715 | ||
2716 | err = pci_read_config_dword(pvt->misc_f3_ctl, K8_NBCFG, &pvt->nbcfg); | |
2717 | if (err) | |
2718 | debugf0("Reading K8_NBCFG failed\n"); | |
2719 | ||
2720 | debugf0("NBCFG= 0x%x CHIPKILL= %s DRAM ECC= %s\n", pvt->nbcfg, | |
2721 | (pvt->nbcfg & K8_NBCFG_CHIPKILL) ? "Enabled" : "Disabled", | |
2722 | (pvt->nbcfg & K8_NBCFG_ECC_ENABLE) ? "Enabled" : "Disabled" | |
2723 | ); | |
2724 | ||
2725 | for (i = 0; i < CHIPSELECT_COUNT; i++) { | |
2726 | csrow = &mci->csrows[i]; | |
2727 | ||
2728 | if ((pvt->dcsb0[i] & K8_DCSB_CS_ENABLE) == 0) { | |
2729 | debugf1("----CSROW %d EMPTY for node %d\n", i, | |
2730 | pvt->mc_node_id); | |
2731 | continue; | |
2732 | } | |
2733 | ||
2734 | debugf1("----CSROW %d VALID for MC node %d\n", | |
2735 | i, pvt->mc_node_id); | |
2736 | ||
2737 | empty = 0; | |
2738 | csrow->nr_pages = amd64_csrow_nr_pages(i, pvt); | |
2739 | find_csrow_limits(mci, i, &input_addr_min, &input_addr_max); | |
2740 | sys_addr = input_addr_to_sys_addr(mci, input_addr_min); | |
2741 | csrow->first_page = (u32) (sys_addr >> PAGE_SHIFT); | |
2742 | sys_addr = input_addr_to_sys_addr(mci, input_addr_max); | |
2743 | csrow->last_page = (u32) (sys_addr >> PAGE_SHIFT); | |
2744 | csrow->page_mask = ~mask_from_dct_mask(pvt, i); | |
2745 | /* 8 bytes of resolution */ | |
2746 | ||
2747 | csrow->mtype = amd64_determine_memory_type(pvt); | |
2748 | ||
2749 | debugf1(" for MC node %d csrow %d:\n", pvt->mc_node_id, i); | |
2750 | debugf1(" input_addr_min: 0x%lx input_addr_max: 0x%lx\n", | |
2751 | (unsigned long)input_addr_min, | |
2752 | (unsigned long)input_addr_max); | |
2753 | debugf1(" sys_addr: 0x%lx page_mask: 0x%lx\n", | |
2754 | (unsigned long)sys_addr, csrow->page_mask); | |
2755 | debugf1(" nr_pages: %u first_page: 0x%lx " | |
2756 | "last_page: 0x%lx\n", | |
2757 | (unsigned)csrow->nr_pages, | |
2758 | csrow->first_page, csrow->last_page); | |
2759 | ||
2760 | /* | |
2761 | * determine whether CHIPKILL or JUST ECC or NO ECC is operating | |
2762 | */ | |
2763 | if (pvt->nbcfg & K8_NBCFG_ECC_ENABLE) | |
2764 | csrow->edac_mode = | |
2765 | (pvt->nbcfg & K8_NBCFG_CHIPKILL) ? | |
2766 | EDAC_S4ECD4ED : EDAC_SECDED; | |
2767 | else | |
2768 | csrow->edac_mode = EDAC_NONE; | |
2769 | } | |
2770 | ||
2771 | return empty; | |
2772 | } | |
d27bf6fa | 2773 | |
f9431992 DT |
2774 | /* |
2775 | * Only if 'ecc_enable_override' is set AND BIOS had ECC disabled, do "we" | |
2776 | * enable it. | |
2777 | */ | |
2778 | static void amd64_enable_ecc_error_reporting(struct mem_ctl_info *mci) | |
2779 | { | |
2780 | struct amd64_pvt *pvt = mci->pvt_info; | |
2781 | const cpumask_t *cpumask = cpumask_of_node(pvt->mc_node_id); | |
2782 | int cpu, idx = 0, err = 0; | |
2783 | struct msr msrs[cpumask_weight(cpumask)]; | |
2784 | u32 value; | |
2785 | u32 mask = K8_NBCTL_CECCEn | K8_NBCTL_UECCEn; | |
2786 | ||
2787 | if (!ecc_enable_override) | |
2788 | return; | |
2789 | ||
2790 | memset(msrs, 0, sizeof(msrs)); | |
2791 | ||
2792 | amd64_printk(KERN_WARNING, | |
2793 | "'ecc_enable_override' parameter is active, " | |
2794 | "Enabling AMD ECC hardware now: CAUTION\n"); | |
2795 | ||
2796 | err = pci_read_config_dword(pvt->misc_f3_ctl, K8_NBCTL, &value); | |
2797 | if (err) | |
2798 | debugf0("Reading K8_NBCTL failed\n"); | |
2799 | ||
2800 | /* turn on UECCn and CECCEn bits */ | |
2801 | pvt->old_nbctl = value & mask; | |
2802 | pvt->nbctl_mcgctl_saved = 1; | |
2803 | ||
2804 | value |= mask; | |
2805 | pci_write_config_dword(pvt->misc_f3_ctl, K8_NBCTL, value); | |
2806 | ||
2807 | rdmsr_on_cpus(cpumask, K8_MSR_MCGCTL, msrs); | |
2808 | ||
2809 | for_each_cpu(cpu, cpumask) { | |
2810 | if (msrs[idx].l & K8_MSR_MCGCTL_NBE) | |
2811 | set_bit(idx, &pvt->old_mcgctl); | |
2812 | ||
2813 | msrs[idx].l |= K8_MSR_MCGCTL_NBE; | |
2814 | idx++; | |
2815 | } | |
2816 | wrmsr_on_cpus(cpumask, K8_MSR_MCGCTL, msrs); | |
2817 | ||
2818 | err = pci_read_config_dword(pvt->misc_f3_ctl, K8_NBCFG, &value); | |
2819 | if (err) | |
2820 | debugf0("Reading K8_NBCFG failed\n"); | |
2821 | ||
2822 | debugf0("NBCFG(1)= 0x%x CHIPKILL= %s ECC_ENABLE= %s\n", value, | |
2823 | (value & K8_NBCFG_CHIPKILL) ? "Enabled" : "Disabled", | |
2824 | (value & K8_NBCFG_ECC_ENABLE) ? "Enabled" : "Disabled"); | |
2825 | ||
2826 | if (!(value & K8_NBCFG_ECC_ENABLE)) { | |
2827 | amd64_printk(KERN_WARNING, | |
2828 | "This node reports that DRAM ECC is " | |
2829 | "currently Disabled; ENABLING now\n"); | |
2830 | ||
2831 | /* Attempt to turn on DRAM ECC Enable */ | |
2832 | value |= K8_NBCFG_ECC_ENABLE; | |
2833 | pci_write_config_dword(pvt->misc_f3_ctl, K8_NBCFG, value); | |
2834 | ||
2835 | err = pci_read_config_dword(pvt->misc_f3_ctl, K8_NBCFG, &value); | |
2836 | if (err) | |
2837 | debugf0("Reading K8_NBCFG failed\n"); | |
2838 | ||
2839 | if (!(value & K8_NBCFG_ECC_ENABLE)) { | |
2840 | amd64_printk(KERN_WARNING, | |
2841 | "Hardware rejects Enabling DRAM ECC checking\n" | |
2842 | "Check memory DIMM configuration\n"); | |
2843 | } else { | |
2844 | amd64_printk(KERN_DEBUG, | |
2845 | "Hardware accepted DRAM ECC Enable\n"); | |
2846 | } | |
2847 | } | |
2848 | debugf0("NBCFG(2)= 0x%x CHIPKILL= %s ECC_ENABLE= %s\n", value, | |
2849 | (value & K8_NBCFG_CHIPKILL) ? "Enabled" : "Disabled", | |
2850 | (value & K8_NBCFG_ECC_ENABLE) ? "Enabled" : "Disabled"); | |
2851 | ||
2852 | pvt->ctl_error_info.nbcfg = value; | |
2853 | } | |
2854 | ||
2855 | static void amd64_restore_ecc_error_reporting(struct amd64_pvt *pvt) | |
2856 | { | |
2857 | const cpumask_t *cpumask = cpumask_of_node(pvt->mc_node_id); | |
2858 | int cpu, idx = 0, err = 0; | |
2859 | struct msr msrs[cpumask_weight(cpumask)]; | |
2860 | u32 value; | |
2861 | u32 mask = K8_NBCTL_CECCEn | K8_NBCTL_UECCEn; | |
2862 | ||
2863 | if (!pvt->nbctl_mcgctl_saved) | |
2864 | return; | |
2865 | ||
2866 | memset(msrs, 0, sizeof(msrs)); | |
2867 | ||
2868 | err = pci_read_config_dword(pvt->misc_f3_ctl, K8_NBCTL, &value); | |
2869 | if (err) | |
2870 | debugf0("Reading K8_NBCTL failed\n"); | |
2871 | value &= ~mask; | |
2872 | value |= pvt->old_nbctl; | |
2873 | ||
2874 | /* restore the NB Enable MCGCTL bit */ | |
2875 | pci_write_config_dword(pvt->misc_f3_ctl, K8_NBCTL, value); | |
2876 | ||
2877 | rdmsr_on_cpus(cpumask, K8_MSR_MCGCTL, msrs); | |
2878 | ||
2879 | for_each_cpu(cpu, cpumask) { | |
2880 | msrs[idx].l &= ~K8_MSR_MCGCTL_NBE; | |
2881 | msrs[idx].l |= | |
2882 | test_bit(idx, &pvt->old_mcgctl) << K8_MSR_MCGCTL_NBE; | |
2883 | idx++; | |
2884 | } | |
2885 | ||
2886 | wrmsr_on_cpus(cpumask, K8_MSR_MCGCTL, msrs); | |
2887 | } | |
2888 | ||
2889 | static void check_mcg_ctl(void *ret) | |
2890 | { | |
2891 | u64 msr_val = 0; | |
2892 | u8 nbe; | |
2893 | ||
2894 | rdmsrl(MSR_IA32_MCG_CTL, msr_val); | |
2895 | nbe = msr_val & K8_MSR_MCGCTL_NBE; | |
2896 | ||
2897 | debugf0("core: %u, MCG_CTL: 0x%llx, NB MSR is %s\n", | |
2898 | raw_smp_processor_id(), msr_val, | |
2899 | (nbe ? "enabled" : "disabled")); | |
2900 | ||
2901 | if (!nbe) | |
2902 | *(int *)ret = 0; | |
2903 | } | |
2904 | ||
2905 | /* check MCG_CTL on all the cpus on this node */ | |
2906 | static int amd64_mcg_ctl_enabled_on_cpus(const cpumask_t *mask) | |
2907 | { | |
2908 | int ret = 1; | |
2909 | preempt_disable(); | |
2910 | smp_call_function_many(mask, check_mcg_ctl, &ret, 1); | |
2911 | preempt_enable(); | |
2912 | ||
2913 | return ret; | |
2914 | } | |
2915 | ||
2916 | /* | |
2917 | * EDAC requires that the BIOS have ECC enabled before taking over the | |
2918 | * processing of ECC errors. This is because the BIOS can properly initialize | |
2919 | * the memory system completely. A command line option allows to force-enable | |
2920 | * hardware ECC later in amd64_enable_ecc_error_reporting(). | |
2921 | */ | |
2922 | static int amd64_check_ecc_enabled(struct amd64_pvt *pvt) | |
2923 | { | |
2924 | u32 value; | |
2925 | int err = 0, ret = 0; | |
2926 | u8 ecc_enabled = 0; | |
2927 | ||
2928 | err = pci_read_config_dword(pvt->misc_f3_ctl, K8_NBCFG, &value); | |
2929 | if (err) | |
2930 | debugf0("Reading K8_NBCTL failed\n"); | |
2931 | ||
2932 | ecc_enabled = !!(value & K8_NBCFG_ECC_ENABLE); | |
2933 | ||
2934 | ret = amd64_mcg_ctl_enabled_on_cpus(cpumask_of_node(pvt->mc_node_id)); | |
2935 | ||
2936 | debugf0("K8_NBCFG=0x%x, DRAM ECC is %s\n", value, | |
2937 | (value & K8_NBCFG_ECC_ENABLE ? "enabled" : "disabled")); | |
2938 | ||
2939 | if (!ecc_enabled || !ret) { | |
2940 | if (!ecc_enabled) { | |
2941 | amd64_printk(KERN_WARNING, "This node reports that " | |
2942 | "Memory ECC is currently " | |
2943 | "disabled.\n"); | |
2944 | ||
2945 | amd64_printk(KERN_WARNING, "bit 0x%lx in register " | |
2946 | "F3x%x of the MISC_CONTROL device (%s) " | |
2947 | "should be enabled\n", K8_NBCFG_ECC_ENABLE, | |
2948 | K8_NBCFG, pci_name(pvt->misc_f3_ctl)); | |
2949 | } | |
2950 | if (!ret) { | |
2951 | amd64_printk(KERN_WARNING, "bit 0x%016lx in MSR 0x%08x " | |
2952 | "of node %d should be enabled\n", | |
2953 | K8_MSR_MCGCTL_NBE, MSR_IA32_MCG_CTL, | |
2954 | pvt->mc_node_id); | |
2955 | } | |
2956 | if (!ecc_enable_override) { | |
2957 | amd64_printk(KERN_WARNING, "WARNING: ECC is NOT " | |
2958 | "currently enabled by the BIOS. Module " | |
2959 | "will NOT be loaded.\n" | |
2960 | " Either Enable ECC in the BIOS, " | |
2961 | "or use the 'ecc_enable_override' " | |
2962 | "parameter.\n" | |
2963 | " Might be a BIOS bug, if BIOS says " | |
2964 | "ECC is enabled\n" | |
2965 | " Use of the override can cause " | |
2966 | "unknown side effects.\n"); | |
2967 | ret = -ENODEV; | |
2968 | } | |
2969 | } else { | |
2970 | amd64_printk(KERN_INFO, | |
2971 | "ECC is enabled by BIOS, Proceeding " | |
2972 | "with EDAC module initialization\n"); | |
2973 | ||
2974 | /* CLEAR the override, since BIOS controlled it */ | |
2975 | ecc_enable_override = 0; | |
2976 | } | |
2977 | ||
2978 | return ret; | |
2979 | } | |
2980 |