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cfe40fdb DT |
1 | /* |
2 | * AMD64 class Memory Controller kernel module | |
3 | * | |
4 | * Copyright (c) 2009 SoftwareBitMaker. | |
5 | * Copyright (c) 2009 Advanced Micro Devices, Inc. | |
6 | * | |
7 | * This file may be distributed under the terms of the | |
8 | * GNU General Public License. | |
9 | * | |
10 | * Originally Written by Thayne Harbaugh | |
11 | * | |
12 | * Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>: | |
13 | * - K8 CPU Revision D and greater support | |
14 | * | |
15 | * Changes by Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>: | |
16 | * - Module largely rewritten, with new (and hopefully correct) | |
17 | * code for dealing with node and chip select interleaving, | |
18 | * various code cleanup, and bug fixes | |
19 | * - Added support for memory hoisting using DRAM hole address | |
20 | * register | |
21 | * | |
22 | * Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>: | |
23 | * -K8 Rev (1207) revision support added, required Revision | |
24 | * specific mini-driver code to support Rev F as well as | |
25 | * prior revisions | |
26 | * | |
27 | * Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>: | |
28 | * -Family 10h revision support added. New PCI Device IDs, | |
29 | * indicating new changes. Actual registers modified | |
30 | * were slight, less than the Rev E to Rev F transition | |
31 | * but changing the PCI Device ID was the proper thing to | |
32 | * do, as it provides for almost automactic family | |
33 | * detection. The mods to Rev F required more family | |
34 | * information detection. | |
35 | * | |
43aff26c | 36 | * Changes/Fixes by Borislav Petkov <bp@alien8.de>: |
cfe40fdb DT |
37 | * - misc fixes and code cleanups |
38 | * | |
39 | * This module is based on the following documents | |
40 | * (available from http://www.amd.com/): | |
41 | * | |
42 | * Title: BIOS and Kernel Developer's Guide for AMD Athlon 64 and AMD | |
43 | * Opteron Processors | |
44 | * AMD publication #: 26094 | |
45 | *` Revision: 3.26 | |
46 | * | |
47 | * Title: BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh | |
48 | * Processors | |
49 | * AMD publication #: 32559 | |
50 | * Revision: 3.00 | |
51 | * Issue Date: May 2006 | |
52 | * | |
53 | * Title: BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h | |
54 | * Processors | |
55 | * AMD publication #: 31116 | |
56 | * Revision: 3.00 | |
57 | * Issue Date: September 07, 2007 | |
58 | * | |
59 | * Sections in the first 2 documents are no longer in sync with each other. | |
60 | * The Family 10h BKDG was totally re-written from scratch with a new | |
61 | * presentation model. | |
62 | * Therefore, comments that refer to a Document section might be off. | |
63 | */ | |
64 | ||
65 | #include <linux/module.h> | |
66 | #include <linux/ctype.h> | |
67 | #include <linux/init.h> | |
68 | #include <linux/pci.h> | |
69 | #include <linux/pci_ids.h> | |
70 | #include <linux/slab.h> | |
71 | #include <linux/mmzone.h> | |
72 | #include <linux/edac.h> | |
f9431992 | 73 | #include <asm/msr.h> |
cfe40fdb | 74 | #include "edac_core.h" |
47ca08a4 | 75 | #include "mce_amd.h" |
cfe40fdb | 76 | |
24f9a7fe BP |
77 | #define amd64_debug(fmt, arg...) \ |
78 | edac_printk(KERN_DEBUG, "amd64", fmt, ##arg) | |
cfe40fdb | 79 | |
24f9a7fe BP |
80 | #define amd64_info(fmt, arg...) \ |
81 | edac_printk(KERN_INFO, "amd64", fmt, ##arg) | |
82 | ||
83 | #define amd64_notice(fmt, arg...) \ | |
84 | edac_printk(KERN_NOTICE, "amd64", fmt, ##arg) | |
85 | ||
86 | #define amd64_warn(fmt, arg...) \ | |
87 | edac_printk(KERN_WARNING, "amd64", fmt, ##arg) | |
88 | ||
89 | #define amd64_err(fmt, arg...) \ | |
90 | edac_printk(KERN_ERR, "amd64", fmt, ##arg) | |
91 | ||
92 | #define amd64_mc_warn(mci, fmt, arg...) \ | |
93 | edac_mc_chipset_printk(mci, KERN_WARNING, "amd64", fmt, ##arg) | |
94 | ||
95 | #define amd64_mc_err(mci, fmt, arg...) \ | |
96 | edac_mc_chipset_printk(mci, KERN_ERR, "amd64", fmt, ##arg) | |
cfe40fdb DT |
97 | |
98 | /* | |
99 | * Throughout the comments in this code, the following terms are used: | |
100 | * | |
101 | * SysAddr, DramAddr, and InputAddr | |
102 | * | |
103 | * These terms come directly from the amd64 documentation | |
104 | * (AMD publication #26094). They are defined as follows: | |
105 | * | |
106 | * SysAddr: | |
107 | * This is a physical address generated by a CPU core or a device | |
108 | * doing DMA. If generated by a CPU core, a SysAddr is the result of | |
109 | * a virtual to physical address translation by the CPU core's address | |
110 | * translation mechanism (MMU). | |
111 | * | |
112 | * DramAddr: | |
113 | * A DramAddr is derived from a SysAddr by subtracting an offset that | |
114 | * depends on which node the SysAddr maps to and whether the SysAddr | |
115 | * is within a range affected by memory hoisting. The DRAM Base | |
116 | * (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers | |
117 | * determine which node a SysAddr maps to. | |
118 | * | |
119 | * If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr | |
120 | * is within the range of addresses specified by this register, then | |
121 | * a value x from the DHAR is subtracted from the SysAddr to produce a | |
122 | * DramAddr. Here, x represents the base address for the node that | |
123 | * the SysAddr maps to plus an offset due to memory hoisting. See | |
124 | * section 3.4.8 and the comments in amd64_get_dram_hole_info() and | |
125 | * sys_addr_to_dram_addr() below for more information. | |
126 | * | |
127 | * If the SysAddr is not affected by the DHAR then a value y is | |
128 | * subtracted from the SysAddr to produce a DramAddr. Here, y is the | |
129 | * base address for the node that the SysAddr maps to. See section | |
130 | * 3.4.4 and the comments in sys_addr_to_dram_addr() below for more | |
131 | * information. | |
132 | * | |
133 | * InputAddr: | |
134 | * A DramAddr is translated to an InputAddr before being passed to the | |
135 | * memory controller for the node that the DramAddr is associated | |
136 | * with. The memory controller then maps the InputAddr to a csrow. | |
137 | * If node interleaving is not in use, then the InputAddr has the same | |
138 | * value as the DramAddr. Otherwise, the InputAddr is produced by | |
139 | * discarding the bits used for node interleaving from the DramAddr. | |
140 | * See section 3.4.4 for more information. | |
141 | * | |
142 | * The memory controller for a given node uses its DRAM CS Base and | |
143 | * DRAM CS Mask registers to map an InputAddr to a csrow. See | |
144 | * sections 3.5.4 and 3.5.5 for more information. | |
145 | */ | |
146 | ||
df71a053 | 147 | #define EDAC_AMD64_VERSION "3.4.0" |
cfe40fdb DT |
148 | #define EDAC_MOD_STR "amd64_edac" |
149 | ||
150 | /* Extended Model from CPUID, for CPU Revision numbers */ | |
1433eb99 BP |
151 | #define K8_REV_D 1 |
152 | #define K8_REV_E 2 | |
153 | #define K8_REV_F 4 | |
cfe40fdb DT |
154 | |
155 | /* Hardware limit on ChipSelect rows per MC and processors per system */ | |
7f19bf75 BP |
156 | #define NUM_CHIPSELECTS 8 |
157 | #define DRAM_RANGES 8 | |
cfe40fdb | 158 | |
f6d6ae96 BP |
159 | #define ON true |
160 | #define OFF false | |
cfe40fdb DT |
161 | |
162 | /* | |
163 | * PCI-defined configuration space registers | |
164 | */ | |
18b94f66 AG |
165 | #define PCI_DEVICE_ID_AMD_15H_M30H_NB_F1 0x141b |
166 | #define PCI_DEVICE_ID_AMD_15H_M30H_NB_F2 0x141c | |
df71a053 BP |
167 | #define PCI_DEVICE_ID_AMD_15H_NB_F1 0x1601 |
168 | #define PCI_DEVICE_ID_AMD_15H_NB_F2 0x1602 | |
94c1acf2 AG |
169 | #define PCI_DEVICE_ID_AMD_16H_NB_F1 0x1531 |
170 | #define PCI_DEVICE_ID_AMD_16H_NB_F2 0x1532 | |
85a8885b AG |
171 | #define PCI_DEVICE_ID_AMD_16H_M30H_NB_F1 0x1581 |
172 | #define PCI_DEVICE_ID_AMD_16H_M30H_NB_F2 0x1582 | |
cfe40fdb DT |
173 | |
174 | /* | |
175 | * Function 1 - Address Map | |
176 | */ | |
7f19bf75 BP |
177 | #define DRAM_BASE_LO 0x40 |
178 | #define DRAM_LIMIT_LO 0x44 | |
179 | ||
18b94f66 AG |
180 | /* |
181 | * F15 M30h D18F1x2[1C:00] | |
182 | */ | |
183 | #define DRAM_CONT_BASE 0x200 | |
184 | #define DRAM_CONT_LIMIT 0x204 | |
185 | ||
186 | /* | |
187 | * F15 M30h D18F1x2[4C:40] | |
188 | */ | |
189 | #define DRAM_CONT_HIGH_OFF 0x240 | |
190 | ||
151fa71c BP |
191 | #define dram_rw(pvt, i) ((u8)(pvt->ranges[i].base.lo & 0x3)) |
192 | #define dram_intlv_sel(pvt, i) ((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7)) | |
193 | #define dram_dst_node(pvt, i) ((u8)(pvt->ranges[i].lim.lo & 0x7)) | |
7f19bf75 | 194 | |
bc21fa57 | 195 | #define DHAR 0xf0 |
c8e518d5 BP |
196 | #define dhar_mem_hoist_valid(pvt) ((pvt)->dhar & BIT(1)) |
197 | #define dhar_base(pvt) ((pvt)->dhar & 0xff000000) | |
198 | #define k8_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff00) << 16) | |
cfe40fdb | 199 | |
cfe40fdb | 200 | /* NOTE: Extra mask bit vs K8 */ |
c8e518d5 | 201 | #define f10_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff80) << 16) |
cfe40fdb | 202 | |
b2b0c605 | 203 | #define DCT_CFG_SEL 0x10C |
cfe40fdb | 204 | |
c1ae6830 | 205 | #define DRAM_LOCAL_NODE_BASE 0x120 |
f08e457c BP |
206 | #define DRAM_LOCAL_NODE_LIM 0x124 |
207 | ||
7f19bf75 BP |
208 | #define DRAM_BASE_HI 0x140 |
209 | #define DRAM_LIMIT_HI 0x144 | |
cfe40fdb DT |
210 | |
211 | ||
212 | /* | |
213 | * Function 2 - DRAM controller | |
214 | */ | |
11c75ead BP |
215 | #define DCSB0 0x40 |
216 | #define DCSB1 0x140 | |
217 | #define DCSB_CS_ENABLE BIT(0) | |
cfe40fdb | 218 | |
11c75ead BP |
219 | #define DCSM0 0x60 |
220 | #define DCSM1 0x160 | |
cfe40fdb | 221 | |
11c75ead | 222 | #define csrow_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE) |
cfe40fdb DT |
223 | |
224 | #define DBAM0 0x80 | |
225 | #define DBAM1 0x180 | |
226 | ||
227 | /* Extract the DIMM 'type' on the i'th DIMM from the DBAM reg value passed */ | |
0a5dfc31 | 228 | #define DBAM_DIMM(i, reg) ((((reg) >> (4*(i)))) & 0xF) |
cfe40fdb DT |
229 | |
230 | #define DBAM_MAX_VALUE 11 | |
231 | ||
cb328507 BP |
232 | #define DCLR0 0x90 |
233 | #define DCLR1 0x190 | |
cfe40fdb | 234 | #define REVE_WIDTH_128 BIT(16) |
41d8bfab | 235 | #define WIDTH_128 BIT(11) |
cfe40fdb | 236 | |
cb328507 BP |
237 | #define DCHR0 0x94 |
238 | #define DCHR1 0x194 | |
1433eb99 | 239 | #define DDR3_MODE BIT(8) |
cfe40fdb | 240 | |
78da121e | 241 | #define DCT_SEL_LO 0x110 |
78da121e BP |
242 | #define dct_high_range_enabled(pvt) ((pvt)->dct_sel_lo & BIT(0)) |
243 | #define dct_interleave_enabled(pvt) ((pvt)->dct_sel_lo & BIT(2)) | |
cb328507 | 244 | |
78da121e | 245 | #define dct_ganging_enabled(pvt) ((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4))) |
cb328507 | 246 | |
78da121e | 247 | #define dct_data_intlv_enabled(pvt) ((pvt)->dct_sel_lo & BIT(5)) |
78da121e | 248 | #define dct_memory_cleared(pvt) ((pvt)->dct_sel_lo & BIT(10)) |
cfe40fdb | 249 | |
95b0ef55 BP |
250 | #define SWAP_INTLV_REG 0x10c |
251 | ||
78da121e | 252 | #define DCT_SEL_HI 0x114 |
cfe40fdb | 253 | |
cfe40fdb DT |
254 | /* |
255 | * Function 3 - Misc Control | |
256 | */ | |
c9f4f26e | 257 | #define NBCTL 0x40 |
cfe40fdb | 258 | |
a97fa68e BP |
259 | #define NBCFG 0x44 |
260 | #define NBCFG_CHIPKILL BIT(23) | |
261 | #define NBCFG_ECC_ENABLE BIT(22) | |
cfe40fdb | 262 | |
5980bb9c | 263 | /* F3x48: NBSL */ |
cfe40fdb | 264 | #define F10_NBSL_EXT_ERR_ECC 0x8 |
5980bb9c | 265 | #define NBSL_PP_OBS 0x2 |
cfe40fdb | 266 | |
5980bb9c | 267 | #define SCRCTRL 0x58 |
cfe40fdb DT |
268 | |
269 | #define F10_ONLINE_SPARE 0xB0 | |
614ec9d8 BP |
270 | #define online_spare_swap_done(pvt, c) (((pvt)->online_spare >> (1 + 2 * (c))) & 0x1) |
271 | #define online_spare_bad_dramcs(pvt, c) (((pvt)->online_spare >> (4 + 4 * (c))) & 0x7) | |
cfe40fdb DT |
272 | |
273 | #define F10_NB_ARRAY_ADDR 0xB8 | |
6e71a870 | 274 | #define F10_NB_ARRAY_DRAM BIT(31) |
cfe40fdb DT |
275 | |
276 | /* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline */ | |
6e71a870 | 277 | #define SET_NB_ARRAY_ADDR(section) (((section) & 0x3) << 1) |
cfe40fdb DT |
278 | |
279 | #define F10_NB_ARRAY_DATA 0xBC | |
66fed2d4 | 280 | #define F10_NB_ARR_ECC_WR_REQ BIT(17) |
6e71a870 BP |
281 | #define SET_NB_DRAM_INJECTION_WRITE(inj) \ |
282 | (BIT(((inj.word) & 0xF) + 20) | \ | |
66fed2d4 | 283 | F10_NB_ARR_ECC_WR_REQ | inj.bit_map) |
6e71a870 BP |
284 | #define SET_NB_DRAM_INJECTION_READ(inj) \ |
285 | (BIT(((inj.word) & 0xF) + 20) | \ | |
286 | BIT(16) | inj.bit_map) | |
287 | ||
cfe40fdb | 288 | |
5980bb9c BP |
289 | #define NBCAP 0xE8 |
290 | #define NBCAP_CHIPKILL BIT(4) | |
291 | #define NBCAP_SECDED BIT(3) | |
292 | #define NBCAP_DCT_DUAL BIT(0) | |
cfe40fdb | 293 | |
ad6a32e9 BP |
294 | #define EXT_NB_MCA_CFG 0x180 |
295 | ||
f6d6ae96 | 296 | /* MSRs */ |
5980bb9c | 297 | #define MSR_MCGCTL_NBE BIT(4) |
cfe40fdb | 298 | |
b2b0c605 | 299 | enum amd_families { |
cfe40fdb DT |
300 | K8_CPUS = 0, |
301 | F10_CPUS, | |
b2b0c605 | 302 | F15_CPUS, |
18b94f66 | 303 | F15_M30H_CPUS, |
94c1acf2 | 304 | F16_CPUS, |
85a8885b | 305 | F16_M30H_CPUS, |
b2b0c605 | 306 | NUM_FAMILIES, |
cfe40fdb DT |
307 | }; |
308 | ||
cfe40fdb DT |
309 | /* Error injection control structure */ |
310 | struct error_injection { | |
66fed2d4 BP |
311 | u32 section; |
312 | u32 word; | |
313 | u32 bit_map; | |
cfe40fdb DT |
314 | }; |
315 | ||
7f19bf75 BP |
316 | /* low and high part of PCI config space regs */ |
317 | struct reg_pair { | |
318 | u32 lo, hi; | |
319 | }; | |
320 | ||
321 | /* | |
322 | * See F1x[1, 0][7C:40] DRAM Base/Limit Registers | |
323 | */ | |
324 | struct dram_range { | |
325 | struct reg_pair base; | |
326 | struct reg_pair lim; | |
327 | }; | |
328 | ||
11c75ead BP |
329 | /* A DCT chip selects collection */ |
330 | struct chip_select { | |
331 | u32 csbases[NUM_CHIPSELECTS]; | |
332 | u8 b_cnt; | |
333 | ||
334 | u32 csmasks[NUM_CHIPSELECTS]; | |
335 | u8 m_cnt; | |
336 | }; | |
337 | ||
cfe40fdb | 338 | struct amd64_pvt { |
b8cfa02f BP |
339 | struct low_ops *ops; |
340 | ||
cfe40fdb | 341 | /* pci_device handles which we utilize */ |
8d5b5d9c | 342 | struct pci_dev *F1, *F2, *F3; |
cfe40fdb | 343 | |
c7e5301a | 344 | u16 mc_node_id; /* MC index of this MC node */ |
18b94f66 | 345 | u8 fam; /* CPU family */ |
a4b4bedc BP |
346 | u8 model; /* ... model */ |
347 | u8 stepping; /* ... stepping */ | |
348 | ||
cfe40fdb | 349 | int ext_model; /* extended model value of this node */ |
cfe40fdb DT |
350 | int channel_count; |
351 | ||
352 | /* Raw registers */ | |
353 | u32 dclr0; /* DRAM Configuration Low DCT0 reg */ | |
354 | u32 dclr1; /* DRAM Configuration Low DCT1 reg */ | |
355 | u32 dchr0; /* DRAM Configuration High DCT0 reg */ | |
356 | u32 dchr1; /* DRAM Configuration High DCT1 reg */ | |
357 | u32 nbcap; /* North Bridge Capabilities */ | |
358 | u32 nbcfg; /* F10 North Bridge Configuration */ | |
359 | u32 ext_nbcfg; /* Extended F10 North Bridge Configuration */ | |
360 | u32 dhar; /* DRAM Hoist reg */ | |
361 | u32 dbam0; /* DRAM Base Address Mapping reg for DCT0 */ | |
362 | u32 dbam1; /* DRAM Base Address Mapping reg for DCT1 */ | |
363 | ||
11c75ead BP |
364 | /* one for each DCT */ |
365 | struct chip_select csels[2]; | |
cfe40fdb | 366 | |
7f19bf75 BP |
367 | /* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */ |
368 | struct dram_range ranges[DRAM_RANGES]; | |
cfe40fdb | 369 | |
cfe40fdb DT |
370 | u64 top_mem; /* top of memory below 4GB */ |
371 | u64 top_mem2; /* top of memory above 4GB */ | |
372 | ||
78da121e BP |
373 | u32 dct_sel_lo; /* DRAM Controller Select Low */ |
374 | u32 dct_sel_hi; /* DRAM Controller Select High */ | |
b2b0c605 | 375 | u32 online_spare; /* On-Line spare Reg */ |
cfe40fdb | 376 | |
ad6a32e9 | 377 | /* x4 or x8 syndromes in use */ |
a3b7db09 | 378 | u8 ecc_sym_sz; |
ad6a32e9 | 379 | |
cfe40fdb DT |
380 | /* place to store error injection parameters prior to issue */ |
381 | struct error_injection injection; | |
ae7bb7c6 BP |
382 | }; |
383 | ||
33ca0643 BP |
384 | enum err_codes { |
385 | DECODE_OK = 0, | |
386 | ERR_NODE = -1, | |
387 | ERR_CSROW = -2, | |
388 | ERR_CHANNEL = -3, | |
389 | }; | |
390 | ||
391 | struct err_info { | |
392 | int err_code; | |
393 | struct mem_ctl_info *src_mci; | |
394 | int csrow; | |
395 | int channel; | |
396 | u16 syndrome; | |
397 | u32 page; | |
398 | u32 offset; | |
399 | }; | |
400 | ||
c7e5301a | 401 | static inline u64 get_dram_base(struct amd64_pvt *pvt, u8 i) |
7f19bf75 BP |
402 | { |
403 | u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8; | |
404 | ||
405 | if (boot_cpu_data.x86 == 0xf) | |
406 | return addr; | |
407 | ||
408 | return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) | addr; | |
409 | } | |
410 | ||
c7e5301a | 411 | static inline u64 get_dram_limit(struct amd64_pvt *pvt, u8 i) |
7f19bf75 BP |
412 | { |
413 | u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) | 0x00ffffff; | |
414 | ||
415 | if (boot_cpu_data.x86 == 0xf) | |
416 | return lim; | |
417 | ||
418 | return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) | lim; | |
419 | } | |
420 | ||
f192c7b1 BP |
421 | static inline u16 extract_syndrome(u64 status) |
422 | { | |
423 | return ((status >> 47) & 0xff) | ((status >> 16) & 0xff00); | |
424 | } | |
425 | ||
18b94f66 AG |
426 | static inline u8 dct_sel_interleave_addr(struct amd64_pvt *pvt) |
427 | { | |
428 | if (pvt->fam == 0x15 && pvt->model >= 0x30) | |
429 | return (((pvt->dct_sel_hi >> 9) & 0x1) << 2) | | |
430 | ((pvt->dct_sel_lo >> 6) & 0x3); | |
431 | ||
432 | return ((pvt)->dct_sel_lo >> 6) & 0x3; | |
433 | } | |
ae7bb7c6 BP |
434 | /* |
435 | * per-node ECC settings descriptor | |
436 | */ | |
437 | struct ecc_settings { | |
438 | u32 old_nbctl; | |
439 | bool nbctl_valid; | |
440 | ||
cfe40fdb | 441 | struct flags { |
d95cf4de BP |
442 | unsigned long nb_mce_enable:1; |
443 | unsigned long nb_ecc_prev:1; | |
cfe40fdb DT |
444 | } flags; |
445 | }; | |
446 | ||
7d6034d3 | 447 | #ifdef CONFIG_EDAC_DEBUG |
c5608759 MCC |
448 | int amd64_create_sysfs_dbg_files(struct mem_ctl_info *mci); |
449 | void amd64_remove_sysfs_dbg_files(struct mem_ctl_info *mci); | |
450 | ||
7d6034d3 | 451 | #else |
c5608759 MCC |
452 | static inline int amd64_create_sysfs_dbg_files(struct mem_ctl_info *mci) |
453 | { | |
454 | return 0; | |
455 | } | |
456 | static void inline amd64_remove_sysfs_dbg_files(struct mem_ctl_info *mci) | |
457 | { | |
458 | } | |
7d6034d3 DT |
459 | #endif |
460 | ||
461 | #ifdef CONFIG_EDAC_AMD64_ERROR_INJECTION | |
c5608759 MCC |
462 | int amd64_create_sysfs_inject_files(struct mem_ctl_info *mci); |
463 | void amd64_remove_sysfs_inject_files(struct mem_ctl_info *mci); | |
464 | ||
7d6034d3 | 465 | #else |
c5608759 MCC |
466 | static inline int amd64_create_sysfs_inject_files(struct mem_ctl_info *mci) |
467 | { | |
468 | return 0; | |
469 | } | |
470 | static inline void amd64_remove_sysfs_inject_files(struct mem_ctl_info *mci) | |
471 | { | |
472 | } | |
7d6034d3 DT |
473 | #endif |
474 | ||
cfe40fdb DT |
475 | /* |
476 | * Each of the PCI Device IDs types have their own set of hardware accessor | |
477 | * functions and per device encoding/decoding logic. | |
478 | */ | |
479 | struct low_ops { | |
1433eb99 | 480 | int (*early_channel_count) (struct amd64_pvt *pvt); |
f192c7b1 | 481 | void (*map_sysaddr_to_csrow) (struct mem_ctl_info *mci, u64 sys_addr, |
33ca0643 | 482 | struct err_info *); |
41d8bfab | 483 | int (*dbam_to_cs) (struct amd64_pvt *pvt, u8 dct, unsigned cs_mode); |
b2b0c605 BP |
484 | int (*read_dct_pci_cfg) (struct amd64_pvt *pvt, int offset, |
485 | u32 *val, const char *func); | |
cfe40fdb DT |
486 | }; |
487 | ||
488 | struct amd64_family_type { | |
489 | const char *ctl_name; | |
8d5b5d9c | 490 | u16 f1_id, f3_id; |
cfe40fdb DT |
491 | struct low_ops ops; |
492 | }; | |
493 | ||
66fed2d4 BP |
494 | int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset, |
495 | u32 *val, const char *func); | |
b2b0c605 BP |
496 | int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset, |
497 | u32 val, const char *func); | |
6ba5dcdc | 498 | |
b2b0c605 BP |
499 | #define amd64_read_pci_cfg(pdev, offset, val) \ |
500 | __amd64_read_pci_cfg_dword(pdev, offset, val, __func__) | |
6ba5dcdc | 501 | |
b2b0c605 BP |
502 | #define amd64_write_pci_cfg(pdev, offset, val) \ |
503 | __amd64_write_pci_cfg_dword(pdev, offset, val, __func__) | |
6ba5dcdc | 504 | |
b2b0c605 BP |
505 | #define amd64_read_dct_pci_cfg(pvt, offset, val) \ |
506 | pvt->ops->read_dct_pci_cfg(pvt, offset, val, __func__) | |
6ba5dcdc | 507 | |
cfe40fdb DT |
508 | int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base, |
509 | u64 *hole_offset, u64 *hole_size); | |
c5608759 MCC |
510 | |
511 | #define to_mci(k) container_of(k, struct mem_ctl_info, dev) | |
66fed2d4 BP |
512 | |
513 | /* Injection helpers */ | |
514 | static inline void disable_caches(void *dummy) | |
515 | { | |
516 | write_cr0(read_cr0() | X86_CR0_CD); | |
517 | wbinvd(); | |
518 | } | |
519 | ||
520 | static inline void enable_caches(void *dummy) | |
521 | { | |
522 | write_cr0(read_cr0() & ~X86_CR0_CD); | |
523 | } | |
18b94f66 AG |
524 | |
525 | static inline u8 dram_intlv_en(struct amd64_pvt *pvt, unsigned int i) | |
526 | { | |
527 | if (pvt->fam == 0x15 && pvt->model >= 0x30) { | |
528 | u32 tmp; | |
529 | amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &tmp); | |
530 | return (u8) tmp & 0xF; | |
531 | } | |
532 | return (u8) (pvt->ranges[i].base.lo >> 8) & 0x7; | |
533 | } | |
534 | ||
535 | static inline u8 dhar_valid(struct amd64_pvt *pvt) | |
536 | { | |
537 | if (pvt->fam == 0x15 && pvt->model >= 0x30) { | |
538 | u32 tmp; | |
539 | amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp); | |
540 | return (tmp >> 1) & BIT(0); | |
541 | } | |
542 | return (pvt)->dhar & BIT(0); | |
543 | } | |
544 | ||
545 | static inline u32 dct_sel_baseaddr(struct amd64_pvt *pvt) | |
546 | { | |
547 | if (pvt->fam == 0x15 && pvt->model >= 0x30) { | |
548 | u32 tmp; | |
549 | amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp); | |
550 | return (tmp >> 11) & 0x1FFF; | |
551 | } | |
552 | return (pvt)->dct_sel_lo & 0xFFFFF800; | |
553 | } |