Commit | Line | Data |
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fd3d6780 DT |
1 | #include "amd64_edac.h" |
2 | ||
9cdeb404 BP |
3 | #define EDAC_DCT_ATTR_SHOW(reg) \ |
4 | static ssize_t amd64_##reg##_show(struct mem_ctl_info *mci, char *data) \ | |
5 | { \ | |
6 | struct amd64_pvt *pvt = mci->pvt_info; \ | |
7 | return sprintf(data, "0x%016llx\n", (u64)pvt->reg); \ | |
fd3d6780 DT |
8 | } |
9 | ||
9cdeb404 BP |
10 | EDAC_DCT_ATTR_SHOW(dhar); |
11 | EDAC_DCT_ATTR_SHOW(dbam0); | |
12 | EDAC_DCT_ATTR_SHOW(top_mem); | |
13 | EDAC_DCT_ATTR_SHOW(top_mem2); | |
fd3d6780 DT |
14 | |
15 | static ssize_t amd64_hole_show(struct mem_ctl_info *mci, char *data) | |
16 | { | |
17 | u64 hole_base = 0; | |
18 | u64 hole_offset = 0; | |
19 | u64 hole_size = 0; | |
20 | ||
21 | amd64_get_dram_hole_info(mci, &hole_base, &hole_offset, &hole_size); | |
22 | ||
23 | return sprintf(data, "%llx %llx %llx\n", hole_base, hole_offset, | |
24 | hole_size); | |
25 | } | |
26 | ||
27 | /* | |
28 | * update NUM_DBG_ATTRS in case you add new members | |
29 | */ | |
30 | struct mcidev_sysfs_attribute amd64_dbg_attrs[] = { | |
31 | ||
fd3d6780 DT |
32 | { |
33 | .attr = { | |
34 | .name = "dhar", | |
35 | .mode = (S_IRUGO) | |
36 | }, | |
37 | .show = amd64_dhar_show, | |
38 | .store = NULL, | |
39 | }, | |
40 | { | |
41 | .attr = { | |
42 | .name = "dbam", | |
43 | .mode = (S_IRUGO) | |
44 | }, | |
9cdeb404 | 45 | .show = amd64_dbam0_show, |
fd3d6780 DT |
46 | .store = NULL, |
47 | }, | |
48 | { | |
49 | .attr = { | |
50 | .name = "topmem", | |
51 | .mode = (S_IRUGO) | |
52 | }, | |
9cdeb404 | 53 | .show = amd64_top_mem_show, |
fd3d6780 DT |
54 | .store = NULL, |
55 | }, | |
56 | { | |
57 | .attr = { | |
58 | .name = "topmem2", | |
59 | .mode = (S_IRUGO) | |
60 | }, | |
9cdeb404 | 61 | .show = amd64_top_mem2_show, |
fd3d6780 DT |
62 | .store = NULL, |
63 | }, | |
64 | { | |
65 | .attr = { | |
66 | .name = "dram_hole", | |
67 | .mode = (S_IRUGO) | |
68 | }, | |
69 | .show = amd64_hole_show, | |
70 | .store = NULL, | |
71 | }, | |
72 | }; |