Commit | Line | Data |
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806c35f5 AC |
1 | /* |
2 | * Intel e752x Memory Controller kernel module | |
3 | * (C) 2004 Linux Networx (http://lnxi.com) | |
4 | * This file may be distributed under the terms of the | |
5 | * GNU General Public License. | |
6 | * | |
7 | * See "enum e752x_chips" below for supported chipsets | |
8 | * | |
9 | * Written by Tom Zimmerman | |
10 | * | |
11 | * Contributors: | |
12 | * Thayne Harbaugh at realmsys.com (?) | |
13 | * Wang Zhenyu at intel.com | |
14 | * Dave Jiang at mvista.com | |
15 | * | |
da9bb1d2 | 16 | * $Id: edac_e752x.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $ |
806c35f5 AC |
17 | * |
18 | */ | |
19 | ||
806c35f5 AC |
20 | #include <linux/module.h> |
21 | #include <linux/init.h> | |
806c35f5 AC |
22 | #include <linux/pci.h> |
23 | #include <linux/pci_ids.h> | |
c0d12172 | 24 | #include <linux/edac.h> |
20bcb7a8 | 25 | #include "edac_core.h" |
806c35f5 | 26 | |
152ba394 | 27 | #define E752X_REVISION " Ver: 2.0.2" |
929a40ec | 28 | #define EDAC_MOD_STR "e752x_edac" |
37f04581 | 29 | |
10d33e9c | 30 | static int report_non_memory_errors; |
96941026 | 31 | static int force_function_unhide; |
94ee1cf5 | 32 | static int sysbus_parity = -1; |
96941026 | 33 | |
91b99041 DJ |
34 | static struct edac_pci_ctl_info *e752x_pci; |
35 | ||
537fba28 | 36 | #define e752x_printk(level, fmt, arg...) \ |
e7ecd891 | 37 | edac_printk(level, "e752x", fmt, ##arg) |
537fba28 DP |
38 | |
39 | #define e752x_mc_printk(mci, level, fmt, arg...) \ | |
e7ecd891 | 40 | edac_mc_chipset_printk(mci, level, "e752x", fmt, ##arg) |
537fba28 | 41 | |
806c35f5 AC |
42 | #ifndef PCI_DEVICE_ID_INTEL_7520_0 |
43 | #define PCI_DEVICE_ID_INTEL_7520_0 0x3590 | |
44 | #endif /* PCI_DEVICE_ID_INTEL_7520_0 */ | |
45 | ||
46 | #ifndef PCI_DEVICE_ID_INTEL_7520_1_ERR | |
47 | #define PCI_DEVICE_ID_INTEL_7520_1_ERR 0x3591 | |
48 | #endif /* PCI_DEVICE_ID_INTEL_7520_1_ERR */ | |
49 | ||
50 | #ifndef PCI_DEVICE_ID_INTEL_7525_0 | |
51 | #define PCI_DEVICE_ID_INTEL_7525_0 0x359E | |
52 | #endif /* PCI_DEVICE_ID_INTEL_7525_0 */ | |
53 | ||
54 | #ifndef PCI_DEVICE_ID_INTEL_7525_1_ERR | |
55 | #define PCI_DEVICE_ID_INTEL_7525_1_ERR 0x3593 | |
56 | #endif /* PCI_DEVICE_ID_INTEL_7525_1_ERR */ | |
57 | ||
58 | #ifndef PCI_DEVICE_ID_INTEL_7320_0 | |
59 | #define PCI_DEVICE_ID_INTEL_7320_0 0x3592 | |
60 | #endif /* PCI_DEVICE_ID_INTEL_7320_0 */ | |
61 | ||
62 | #ifndef PCI_DEVICE_ID_INTEL_7320_1_ERR | |
63 | #define PCI_DEVICE_ID_INTEL_7320_1_ERR 0x3593 | |
64 | #endif /* PCI_DEVICE_ID_INTEL_7320_1_ERR */ | |
65 | ||
5135b797 AK |
66 | #ifndef PCI_DEVICE_ID_INTEL_3100_0 |
67 | #define PCI_DEVICE_ID_INTEL_3100_0 0x35B0 | |
68 | #endif /* PCI_DEVICE_ID_INTEL_3100_0 */ | |
69 | ||
70 | #ifndef PCI_DEVICE_ID_INTEL_3100_1_ERR | |
71 | #define PCI_DEVICE_ID_INTEL_3100_1_ERR 0x35B1 | |
72 | #endif /* PCI_DEVICE_ID_INTEL_3100_1_ERR */ | |
73 | ||
806c35f5 AC |
74 | #define E752X_NR_CSROWS 8 /* number of csrows */ |
75 | ||
806c35f5 | 76 | /* E752X register addresses - device 0 function 0 */ |
8004fd2a PT |
77 | #define E752X_MCHSCRB 0x52 /* Memory Scrub register (16b) */ |
78 | /* | |
79 | * 6:5 Scrub Completion Count | |
80 | * 3:2 Scrub Rate (i3100 only) | |
81 | * 01=fast 10=normal | |
82 | * 1:0 Scrub Mode enable | |
83 | * 00=off 10=on | |
84 | */ | |
806c35f5 AC |
85 | #define E752X_DRB 0x60 /* DRAM row boundary register (8b) */ |
86 | #define E752X_DRA 0x70 /* DRAM row attribute register (8b) */ | |
87 | /* | |
88 | * 31:30 Device width row 7 | |
89 | * 01=x8 10=x4 11=x8 DDR2 | |
90 | * 27:26 Device width row 6 | |
91 | * 23:22 Device width row 5 | |
92 | * 19:20 Device width row 4 | |
93 | * 15:14 Device width row 3 | |
94 | * 11:10 Device width row 2 | |
95 | * 7:6 Device width row 1 | |
96 | * 3:2 Device width row 0 | |
97 | */ | |
98 | #define E752X_DRC 0x7C /* DRAM controller mode reg (32b) */ | |
99 | /* FIXME:IS THIS RIGHT? */ | |
100 | /* | |
101 | * 22 Number channels 0=1,1=2 | |
102 | * 19:18 DRB Granularity 32/64MB | |
103 | */ | |
104 | #define E752X_DRM 0x80 /* Dimm mapping register */ | |
105 | #define E752X_DDRCSR 0x9A /* DDR control and status reg (16b) */ | |
106 | /* | |
107 | * 14:12 1 single A, 2 single B, 3 dual | |
108 | */ | |
109 | #define E752X_TOLM 0xC4 /* DRAM top of low memory reg (16b) */ | |
110 | #define E752X_REMAPBASE 0xC6 /* DRAM remap base address reg (16b) */ | |
111 | #define E752X_REMAPLIMIT 0xC8 /* DRAM remap limit address reg (16b) */ | |
112 | #define E752X_REMAPOFFSET 0xCA /* DRAM remap limit offset reg (16b) */ | |
113 | ||
114 | /* E752X register addresses - device 0 function 1 */ | |
115 | #define E752X_FERR_GLOBAL 0x40 /* Global first error register (32b) */ | |
116 | #define E752X_NERR_GLOBAL 0x44 /* Global next error register (32b) */ | |
117 | #define E752X_HI_FERR 0x50 /* Hub interface first error reg (8b) */ | |
118 | #define E752X_HI_NERR 0x52 /* Hub interface next error reg (8b) */ | |
119 | #define E752X_HI_ERRMASK 0x54 /* Hub interface error mask reg (8b) */ | |
120 | #define E752X_HI_SMICMD 0x5A /* Hub interface SMI command reg (8b) */ | |
121 | #define E752X_SYSBUS_FERR 0x60 /* System buss first error reg (16b) */ | |
122 | #define E752X_SYSBUS_NERR 0x62 /* System buss next error reg (16b) */ | |
123 | #define E752X_SYSBUS_ERRMASK 0x64 /* System buss error mask reg (16b) */ | |
124 | #define E752X_SYSBUS_SMICMD 0x6A /* System buss SMI command reg (16b) */ | |
125 | #define E752X_BUF_FERR 0x70 /* Memory buffer first error reg (8b) */ | |
126 | #define E752X_BUF_NERR 0x72 /* Memory buffer next error reg (8b) */ | |
127 | #define E752X_BUF_ERRMASK 0x74 /* Memory buffer error mask reg (8b) */ | |
10d33e9c | 128 | #define E752X_BUF_SMICMD 0x7A /* Memory buffer SMI cmd reg (8b) */ |
806c35f5 AC |
129 | #define E752X_DRAM_FERR 0x80 /* DRAM first error register (16b) */ |
130 | #define E752X_DRAM_NERR 0x82 /* DRAM next error register (16b) */ | |
131 | #define E752X_DRAM_ERRMASK 0x84 /* DRAM error mask register (8b) */ | |
132 | #define E752X_DRAM_SMICMD 0x8A /* DRAM SMI command register (8b) */ | |
133 | #define E752X_DRAM_RETR_ADD 0xAC /* DRAM Retry address register (32b) */ | |
134 | #define E752X_DRAM_SEC1_ADD 0xA0 /* DRAM first correctable memory */ | |
135 | /* error address register (32b) */ | |
136 | /* | |
137 | * 31 Reserved | |
10d33e9c | 138 | * 30:2 CE address (64 byte block 34:6 |
806c35f5 AC |
139 | * 1 Reserved |
140 | * 0 HiLoCS | |
141 | */ | |
142 | #define E752X_DRAM_SEC2_ADD 0xC8 /* DRAM first correctable memory */ | |
143 | /* error address register (32b) */ | |
144 | /* | |
145 | * 31 Reserved | |
146 | * 30:2 CE address (64 byte block 34:6) | |
147 | * 1 Reserved | |
148 | * 0 HiLoCS | |
149 | */ | |
150 | #define E752X_DRAM_DED_ADD 0xA4 /* DRAM first uncorrectable memory */ | |
151 | /* error address register (32b) */ | |
152 | /* | |
153 | * 31 Reserved | |
154 | * 30:2 CE address (64 byte block 34:6) | |
155 | * 1 Reserved | |
156 | * 0 HiLoCS | |
157 | */ | |
10d33e9c | 158 | #define E752X_DRAM_SCRB_ADD 0xA8 /* DRAM 1st uncorrectable scrub mem */ |
806c35f5 AC |
159 | /* error address register (32b) */ |
160 | /* | |
161 | * 31 Reserved | |
10d33e9c | 162 | * 30:2 CE address (64 byte block 34:6 |
806c35f5 AC |
163 | * 1 Reserved |
164 | * 0 HiLoCS | |
165 | */ | |
166 | #define E752X_DRAM_SEC1_SYNDROME 0xC4 /* DRAM first correctable memory */ | |
167 | /* error syndrome register (16b) */ | |
168 | #define E752X_DRAM_SEC2_SYNDROME 0xC6 /* DRAM second correctable memory */ | |
169 | /* error syndrome register (16b) */ | |
170 | #define E752X_DEVPRES1 0xF4 /* Device Present 1 register (8b) */ | |
171 | ||
5135b797 AK |
172 | /* 3100 IMCH specific register addresses - device 0 function 1 */ |
173 | #define I3100_NSI_FERR 0x48 /* NSI first error reg (32b) */ | |
174 | #define I3100_NSI_NERR 0x4C /* NSI next error reg (32b) */ | |
175 | #define I3100_NSI_SMICMD 0x54 /* NSI SMI command register (32b) */ | |
176 | #define I3100_NSI_EMASK 0x90 /* NSI error mask register (32b) */ | |
177 | ||
806c35f5 AC |
178 | /* ICH5R register addresses - device 30 function 0 */ |
179 | #define ICH5R_PCI_STAT 0x06 /* PCI status register (16b) */ | |
180 | #define ICH5R_PCI_2ND_STAT 0x1E /* PCI status secondary reg (16b) */ | |
181 | #define ICH5R_PCI_BRIDGE_CTL 0x3E /* PCI bridge control register (16b) */ | |
182 | ||
183 | enum e752x_chips { | |
184 | E7520 = 0, | |
185 | E7525 = 1, | |
5135b797 AK |
186 | E7320 = 2, |
187 | I3100 = 3 | |
806c35f5 AC |
188 | }; |
189 | ||
806c35f5 AC |
190 | struct e752x_pvt { |
191 | struct pci_dev *bridge_ck; | |
192 | struct pci_dev *dev_d0f0; | |
193 | struct pci_dev *dev_d0f1; | |
194 | u32 tolm; | |
195 | u32 remapbase; | |
196 | u32 remaplimit; | |
197 | int mc_symmetric; | |
198 | u8 map[8]; | |
199 | int map_type; | |
200 | const struct e752x_dev_info *dev_info; | |
201 | }; | |
202 | ||
806c35f5 AC |
203 | struct e752x_dev_info { |
204 | u16 err_dev; | |
3847bccc | 205 | u16 ctl_dev; |
806c35f5 AC |
206 | const char *ctl_name; |
207 | }; | |
208 | ||
209 | struct e752x_error_info { | |
210 | u32 ferr_global; | |
211 | u32 nerr_global; | |
5135b797 AK |
212 | u32 nsi_ferr; /* 3100 only */ |
213 | u32 nsi_nerr; /* 3100 only */ | |
214 | u8 hi_ferr; /* all but 3100 */ | |
215 | u8 hi_nerr; /* all but 3100 */ | |
806c35f5 AC |
216 | u16 sysbus_ferr; |
217 | u16 sysbus_nerr; | |
218 | u8 buf_ferr; | |
219 | u8 buf_nerr; | |
220 | u16 dram_ferr; | |
221 | u16 dram_nerr; | |
222 | u32 dram_sec1_add; | |
223 | u32 dram_sec2_add; | |
224 | u16 dram_sec1_syndrome; | |
225 | u16 dram_sec2_syndrome; | |
226 | u32 dram_ded_add; | |
227 | u32 dram_scrb_add; | |
228 | u32 dram_retr_add; | |
229 | }; | |
230 | ||
231 | static const struct e752x_dev_info e752x_devs[] = { | |
232 | [E7520] = { | |
052dfb45 DT |
233 | .err_dev = PCI_DEVICE_ID_INTEL_7520_1_ERR, |
234 | .ctl_dev = PCI_DEVICE_ID_INTEL_7520_0, | |
235 | .ctl_name = "E7520"}, | |
806c35f5 | 236 | [E7525] = { |
052dfb45 DT |
237 | .err_dev = PCI_DEVICE_ID_INTEL_7525_1_ERR, |
238 | .ctl_dev = PCI_DEVICE_ID_INTEL_7525_0, | |
239 | .ctl_name = "E7525"}, | |
806c35f5 | 240 | [E7320] = { |
052dfb45 DT |
241 | .err_dev = PCI_DEVICE_ID_INTEL_7320_1_ERR, |
242 | .ctl_dev = PCI_DEVICE_ID_INTEL_7320_0, | |
243 | .ctl_name = "E7320"}, | |
5135b797 AK |
244 | [I3100] = { |
245 | .err_dev = PCI_DEVICE_ID_INTEL_3100_1_ERR, | |
246 | .ctl_dev = PCI_DEVICE_ID_INTEL_3100_0, | |
247 | .ctl_name = "3100"}, | |
806c35f5 AC |
248 | }; |
249 | ||
8004fd2a PT |
250 | /* Valid scrub rates for the e752x/3100 hardware memory scrubber. We |
251 | * map the scrubbing bandwidth to a hardware register value. The 'set' | |
252 | * operation finds the 'matching or higher value'. Note that scrubbing | |
253 | * on the e752x can only be enabled/disabled. The 3100 supports | |
254 | * a normal and fast mode. | |
255 | */ | |
256 | ||
257 | #define SDRATE_EOT 0xFFFFFFFF | |
258 | ||
259 | struct scrubrate { | |
260 | u32 bandwidth; /* bandwidth consumed by scrubbing in bytes/sec */ | |
261 | u16 scrubval; /* register value for scrub rate */ | |
262 | }; | |
263 | ||
264 | /* Rate below assumes same performance as i3100 using PC3200 DDR2 in | |
265 | * normal mode. e752x bridges don't support choosing normal or fast mode, | |
266 | * so the scrubbing bandwidth value isn't all that important - scrubbing is | |
267 | * either on or off. | |
268 | */ | |
269 | static const struct scrubrate scrubrates_e752x[] = { | |
270 | {0, 0x00}, /* Scrubbing Off */ | |
271 | {500000, 0x02}, /* Scrubbing On */ | |
272 | {SDRATE_EOT, 0x00} /* End of Table */ | |
273 | }; | |
274 | ||
275 | /* Fast mode: 2 GByte PC3200 DDR2 scrubbed in 33s = 63161283 bytes/s | |
276 | * Normal mode: 125 (32000 / 256) times slower than fast mode. | |
277 | */ | |
278 | static const struct scrubrate scrubrates_i3100[] = { | |
279 | {0, 0x00}, /* Scrubbing Off */ | |
280 | {500000, 0x0a}, /* Normal mode - 32k clocks */ | |
281 | {62500000, 0x06}, /* Fast mode - 256 clocks */ | |
282 | {SDRATE_EOT, 0x00} /* End of Table */ | |
283 | }; | |
284 | ||
806c35f5 | 285 | static unsigned long ctl_page_to_phys(struct mem_ctl_info *mci, |
052dfb45 | 286 | unsigned long page) |
806c35f5 AC |
287 | { |
288 | u32 remap; | |
203333cb | 289 | struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info; |
806c35f5 | 290 | |
537fba28 | 291 | debugf3("%s()\n", __func__); |
806c35f5 AC |
292 | |
293 | if (page < pvt->tolm) | |
294 | return page; | |
e7ecd891 | 295 | |
806c35f5 AC |
296 | if ((page >= 0x100000) && (page < pvt->remapbase)) |
297 | return page; | |
e7ecd891 | 298 | |
806c35f5 | 299 | remap = (page - pvt->tolm) + pvt->remapbase; |
e7ecd891 | 300 | |
806c35f5 AC |
301 | if (remap < pvt->remaplimit) |
302 | return remap; | |
e7ecd891 | 303 | |
537fba28 | 304 | e752x_printk(KERN_ERR, "Invalid page %lx - out of range\n", page); |
806c35f5 AC |
305 | return pvt->tolm - 1; |
306 | } | |
307 | ||
308 | static void do_process_ce(struct mem_ctl_info *mci, u16 error_one, | |
052dfb45 | 309 | u32 sec1_add, u16 sec1_syndrome) |
806c35f5 AC |
310 | { |
311 | u32 page; | |
312 | int row; | |
313 | int channel; | |
314 | int i; | |
203333cb | 315 | struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info; |
806c35f5 | 316 | |
537fba28 | 317 | debugf3("%s()\n", __func__); |
806c35f5 AC |
318 | |
319 | /* convert the addr to 4k page */ | |
320 | page = sec1_add >> (PAGE_SHIFT - 4); | |
321 | ||
322 | /* FIXME - check for -1 */ | |
323 | if (pvt->mc_symmetric) { | |
324 | /* chip select are bits 14 & 13 */ | |
325 | row = ((page >> 1) & 3); | |
537fba28 | 326 | e752x_printk(KERN_WARNING, |
052dfb45 DT |
327 | "Test row %d Table %d %d %d %d %d %d %d %d\n", row, |
328 | pvt->map[0], pvt->map[1], pvt->map[2], pvt->map[3], | |
329 | pvt->map[4], pvt->map[5], pvt->map[6], | |
330 | pvt->map[7]); | |
806c35f5 AC |
331 | |
332 | /* test for channel remapping */ | |
333 | for (i = 0; i < 8; i++) { | |
334 | if (pvt->map[i] == row) | |
335 | break; | |
336 | } | |
e7ecd891 | 337 | |
537fba28 | 338 | e752x_printk(KERN_WARNING, "Test computed row %d\n", i); |
e7ecd891 | 339 | |
806c35f5 AC |
340 | if (i < 8) |
341 | row = i; | |
342 | else | |
537fba28 | 343 | e752x_mc_printk(mci, KERN_WARNING, |
203333cb DJ |
344 | "row %d not found in remap table\n", |
345 | row); | |
806c35f5 AC |
346 | } else |
347 | row = edac_mc_find_csrow_by_page(mci, page); | |
e7ecd891 | 348 | |
806c35f5 AC |
349 | /* 0 = channel A, 1 = channel B */ |
350 | channel = !(error_one & 1); | |
351 | ||
84db003f MC |
352 | /* e752x mc reads 34:6 of the DRAM linear address */ |
353 | edac_mc_handle_ce(mci, page, offset_in_page(sec1_add << 4), | |
052dfb45 | 354 | sec1_syndrome, row, channel, "e752x CE"); |
806c35f5 AC |
355 | } |
356 | ||
806c35f5 | 357 | static inline void process_ce(struct mem_ctl_info *mci, u16 error_one, |
052dfb45 DT |
358 | u32 sec1_add, u16 sec1_syndrome, int *error_found, |
359 | int handle_error) | |
806c35f5 AC |
360 | { |
361 | *error_found = 1; | |
362 | ||
363 | if (handle_error) | |
364 | do_process_ce(mci, error_one, sec1_add, sec1_syndrome); | |
365 | } | |
366 | ||
e7ecd891 | 367 | static void do_process_ue(struct mem_ctl_info *mci, u16 error_one, |
052dfb45 | 368 | u32 ded_add, u32 scrb_add) |
806c35f5 AC |
369 | { |
370 | u32 error_2b, block_page; | |
371 | int row; | |
203333cb | 372 | struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info; |
806c35f5 | 373 | |
537fba28 | 374 | debugf3("%s()\n", __func__); |
806c35f5 AC |
375 | |
376 | if (error_one & 0x0202) { | |
377 | error_2b = ded_add; | |
e7ecd891 | 378 | |
806c35f5 AC |
379 | /* convert to 4k address */ |
380 | block_page = error_2b >> (PAGE_SHIFT - 4); | |
e7ecd891 | 381 | |
806c35f5 | 382 | row = pvt->mc_symmetric ? |
052dfb45 DT |
383 | /* chip select are bits 14 & 13 */ |
384 | ((block_page >> 1) & 3) : | |
385 | edac_mc_find_csrow_by_page(mci, block_page); | |
e7ecd891 | 386 | |
84db003f MC |
387 | /* e752x mc reads 34:6 of the DRAM linear address */ |
388 | edac_mc_handle_ue(mci, block_page, | |
052dfb45 DT |
389 | offset_in_page(error_2b << 4), |
390 | row, "e752x UE from Read"); | |
806c35f5 AC |
391 | } |
392 | if (error_one & 0x0404) { | |
393 | error_2b = scrb_add; | |
e7ecd891 | 394 | |
806c35f5 AC |
395 | /* convert to 4k address */ |
396 | block_page = error_2b >> (PAGE_SHIFT - 4); | |
e7ecd891 | 397 | |
806c35f5 | 398 | row = pvt->mc_symmetric ? |
052dfb45 DT |
399 | /* chip select are bits 14 & 13 */ |
400 | ((block_page >> 1) & 3) : | |
401 | edac_mc_find_csrow_by_page(mci, block_page); | |
e7ecd891 | 402 | |
84db003f MC |
403 | /* e752x mc reads 34:6 of the DRAM linear address */ |
404 | edac_mc_handle_ue(mci, block_page, | |
052dfb45 DT |
405 | offset_in_page(error_2b << 4), |
406 | row, "e752x UE from Scruber"); | |
806c35f5 AC |
407 | } |
408 | } | |
409 | ||
410 | static inline void process_ue(struct mem_ctl_info *mci, u16 error_one, | |
052dfb45 DT |
411 | u32 ded_add, u32 scrb_add, int *error_found, |
412 | int handle_error) | |
806c35f5 AC |
413 | { |
414 | *error_found = 1; | |
415 | ||
416 | if (handle_error) | |
417 | do_process_ue(mci, error_one, ded_add, scrb_add); | |
418 | } | |
419 | ||
420 | static inline void process_ue_no_info_wr(struct mem_ctl_info *mci, | |
203333cb | 421 | int *error_found, int handle_error) |
806c35f5 AC |
422 | { |
423 | *error_found = 1; | |
424 | ||
425 | if (!handle_error) | |
426 | return; | |
427 | ||
537fba28 | 428 | debugf3("%s()\n", __func__); |
806c35f5 AC |
429 | edac_mc_handle_ue_no_info(mci, "e752x UE log memory write"); |
430 | } | |
431 | ||
432 | static void do_process_ded_retry(struct mem_ctl_info *mci, u16 error, | |
203333cb | 433 | u32 retry_add) |
806c35f5 AC |
434 | { |
435 | u32 error_1b, page; | |
436 | int row; | |
203333cb | 437 | struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info; |
806c35f5 AC |
438 | |
439 | error_1b = retry_add; | |
10d33e9c DT |
440 | page = error_1b >> (PAGE_SHIFT - 4); /* convert the addr to 4k page */ |
441 | ||
442 | /* chip select are bits 14 & 13 */ | |
443 | row = pvt->mc_symmetric ? ((page >> 1) & 3) : | |
052dfb45 | 444 | edac_mc_find_csrow_by_page(mci, page); |
10d33e9c | 445 | |
537fba28 | 446 | e752x_mc_printk(mci, KERN_WARNING, |
203333cb DJ |
447 | "CE page 0x%lx, row %d : Memory read retry\n", |
448 | (long unsigned int)page, row); | |
806c35f5 AC |
449 | } |
450 | ||
451 | static inline void process_ded_retry(struct mem_ctl_info *mci, u16 error, | |
052dfb45 DT |
452 | u32 retry_add, int *error_found, |
453 | int handle_error) | |
806c35f5 AC |
454 | { |
455 | *error_found = 1; | |
456 | ||
457 | if (handle_error) | |
458 | do_process_ded_retry(mci, error, retry_add); | |
459 | } | |
460 | ||
461 | static inline void process_threshold_ce(struct mem_ctl_info *mci, u16 error, | |
203333cb | 462 | int *error_found, int handle_error) |
806c35f5 AC |
463 | { |
464 | *error_found = 1; | |
465 | ||
466 | if (handle_error) | |
537fba28 | 467 | e752x_mc_printk(mci, KERN_WARNING, "Memory threshold CE\n"); |
806c35f5 AC |
468 | } |
469 | ||
da9bb1d2 | 470 | static char *global_message[11] = { |
10d33e9c DT |
471 | "PCI Express C1", |
472 | "PCI Express C", | |
473 | "PCI Express B1", | |
474 | "PCI Express B", | |
475 | "PCI Express A1", | |
476 | "PCI Express A", | |
477 | "DMA Controller", | |
478 | "HUB or NS Interface", | |
479 | "System Bus", | |
480 | "DRAM Controller", /* 9th entry */ | |
481 | "Internal Buffer" | |
806c35f5 AC |
482 | }; |
483 | ||
10d33e9c DT |
484 | #define DRAM_ENTRY 9 |
485 | ||
da9bb1d2 | 486 | static char *fatal_message[2] = { "Non-Fatal ", "Fatal " }; |
806c35f5 AC |
487 | |
488 | static void do_global_error(int fatal, u32 errors) | |
489 | { | |
490 | int i; | |
491 | ||
492 | for (i = 0; i < 11; i++) { | |
10d33e9c DT |
493 | if (errors & (1 << i)) { |
494 | /* If the error is from DRAM Controller OR | |
495 | * we are to report ALL errors, then | |
496 | * report the error | |
497 | */ | |
498 | if ((i == DRAM_ENTRY) || report_non_memory_errors) | |
499 | e752x_printk(KERN_WARNING, "%sError %s\n", | |
500 | fatal_message[fatal], | |
501 | global_message[i]); | |
502 | } | |
806c35f5 AC |
503 | } |
504 | } | |
505 | ||
506 | static inline void global_error(int fatal, u32 errors, int *error_found, | |
203333cb | 507 | int handle_error) |
806c35f5 AC |
508 | { |
509 | *error_found = 1; | |
510 | ||
511 | if (handle_error) | |
512 | do_global_error(fatal, errors); | |
513 | } | |
514 | ||
da9bb1d2 | 515 | static char *hub_message[7] = { |
806c35f5 AC |
516 | "HI Address or Command Parity", "HI Illegal Access", |
517 | "HI Internal Parity", "Out of Range Access", | |
518 | "HI Data Parity", "Enhanced Config Access", | |
519 | "Hub Interface Target Abort" | |
520 | }; | |
521 | ||
522 | static void do_hub_error(int fatal, u8 errors) | |
523 | { | |
524 | int i; | |
525 | ||
526 | for (i = 0; i < 7; i++) { | |
527 | if (errors & (1 << i)) | |
537fba28 | 528 | e752x_printk(KERN_WARNING, "%sError %s\n", |
052dfb45 | 529 | fatal_message[fatal], hub_message[i]); |
806c35f5 AC |
530 | } |
531 | } | |
532 | ||
533 | static inline void hub_error(int fatal, u8 errors, int *error_found, | |
052dfb45 | 534 | int handle_error) |
806c35f5 AC |
535 | { |
536 | *error_found = 1; | |
537 | ||
538 | if (handle_error) | |
539 | do_hub_error(fatal, errors); | |
540 | } | |
541 | ||
5135b797 AK |
542 | #define NSI_FATAL_MASK 0x0c080081 |
543 | #define NSI_NON_FATAL_MASK 0x23a0ba64 | |
544 | #define NSI_ERR_MASK (NSI_FATAL_MASK | NSI_NON_FATAL_MASK) | |
545 | ||
546 | static char *nsi_message[30] = { | |
547 | "NSI Link Down", /* NSI_FERR/NSI_NERR bit 0, fatal error */ | |
548 | "", /* reserved */ | |
549 | "NSI Parity Error", /* bit 2, non-fatal */ | |
550 | "", /* reserved */ | |
551 | "", /* reserved */ | |
552 | "Correctable Error Message", /* bit 5, non-fatal */ | |
553 | "Non-Fatal Error Message", /* bit 6, non-fatal */ | |
554 | "Fatal Error Message", /* bit 7, fatal */ | |
555 | "", /* reserved */ | |
556 | "Receiver Error", /* bit 9, non-fatal */ | |
557 | "", /* reserved */ | |
558 | "Bad TLP", /* bit 11, non-fatal */ | |
559 | "Bad DLLP", /* bit 12, non-fatal */ | |
560 | "REPLAY_NUM Rollover", /* bit 13, non-fatal */ | |
561 | "", /* reserved */ | |
562 | "Replay Timer Timeout", /* bit 15, non-fatal */ | |
563 | "", /* reserved */ | |
564 | "", /* reserved */ | |
565 | "", /* reserved */ | |
566 | "Data Link Protocol Error", /* bit 19, fatal */ | |
567 | "", /* reserved */ | |
568 | "Poisoned TLP", /* bit 21, non-fatal */ | |
569 | "", /* reserved */ | |
570 | "Completion Timeout", /* bit 23, non-fatal */ | |
571 | "Completer Abort", /* bit 24, non-fatal */ | |
572 | "Unexpected Completion", /* bit 25, non-fatal */ | |
573 | "Receiver Overflow", /* bit 26, fatal */ | |
574 | "Malformed TLP", /* bit 27, fatal */ | |
575 | "", /* reserved */ | |
576 | "Unsupported Request" /* bit 29, non-fatal */ | |
577 | }; | |
578 | ||
579 | static void do_nsi_error(int fatal, u32 errors) | |
580 | { | |
581 | int i; | |
582 | ||
583 | for (i = 0; i < 30; i++) { | |
584 | if (errors & (1 << i)) | |
585 | printk(KERN_WARNING "%sError %s\n", | |
586 | fatal_message[fatal], nsi_message[i]); | |
587 | } | |
588 | } | |
589 | ||
590 | static inline void nsi_error(int fatal, u32 errors, int *error_found, | |
591 | int handle_error) | |
592 | { | |
593 | *error_found = 1; | |
594 | ||
595 | if (handle_error) | |
596 | do_nsi_error(fatal, errors); | |
597 | } | |
598 | ||
da9bb1d2 | 599 | static char *membuf_message[4] = { |
806c35f5 AC |
600 | "Internal PMWB to DRAM parity", |
601 | "Internal PMWB to System Bus Parity", | |
602 | "Internal System Bus or IO to PMWB Parity", | |
603 | "Internal DRAM to PMWB Parity" | |
604 | }; | |
605 | ||
606 | static void do_membuf_error(u8 errors) | |
607 | { | |
608 | int i; | |
609 | ||
610 | for (i = 0; i < 4; i++) { | |
611 | if (errors & (1 << i)) | |
537fba28 | 612 | e752x_printk(KERN_WARNING, "Non-Fatal Error %s\n", |
052dfb45 | 613 | membuf_message[i]); |
806c35f5 AC |
614 | } |
615 | } | |
616 | ||
617 | static inline void membuf_error(u8 errors, int *error_found, int handle_error) | |
618 | { | |
619 | *error_found = 1; | |
620 | ||
621 | if (handle_error) | |
622 | do_membuf_error(errors); | |
623 | } | |
624 | ||
e009356f | 625 | static char *sysbus_message[10] = { |
806c35f5 AC |
626 | "Addr or Request Parity", |
627 | "Data Strobe Glitch", | |
628 | "Addr Strobe Glitch", | |
629 | "Data Parity", | |
630 | "Addr Above TOM", | |
631 | "Non DRAM Lock Error", | |
632 | "MCERR", "BINIT", | |
633 | "Memory Parity", | |
634 | "IO Subsystem Parity" | |
635 | }; | |
636 | ||
637 | static void do_sysbus_error(int fatal, u32 errors) | |
638 | { | |
639 | int i; | |
640 | ||
641 | for (i = 0; i < 10; i++) { | |
642 | if (errors & (1 << i)) | |
537fba28 | 643 | e752x_printk(KERN_WARNING, "%sError System Bus %s\n", |
052dfb45 | 644 | fatal_message[fatal], sysbus_message[i]); |
806c35f5 AC |
645 | } |
646 | } | |
647 | ||
648 | static inline void sysbus_error(int fatal, u32 errors, int *error_found, | |
203333cb | 649 | int handle_error) |
806c35f5 AC |
650 | { |
651 | *error_found = 1; | |
652 | ||
653 | if (handle_error) | |
654 | do_sysbus_error(fatal, errors); | |
655 | } | |
656 | ||
e7ecd891 | 657 | static void e752x_check_hub_interface(struct e752x_error_info *info, |
052dfb45 | 658 | int *error_found, int handle_error) |
806c35f5 AC |
659 | { |
660 | u8 stat8; | |
661 | ||
662 | //pci_read_config_byte(dev,E752X_HI_FERR,&stat8); | |
e7ecd891 | 663 | |
806c35f5 | 664 | stat8 = info->hi_ferr; |
e7ecd891 | 665 | |
203333cb | 666 | if (stat8 & 0x7f) { /* Error, so process */ |
806c35f5 | 667 | stat8 &= 0x7f; |
e7ecd891 | 668 | |
203333cb | 669 | if (stat8 & 0x2b) |
806c35f5 | 670 | hub_error(1, stat8 & 0x2b, error_found, handle_error); |
e7ecd891 | 671 | |
203333cb | 672 | if (stat8 & 0x54) |
806c35f5 AC |
673 | hub_error(0, stat8 & 0x54, error_found, handle_error); |
674 | } | |
675 | //pci_read_config_byte(dev,E752X_HI_NERR,&stat8); | |
e7ecd891 | 676 | |
806c35f5 | 677 | stat8 = info->hi_nerr; |
e7ecd891 | 678 | |
203333cb | 679 | if (stat8 & 0x7f) { /* Error, so process */ |
806c35f5 | 680 | stat8 &= 0x7f; |
e7ecd891 | 681 | |
806c35f5 AC |
682 | if (stat8 & 0x2b) |
683 | hub_error(1, stat8 & 0x2b, error_found, handle_error); | |
e7ecd891 | 684 | |
203333cb | 685 | if (stat8 & 0x54) |
806c35f5 AC |
686 | hub_error(0, stat8 & 0x54, error_found, handle_error); |
687 | } | |
688 | } | |
689 | ||
5135b797 AK |
690 | static void e752x_check_ns_interface(struct e752x_error_info *info, |
691 | int *error_found, int handle_error) | |
692 | { | |
693 | u32 stat32; | |
694 | ||
695 | stat32 = info->nsi_ferr; | |
696 | if (stat32 & NSI_ERR_MASK) { /* Error, so process */ | |
697 | if (stat32 & NSI_FATAL_MASK) /* check for fatal errors */ | |
698 | nsi_error(1, stat32 & NSI_FATAL_MASK, error_found, | |
699 | handle_error); | |
700 | if (stat32 & NSI_NON_FATAL_MASK) /* check for non-fatal ones */ | |
701 | nsi_error(0, stat32 & NSI_NON_FATAL_MASK, error_found, | |
702 | handle_error); | |
703 | } | |
704 | stat32 = info->nsi_nerr; | |
705 | if (stat32 & NSI_ERR_MASK) { | |
706 | if (stat32 & NSI_FATAL_MASK) | |
707 | nsi_error(1, stat32 & NSI_FATAL_MASK, error_found, | |
708 | handle_error); | |
709 | if (stat32 & NSI_NON_FATAL_MASK) | |
710 | nsi_error(0, stat32 & NSI_NON_FATAL_MASK, error_found, | |
711 | handle_error); | |
712 | } | |
713 | } | |
714 | ||
e7ecd891 | 715 | static void e752x_check_sysbus(struct e752x_error_info *info, |
052dfb45 | 716 | int *error_found, int handle_error) |
806c35f5 AC |
717 | { |
718 | u32 stat32, error32; | |
719 | ||
720 | //pci_read_config_dword(dev,E752X_SYSBUS_FERR,&stat32); | |
721 | stat32 = info->sysbus_ferr + (info->sysbus_nerr << 16); | |
722 | ||
723 | if (stat32 == 0) | |
203333cb | 724 | return; /* no errors */ |
806c35f5 AC |
725 | |
726 | error32 = (stat32 >> 16) & 0x3ff; | |
727 | stat32 = stat32 & 0x3ff; | |
e7ecd891 | 728 | |
203333cb | 729 | if (stat32 & 0x087) |
dfb2a763 | 730 | sysbus_error(1, stat32 & 0x087, error_found, handle_error); |
e7ecd891 | 731 | |
203333cb | 732 | if (stat32 & 0x378) |
dfb2a763 | 733 | sysbus_error(0, stat32 & 0x378, error_found, handle_error); |
e7ecd891 | 734 | |
203333cb | 735 | if (error32 & 0x087) |
dfb2a763 | 736 | sysbus_error(1, error32 & 0x087, error_found, handle_error); |
e7ecd891 | 737 | |
203333cb | 738 | if (error32 & 0x378) |
dfb2a763 | 739 | sysbus_error(0, error32 & 0x378, error_found, handle_error); |
806c35f5 AC |
740 | } |
741 | ||
203333cb | 742 | static void e752x_check_membuf(struct e752x_error_info *info, |
052dfb45 | 743 | int *error_found, int handle_error) |
806c35f5 AC |
744 | { |
745 | u8 stat8; | |
746 | ||
747 | stat8 = info->buf_ferr; | |
e7ecd891 | 748 | |
203333cb | 749 | if (stat8 & 0x0f) { /* Error, so process */ |
806c35f5 AC |
750 | stat8 &= 0x0f; |
751 | membuf_error(stat8, error_found, handle_error); | |
752 | } | |
e7ecd891 | 753 | |
806c35f5 | 754 | stat8 = info->buf_nerr; |
e7ecd891 | 755 | |
203333cb | 756 | if (stat8 & 0x0f) { /* Error, so process */ |
806c35f5 AC |
757 | stat8 &= 0x0f; |
758 | membuf_error(stat8, error_found, handle_error); | |
759 | } | |
760 | } | |
761 | ||
203333cb | 762 | static void e752x_check_dram(struct mem_ctl_info *mci, |
052dfb45 DT |
763 | struct e752x_error_info *info, int *error_found, |
764 | int handle_error) | |
806c35f5 AC |
765 | { |
766 | u16 error_one, error_next; | |
767 | ||
768 | error_one = info->dram_ferr; | |
769 | error_next = info->dram_nerr; | |
770 | ||
771 | /* decode and report errors */ | |
203333cb | 772 | if (error_one & 0x0101) /* check first error correctable */ |
806c35f5 | 773 | process_ce(mci, error_one, info->dram_sec1_add, |
052dfb45 | 774 | info->dram_sec1_syndrome, error_found, handle_error); |
806c35f5 | 775 | |
203333cb | 776 | if (error_next & 0x0101) /* check next error correctable */ |
806c35f5 | 777 | process_ce(mci, error_next, info->dram_sec2_add, |
052dfb45 | 778 | info->dram_sec2_syndrome, error_found, handle_error); |
806c35f5 | 779 | |
203333cb | 780 | if (error_one & 0x4040) |
806c35f5 AC |
781 | process_ue_no_info_wr(mci, error_found, handle_error); |
782 | ||
203333cb | 783 | if (error_next & 0x4040) |
806c35f5 AC |
784 | process_ue_no_info_wr(mci, error_found, handle_error); |
785 | ||
203333cb | 786 | if (error_one & 0x2020) |
806c35f5 | 787 | process_ded_retry(mci, error_one, info->dram_retr_add, |
052dfb45 | 788 | error_found, handle_error); |
806c35f5 | 789 | |
203333cb | 790 | if (error_next & 0x2020) |
806c35f5 | 791 | process_ded_retry(mci, error_next, info->dram_retr_add, |
052dfb45 | 792 | error_found, handle_error); |
806c35f5 | 793 | |
203333cb DJ |
794 | if (error_one & 0x0808) |
795 | process_threshold_ce(mci, error_one, error_found, handle_error); | |
806c35f5 | 796 | |
203333cb | 797 | if (error_next & 0x0808) |
806c35f5 | 798 | process_threshold_ce(mci, error_next, error_found, |
052dfb45 | 799 | handle_error); |
806c35f5 | 800 | |
203333cb | 801 | if (error_one & 0x0606) |
806c35f5 | 802 | process_ue(mci, error_one, info->dram_ded_add, |
052dfb45 | 803 | info->dram_scrb_add, error_found, handle_error); |
806c35f5 | 804 | |
203333cb | 805 | if (error_next & 0x0606) |
806c35f5 | 806 | process_ue(mci, error_next, info->dram_ded_add, |
052dfb45 | 807 | info->dram_scrb_add, error_found, handle_error); |
806c35f5 AC |
808 | } |
809 | ||
203333cb DJ |
810 | static void e752x_get_error_info(struct mem_ctl_info *mci, |
811 | struct e752x_error_info *info) | |
806c35f5 AC |
812 | { |
813 | struct pci_dev *dev; | |
814 | struct e752x_pvt *pvt; | |
815 | ||
816 | memset(info, 0, sizeof(*info)); | |
203333cb | 817 | pvt = (struct e752x_pvt *)mci->pvt_info; |
806c35f5 | 818 | dev = pvt->dev_d0f1; |
806c35f5 AC |
819 | pci_read_config_dword(dev, E752X_FERR_GLOBAL, &info->ferr_global); |
820 | ||
821 | if (info->ferr_global) { | |
5135b797 AK |
822 | if (pvt->dev_info->err_dev == PCI_DEVICE_ID_INTEL_3100_1_ERR) { |
823 | pci_read_config_dword(dev, I3100_NSI_FERR, | |
824 | &info->nsi_ferr); | |
825 | info->hi_ferr = 0; | |
826 | } else { | |
827 | pci_read_config_byte(dev, E752X_HI_FERR, | |
828 | &info->hi_ferr); | |
829 | info->nsi_ferr = 0; | |
830 | } | |
806c35f5 | 831 | pci_read_config_word(dev, E752X_SYSBUS_FERR, |
052dfb45 | 832 | &info->sysbus_ferr); |
806c35f5 | 833 | pci_read_config_byte(dev, E752X_BUF_FERR, &info->buf_ferr); |
203333cb | 834 | pci_read_config_word(dev, E752X_DRAM_FERR, &info->dram_ferr); |
806c35f5 | 835 | pci_read_config_dword(dev, E752X_DRAM_SEC1_ADD, |
052dfb45 | 836 | &info->dram_sec1_add); |
806c35f5 | 837 | pci_read_config_word(dev, E752X_DRAM_SEC1_SYNDROME, |
052dfb45 | 838 | &info->dram_sec1_syndrome); |
806c35f5 | 839 | pci_read_config_dword(dev, E752X_DRAM_DED_ADD, |
052dfb45 | 840 | &info->dram_ded_add); |
806c35f5 | 841 | pci_read_config_dword(dev, E752X_DRAM_SCRB_ADD, |
052dfb45 | 842 | &info->dram_scrb_add); |
806c35f5 | 843 | pci_read_config_dword(dev, E752X_DRAM_RETR_ADD, |
052dfb45 | 844 | &info->dram_retr_add); |
806c35f5 | 845 | |
5135b797 | 846 | /* ignore the reserved bits just in case */ |
806c35f5 AC |
847 | if (info->hi_ferr & 0x7f) |
848 | pci_write_config_byte(dev, E752X_HI_FERR, | |
052dfb45 | 849 | info->hi_ferr); |
806c35f5 | 850 | |
5135b797 AK |
851 | if (info->nsi_ferr & NSI_ERR_MASK) |
852 | pci_write_config_dword(dev, I3100_NSI_FERR, | |
853 | info->nsi_ferr); | |
854 | ||
806c35f5 AC |
855 | if (info->sysbus_ferr) |
856 | pci_write_config_word(dev, E752X_SYSBUS_FERR, | |
052dfb45 | 857 | info->sysbus_ferr); |
806c35f5 AC |
858 | |
859 | if (info->buf_ferr & 0x0f) | |
860 | pci_write_config_byte(dev, E752X_BUF_FERR, | |
052dfb45 | 861 | info->buf_ferr); |
806c35f5 AC |
862 | |
863 | if (info->dram_ferr) | |
864 | pci_write_bits16(pvt->bridge_ck, E752X_DRAM_FERR, | |
203333cb | 865 | info->dram_ferr, info->dram_ferr); |
806c35f5 AC |
866 | |
867 | pci_write_config_dword(dev, E752X_FERR_GLOBAL, | |
052dfb45 | 868 | info->ferr_global); |
806c35f5 AC |
869 | } |
870 | ||
871 | pci_read_config_dword(dev, E752X_NERR_GLOBAL, &info->nerr_global); | |
872 | ||
873 | if (info->nerr_global) { | |
5135b797 AK |
874 | if (pvt->dev_info->err_dev == PCI_DEVICE_ID_INTEL_3100_1_ERR) { |
875 | pci_read_config_dword(dev, I3100_NSI_NERR, | |
876 | &info->nsi_nerr); | |
877 | info->hi_nerr = 0; | |
878 | } else { | |
879 | pci_read_config_byte(dev, E752X_HI_NERR, | |
880 | &info->hi_nerr); | |
881 | info->nsi_nerr = 0; | |
882 | } | |
806c35f5 | 883 | pci_read_config_word(dev, E752X_SYSBUS_NERR, |
052dfb45 | 884 | &info->sysbus_nerr); |
806c35f5 | 885 | pci_read_config_byte(dev, E752X_BUF_NERR, &info->buf_nerr); |
203333cb | 886 | pci_read_config_word(dev, E752X_DRAM_NERR, &info->dram_nerr); |
806c35f5 | 887 | pci_read_config_dword(dev, E752X_DRAM_SEC2_ADD, |
052dfb45 | 888 | &info->dram_sec2_add); |
806c35f5 | 889 | pci_read_config_word(dev, E752X_DRAM_SEC2_SYNDROME, |
052dfb45 | 890 | &info->dram_sec2_syndrome); |
806c35f5 AC |
891 | |
892 | if (info->hi_nerr & 0x7f) | |
893 | pci_write_config_byte(dev, E752X_HI_NERR, | |
052dfb45 | 894 | info->hi_nerr); |
806c35f5 | 895 | |
5135b797 AK |
896 | if (info->nsi_nerr & NSI_ERR_MASK) |
897 | pci_write_config_dword(dev, I3100_NSI_NERR, | |
898 | info->nsi_nerr); | |
899 | ||
806c35f5 AC |
900 | if (info->sysbus_nerr) |
901 | pci_write_config_word(dev, E752X_SYSBUS_NERR, | |
052dfb45 | 902 | info->sysbus_nerr); |
806c35f5 AC |
903 | |
904 | if (info->buf_nerr & 0x0f) | |
905 | pci_write_config_byte(dev, E752X_BUF_NERR, | |
052dfb45 | 906 | info->buf_nerr); |
806c35f5 AC |
907 | |
908 | if (info->dram_nerr) | |
909 | pci_write_bits16(pvt->bridge_ck, E752X_DRAM_NERR, | |
203333cb | 910 | info->dram_nerr, info->dram_nerr); |
806c35f5 AC |
911 | |
912 | pci_write_config_dword(dev, E752X_NERR_GLOBAL, | |
052dfb45 | 913 | info->nerr_global); |
806c35f5 AC |
914 | } |
915 | } | |
916 | ||
203333cb | 917 | static int e752x_process_error_info(struct mem_ctl_info *mci, |
052dfb45 DT |
918 | struct e752x_error_info *info, |
919 | int handle_errors) | |
806c35f5 AC |
920 | { |
921 | u32 error32, stat32; | |
922 | int error_found; | |
923 | ||
924 | error_found = 0; | |
925 | error32 = (info->ferr_global >> 18) & 0x3ff; | |
926 | stat32 = (info->ferr_global >> 4) & 0x7ff; | |
927 | ||
928 | if (error32) | |
929 | global_error(1, error32, &error_found, handle_errors); | |
930 | ||
931 | if (stat32) | |
932 | global_error(0, stat32, &error_found, handle_errors); | |
933 | ||
934 | error32 = (info->nerr_global >> 18) & 0x3ff; | |
935 | stat32 = (info->nerr_global >> 4) & 0x7ff; | |
936 | ||
937 | if (error32) | |
938 | global_error(1, error32, &error_found, handle_errors); | |
939 | ||
940 | if (stat32) | |
941 | global_error(0, stat32, &error_found, handle_errors); | |
942 | ||
943 | e752x_check_hub_interface(info, &error_found, handle_errors); | |
5135b797 | 944 | e752x_check_ns_interface(info, &error_found, handle_errors); |
806c35f5 AC |
945 | e752x_check_sysbus(info, &error_found, handle_errors); |
946 | e752x_check_membuf(info, &error_found, handle_errors); | |
947 | e752x_check_dram(mci, info, &error_found, handle_errors); | |
948 | return error_found; | |
949 | } | |
950 | ||
951 | static void e752x_check(struct mem_ctl_info *mci) | |
952 | { | |
953 | struct e752x_error_info info; | |
e7ecd891 | 954 | |
537fba28 | 955 | debugf3("%s()\n", __func__); |
806c35f5 AC |
956 | e752x_get_error_info(mci, &info); |
957 | e752x_process_error_info(mci, &info, 1); | |
958 | } | |
959 | ||
8004fd2a | 960 | /* Program byte/sec bandwidth scrub rate to hardware */ |
eba042a8 | 961 | static int set_sdram_scrub_rate(struct mem_ctl_info *mci, u32 new_bw) |
8004fd2a PT |
962 | { |
963 | const struct scrubrate *scrubrates; | |
964 | struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info; | |
965 | struct pci_dev *pdev = pvt->dev_d0f0; | |
966 | int i; | |
967 | ||
968 | if (pvt->dev_info->ctl_dev == PCI_DEVICE_ID_INTEL_3100_0) | |
969 | scrubrates = scrubrates_i3100; | |
970 | else | |
971 | scrubrates = scrubrates_e752x; | |
972 | ||
973 | /* Translate the desired scrub rate to a e752x/3100 register value. | |
974 | * Search for the bandwidth that is equal or greater than the | |
975 | * desired rate and program the cooresponding register value. | |
976 | */ | |
977 | for (i = 0; scrubrates[i].bandwidth != SDRATE_EOT; i++) | |
eba042a8 | 978 | if (scrubrates[i].bandwidth >= new_bw) |
8004fd2a PT |
979 | break; |
980 | ||
981 | if (scrubrates[i].bandwidth == SDRATE_EOT) | |
982 | return -1; | |
983 | ||
984 | pci_write_config_word(pdev, E752X_MCHSCRB, scrubrates[i].scrubval); | |
985 | ||
39094443 | 986 | return scrubrates[i].bandwidth; |
8004fd2a PT |
987 | } |
988 | ||
989 | /* Convert current scrub rate value into byte/sec bandwidth */ | |
39094443 | 990 | static int get_sdram_scrub_rate(struct mem_ctl_info *mci) |
8004fd2a PT |
991 | { |
992 | const struct scrubrate *scrubrates; | |
993 | struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info; | |
994 | struct pci_dev *pdev = pvt->dev_d0f0; | |
995 | u16 scrubval; | |
996 | int i; | |
997 | ||
998 | if (pvt->dev_info->ctl_dev == PCI_DEVICE_ID_INTEL_3100_0) | |
999 | scrubrates = scrubrates_i3100; | |
1000 | else | |
1001 | scrubrates = scrubrates_e752x; | |
1002 | ||
1003 | /* Find the bandwidth matching the memory scrubber configuration */ | |
1004 | pci_read_config_word(pdev, E752X_MCHSCRB, &scrubval); | |
1005 | scrubval = scrubval & 0x0f; | |
1006 | ||
1007 | for (i = 0; scrubrates[i].bandwidth != SDRATE_EOT; i++) | |
1008 | if (scrubrates[i].scrubval == scrubval) | |
1009 | break; | |
1010 | ||
1011 | if (scrubrates[i].bandwidth == SDRATE_EOT) { | |
1012 | e752x_printk(KERN_WARNING, | |
1013 | "Invalid sdram scrub control value: 0x%x\n", scrubval); | |
1014 | return -1; | |
1015 | } | |
39094443 | 1016 | return scrubrates[i].bandwidth; |
8004fd2a | 1017 | |
8004fd2a PT |
1018 | } |
1019 | ||
13189525 DT |
1020 | /* Return 1 if dual channel mode is active. Else return 0. */ |
1021 | static inline int dual_channel_active(u16 ddrcsr) | |
1022 | { | |
1023 | return (((ddrcsr >> 12) & 3) == 3); | |
1024 | } | |
1025 | ||
7297c261 MG |
1026 | /* Remap csrow index numbers if map_type is "reverse" |
1027 | */ | |
1028 | static inline int remap_csrow_index(struct mem_ctl_info *mci, int index) | |
1029 | { | |
1030 | struct e752x_pvt *pvt = mci->pvt_info; | |
1031 | ||
1032 | if (!pvt->map_type) | |
1033 | return (7 - index); | |
1034 | ||
1035 | return (index); | |
1036 | } | |
1037 | ||
13189525 | 1038 | static void e752x_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev, |
052dfb45 | 1039 | u16 ddrcsr) |
13189525 DT |
1040 | { |
1041 | struct csrow_info *csrow; | |
1042 | unsigned long last_cumul_size; | |
1043 | int index, mem_dev, drc_chan; | |
203333cb DJ |
1044 | int drc_drbg; /* DRB granularity 0=64mb, 1=128mb */ |
1045 | int drc_ddim; /* DRAM Data Integrity Mode 0=none, 2=edac */ | |
13189525 DT |
1046 | u8 value; |
1047 | u32 dra, drc, cumul_size; | |
1048 | ||
9962fd01 | 1049 | dra = 0; |
203333cb | 1050 | for (index = 0; index < 4; index++) { |
9962fd01 | 1051 | u8 dra_reg; |
203333cb | 1052 | pci_read_config_byte(pdev, E752X_DRA + index, &dra_reg); |
9962fd01 BP |
1053 | dra |= dra_reg << (index * 8); |
1054 | } | |
13189525 DT |
1055 | pci_read_config_dword(pdev, E752X_DRC, &drc); |
1056 | drc_chan = dual_channel_active(ddrcsr); | |
203333cb | 1057 | drc_drbg = drc_chan + 1; /* 128 in dual mode, 64 in single */ |
13189525 DT |
1058 | drc_ddim = (drc >> 20) & 0x3; |
1059 | ||
1060 | /* The dram row boundary (DRB) reg values are boundary address for | |
1061 | * each DRAM row with a granularity of 64 or 128MB (single/dual | |
1062 | * channel operation). DRB regs are cumulative; therefore DRB7 will | |
1063 | * contain the total memory contained in all eight rows. | |
1064 | */ | |
1065 | for (last_cumul_size = index = 0; index < mci->nr_csrows; index++) { | |
1066 | /* mem_dev 0=x8, 1=x4 */ | |
1067 | mem_dev = (dra >> (index * 4 + 2)) & 0x3; | |
7297c261 | 1068 | csrow = &mci->csrows[remap_csrow_index(mci, index)]; |
13189525 DT |
1069 | |
1070 | mem_dev = (mem_dev == 2); | |
1071 | pci_read_config_byte(pdev, E752X_DRB + index, &value); | |
1072 | /* convert a 128 or 64 MiB DRB to a page size. */ | |
1073 | cumul_size = value << (25 + drc_drbg - PAGE_SHIFT); | |
1074 | debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index, | |
1075 | cumul_size); | |
1076 | if (cumul_size == last_cumul_size) | |
1077 | continue; /* not populated */ | |
1078 | ||
1079 | csrow->first_page = last_cumul_size; | |
1080 | csrow->last_page = cumul_size - 1; | |
1081 | csrow->nr_pages = cumul_size - last_cumul_size; | |
1082 | last_cumul_size = cumul_size; | |
1083 | csrow->grain = 1 << 12; /* 4KiB - resolution of CELOG */ | |
1084 | csrow->mtype = MEM_RDDR; /* only one type supported */ | |
1085 | csrow->dtype = mem_dev ? DEV_X4 : DEV_X8; | |
1086 | ||
1087 | /* | |
1088 | * if single channel or x8 devices then SECDED | |
1089 | * if dual channel and x4 then S4ECD4ED | |
1090 | */ | |
1091 | if (drc_ddim) { | |
1092 | if (drc_chan && mem_dev) { | |
1093 | csrow->edac_mode = EDAC_S4ECD4ED; | |
1094 | mci->edac_cap |= EDAC_FLAG_S4ECD4ED; | |
1095 | } else { | |
1096 | csrow->edac_mode = EDAC_SECDED; | |
1097 | mci->edac_cap |= EDAC_FLAG_SECDED; | |
1098 | } | |
1099 | } else | |
1100 | csrow->edac_mode = EDAC_NONE; | |
1101 | } | |
1102 | } | |
1103 | ||
1104 | static void e752x_init_mem_map_table(struct pci_dev *pdev, | |
052dfb45 | 1105 | struct e752x_pvt *pvt) |
806c35f5 | 1106 | { |
806c35f5 | 1107 | int index; |
7297c261 | 1108 | u8 value, last, row; |
13189525 DT |
1109 | |
1110 | last = 0; | |
1111 | row = 0; | |
1112 | ||
1113 | for (index = 0; index < 8; index += 2) { | |
1114 | pci_read_config_byte(pdev, E752X_DRB + index, &value); | |
1115 | /* test if there is a dimm in this slot */ | |
1116 | if (value == last) { | |
1117 | /* no dimm in the slot, so flag it as empty */ | |
1118 | pvt->map[index] = 0xff; | |
1119 | pvt->map[index + 1] = 0xff; | |
203333cb | 1120 | } else { /* there is a dimm in the slot */ |
13189525 DT |
1121 | pvt->map[index] = row; |
1122 | row++; | |
1123 | last = value; | |
1124 | /* test the next value to see if the dimm is double | |
1125 | * sided | |
1126 | */ | |
1127 | pci_read_config_byte(pdev, E752X_DRB + index + 1, | |
052dfb45 DT |
1128 | &value); |
1129 | ||
1130 | /* the dimm is single sided, so flag as empty */ | |
1131 | /* this is a double sided dimm to save the next row #*/ | |
1132 | pvt->map[index + 1] = (value == last) ? 0xff : row; | |
13189525 DT |
1133 | row++; |
1134 | last = value; | |
1135 | } | |
1136 | } | |
13189525 DT |
1137 | } |
1138 | ||
1139 | /* Return 0 on success or 1 on failure. */ | |
1140 | static int e752x_get_devs(struct pci_dev *pdev, int dev_idx, | |
052dfb45 | 1141 | struct e752x_pvt *pvt) |
13189525 DT |
1142 | { |
1143 | struct pci_dev *dev; | |
1144 | ||
1145 | pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL, | |
10d33e9c | 1146 | pvt->dev_info->err_dev, pvt->bridge_ck); |
13189525 DT |
1147 | |
1148 | if (pvt->bridge_ck == NULL) | |
1149 | pvt->bridge_ck = pci_scan_single_device(pdev->bus, | |
1150 | PCI_DEVFN(0, 1)); | |
1151 | ||
1152 | if (pvt->bridge_ck == NULL) { | |
1153 | e752x_printk(KERN_ERR, "error reporting device not found:" | |
052dfb45 DT |
1154 | "vendor %x device 0x%x (broken BIOS?)\n", |
1155 | PCI_VENDOR_ID_INTEL, e752x_devs[dev_idx].err_dev); | |
13189525 DT |
1156 | return 1; |
1157 | } | |
1158 | ||
10d33e9c DT |
1159 | dev = pci_get_device(PCI_VENDOR_ID_INTEL, |
1160 | e752x_devs[dev_idx].ctl_dev, | |
1161 | NULL); | |
13189525 DT |
1162 | |
1163 | if (dev == NULL) | |
1164 | goto fail; | |
1165 | ||
1166 | pvt->dev_d0f0 = dev; | |
1167 | pvt->dev_d0f1 = pci_dev_get(pvt->bridge_ck); | |
1168 | ||
1169 | return 0; | |
1170 | ||
052dfb45 | 1171 | fail: |
13189525 DT |
1172 | pci_dev_put(pvt->bridge_ck); |
1173 | return 1; | |
1174 | } | |
1175 | ||
94ee1cf5 PT |
1176 | /* Setup system bus parity mask register. |
1177 | * Sysbus parity supported on: | |
8de5c1a1 | 1178 | * e7320/e7520/e7525 + Xeon |
94ee1cf5 PT |
1179 | */ |
1180 | static void e752x_init_sysbus_parity_mask(struct e752x_pvt *pvt) | |
1181 | { | |
1182 | char *cpu_id = cpu_data(0).x86_model_id; | |
1183 | struct pci_dev *dev = pvt->dev_d0f1; | |
1184 | int enable = 1; | |
1185 | ||
98a1708d | 1186 | /* Allow module parameter override, else see if CPU supports parity */ |
94ee1cf5 PT |
1187 | if (sysbus_parity != -1) { |
1188 | enable = sysbus_parity; | |
8de5c1a1 | 1189 | } else if (cpu_id[0] && !strstr(cpu_id, "Xeon")) { |
94ee1cf5 PT |
1190 | e752x_printk(KERN_INFO, "System Bus Parity not " |
1191 | "supported by CPU, disabling\n"); | |
1192 | enable = 0; | |
1193 | } | |
1194 | ||
1195 | if (enable) | |
1196 | pci_write_config_word(dev, E752X_SYSBUS_ERRMASK, 0x0000); | |
1197 | else | |
1198 | pci_write_config_word(dev, E752X_SYSBUS_ERRMASK, 0x0309); | |
1199 | } | |
1200 | ||
13189525 DT |
1201 | static void e752x_init_error_reporting_regs(struct e752x_pvt *pvt) |
1202 | { | |
1203 | struct pci_dev *dev; | |
1204 | ||
1205 | dev = pvt->dev_d0f1; | |
1206 | /* Turn off error disable & SMI in case the BIOS turned it on */ | |
5135b797 AK |
1207 | if (pvt->dev_info->err_dev == PCI_DEVICE_ID_INTEL_3100_1_ERR) { |
1208 | pci_write_config_dword(dev, I3100_NSI_EMASK, 0); | |
1209 | pci_write_config_dword(dev, I3100_NSI_SMICMD, 0); | |
1210 | } else { | |
1211 | pci_write_config_byte(dev, E752X_HI_ERRMASK, 0x00); | |
1212 | pci_write_config_byte(dev, E752X_HI_SMICMD, 0x00); | |
1213 | } | |
94ee1cf5 PT |
1214 | |
1215 | e752x_init_sysbus_parity_mask(pvt); | |
1216 | ||
13189525 DT |
1217 | pci_write_config_word(dev, E752X_SYSBUS_SMICMD, 0x00); |
1218 | pci_write_config_byte(dev, E752X_BUF_ERRMASK, 0x00); | |
1219 | pci_write_config_byte(dev, E752X_BUF_SMICMD, 0x00); | |
1220 | pci_write_config_byte(dev, E752X_DRAM_ERRMASK, 0x00); | |
1221 | pci_write_config_byte(dev, E752X_DRAM_SMICMD, 0x00); | |
1222 | } | |
1223 | ||
1224 | static int e752x_probe1(struct pci_dev *pdev, int dev_idx) | |
1225 | { | |
3847bccc | 1226 | u16 pci_data; |
806c35f5 | 1227 | u8 stat8; |
13189525 DT |
1228 | struct mem_ctl_info *mci; |
1229 | struct e752x_pvt *pvt; | |
806c35f5 | 1230 | u16 ddrcsr; |
203333cb | 1231 | int drc_chan; /* Number of channels 0=1chan,1=2chan */ |
749ede57 | 1232 | struct e752x_error_info discard; |
806c35f5 | 1233 | |
537fba28 | 1234 | debugf0("%s(): mci\n", __func__); |
806c35f5 AC |
1235 | debugf0("Starting Probe1\n"); |
1236 | ||
96941026 | 1237 | /* check to see if device 0 function 1 is enabled; if it isn't, we |
1238 | * assume the BIOS has reserved it for a reason and is expecting | |
1239 | * exclusive access, we take care not to violate that assumption and | |
1240 | * fail the probe. */ | |
806c35f5 | 1241 | pci_read_config_byte(pdev, E752X_DEVPRES1, &stat8); |
96941026 | 1242 | if (!force_function_unhide && !(stat8 & (1 << 5))) { |
1243 | printk(KERN_INFO "Contact your BIOS vendor to see if the " | |
052dfb45 | 1244 | "E752x error registers can be safely un-hidden\n"); |
f9b5a5d1 | 1245 | return -ENODEV; |
96941026 | 1246 | } |
806c35f5 AC |
1247 | stat8 |= (1 << 5); |
1248 | pci_write_config_byte(pdev, E752X_DEVPRES1, stat8); | |
1249 | ||
806c35f5 AC |
1250 | pci_read_config_word(pdev, E752X_DDRCSR, &ddrcsr); |
1251 | /* FIXME: should check >>12 or 0xf, true for all? */ | |
1252 | /* Dual channel = 1, Single channel = 0 */ | |
13189525 | 1253 | drc_chan = dual_channel_active(ddrcsr); |
806c35f5 | 1254 | |
b8f6f975 | 1255 | mci = edac_mc_alloc(sizeof(*pvt), E752X_NR_CSROWS, drc_chan + 1, 0); |
806c35f5 AC |
1256 | |
1257 | if (mci == NULL) { | |
13189525 | 1258 | return -ENOMEM; |
806c35f5 AC |
1259 | } |
1260 | ||
537fba28 | 1261 | debugf3("%s(): init mci\n", __func__); |
806c35f5 | 1262 | mci->mtype_cap = MEM_FLAG_RDDR; |
5135b797 AK |
1263 | /* 3100 IMCH supports SECDEC only */ |
1264 | mci->edac_ctl_cap = (dev_idx == I3100) ? EDAC_FLAG_SECDED : | |
1265 | (EDAC_FLAG_NONE | EDAC_FLAG_SECDED | EDAC_FLAG_S4ECD4ED); | |
806c35f5 | 1266 | /* FIXME - what if different memory types are in different csrows? */ |
680cbbbb | 1267 | mci->mod_name = EDAC_MOD_STR; |
37f04581 DT |
1268 | mci->mod_ver = E752X_REVISION; |
1269 | mci->dev = &pdev->dev; | |
806c35f5 | 1270 | |
537fba28 | 1271 | debugf3("%s(): init pvt\n", __func__); |
203333cb | 1272 | pvt = (struct e752x_pvt *)mci->pvt_info; |
806c35f5 | 1273 | pvt->dev_info = &e752x_devs[dev_idx]; |
13189525 | 1274 | pvt->mc_symmetric = ((ddrcsr & 0x10) != 0); |
e7ecd891 | 1275 | |
13189525 DT |
1276 | if (e752x_get_devs(pdev, dev_idx, pvt)) { |
1277 | edac_mc_free(mci); | |
1278 | return -ENODEV; | |
806c35f5 | 1279 | } |
806c35f5 | 1280 | |
537fba28 | 1281 | debugf3("%s(): more mci init\n", __func__); |
806c35f5 | 1282 | mci->ctl_name = pvt->dev_info->ctl_name; |
c4192705 | 1283 | mci->dev_name = pci_name(pdev); |
806c35f5 AC |
1284 | mci->edac_check = e752x_check; |
1285 | mci->ctl_page_to_phys = ctl_page_to_phys; | |
8004fd2a PT |
1286 | mci->set_sdram_scrub_rate = set_sdram_scrub_rate; |
1287 | mci->get_sdram_scrub_rate = get_sdram_scrub_rate; | |
806c35f5 | 1288 | |
7297c261 MG |
1289 | /* set the map type. 1 = normal, 0 = reversed |
1290 | * Must be set before e752x_init_csrows in case csrow mapping | |
1291 | * is reversed. | |
1292 | */ | |
37f04581 | 1293 | pci_read_config_byte(pdev, E752X_DRM, &stat8); |
806c35f5 AC |
1294 | pvt->map_type = ((stat8 & 0x0f) > ((stat8 >> 4) & 0x0f)); |
1295 | ||
7297c261 MG |
1296 | e752x_init_csrows(mci, pdev, ddrcsr); |
1297 | e752x_init_mem_map_table(pdev, pvt); | |
1298 | ||
5135b797 AK |
1299 | if (dev_idx == I3100) |
1300 | mci->edac_cap = EDAC_FLAG_SECDED; /* the only mode supported */ | |
1301 | else | |
1302 | mci->edac_cap |= EDAC_FLAG_NONE; | |
537fba28 | 1303 | debugf3("%s(): tolm, remapbase, remaplimit\n", __func__); |
e7ecd891 | 1304 | |
806c35f5 | 1305 | /* load the top of low memory, remap base, and remap limit vars */ |
37f04581 | 1306 | pci_read_config_word(pdev, E752X_TOLM, &pci_data); |
806c35f5 | 1307 | pvt->tolm = ((u32) pci_data) << 4; |
37f04581 | 1308 | pci_read_config_word(pdev, E752X_REMAPBASE, &pci_data); |
806c35f5 | 1309 | pvt->remapbase = ((u32) pci_data) << 14; |
37f04581 | 1310 | pci_read_config_word(pdev, E752X_REMAPLIMIT, &pci_data); |
806c35f5 | 1311 | pvt->remaplimit = ((u32) pci_data) << 14; |
537fba28 | 1312 | e752x_printk(KERN_INFO, |
052dfb45 DT |
1313 | "tolm = %x, remapbase = %x, remaplimit = %x\n", |
1314 | pvt->tolm, pvt->remapbase, pvt->remaplimit); | |
806c35f5 | 1315 | |
2d7bbb91 DT |
1316 | /* Here we assume that we will never see multiple instances of this |
1317 | * type of memory controller. The ID is therefore hardcoded to 0. | |
1318 | */ | |
b8f6f975 | 1319 | if (edac_mc_add_mc(mci)) { |
537fba28 | 1320 | debugf3("%s(): failed edac_mc_add_mc()\n", __func__); |
806c35f5 AC |
1321 | goto fail; |
1322 | } | |
1323 | ||
13189525 | 1324 | e752x_init_error_reporting_regs(pvt); |
203333cb | 1325 | e752x_get_error_info(mci, &discard); /* clear other MCH errors */ |
806c35f5 | 1326 | |
91b99041 DJ |
1327 | /* allocating generic PCI control info */ |
1328 | e752x_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR); | |
1329 | if (!e752x_pci) { | |
1330 | printk(KERN_WARNING | |
052dfb45 | 1331 | "%s(): Unable to create PCI control\n", __func__); |
91b99041 | 1332 | printk(KERN_WARNING |
052dfb45 DT |
1333 | "%s(): PCI error report via EDAC not setup\n", |
1334 | __func__); | |
91b99041 DJ |
1335 | } |
1336 | ||
806c35f5 | 1337 | /* get this far and it's successful */ |
537fba28 | 1338 | debugf3("%s(): success\n", __func__); |
806c35f5 AC |
1339 | return 0; |
1340 | ||
052dfb45 | 1341 | fail: |
13189525 DT |
1342 | pci_dev_put(pvt->dev_d0f0); |
1343 | pci_dev_put(pvt->dev_d0f1); | |
1344 | pci_dev_put(pvt->bridge_ck); | |
1345 | edac_mc_free(mci); | |
e7ecd891 | 1346 | |
13189525 | 1347 | return -ENODEV; |
806c35f5 AC |
1348 | } |
1349 | ||
1350 | /* returns count (>= 0), or negative on error */ | |
1351 | static int __devinit e752x_init_one(struct pci_dev *pdev, | |
052dfb45 | 1352 | const struct pci_device_id *ent) |
806c35f5 | 1353 | { |
537fba28 | 1354 | debugf0("%s()\n", __func__); |
806c35f5 AC |
1355 | |
1356 | /* wake up and enable device */ | |
203333cb | 1357 | if (pci_enable_device(pdev) < 0) |
806c35f5 | 1358 | return -EIO; |
e7ecd891 | 1359 | |
806c35f5 AC |
1360 | return e752x_probe1(pdev, ent->driver_data); |
1361 | } | |
1362 | ||
806c35f5 AC |
1363 | static void __devexit e752x_remove_one(struct pci_dev *pdev) |
1364 | { | |
1365 | struct mem_ctl_info *mci; | |
1366 | struct e752x_pvt *pvt; | |
1367 | ||
537fba28 | 1368 | debugf0("%s()\n", __func__); |
806c35f5 | 1369 | |
91b99041 DJ |
1370 | if (e752x_pci) |
1371 | edac_pci_release_generic_ctl(e752x_pci); | |
1372 | ||
37f04581 | 1373 | if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL) |
806c35f5 AC |
1374 | return; |
1375 | ||
203333cb | 1376 | pvt = (struct e752x_pvt *)mci->pvt_info; |
806c35f5 AC |
1377 | pci_dev_put(pvt->dev_d0f0); |
1378 | pci_dev_put(pvt->dev_d0f1); | |
1379 | pci_dev_put(pvt->bridge_ck); | |
1380 | edac_mc_free(mci); | |
1381 | } | |
1382 | ||
36c46f31 | 1383 | static DEFINE_PCI_DEVICE_TABLE(e752x_pci_tbl) = { |
e7ecd891 | 1384 | { |
203333cb DJ |
1385 | PCI_VEND_DEV(INTEL, 7520_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
1386 | E7520}, | |
e7ecd891 | 1387 | { |
203333cb DJ |
1388 | PCI_VEND_DEV(INTEL, 7525_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
1389 | E7525}, | |
e7ecd891 | 1390 | { |
203333cb DJ |
1391 | PCI_VEND_DEV(INTEL, 7320_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
1392 | E7320}, | |
5135b797 AK |
1393 | { |
1394 | PCI_VEND_DEV(INTEL, 3100_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1395 | I3100}, | |
e7ecd891 | 1396 | { |
203333cb DJ |
1397 | 0, |
1398 | } /* 0 terminated list. */ | |
806c35f5 AC |
1399 | }; |
1400 | ||
1401 | MODULE_DEVICE_TABLE(pci, e752x_pci_tbl); | |
1402 | ||
806c35f5 | 1403 | static struct pci_driver e752x_driver = { |
680cbbbb | 1404 | .name = EDAC_MOD_STR, |
0d38b049 RD |
1405 | .probe = e752x_init_one, |
1406 | .remove = __devexit_p(e752x_remove_one), | |
1407 | .id_table = e752x_pci_tbl, | |
806c35f5 AC |
1408 | }; |
1409 | ||
da9bb1d2 | 1410 | static int __init e752x_init(void) |
806c35f5 AC |
1411 | { |
1412 | int pci_rc; | |
1413 | ||
537fba28 | 1414 | debugf3("%s()\n", __func__); |
c3c52bce HM |
1415 | |
1416 | /* Ensure that the OPSTATE is set correctly for POLL or NMI */ | |
1417 | opstate_init(); | |
1418 | ||
806c35f5 AC |
1419 | pci_rc = pci_register_driver(&e752x_driver); |
1420 | return (pci_rc < 0) ? pci_rc : 0; | |
1421 | } | |
1422 | ||
806c35f5 AC |
1423 | static void __exit e752x_exit(void) |
1424 | { | |
537fba28 | 1425 | debugf3("%s()\n", __func__); |
806c35f5 AC |
1426 | pci_unregister_driver(&e752x_driver); |
1427 | } | |
1428 | ||
806c35f5 AC |
1429 | module_init(e752x_init); |
1430 | module_exit(e752x_exit); | |
1431 | ||
1432 | MODULE_LICENSE("GPL"); | |
1433 | MODULE_AUTHOR("Linux Networx (http://lnxi.com) Tom Zimmerman\n"); | |
5135b797 | 1434 | MODULE_DESCRIPTION("MC support for Intel e752x/3100 memory controllers"); |
96941026 | 1435 | |
1436 | module_param(force_function_unhide, int, 0444); | |
1437 | MODULE_PARM_DESC(force_function_unhide, "if BIOS sets Dev0:Fun1 up as hidden:" | |
10d33e9c DT |
1438 | " 1=force unhide and hope BIOS doesn't fight driver for " |
1439 | "Dev0:Fun1 access"); | |
c3c52bce | 1440 | |
c0d12172 DJ |
1441 | module_param(edac_op_state, int, 0444); |
1442 | MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); | |
94ee1cf5 PT |
1443 | |
1444 | module_param(sysbus_parity, int, 0444); | |
1445 | MODULE_PARM_DESC(sysbus_parity, "0=disable system bus parity checking," | |
1446 | " 1=enable system bus parity checking, default=auto-detect"); | |
10d33e9c DT |
1447 | module_param(report_non_memory_errors, int, 0644); |
1448 | MODULE_PARM_DESC(report_non_memory_errors, "0=disable non-memory error " | |
1449 | "reporting, 1=enable non-memory error reporting"); |