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Merge branch 'master' of ssh://master.kernel.org/pub/scm/linux/kernel/git/mchehab...
[deliverable/linux.git] / drivers / edac / e752x_edac.c
CommitLineData
806c35f5
AC		 1/*
2 * Intel e752x Memory Controller kernel module
3 * (C) 2004 Linux Networx (http://lnxi.com)
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
6 *
7 * See "enum e752x_chips" below for supported chipsets
8 *
9 * Written by Tom Zimmerman
10 *
11 * Contributors:
12 * Thayne Harbaugh at realmsys.com (?)
13 * Wang Zhenyu at intel.com
14 * Dave Jiang at mvista.com
15 *
da9bb1d2 16 * $Id: edac_e752x.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $
806c35f5
AC		 17 *
18 */
19
806c35f5
AC		 20#include <linux/module.h>
21#include <linux/init.h>
806c35f5
AC		 22#include <linux/pci.h>
23#include <linux/pci_ids.h>
806c35f5 24#include <linux/slab.h>
806c35f5
AC		 25#include "edac_mc.h"
26
929a40ec
DT		 27#define E752X_REVISION " Ver: 2.0.1 " __DATE__
28#define EDAC_MOD_STR "e752x_edac"
37f04581 29
96941026 30static int force_function_unhide;
31
537fba28 32#define e752x_printk(level, fmt, arg...) \
e7ecd891 33 edac_printk(level, "e752x", fmt, ##arg)
537fba28
DP		 34
35#define e752x_mc_printk(mci, level, fmt, arg...) \
e7ecd891 36 edac_mc_chipset_printk(mci, level, "e752x", fmt, ##arg)
537fba28 37
806c35f5
AC		 38#ifndef PCI_DEVICE_ID_INTEL_7520_0
39#define PCI_DEVICE_ID_INTEL_7520_0 0x3590
40#endif /* PCI_DEVICE_ID_INTEL_7520_0 */
41
42#ifndef PCI_DEVICE_ID_INTEL_7520_1_ERR
43#define PCI_DEVICE_ID_INTEL_7520_1_ERR 0x3591
44#endif /* PCI_DEVICE_ID_INTEL_7520_1_ERR */
45
46#ifndef PCI_DEVICE_ID_INTEL_7525_0
47#define PCI_DEVICE_ID_INTEL_7525_0 0x359E
48#endif /* PCI_DEVICE_ID_INTEL_7525_0 */
49
50#ifndef PCI_DEVICE_ID_INTEL_7525_1_ERR
51#define PCI_DEVICE_ID_INTEL_7525_1_ERR 0x3593
52#endif /* PCI_DEVICE_ID_INTEL_7525_1_ERR */
53
54#ifndef PCI_DEVICE_ID_INTEL_7320_0
55#define PCI_DEVICE_ID_INTEL_7320_0 0x3592
56#endif /* PCI_DEVICE_ID_INTEL_7320_0 */
57
58#ifndef PCI_DEVICE_ID_INTEL_7320_1_ERR
59#define PCI_DEVICE_ID_INTEL_7320_1_ERR 0x3593
60#endif /* PCI_DEVICE_ID_INTEL_7320_1_ERR */
61
62#define E752X_NR_CSROWS 8 /* number of csrows */
63
806c35f5
AC		 64/* E752X register addresses - device 0 function 0 */
65#define E752X_DRB 0x60 /* DRAM row boundary register (8b) */
66#define E752X_DRA 0x70 /* DRAM row attribute register (8b) */
67 /*
68 * 31:30 Device width row 7
69 * 01=x8 10=x4 11=x8 DDR2
70 * 27:26 Device width row 6
71 * 23:22 Device width row 5
72 * 19:20 Device width row 4
73 * 15:14 Device width row 3
74 * 11:10 Device width row 2
75 * 7:6 Device width row 1
76 * 3:2 Device width row 0
77 */
78#define E752X_DRC 0x7C /* DRAM controller mode reg (32b) */
79 /* FIXME:IS THIS RIGHT? */
80 /*
81 * 22 Number channels 0=1,1=2
82 * 19:18 DRB Granularity 32/64MB
83 */
84#define E752X_DRM 0x80 /* Dimm mapping register */
85#define E752X_DDRCSR 0x9A /* DDR control and status reg (16b) */
86 /*
87 * 14:12 1 single A, 2 single B, 3 dual
88 */
89#define E752X_TOLM 0xC4 /* DRAM top of low memory reg (16b) */
90#define E752X_REMAPBASE 0xC6 /* DRAM remap base address reg (16b) */
91#define E752X_REMAPLIMIT 0xC8 /* DRAM remap limit address reg (16b) */
92#define E752X_REMAPOFFSET 0xCA /* DRAM remap limit offset reg (16b) */
93
94/* E752X register addresses - device 0 function 1 */
95#define E752X_FERR_GLOBAL 0x40 /* Global first error register (32b) */
96#define E752X_NERR_GLOBAL 0x44 /* Global next error register (32b) */
97#define E752X_HI_FERR 0x50 /* Hub interface first error reg (8b) */
98#define E752X_HI_NERR 0x52 /* Hub interface next error reg (8b) */
99#define E752X_HI_ERRMASK 0x54 /* Hub interface error mask reg (8b) */
100#define E752X_HI_SMICMD 0x5A /* Hub interface SMI command reg (8b) */
101#define E752X_SYSBUS_FERR 0x60 /* System buss first error reg (16b) */
102#define E752X_SYSBUS_NERR 0x62 /* System buss next error reg (16b) */
103#define E752X_SYSBUS_ERRMASK 0x64 /* System buss error mask reg (16b) */
104#define E752X_SYSBUS_SMICMD 0x6A /* System buss SMI command reg (16b) */
105#define E752X_BUF_FERR 0x70 /* Memory buffer first error reg (8b) */
106#define E752X_BUF_NERR 0x72 /* Memory buffer next error reg (8b) */
107#define E752X_BUF_ERRMASK 0x74 /* Memory buffer error mask reg (8b) */
108#define E752X_BUF_SMICMD 0x7A /* Memory buffer SMI command reg (8b) */
109#define E752X_DRAM_FERR 0x80 /* DRAM first error register (16b) */
110#define E752X_DRAM_NERR 0x82 /* DRAM next error register (16b) */
111#define E752X_DRAM_ERRMASK 0x84 /* DRAM error mask register (8b) */
112#define E752X_DRAM_SMICMD 0x8A /* DRAM SMI command register (8b) */
113#define E752X_DRAM_RETR_ADD 0xAC /* DRAM Retry address register (32b) */
114#define E752X_DRAM_SEC1_ADD 0xA0 /* DRAM first correctable memory */
115 /* error address register (32b) */
116 /*
117 * 31 Reserved
118 * 30:2 CE address (64 byte block 34:6)
119 * 1 Reserved
120 * 0 HiLoCS
121 */
122#define E752X_DRAM_SEC2_ADD 0xC8 /* DRAM first correctable memory */
123 /* error address register (32b) */
124 /*
125 * 31 Reserved
126 * 30:2 CE address (64 byte block 34:6)
127 * 1 Reserved
128 * 0 HiLoCS
129 */
130#define E752X_DRAM_DED_ADD 0xA4 /* DRAM first uncorrectable memory */
131 /* error address register (32b) */
132 /*
133 * 31 Reserved
134 * 30:2 CE address (64 byte block 34:6)
135 * 1 Reserved
136 * 0 HiLoCS
137 */
138#define E752X_DRAM_SCRB_ADD 0xA8 /* DRAM first uncorrectable scrub memory */
139 /* error address register (32b) */
140 /*
141 * 31 Reserved
142 * 30:2 CE address (64 byte block 34:6)
143 * 1 Reserved
144 * 0 HiLoCS
145 */
146#define E752X_DRAM_SEC1_SYNDROME 0xC4 /* DRAM first correctable memory */
147 /* error syndrome register (16b) */
148#define E752X_DRAM_SEC2_SYNDROME 0xC6 /* DRAM second correctable memory */
149 /* error syndrome register (16b) */
150#define E752X_DEVPRES1 0xF4 /* Device Present 1 register (8b) */
151
152/* ICH5R register addresses - device 30 function 0 */
153#define ICH5R_PCI_STAT 0x06 /* PCI status register (16b) */
154#define ICH5R_PCI_2ND_STAT 0x1E /* PCI status secondary reg (16b) */
155#define ICH5R_PCI_BRIDGE_CTL 0x3E /* PCI bridge control register (16b) */
156
157enum e752x_chips {
158 E7520 = 0,
159 E7525 = 1,
160 E7320 = 2
161};
162
806c35f5
AC		 163struct e752x_pvt {
164 struct pci_dev *bridge_ck;
165 struct pci_dev *dev_d0f0;
166 struct pci_dev *dev_d0f1;
167 u32 tolm;
168 u32 remapbase;
169 u32 remaplimit;
170 int mc_symmetric;
171 u8 map[8];
172 int map_type;
173 const struct e752x_dev_info *dev_info;
174};
175
806c35f5
AC		 176struct e752x_dev_info {
177 u16 err_dev;
3847bccc 178 u16 ctl_dev;
806c35f5
AC		 179 const char *ctl_name;
180};
181
182struct e752x_error_info {
183 u32 ferr_global;
184 u32 nerr_global;
185 u8 hi_ferr;
186 u8 hi_nerr;
187 u16 sysbus_ferr;
188 u16 sysbus_nerr;
189 u8 buf_ferr;
190 u8 buf_nerr;
191 u16 dram_ferr;
192 u16 dram_nerr;
193 u32 dram_sec1_add;
194 u32 dram_sec2_add;
195 u16 dram_sec1_syndrome;
196 u16 dram_sec2_syndrome;
197 u32 dram_ded_add;
198 u32 dram_scrb_add;
199 u32 dram_retr_add;
200};
201
202static const struct e752x_dev_info e752x_devs[] = {
203 [E7520] = {
e7ecd891
DP		 204 .err_dev = PCI_DEVICE_ID_INTEL_7520_1_ERR,
205 .ctl_dev = PCI_DEVICE_ID_INTEL_7520_0,
206 .ctl_name = "E7520"
207 },
806c35f5 208 [E7525] = {
e7ecd891
DP		 209 .err_dev = PCI_DEVICE_ID_INTEL_7525_1_ERR,
210 .ctl_dev = PCI_DEVICE_ID_INTEL_7525_0,
211 .ctl_name = "E7525"
212 },
806c35f5 213 [E7320] = {
e7ecd891
DP		 214 .err_dev = PCI_DEVICE_ID_INTEL_7320_1_ERR,
215 .ctl_dev = PCI_DEVICE_ID_INTEL_7320_0,
216 .ctl_name = "E7320"
217 },
806c35f5
AC		 218};
219
806c35f5 220static unsigned long ctl_page_to_phys(struct mem_ctl_info *mci,
e7ecd891 221 unsigned long page)
806c35f5
AC		 222{
223 u32 remap;
224 struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
225
537fba28 226 debugf3("%s()\n", __func__);
806c35f5
AC		 227
228 if (page < pvt->tolm)
229 return page;
e7ecd891 230
806c35f5
AC		 231 if ((page >= 0x100000) && (page < pvt->remapbase))
232 return page;
e7ecd891 233
806c35f5 234 remap = (page - pvt->tolm) + pvt->remapbase;
e7ecd891 235
806c35f5
AC		 236 if (remap < pvt->remaplimit)
237 return remap;
e7ecd891 238
537fba28 239 e752x_printk(KERN_ERR, "Invalid page %lx - out of range\n", page);
806c35f5
AC		 240 return pvt->tolm - 1;
241}
242
243static void do_process_ce(struct mem_ctl_info *mci, u16 error_one,
e7ecd891 244 u32 sec1_add, u16 sec1_syndrome)
806c35f5
AC		 245{
246 u32 page;
247 int row;
248 int channel;
249 int i;
250 struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
251
537fba28 252 debugf3("%s()\n", __func__);
806c35f5
AC		 253
254 /* convert the addr to 4k page */
255 page = sec1_add >> (PAGE_SHIFT - 4);
256
257 /* FIXME - check for -1 */
258 if (pvt->mc_symmetric) {
259 /* chip select are bits 14 & 13 */
260 row = ((page >> 1) & 3);
537fba28 261 e752x_printk(KERN_WARNING,
e7ecd891
DP		 262 "Test row %d Table %d %d %d %d %d %d %d %d\n", row,
263 pvt->map[0], pvt->map[1], pvt->map[2], pvt->map[3],
264 pvt->map[4], pvt->map[5], pvt->map[6], pvt->map[7]);
806c35f5
AC		 265
266 /* test for channel remapping */
267 for (i = 0; i < 8; i++) {
268 if (pvt->map[i] == row)
269 break;
270 }
e7ecd891 271
537fba28 272 e752x_printk(KERN_WARNING, "Test computed row %d\n", i);
e7ecd891 273
806c35f5
AC		 274 if (i < 8)
275 row = i;
276 else
537fba28 277 e752x_mc_printk(mci, KERN_WARNING,
e7ecd891 278 "row %d not found in remap table\n", row);
806c35f5
AC		 279 } else
280 row = edac_mc_find_csrow_by_page(mci, page);
e7ecd891 281
806c35f5
AC		 282 /* 0 = channel A, 1 = channel B */
283 channel = !(error_one & 1);
284
285 if (!pvt->map_type)
286 row = 7 - row;
e7ecd891 287
84db003f
MC		 288 /* e752x mc reads 34:6 of the DRAM linear address */
289 edac_mc_handle_ce(mci, page, offset_in_page(sec1_add << 4),
290 sec1_syndrome, row, channel, "e752x CE");
806c35f5
AC		 291}
292
806c35f5
AC		 293static inline void process_ce(struct mem_ctl_info *mci, u16 error_one,
294 u32 sec1_add, u16 sec1_syndrome, int *error_found,
295 int handle_error)
296{
297 *error_found = 1;
298
299 if (handle_error)
300 do_process_ce(mci, error_one, sec1_add, sec1_syndrome);
301}
302
e7ecd891
DP		 303static void do_process_ue(struct mem_ctl_info *mci, u16 error_one,
304 u32 ded_add, u32 scrb_add)
806c35f5
AC		 305{
306 u32 error_2b, block_page;
307 int row;
308 struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
309
537fba28 310 debugf3("%s()\n", __func__);
806c35f5
AC		 311
312 if (error_one & 0x0202) {
313 error_2b = ded_add;
e7ecd891 314
806c35f5
AC		 315 /* convert to 4k address */
316 block_page = error_2b >> (PAGE_SHIFT - 4);
e7ecd891 317
806c35f5 318 row = pvt->mc_symmetric ?
e7ecd891
DP		 319 /* chip select are bits 14 & 13 */
320 ((block_page >> 1) & 3) :
321 edac_mc_find_csrow_by_page(mci, block_page);
322
84db003f
MC		 323 /* e752x mc reads 34:6 of the DRAM linear address */
324 edac_mc_handle_ue(mci, block_page,
325 offset_in_page(error_2b << 4),
326 row, "e752x UE from Read");
806c35f5
AC		 327 }
328 if (error_one & 0x0404) {
329 error_2b = scrb_add;
e7ecd891 330
806c35f5
AC		 331 /* convert to 4k address */
332 block_page = error_2b >> (PAGE_SHIFT - 4);
e7ecd891 333
806c35f5 334 row = pvt->mc_symmetric ?
e7ecd891
DP		 335 /* chip select are bits 14 & 13 */
336 ((block_page >> 1) & 3) :
337 edac_mc_find_csrow_by_page(mci, block_page);
338
84db003f
MC		 339 /* e752x mc reads 34:6 of the DRAM linear address */
340 edac_mc_handle_ue(mci, block_page,
341 offset_in_page(error_2b << 4),
342 row, "e752x UE from Scruber");
806c35f5
AC		 343 }
344}
345
346static inline void process_ue(struct mem_ctl_info *mci, u16 error_one,
347 u32 ded_add, u32 scrb_add, int *error_found, int handle_error)
348{
349 *error_found = 1;
350
351 if (handle_error)
352 do_process_ue(mci, error_one, ded_add, scrb_add);
353}
354
355static inline void process_ue_no_info_wr(struct mem_ctl_info *mci,
356 int *error_found, int handle_error)
357{
358 *error_found = 1;
359
360 if (!handle_error)
361 return;
362
537fba28 363 debugf3("%s()\n", __func__);
806c35f5
AC		 364 edac_mc_handle_ue_no_info(mci, "e752x UE log memory write");
365}
366
367static void do_process_ded_retry(struct mem_ctl_info *mci, u16 error,
368 u32 retry_add)
369{
370 u32 error_1b, page;
371 int row;
372 struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
373
374 error_1b = retry_add;
e7ecd891 375 page = error_1b >> (PAGE_SHIFT - 4); /* convert the addr to 4k page */
806c35f5 376 row = pvt->mc_symmetric ?
e7ecd891
DP		 377 ((page >> 1) & 3) : /* chip select are bits 14 & 13 */
378 edac_mc_find_csrow_by_page(mci, page);
537fba28 379 e752x_mc_printk(mci, KERN_WARNING,
e7ecd891
DP		 380 "CE page 0x%lx, row %d : Memory read retry\n",
381 (long unsigned int) page, row);
806c35f5
AC		 382}
383
384static inline void process_ded_retry(struct mem_ctl_info *mci, u16 error,
385 u32 retry_add, int *error_found, int handle_error)
386{
387 *error_found = 1;
388
389 if (handle_error)
390 do_process_ded_retry(mci, error, retry_add);
391}
392
393static inline void process_threshold_ce(struct mem_ctl_info *mci, u16 error,
394 int *error_found, int handle_error)
395{
396 *error_found = 1;
397
398 if (handle_error)
537fba28 399 e752x_mc_printk(mci, KERN_WARNING, "Memory threshold CE\n");
806c35f5
AC		 400}
401
da9bb1d2 402static char *global_message[11] = {
806c35f5
AC		 403 "PCI Express C1", "PCI Express C", "PCI Express B1",
404 "PCI Express B", "PCI Express A1", "PCI Express A",
405 "DMA Controler", "HUB Interface", "System Bus",
406 "DRAM Controler", "Internal Buffer"
407};
408
da9bb1d2 409static char *fatal_message[2] = { "Non-Fatal ", "Fatal " };
806c35f5
AC		 410
411static void do_global_error(int fatal, u32 errors)
412{
413 int i;
414
415 for (i = 0; i < 11; i++) {
416 if (errors & (1 << i))
537fba28 417 e752x_printk(KERN_WARNING, "%sError %s\n",
e7ecd891 418 fatal_message[fatal], global_message[i]);
806c35f5
AC		 419 }
420}
421
422static inline void global_error(int fatal, u32 errors, int *error_found,
423 int handle_error)
424{
425 *error_found = 1;
426
427 if (handle_error)
428 do_global_error(fatal, errors);
429}
430
da9bb1d2 431static char *hub_message[7] = {
806c35f5
AC		 432 "HI Address or Command Parity", "HI Illegal Access",
433 "HI Internal Parity", "Out of Range Access",
434 "HI Data Parity", "Enhanced Config Access",
435 "Hub Interface Target Abort"
436};
437
438static void do_hub_error(int fatal, u8 errors)
439{
440 int i;
441
442 for (i = 0; i < 7; i++) {
443 if (errors & (1 << i))
537fba28 444 e752x_printk(KERN_WARNING, "%sError %s\n",
e7ecd891 445 fatal_message[fatal], hub_message[i]);
806c35f5
AC		 446 }
447}
448
449static inline void hub_error(int fatal, u8 errors, int *error_found,
450 int handle_error)
451{
452 *error_found = 1;
453
454 if (handle_error)
455 do_hub_error(fatal, errors);
456}
457
da9bb1d2 458static char *membuf_message[4] = {
806c35f5
AC		 459 "Internal PMWB to DRAM parity",
460 "Internal PMWB to System Bus Parity",
461 "Internal System Bus or IO to PMWB Parity",
462 "Internal DRAM to PMWB Parity"
463};
464
465static void do_membuf_error(u8 errors)
466{
467 int i;
468
469 for (i = 0; i < 4; i++) {
470 if (errors & (1 << i))
537fba28 471 e752x_printk(KERN_WARNING, "Non-Fatal Error %s\n",
e7ecd891 472 membuf_message[i]);
806c35f5
AC		 473 }
474}
475
476static inline void membuf_error(u8 errors, int *error_found, int handle_error)
477{
478 *error_found = 1;
479
480 if (handle_error)
481 do_membuf_error(errors);
482}
483
e009356f 484static char *sysbus_message[10] = {
806c35f5
AC		 485 "Addr or Request Parity",
486 "Data Strobe Glitch",
487 "Addr Strobe Glitch",
488 "Data Parity",
489 "Addr Above TOM",
490 "Non DRAM Lock Error",
491 "MCERR", "BINIT",
492 "Memory Parity",
493 "IO Subsystem Parity"
494};
495
496static void do_sysbus_error(int fatal, u32 errors)
497{
498 int i;
499
500 for (i = 0; i < 10; i++) {
501 if (errors & (1 << i))
537fba28 502 e752x_printk(KERN_WARNING, "%sError System Bus %s\n",
e009356f 503 fatal_message[fatal], sysbus_message[i]);
806c35f5
AC		 504 }
505}
506
507static inline void sysbus_error(int fatal, u32 errors, int *error_found,
508 int handle_error)
509{
510 *error_found = 1;
511
512 if (handle_error)
513 do_sysbus_error(fatal, errors);
514}
515
e7ecd891 516static void e752x_check_hub_interface(struct e752x_error_info *info,
806c35f5
AC		 517 int *error_found, int handle_error)
518{
519 u8 stat8;
520
521 //pci_read_config_byte(dev,E752X_HI_FERR,&stat8);
e7ecd891 522
806c35f5 523 stat8 = info->hi_ferr;
e7ecd891 524
806c35f5
AC		 525 if(stat8 & 0x7f) { /* Error, so process */
526 stat8 &= 0x7f;
e7ecd891 527
806c35f5
AC		 528 if(stat8 & 0x2b)
529 hub_error(1, stat8 & 0x2b, error_found, handle_error);
e7ecd891 530
806c35f5
AC		 531 if(stat8 & 0x54)
532 hub_error(0, stat8 & 0x54, error_found, handle_error);
533 }
e7ecd891 534
806c35f5 535 //pci_read_config_byte(dev,E752X_HI_NERR,&stat8);
e7ecd891 536
806c35f5 537 stat8 = info->hi_nerr;
e7ecd891 538
806c35f5
AC		 539 if(stat8 & 0x7f) { /* Error, so process */
540 stat8 &= 0x7f;
e7ecd891 541
806c35f5
AC		 542 if (stat8 & 0x2b)
543 hub_error(1, stat8 & 0x2b, error_found, handle_error);
e7ecd891 544
806c35f5
AC		 545 if(stat8 & 0x54)
546 hub_error(0, stat8 & 0x54, error_found, handle_error);
547 }
548}
549
e7ecd891
DP		 550static void e752x_check_sysbus(struct e752x_error_info *info,
551 int *error_found, int handle_error)
806c35f5
AC		 552{
553 u32 stat32, error32;
554
555 //pci_read_config_dword(dev,E752X_SYSBUS_FERR,&stat32);
556 stat32 = info->sysbus_ferr + (info->sysbus_nerr << 16);
557
558 if (stat32 == 0)
559 return; /* no errors */
560
561 error32 = (stat32 >> 16) & 0x3ff;
562 stat32 = stat32 & 0x3ff;
e7ecd891 563
dfb2a763
BP		 564 if(stat32 & 0x087)
565 sysbus_error(1, stat32 & 0x087, error_found, handle_error);
e7ecd891 566
dfb2a763
BP		 567 if(stat32 & 0x378)
568 sysbus_error(0, stat32 & 0x378, error_found, handle_error);
e7ecd891 569
dfb2a763
BP		 570 if(error32 & 0x087)
571 sysbus_error(1, error32 & 0x087, error_found, handle_error);
e7ecd891 572
dfb2a763
BP		 573 if(error32 & 0x378)
574 sysbus_error(0, error32 & 0x378, error_found, handle_error);
806c35f5
AC		 575}
576
e7ecd891
DP		 577static void e752x_check_membuf (struct e752x_error_info *info,
578 int *error_found, int handle_error)
806c35f5
AC		 579{
580 u8 stat8;
581
582 stat8 = info->buf_ferr;
e7ecd891 583
806c35f5
AC		 584 if (stat8 & 0x0f) { /* Error, so process */
585 stat8 &= 0x0f;
586 membuf_error(stat8, error_found, handle_error);
587 }
e7ecd891 588
806c35f5 589 stat8 = info->buf_nerr;
e7ecd891 590
806c35f5
AC		 591 if (stat8 & 0x0f) { /* Error, so process */
592 stat8 &= 0x0f;
593 membuf_error(stat8, error_found, handle_error);
594 }
595}
596
597static void e752x_check_dram (struct mem_ctl_info *mci,
e7ecd891
DP		 598 struct e752x_error_info *info, int *error_found,
599 int handle_error)
806c35f5
AC		 600{
601 u16 error_one, error_next;
602
603 error_one = info->dram_ferr;
604 error_next = info->dram_nerr;
605
606 /* decode and report errors */
607 if(error_one & 0x0101) /* check first error correctable */
608 process_ce(mci, error_one, info->dram_sec1_add,
609 info->dram_sec1_syndrome, error_found,
610 handle_error);
611
612 if(error_next & 0x0101) /* check next error correctable */
613 process_ce(mci, error_next, info->dram_sec2_add,
614 info->dram_sec2_syndrome, error_found,
615 handle_error);
616
617 if(error_one & 0x4040)
618 process_ue_no_info_wr(mci, error_found, handle_error);
619
620 if(error_next & 0x4040)
621 process_ue_no_info_wr(mci, error_found, handle_error);
622
623 if(error_one & 0x2020)
624 process_ded_retry(mci, error_one, info->dram_retr_add,
625 error_found, handle_error);
626
627 if(error_next & 0x2020)
628 process_ded_retry(mci, error_next, info->dram_retr_add,
629 error_found, handle_error);
630
631 if(error_one & 0x0808)
632 process_threshold_ce(mci, error_one, error_found,
633 handle_error);
634
635 if(error_next & 0x0808)
636 process_threshold_ce(mci, error_next, error_found,
637 handle_error);
638
639 if(error_one & 0x0606)
640 process_ue(mci, error_one, info->dram_ded_add,
641 info->dram_scrb_add, error_found, handle_error);
642
643 if(error_next & 0x0606)
644 process_ue(mci, error_next, info->dram_ded_add,
645 info->dram_scrb_add, error_found, handle_error);
646}
647
648static void e752x_get_error_info (struct mem_ctl_info *mci,
e7ecd891 649 struct e752x_error_info *info)
806c35f5
AC		 650{
651 struct pci_dev *dev;
652 struct e752x_pvt *pvt;
653
654 memset(info, 0, sizeof(*info));
655 pvt = (struct e752x_pvt *) mci->pvt_info;
656 dev = pvt->dev_d0f1;
806c35f5
AC		 657 pci_read_config_dword(dev, E752X_FERR_GLOBAL, &info->ferr_global);
658
659 if (info->ferr_global) {
660 pci_read_config_byte(dev, E752X_HI_FERR, &info->hi_ferr);
661 pci_read_config_word(dev, E752X_SYSBUS_FERR,
662 &info->sysbus_ferr);
663 pci_read_config_byte(dev, E752X_BUF_FERR, &info->buf_ferr);
664 pci_read_config_word(dev, E752X_DRAM_FERR,
665 &info->dram_ferr);
666 pci_read_config_dword(dev, E752X_DRAM_SEC1_ADD,
667 &info->dram_sec1_add);
668 pci_read_config_word(dev, E752X_DRAM_SEC1_SYNDROME,
669 &info->dram_sec1_syndrome);
670 pci_read_config_dword(dev, E752X_DRAM_DED_ADD,
671 &info->dram_ded_add);
672 pci_read_config_dword(dev, E752X_DRAM_SCRB_ADD,
673 &info->dram_scrb_add);
674 pci_read_config_dword(dev, E752X_DRAM_RETR_ADD,
675 &info->dram_retr_add);
676
677 if (info->hi_ferr & 0x7f)
678 pci_write_config_byte(dev, E752X_HI_FERR,
679 info->hi_ferr);
680
681 if (info->sysbus_ferr)
682 pci_write_config_word(dev, E752X_SYSBUS_FERR,
683 info->sysbus_ferr);
684
685 if (info->buf_ferr & 0x0f)
686 pci_write_config_byte(dev, E752X_BUF_FERR,
687 info->buf_ferr);
688
689 if (info->dram_ferr)
690 pci_write_bits16(pvt->bridge_ck, E752X_DRAM_FERR,
691 info->dram_ferr, info->dram_ferr);
692
693 pci_write_config_dword(dev, E752X_FERR_GLOBAL,
694 info->ferr_global);
695 }
696
697 pci_read_config_dword(dev, E752X_NERR_GLOBAL, &info->nerr_global);
698
699 if (info->nerr_global) {
700 pci_read_config_byte(dev, E752X_HI_NERR, &info->hi_nerr);
701 pci_read_config_word(dev, E752X_SYSBUS_NERR,
702 &info->sysbus_nerr);
703 pci_read_config_byte(dev, E752X_BUF_NERR, &info->buf_nerr);
704 pci_read_config_word(dev, E752X_DRAM_NERR,
705 &info->dram_nerr);
706 pci_read_config_dword(dev, E752X_DRAM_SEC2_ADD,
707 &info->dram_sec2_add);
708 pci_read_config_word(dev, E752X_DRAM_SEC2_SYNDROME,
709 &info->dram_sec2_syndrome);
710
711 if (info->hi_nerr & 0x7f)
712 pci_write_config_byte(dev, E752X_HI_NERR,
713 info->hi_nerr);
714
715 if (info->sysbus_nerr)
716 pci_write_config_word(dev, E752X_SYSBUS_NERR,
717 info->sysbus_nerr);
718
719 if (info->buf_nerr & 0x0f)
720 pci_write_config_byte(dev, E752X_BUF_NERR,
721 info->buf_nerr);
722
723 if (info->dram_nerr)
724 pci_write_bits16(pvt->bridge_ck, E752X_DRAM_NERR,
725 info->dram_nerr, info->dram_nerr);
726
727 pci_write_config_dword(dev, E752X_NERR_GLOBAL,
728 info->nerr_global);
729 }
730}
731
732static int e752x_process_error_info (struct mem_ctl_info *mci,
733 struct e752x_error_info *info, int handle_errors)
734{
735 u32 error32, stat32;
736 int error_found;
737
738 error_found = 0;
739 error32 = (info->ferr_global >> 18) & 0x3ff;
740 stat32 = (info->ferr_global >> 4) & 0x7ff;
741
742 if (error32)
743 global_error(1, error32, &error_found, handle_errors);
744
745 if (stat32)
746 global_error(0, stat32, &error_found, handle_errors);
747
748 error32 = (info->nerr_global >> 18) & 0x3ff;
749 stat32 = (info->nerr_global >> 4) & 0x7ff;
750
751 if (error32)
752 global_error(1, error32, &error_found, handle_errors);
753
754 if (stat32)
755 global_error(0, stat32, &error_found, handle_errors);
756
757 e752x_check_hub_interface(info, &error_found, handle_errors);
758 e752x_check_sysbus(info, &error_found, handle_errors);
759 e752x_check_membuf(info, &error_found, handle_errors);
760 e752x_check_dram(mci, info, &error_found, handle_errors);
761 return error_found;
762}
763
764static void e752x_check(struct mem_ctl_info *mci)
765{
766 struct e752x_error_info info;
e7ecd891 767
537fba28 768 debugf3("%s()\n", __func__);
806c35f5
AC		 769 e752x_get_error_info(mci, &info);
770 e752x_process_error_info(mci, &info, 1);
771}
772
13189525
DT		 773/* Return 1 if dual channel mode is active. Else return 0. */
774static inline int dual_channel_active(u16 ddrcsr)
775{
776 return (((ddrcsr >> 12) & 3) == 3);
777}
778
779static void e752x_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
780 u16 ddrcsr)
781{
782 struct csrow_info *csrow;
783 unsigned long last_cumul_size;
784 int index, mem_dev, drc_chan;
785 int drc_drbg; /* DRB granularity 0=64mb, 1=128mb */
786 int drc_ddim; /* DRAM Data Integrity Mode 0=none, 2=edac */
787 u8 value;
788 u32 dra, drc, cumul_size;
789
9962fd01
BP		 790 dra = 0;
791 for (index=0; index < 4; index++) {
792 u8 dra_reg;
793 pci_read_config_byte(pdev, E752X_DRA+index, &dra_reg);
794 dra |= dra_reg << (index * 8);
795 }
13189525
DT		 796 pci_read_config_dword(pdev, E752X_DRC, &drc);
797 drc_chan = dual_channel_active(ddrcsr);
798 drc_drbg = drc_chan + 1; /* 128 in dual mode, 64 in single */
799 drc_ddim = (drc >> 20) & 0x3;
800
801 /* The dram row boundary (DRB) reg values are boundary address for
802 * each DRAM row with a granularity of 64 or 128MB (single/dual
803 * channel operation). DRB regs are cumulative; therefore DRB7 will
804 * contain the total memory contained in all eight rows.
805 */
806 for (last_cumul_size = index = 0; index < mci->nr_csrows; index++) {
807 /* mem_dev 0=x8, 1=x4 */
808 mem_dev = (dra >> (index * 4 + 2)) & 0x3;
809 csrow = &mci->csrows[index];
810
811 mem_dev = (mem_dev == 2);
812 pci_read_config_byte(pdev, E752X_DRB + index, &value);
813 /* convert a 128 or 64 MiB DRB to a page size. */
814 cumul_size = value << (25 + drc_drbg - PAGE_SHIFT);
815 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
816 cumul_size);
817 if (cumul_size == last_cumul_size)
818 continue; /* not populated */
819
820 csrow->first_page = last_cumul_size;
821 csrow->last_page = cumul_size - 1;
822 csrow->nr_pages = cumul_size - last_cumul_size;
823 last_cumul_size = cumul_size;
824 csrow->grain = 1 << 12; /* 4KiB - resolution of CELOG */
825 csrow->mtype = MEM_RDDR; /* only one type supported */
826 csrow->dtype = mem_dev ? DEV_X4 : DEV_X8;
827
828 /*
829 * if single channel or x8 devices then SECDED
830 * if dual channel and x4 then S4ECD4ED
831 */
832 if (drc_ddim) {
833 if (drc_chan && mem_dev) {
834 csrow->edac_mode = EDAC_S4ECD4ED;
835 mci->edac_cap |= EDAC_FLAG_S4ECD4ED;
836 } else {
837 csrow->edac_mode = EDAC_SECDED;
838 mci->edac_cap |= EDAC_FLAG_SECDED;
839 }
840 } else
841 csrow->edac_mode = EDAC_NONE;
842 }
843}
844
845static void e752x_init_mem_map_table(struct pci_dev *pdev,
846 struct e752x_pvt *pvt)
806c35f5 847{
806c35f5 848 int index;
13189525
DT		 849 u8 value, last, row, stat8;
850
851 last = 0;
852 row = 0;
853
854 for (index = 0; index < 8; index += 2) {
855 pci_read_config_byte(pdev, E752X_DRB + index, &value);
856 /* test if there is a dimm in this slot */
857 if (value == last) {
858 /* no dimm in the slot, so flag it as empty */
859 pvt->map[index] = 0xff;
860 pvt->map[index + 1] = 0xff;
861 } else { /* there is a dimm in the slot */
862 pvt->map[index] = row;
863 row++;
864 last = value;
865 /* test the next value to see if the dimm is double
866 * sided
867 */
868 pci_read_config_byte(pdev, E752X_DRB + index + 1,
869 &value);
870 pvt->map[index + 1] = (value == last) ?
871 0xff : /* the dimm is single sided,
872 so flag as empty */
873 row; /* this is a double sided dimm
874 to save the next row # */
875 row++;
876 last = value;
877 }
878 }
879
880 /* set the map type. 1 = normal, 0 = reversed */
881 pci_read_config_byte(pdev, E752X_DRM, &stat8);
882 pvt->map_type = ((stat8 & 0x0f) > ((stat8 >> 4) & 0x0f));
883}
884
885/* Return 0 on success or 1 on failure. */
886static int e752x_get_devs(struct pci_dev *pdev, int dev_idx,
887 struct e752x_pvt *pvt)
888{
889 struct pci_dev *dev;
890
891 pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL,
892 pvt->dev_info->err_dev,
893 pvt->bridge_ck);
894
895 if (pvt->bridge_ck == NULL)
896 pvt->bridge_ck = pci_scan_single_device(pdev->bus,
897 PCI_DEVFN(0, 1));
898
899 if (pvt->bridge_ck == NULL) {
900 e752x_printk(KERN_ERR, "error reporting device not found:"
901 "vendor %x device 0x%x (broken BIOS?)\n",
902 PCI_VENDOR_ID_INTEL, e752x_devs[dev_idx].err_dev);
903 return 1;
904 }
905
906 dev = pci_get_device(PCI_VENDOR_ID_INTEL, e752x_devs[dev_idx].ctl_dev,
907 NULL);
908
909 if (dev == NULL)
910 goto fail;
911
912 pvt->dev_d0f0 = dev;
913 pvt->dev_d0f1 = pci_dev_get(pvt->bridge_ck);
914
915 return 0;
916
917fail:
918 pci_dev_put(pvt->bridge_ck);
919 return 1;
920}
921
922static void e752x_init_error_reporting_regs(struct e752x_pvt *pvt)
923{
924 struct pci_dev *dev;
925
926 dev = pvt->dev_d0f1;
927 /* Turn off error disable & SMI in case the BIOS turned it on */
928 pci_write_config_byte(dev, E752X_HI_ERRMASK, 0x00);
929 pci_write_config_byte(dev, E752X_HI_SMICMD, 0x00);
930 pci_write_config_word(dev, E752X_SYSBUS_ERRMASK, 0x00);
931 pci_write_config_word(dev, E752X_SYSBUS_SMICMD, 0x00);
932 pci_write_config_byte(dev, E752X_BUF_ERRMASK, 0x00);
933 pci_write_config_byte(dev, E752X_BUF_SMICMD, 0x00);
934 pci_write_config_byte(dev, E752X_DRAM_ERRMASK, 0x00);
935 pci_write_config_byte(dev, E752X_DRAM_SMICMD, 0x00);
936}
937
938static int e752x_probe1(struct pci_dev *pdev, int dev_idx)
939{
3847bccc 940 u16 pci_data;
806c35f5 941 u8 stat8;
13189525
DT		 942 struct mem_ctl_info *mci;
943 struct e752x_pvt *pvt;
806c35f5 944 u16 ddrcsr;
e7ecd891 945 int drc_chan; /* Number of channels 0=1chan,1=2chan */
749ede57 946 struct e752x_error_info discard;
806c35f5 947
537fba28 948 debugf0("%s(): mci\n", __func__);
806c35f5
AC		 949 debugf0("Starting Probe1\n");
950
96941026 951 /* check to see if device 0 function 1 is enabled; if it isn't, we
952 * assume the BIOS has reserved it for a reason and is expecting
953 * exclusive access, we take care not to violate that assumption and
954 * fail the probe. */
806c35f5 955 pci_read_config_byte(pdev, E752X_DEVPRES1, &stat8);
96941026 956 if (!force_function_unhide && !(stat8 & (1 << 5))) {
957 printk(KERN_INFO "Contact your BIOS vendor to see if the "
958 "E752x error registers can be safely un-hidden\n");
13189525 959 return -ENOMEM;
96941026 960 }
806c35f5
AC		 961 stat8 |= (1 << 5);
962 pci_write_config_byte(pdev, E752X_DEVPRES1, stat8);
963
806c35f5
AC		 964 pci_read_config_word(pdev, E752X_DDRCSR, &ddrcsr);
965 /* FIXME: should check >>12 or 0xf, true for all? */
966 /* Dual channel = 1, Single channel = 0 */
13189525 967 drc_chan = dual_channel_active(ddrcsr);
806c35f5
AC		 968
969 mci = edac_mc_alloc(sizeof(*pvt), E752X_NR_CSROWS, drc_chan + 1);
970
971 if (mci == NULL) {
13189525 972 return -ENOMEM;
806c35f5
AC		 973 }
974
537fba28 975 debugf3("%s(): init mci\n", __func__);
806c35f5
AC		 976 mci->mtype_cap = MEM_FLAG_RDDR;
977 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED |
978 EDAC_FLAG_S4ECD4ED;
979 /* FIXME - what if different memory types are in different csrows? */
680cbbbb 980 mci->mod_name = EDAC_MOD_STR;
37f04581
DT		 981 mci->mod_ver = E752X_REVISION;
982 mci->dev = &pdev->dev;
806c35f5 983
537fba28 984 debugf3("%s(): init pvt\n", __func__);
806c35f5
AC		 985 pvt = (struct e752x_pvt *) mci->pvt_info;
986 pvt->dev_info = &e752x_devs[dev_idx];
13189525 987 pvt->mc_symmetric = ((ddrcsr & 0x10) != 0);
e7ecd891 988
13189525
DT		 989 if (e752x_get_devs(pdev, dev_idx, pvt)) {
990 edac_mc_free(mci);
991 return -ENODEV;
806c35f5 992 }
806c35f5 993
537fba28 994 debugf3("%s(): more mci init\n", __func__);
806c35f5
AC		 995 mci->ctl_name = pvt->dev_info->ctl_name;
996 mci->edac_check = e752x_check;
997 mci->ctl_page_to_phys = ctl_page_to_phys;
998
13189525
DT		 999 e752x_init_csrows(mci, pdev, ddrcsr);
1000 e752x_init_mem_map_table(pdev, pvt);
806c35f5
AC		 1001
1002 /* set the map type. 1 = normal, 0 = reversed */
37f04581 1003 pci_read_config_byte(pdev, E752X_DRM, &stat8);
806c35f5
AC		 1004 pvt->map_type = ((stat8 & 0x0f) > ((stat8 >> 4) & 0x0f));
1005
1006 mci->edac_cap |= EDAC_FLAG_NONE;
537fba28 1007 debugf3("%s(): tolm, remapbase, remaplimit\n", __func__);
e7ecd891 1008
806c35f5 1009 /* load the top of low memory, remap base, and remap limit vars */
37f04581 1010 pci_read_config_word(pdev, E752X_TOLM, &pci_data);
806c35f5 1011 pvt->tolm = ((u32) pci_data) << 4;
37f04581 1012 pci_read_config_word(pdev, E752X_REMAPBASE, &pci_data);
806c35f5 1013 pvt->remapbase = ((u32) pci_data) << 14;
37f04581 1014 pci_read_config_word(pdev, E752X_REMAPLIMIT, &pci_data);
806c35f5 1015 pvt->remaplimit = ((u32) pci_data) << 14;
537fba28 1016 e752x_printk(KERN_INFO,
e7ecd891
DP		 1017 "tolm = %x, remapbase = %x, remaplimit = %x\n", pvt->tolm,
1018 pvt->remapbase, pvt->remaplimit);
806c35f5 1019
2d7bbb91
DT		 1020 /* Here we assume that we will never see multiple instances of this
1021 * type of memory controller. The ID is therefore hardcoded to 0.
1022 */
1023 if (edac_mc_add_mc(mci,0)) {
537fba28 1024 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
806c35f5
AC		 1025 goto fail;
1026 }
1027
13189525 1028 e752x_init_error_reporting_regs(pvt);
e7ecd891 1029 e752x_get_error_info(mci, &discard); /* clear other MCH errors */
806c35f5
AC		 1030
1031 /* get this far and it's successful */
537fba28 1032 debugf3("%s(): success\n", __func__);
806c35f5
AC		 1033 return 0;
1034
1035fail:
13189525
DT		 1036 pci_dev_put(pvt->dev_d0f0);
1037 pci_dev_put(pvt->dev_d0f1);
1038 pci_dev_put(pvt->bridge_ck);
1039 edac_mc_free(mci);
e7ecd891 1040
13189525 1041 return -ENODEV;
806c35f5
AC		 1042}
1043
1044/* returns count (>= 0), or negative on error */
1045static int __devinit e752x_init_one(struct pci_dev *pdev,
e7ecd891 1046 const struct pci_device_id *ent)
806c35f5 1047{
537fba28 1048 debugf0("%s()\n", __func__);
806c35f5
AC		 1049
1050 /* wake up and enable device */
1051 if(pci_enable_device(pdev) < 0)
1052 return -EIO;
e7ecd891 1053
806c35f5
AC		 1054 return e752x_probe1(pdev, ent->driver_data);
1055}
1056
806c35f5
AC		 1057static void __devexit e752x_remove_one(struct pci_dev *pdev)
1058{
1059 struct mem_ctl_info *mci;
1060 struct e752x_pvt *pvt;
1061
537fba28 1062 debugf0("%s()\n", __func__);
806c35f5 1063
37f04581 1064 if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
806c35f5
AC		 1065 return;
1066
1067 pvt = (struct e752x_pvt *) mci->pvt_info;
1068 pci_dev_put(pvt->dev_d0f0);
1069 pci_dev_put(pvt->dev_d0f1);
1070 pci_dev_put(pvt->bridge_ck);
1071 edac_mc_free(mci);
1072}
1073
806c35f5 1074static const struct pci_device_id e752x_pci_tbl[] __devinitdata = {
e7ecd891
DP		 1075 {
1076 PCI_VEND_DEV(INTEL, 7520_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1077 E7520
1078 },
1079 {
1080 PCI_VEND_DEV(INTEL, 7525_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1081 E7525
1082 },
1083 {
1084 PCI_VEND_DEV(INTEL, 7320_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1085 E7320
1086 },
1087 {
1088 0,
1089 } /* 0 terminated list. */
806c35f5
AC		 1090};
1091
1092MODULE_DEVICE_TABLE(pci, e752x_pci_tbl);
1093
806c35f5 1094static struct pci_driver e752x_driver = {
680cbbbb 1095 .name = EDAC_MOD_STR,
0d38b049
RD		 1096 .probe = e752x_init_one,
1097 .remove = __devexit_p(e752x_remove_one),
1098 .id_table = e752x_pci_tbl,
806c35f5
AC		 1099};
1100
da9bb1d2 1101static int __init e752x_init(void)
806c35f5
AC		 1102{
1103 int pci_rc;
1104
537fba28 1105 debugf3("%s()\n", __func__);
806c35f5
AC		 1106 pci_rc = pci_register_driver(&e752x_driver);
1107 return (pci_rc < 0) ? pci_rc : 0;
1108}
1109
806c35f5
AC		 1110static void __exit e752x_exit(void)
1111{
537fba28 1112 debugf3("%s()\n", __func__);
806c35f5
AC		 1113 pci_unregister_driver(&e752x_driver);
1114}
1115
806c35f5
AC		 1116module_init(e752x_init);
1117module_exit(e752x_exit);
1118
1119MODULE_LICENSE("GPL");
1120MODULE_AUTHOR("Linux Networx (http://lnxi.com) Tom Zimmerman\n");
1121MODULE_DESCRIPTION("MC support for Intel e752x memory controllers");
96941026 1122
1123module_param(force_function_unhide, int, 0444);
1124MODULE_PARM_DESC(force_function_unhide, "if BIOS sets Dev0:Fun1 up as hidden:"
1125" 1=force unhide and hope BIOS doesn't fight driver for Dev0:Fun1 access");
1126
Linux kernel - Deliverables
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