Commit | Line | Data |
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806c35f5 AC |
1 | /* |
2 | * Intel e752x Memory Controller kernel module | |
3 | * (C) 2004 Linux Networx (http://lnxi.com) | |
4 | * This file may be distributed under the terms of the | |
5 | * GNU General Public License. | |
6 | * | |
7 | * See "enum e752x_chips" below for supported chipsets | |
8 | * | |
9 | * Written by Tom Zimmerman | |
10 | * | |
11 | * Contributors: | |
12 | * Thayne Harbaugh at realmsys.com (?) | |
13 | * Wang Zhenyu at intel.com | |
14 | * Dave Jiang at mvista.com | |
15 | * | |
da9bb1d2 | 16 | * $Id: edac_e752x.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $ |
806c35f5 AC |
17 | * |
18 | */ | |
19 | ||
806c35f5 AC |
20 | #include <linux/module.h> |
21 | #include <linux/init.h> | |
806c35f5 AC |
22 | #include <linux/pci.h> |
23 | #include <linux/pci_ids.h> | |
806c35f5 | 24 | #include <linux/slab.h> |
c0d12172 | 25 | #include <linux/edac.h> |
20bcb7a8 | 26 | #include "edac_core.h" |
806c35f5 | 27 | |
20bcb7a8 | 28 | #define E752X_REVISION " Ver: 2.0.2 " __DATE__ |
929a40ec | 29 | #define EDAC_MOD_STR "e752x_edac" |
37f04581 | 30 | |
10d33e9c | 31 | static int report_non_memory_errors; |
96941026 | 32 | static int force_function_unhide; |
94ee1cf5 | 33 | static int sysbus_parity = -1; |
96941026 | 34 | |
91b99041 DJ |
35 | static struct edac_pci_ctl_info *e752x_pci; |
36 | ||
537fba28 | 37 | #define e752x_printk(level, fmt, arg...) \ |
e7ecd891 | 38 | edac_printk(level, "e752x", fmt, ##arg) |
537fba28 DP |
39 | |
40 | #define e752x_mc_printk(mci, level, fmt, arg...) \ | |
e7ecd891 | 41 | edac_mc_chipset_printk(mci, level, "e752x", fmt, ##arg) |
537fba28 | 42 | |
806c35f5 AC |
43 | #ifndef PCI_DEVICE_ID_INTEL_7520_0 |
44 | #define PCI_DEVICE_ID_INTEL_7520_0 0x3590 | |
45 | #endif /* PCI_DEVICE_ID_INTEL_7520_0 */ | |
46 | ||
47 | #ifndef PCI_DEVICE_ID_INTEL_7520_1_ERR | |
48 | #define PCI_DEVICE_ID_INTEL_7520_1_ERR 0x3591 | |
49 | #endif /* PCI_DEVICE_ID_INTEL_7520_1_ERR */ | |
50 | ||
51 | #ifndef PCI_DEVICE_ID_INTEL_7525_0 | |
52 | #define PCI_DEVICE_ID_INTEL_7525_0 0x359E | |
53 | #endif /* PCI_DEVICE_ID_INTEL_7525_0 */ | |
54 | ||
55 | #ifndef PCI_DEVICE_ID_INTEL_7525_1_ERR | |
56 | #define PCI_DEVICE_ID_INTEL_7525_1_ERR 0x3593 | |
57 | #endif /* PCI_DEVICE_ID_INTEL_7525_1_ERR */ | |
58 | ||
59 | #ifndef PCI_DEVICE_ID_INTEL_7320_0 | |
60 | #define PCI_DEVICE_ID_INTEL_7320_0 0x3592 | |
61 | #endif /* PCI_DEVICE_ID_INTEL_7320_0 */ | |
62 | ||
63 | #ifndef PCI_DEVICE_ID_INTEL_7320_1_ERR | |
64 | #define PCI_DEVICE_ID_INTEL_7320_1_ERR 0x3593 | |
65 | #endif /* PCI_DEVICE_ID_INTEL_7320_1_ERR */ | |
66 | ||
5135b797 AK |
67 | #ifndef PCI_DEVICE_ID_INTEL_3100_0 |
68 | #define PCI_DEVICE_ID_INTEL_3100_0 0x35B0 | |
69 | #endif /* PCI_DEVICE_ID_INTEL_3100_0 */ | |
70 | ||
71 | #ifndef PCI_DEVICE_ID_INTEL_3100_1_ERR | |
72 | #define PCI_DEVICE_ID_INTEL_3100_1_ERR 0x35B1 | |
73 | #endif /* PCI_DEVICE_ID_INTEL_3100_1_ERR */ | |
74 | ||
806c35f5 AC |
75 | #define E752X_NR_CSROWS 8 /* number of csrows */ |
76 | ||
806c35f5 AC |
77 | /* E752X register addresses - device 0 function 0 */ |
78 | #define E752X_DRB 0x60 /* DRAM row boundary register (8b) */ | |
79 | #define E752X_DRA 0x70 /* DRAM row attribute register (8b) */ | |
80 | /* | |
81 | * 31:30 Device width row 7 | |
82 | * 01=x8 10=x4 11=x8 DDR2 | |
83 | * 27:26 Device width row 6 | |
84 | * 23:22 Device width row 5 | |
85 | * 19:20 Device width row 4 | |
86 | * 15:14 Device width row 3 | |
87 | * 11:10 Device width row 2 | |
88 | * 7:6 Device width row 1 | |
89 | * 3:2 Device width row 0 | |
90 | */ | |
91 | #define E752X_DRC 0x7C /* DRAM controller mode reg (32b) */ | |
92 | /* FIXME:IS THIS RIGHT? */ | |
93 | /* | |
94 | * 22 Number channels 0=1,1=2 | |
95 | * 19:18 DRB Granularity 32/64MB | |
96 | */ | |
97 | #define E752X_DRM 0x80 /* Dimm mapping register */ | |
98 | #define E752X_DDRCSR 0x9A /* DDR control and status reg (16b) */ | |
99 | /* | |
100 | * 14:12 1 single A, 2 single B, 3 dual | |
101 | */ | |
102 | #define E752X_TOLM 0xC4 /* DRAM top of low memory reg (16b) */ | |
103 | #define E752X_REMAPBASE 0xC6 /* DRAM remap base address reg (16b) */ | |
104 | #define E752X_REMAPLIMIT 0xC8 /* DRAM remap limit address reg (16b) */ | |
105 | #define E752X_REMAPOFFSET 0xCA /* DRAM remap limit offset reg (16b) */ | |
106 | ||
107 | /* E752X register addresses - device 0 function 1 */ | |
108 | #define E752X_FERR_GLOBAL 0x40 /* Global first error register (32b) */ | |
109 | #define E752X_NERR_GLOBAL 0x44 /* Global next error register (32b) */ | |
110 | #define E752X_HI_FERR 0x50 /* Hub interface first error reg (8b) */ | |
111 | #define E752X_HI_NERR 0x52 /* Hub interface next error reg (8b) */ | |
112 | #define E752X_HI_ERRMASK 0x54 /* Hub interface error mask reg (8b) */ | |
113 | #define E752X_HI_SMICMD 0x5A /* Hub interface SMI command reg (8b) */ | |
114 | #define E752X_SYSBUS_FERR 0x60 /* System buss first error reg (16b) */ | |
115 | #define E752X_SYSBUS_NERR 0x62 /* System buss next error reg (16b) */ | |
116 | #define E752X_SYSBUS_ERRMASK 0x64 /* System buss error mask reg (16b) */ | |
117 | #define E752X_SYSBUS_SMICMD 0x6A /* System buss SMI command reg (16b) */ | |
118 | #define E752X_BUF_FERR 0x70 /* Memory buffer first error reg (8b) */ | |
119 | #define E752X_BUF_NERR 0x72 /* Memory buffer next error reg (8b) */ | |
120 | #define E752X_BUF_ERRMASK 0x74 /* Memory buffer error mask reg (8b) */ | |
10d33e9c | 121 | #define E752X_BUF_SMICMD 0x7A /* Memory buffer SMI cmd reg (8b) */ |
806c35f5 AC |
122 | #define E752X_DRAM_FERR 0x80 /* DRAM first error register (16b) */ |
123 | #define E752X_DRAM_NERR 0x82 /* DRAM next error register (16b) */ | |
124 | #define E752X_DRAM_ERRMASK 0x84 /* DRAM error mask register (8b) */ | |
125 | #define E752X_DRAM_SMICMD 0x8A /* DRAM SMI command register (8b) */ | |
126 | #define E752X_DRAM_RETR_ADD 0xAC /* DRAM Retry address register (32b) */ | |
127 | #define E752X_DRAM_SEC1_ADD 0xA0 /* DRAM first correctable memory */ | |
128 | /* error address register (32b) */ | |
129 | /* | |
130 | * 31 Reserved | |
10d33e9c | 131 | * 30:2 CE address (64 byte block 34:6 |
806c35f5 AC |
132 | * 1 Reserved |
133 | * 0 HiLoCS | |
134 | */ | |
135 | #define E752X_DRAM_SEC2_ADD 0xC8 /* DRAM first correctable memory */ | |
136 | /* error address register (32b) */ | |
137 | /* | |
138 | * 31 Reserved | |
139 | * 30:2 CE address (64 byte block 34:6) | |
140 | * 1 Reserved | |
141 | * 0 HiLoCS | |
142 | */ | |
143 | #define E752X_DRAM_DED_ADD 0xA4 /* DRAM first uncorrectable memory */ | |
144 | /* error address register (32b) */ | |
145 | /* | |
146 | * 31 Reserved | |
147 | * 30:2 CE address (64 byte block 34:6) | |
148 | * 1 Reserved | |
149 | * 0 HiLoCS | |
150 | */ | |
10d33e9c | 151 | #define E752X_DRAM_SCRB_ADD 0xA8 /* DRAM 1st uncorrectable scrub mem */ |
806c35f5 AC |
152 | /* error address register (32b) */ |
153 | /* | |
154 | * 31 Reserved | |
10d33e9c | 155 | * 30:2 CE address (64 byte block 34:6 |
806c35f5 AC |
156 | * 1 Reserved |
157 | * 0 HiLoCS | |
158 | */ | |
159 | #define E752X_DRAM_SEC1_SYNDROME 0xC4 /* DRAM first correctable memory */ | |
160 | /* error syndrome register (16b) */ | |
161 | #define E752X_DRAM_SEC2_SYNDROME 0xC6 /* DRAM second correctable memory */ | |
162 | /* error syndrome register (16b) */ | |
163 | #define E752X_DEVPRES1 0xF4 /* Device Present 1 register (8b) */ | |
164 | ||
5135b797 AK |
165 | /* 3100 IMCH specific register addresses - device 0 function 1 */ |
166 | #define I3100_NSI_FERR 0x48 /* NSI first error reg (32b) */ | |
167 | #define I3100_NSI_NERR 0x4C /* NSI next error reg (32b) */ | |
168 | #define I3100_NSI_SMICMD 0x54 /* NSI SMI command register (32b) */ | |
169 | #define I3100_NSI_EMASK 0x90 /* NSI error mask register (32b) */ | |
170 | ||
806c35f5 AC |
171 | /* ICH5R register addresses - device 30 function 0 */ |
172 | #define ICH5R_PCI_STAT 0x06 /* PCI status register (16b) */ | |
173 | #define ICH5R_PCI_2ND_STAT 0x1E /* PCI status secondary reg (16b) */ | |
174 | #define ICH5R_PCI_BRIDGE_CTL 0x3E /* PCI bridge control register (16b) */ | |
175 | ||
176 | enum e752x_chips { | |
177 | E7520 = 0, | |
178 | E7525 = 1, | |
5135b797 AK |
179 | E7320 = 2, |
180 | I3100 = 3 | |
806c35f5 AC |
181 | }; |
182 | ||
806c35f5 AC |
183 | struct e752x_pvt { |
184 | struct pci_dev *bridge_ck; | |
185 | struct pci_dev *dev_d0f0; | |
186 | struct pci_dev *dev_d0f1; | |
187 | u32 tolm; | |
188 | u32 remapbase; | |
189 | u32 remaplimit; | |
190 | int mc_symmetric; | |
191 | u8 map[8]; | |
192 | int map_type; | |
193 | const struct e752x_dev_info *dev_info; | |
194 | }; | |
195 | ||
806c35f5 AC |
196 | struct e752x_dev_info { |
197 | u16 err_dev; | |
3847bccc | 198 | u16 ctl_dev; |
806c35f5 AC |
199 | const char *ctl_name; |
200 | }; | |
201 | ||
202 | struct e752x_error_info { | |
203 | u32 ferr_global; | |
204 | u32 nerr_global; | |
5135b797 AK |
205 | u32 nsi_ferr; /* 3100 only */ |
206 | u32 nsi_nerr; /* 3100 only */ | |
207 | u8 hi_ferr; /* all but 3100 */ | |
208 | u8 hi_nerr; /* all but 3100 */ | |
806c35f5 AC |
209 | u16 sysbus_ferr; |
210 | u16 sysbus_nerr; | |
211 | u8 buf_ferr; | |
212 | u8 buf_nerr; | |
213 | u16 dram_ferr; | |
214 | u16 dram_nerr; | |
215 | u32 dram_sec1_add; | |
216 | u32 dram_sec2_add; | |
217 | u16 dram_sec1_syndrome; | |
218 | u16 dram_sec2_syndrome; | |
219 | u32 dram_ded_add; | |
220 | u32 dram_scrb_add; | |
221 | u32 dram_retr_add; | |
222 | }; | |
223 | ||
224 | static const struct e752x_dev_info e752x_devs[] = { | |
225 | [E7520] = { | |
052dfb45 DT |
226 | .err_dev = PCI_DEVICE_ID_INTEL_7520_1_ERR, |
227 | .ctl_dev = PCI_DEVICE_ID_INTEL_7520_0, | |
228 | .ctl_name = "E7520"}, | |
806c35f5 | 229 | [E7525] = { |
052dfb45 DT |
230 | .err_dev = PCI_DEVICE_ID_INTEL_7525_1_ERR, |
231 | .ctl_dev = PCI_DEVICE_ID_INTEL_7525_0, | |
232 | .ctl_name = "E7525"}, | |
806c35f5 | 233 | [E7320] = { |
052dfb45 DT |
234 | .err_dev = PCI_DEVICE_ID_INTEL_7320_1_ERR, |
235 | .ctl_dev = PCI_DEVICE_ID_INTEL_7320_0, | |
236 | .ctl_name = "E7320"}, | |
5135b797 AK |
237 | [I3100] = { |
238 | .err_dev = PCI_DEVICE_ID_INTEL_3100_1_ERR, | |
239 | .ctl_dev = PCI_DEVICE_ID_INTEL_3100_0, | |
240 | .ctl_name = "3100"}, | |
806c35f5 AC |
241 | }; |
242 | ||
806c35f5 | 243 | static unsigned long ctl_page_to_phys(struct mem_ctl_info *mci, |
052dfb45 | 244 | unsigned long page) |
806c35f5 AC |
245 | { |
246 | u32 remap; | |
203333cb | 247 | struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info; |
806c35f5 | 248 | |
537fba28 | 249 | debugf3("%s()\n", __func__); |
806c35f5 AC |
250 | |
251 | if (page < pvt->tolm) | |
252 | return page; | |
e7ecd891 | 253 | |
806c35f5 AC |
254 | if ((page >= 0x100000) && (page < pvt->remapbase)) |
255 | return page; | |
e7ecd891 | 256 | |
806c35f5 | 257 | remap = (page - pvt->tolm) + pvt->remapbase; |
e7ecd891 | 258 | |
806c35f5 AC |
259 | if (remap < pvt->remaplimit) |
260 | return remap; | |
e7ecd891 | 261 | |
537fba28 | 262 | e752x_printk(KERN_ERR, "Invalid page %lx - out of range\n", page); |
806c35f5 AC |
263 | return pvt->tolm - 1; |
264 | } | |
265 | ||
266 | static void do_process_ce(struct mem_ctl_info *mci, u16 error_one, | |
052dfb45 | 267 | u32 sec1_add, u16 sec1_syndrome) |
806c35f5 AC |
268 | { |
269 | u32 page; | |
270 | int row; | |
271 | int channel; | |
272 | int i; | |
203333cb | 273 | struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info; |
806c35f5 | 274 | |
537fba28 | 275 | debugf3("%s()\n", __func__); |
806c35f5 AC |
276 | |
277 | /* convert the addr to 4k page */ | |
278 | page = sec1_add >> (PAGE_SHIFT - 4); | |
279 | ||
280 | /* FIXME - check for -1 */ | |
281 | if (pvt->mc_symmetric) { | |
282 | /* chip select are bits 14 & 13 */ | |
283 | row = ((page >> 1) & 3); | |
537fba28 | 284 | e752x_printk(KERN_WARNING, |
052dfb45 DT |
285 | "Test row %d Table %d %d %d %d %d %d %d %d\n", row, |
286 | pvt->map[0], pvt->map[1], pvt->map[2], pvt->map[3], | |
287 | pvt->map[4], pvt->map[5], pvt->map[6], | |
288 | pvt->map[7]); | |
806c35f5 AC |
289 | |
290 | /* test for channel remapping */ | |
291 | for (i = 0; i < 8; i++) { | |
292 | if (pvt->map[i] == row) | |
293 | break; | |
294 | } | |
e7ecd891 | 295 | |
537fba28 | 296 | e752x_printk(KERN_WARNING, "Test computed row %d\n", i); |
e7ecd891 | 297 | |
806c35f5 AC |
298 | if (i < 8) |
299 | row = i; | |
300 | else | |
537fba28 | 301 | e752x_mc_printk(mci, KERN_WARNING, |
203333cb DJ |
302 | "row %d not found in remap table\n", |
303 | row); | |
806c35f5 AC |
304 | } else |
305 | row = edac_mc_find_csrow_by_page(mci, page); | |
e7ecd891 | 306 | |
806c35f5 AC |
307 | /* 0 = channel A, 1 = channel B */ |
308 | channel = !(error_one & 1); | |
309 | ||
84db003f MC |
310 | /* e752x mc reads 34:6 of the DRAM linear address */ |
311 | edac_mc_handle_ce(mci, page, offset_in_page(sec1_add << 4), | |
052dfb45 | 312 | sec1_syndrome, row, channel, "e752x CE"); |
806c35f5 AC |
313 | } |
314 | ||
806c35f5 | 315 | static inline void process_ce(struct mem_ctl_info *mci, u16 error_one, |
052dfb45 DT |
316 | u32 sec1_add, u16 sec1_syndrome, int *error_found, |
317 | int handle_error) | |
806c35f5 AC |
318 | { |
319 | *error_found = 1; | |
320 | ||
321 | if (handle_error) | |
322 | do_process_ce(mci, error_one, sec1_add, sec1_syndrome); | |
323 | } | |
324 | ||
e7ecd891 | 325 | static void do_process_ue(struct mem_ctl_info *mci, u16 error_one, |
052dfb45 | 326 | u32 ded_add, u32 scrb_add) |
806c35f5 AC |
327 | { |
328 | u32 error_2b, block_page; | |
329 | int row; | |
203333cb | 330 | struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info; |
806c35f5 | 331 | |
537fba28 | 332 | debugf3("%s()\n", __func__); |
806c35f5 AC |
333 | |
334 | if (error_one & 0x0202) { | |
335 | error_2b = ded_add; | |
e7ecd891 | 336 | |
806c35f5 AC |
337 | /* convert to 4k address */ |
338 | block_page = error_2b >> (PAGE_SHIFT - 4); | |
e7ecd891 | 339 | |
806c35f5 | 340 | row = pvt->mc_symmetric ? |
052dfb45 DT |
341 | /* chip select are bits 14 & 13 */ |
342 | ((block_page >> 1) & 3) : | |
343 | edac_mc_find_csrow_by_page(mci, block_page); | |
e7ecd891 | 344 | |
84db003f MC |
345 | /* e752x mc reads 34:6 of the DRAM linear address */ |
346 | edac_mc_handle_ue(mci, block_page, | |
052dfb45 DT |
347 | offset_in_page(error_2b << 4), |
348 | row, "e752x UE from Read"); | |
806c35f5 AC |
349 | } |
350 | if (error_one & 0x0404) { | |
351 | error_2b = scrb_add; | |
e7ecd891 | 352 | |
806c35f5 AC |
353 | /* convert to 4k address */ |
354 | block_page = error_2b >> (PAGE_SHIFT - 4); | |
e7ecd891 | 355 | |
806c35f5 | 356 | row = pvt->mc_symmetric ? |
052dfb45 DT |
357 | /* chip select are bits 14 & 13 */ |
358 | ((block_page >> 1) & 3) : | |
359 | edac_mc_find_csrow_by_page(mci, block_page); | |
e7ecd891 | 360 | |
84db003f MC |
361 | /* e752x mc reads 34:6 of the DRAM linear address */ |
362 | edac_mc_handle_ue(mci, block_page, | |
052dfb45 DT |
363 | offset_in_page(error_2b << 4), |
364 | row, "e752x UE from Scruber"); | |
806c35f5 AC |
365 | } |
366 | } | |
367 | ||
368 | static inline void process_ue(struct mem_ctl_info *mci, u16 error_one, | |
052dfb45 DT |
369 | u32 ded_add, u32 scrb_add, int *error_found, |
370 | int handle_error) | |
806c35f5 AC |
371 | { |
372 | *error_found = 1; | |
373 | ||
374 | if (handle_error) | |
375 | do_process_ue(mci, error_one, ded_add, scrb_add); | |
376 | } | |
377 | ||
378 | static inline void process_ue_no_info_wr(struct mem_ctl_info *mci, | |
203333cb | 379 | int *error_found, int handle_error) |
806c35f5 AC |
380 | { |
381 | *error_found = 1; | |
382 | ||
383 | if (!handle_error) | |
384 | return; | |
385 | ||
537fba28 | 386 | debugf3("%s()\n", __func__); |
806c35f5 AC |
387 | edac_mc_handle_ue_no_info(mci, "e752x UE log memory write"); |
388 | } | |
389 | ||
390 | static void do_process_ded_retry(struct mem_ctl_info *mci, u16 error, | |
203333cb | 391 | u32 retry_add) |
806c35f5 AC |
392 | { |
393 | u32 error_1b, page; | |
394 | int row; | |
203333cb | 395 | struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info; |
806c35f5 AC |
396 | |
397 | error_1b = retry_add; | |
10d33e9c DT |
398 | page = error_1b >> (PAGE_SHIFT - 4); /* convert the addr to 4k page */ |
399 | ||
400 | /* chip select are bits 14 & 13 */ | |
401 | row = pvt->mc_symmetric ? ((page >> 1) & 3) : | |
052dfb45 | 402 | edac_mc_find_csrow_by_page(mci, page); |
10d33e9c | 403 | |
537fba28 | 404 | e752x_mc_printk(mci, KERN_WARNING, |
203333cb DJ |
405 | "CE page 0x%lx, row %d : Memory read retry\n", |
406 | (long unsigned int)page, row); | |
806c35f5 AC |
407 | } |
408 | ||
409 | static inline void process_ded_retry(struct mem_ctl_info *mci, u16 error, | |
052dfb45 DT |
410 | u32 retry_add, int *error_found, |
411 | int handle_error) | |
806c35f5 AC |
412 | { |
413 | *error_found = 1; | |
414 | ||
415 | if (handle_error) | |
416 | do_process_ded_retry(mci, error, retry_add); | |
417 | } | |
418 | ||
419 | static inline void process_threshold_ce(struct mem_ctl_info *mci, u16 error, | |
203333cb | 420 | int *error_found, int handle_error) |
806c35f5 AC |
421 | { |
422 | *error_found = 1; | |
423 | ||
424 | if (handle_error) | |
537fba28 | 425 | e752x_mc_printk(mci, KERN_WARNING, "Memory threshold CE\n"); |
806c35f5 AC |
426 | } |
427 | ||
da9bb1d2 | 428 | static char *global_message[11] = { |
10d33e9c DT |
429 | "PCI Express C1", |
430 | "PCI Express C", | |
431 | "PCI Express B1", | |
432 | "PCI Express B", | |
433 | "PCI Express A1", | |
434 | "PCI Express A", | |
435 | "DMA Controller", | |
436 | "HUB or NS Interface", | |
437 | "System Bus", | |
438 | "DRAM Controller", /* 9th entry */ | |
439 | "Internal Buffer" | |
806c35f5 AC |
440 | }; |
441 | ||
10d33e9c DT |
442 | #define DRAM_ENTRY 9 |
443 | ||
da9bb1d2 | 444 | static char *fatal_message[2] = { "Non-Fatal ", "Fatal " }; |
806c35f5 AC |
445 | |
446 | static void do_global_error(int fatal, u32 errors) | |
447 | { | |
448 | int i; | |
449 | ||
450 | for (i = 0; i < 11; i++) { | |
10d33e9c DT |
451 | if (errors & (1 << i)) { |
452 | /* If the error is from DRAM Controller OR | |
453 | * we are to report ALL errors, then | |
454 | * report the error | |
455 | */ | |
456 | if ((i == DRAM_ENTRY) || report_non_memory_errors) | |
457 | e752x_printk(KERN_WARNING, "%sError %s\n", | |
458 | fatal_message[fatal], | |
459 | global_message[i]); | |
460 | } | |
806c35f5 AC |
461 | } |
462 | } | |
463 | ||
464 | static inline void global_error(int fatal, u32 errors, int *error_found, | |
203333cb | 465 | int handle_error) |
806c35f5 AC |
466 | { |
467 | *error_found = 1; | |
468 | ||
469 | if (handle_error) | |
470 | do_global_error(fatal, errors); | |
471 | } | |
472 | ||
da9bb1d2 | 473 | static char *hub_message[7] = { |
806c35f5 AC |
474 | "HI Address or Command Parity", "HI Illegal Access", |
475 | "HI Internal Parity", "Out of Range Access", | |
476 | "HI Data Parity", "Enhanced Config Access", | |
477 | "Hub Interface Target Abort" | |
478 | }; | |
479 | ||
480 | static void do_hub_error(int fatal, u8 errors) | |
481 | { | |
482 | int i; | |
483 | ||
484 | for (i = 0; i < 7; i++) { | |
485 | if (errors & (1 << i)) | |
537fba28 | 486 | e752x_printk(KERN_WARNING, "%sError %s\n", |
052dfb45 | 487 | fatal_message[fatal], hub_message[i]); |
806c35f5 AC |
488 | } |
489 | } | |
490 | ||
491 | static inline void hub_error(int fatal, u8 errors, int *error_found, | |
052dfb45 | 492 | int handle_error) |
806c35f5 AC |
493 | { |
494 | *error_found = 1; | |
495 | ||
496 | if (handle_error) | |
497 | do_hub_error(fatal, errors); | |
498 | } | |
499 | ||
5135b797 AK |
500 | #define NSI_FATAL_MASK 0x0c080081 |
501 | #define NSI_NON_FATAL_MASK 0x23a0ba64 | |
502 | #define NSI_ERR_MASK (NSI_FATAL_MASK | NSI_NON_FATAL_MASK) | |
503 | ||
504 | static char *nsi_message[30] = { | |
505 | "NSI Link Down", /* NSI_FERR/NSI_NERR bit 0, fatal error */ | |
506 | "", /* reserved */ | |
507 | "NSI Parity Error", /* bit 2, non-fatal */ | |
508 | "", /* reserved */ | |
509 | "", /* reserved */ | |
510 | "Correctable Error Message", /* bit 5, non-fatal */ | |
511 | "Non-Fatal Error Message", /* bit 6, non-fatal */ | |
512 | "Fatal Error Message", /* bit 7, fatal */ | |
513 | "", /* reserved */ | |
514 | "Receiver Error", /* bit 9, non-fatal */ | |
515 | "", /* reserved */ | |
516 | "Bad TLP", /* bit 11, non-fatal */ | |
517 | "Bad DLLP", /* bit 12, non-fatal */ | |
518 | "REPLAY_NUM Rollover", /* bit 13, non-fatal */ | |
519 | "", /* reserved */ | |
520 | "Replay Timer Timeout", /* bit 15, non-fatal */ | |
521 | "", /* reserved */ | |
522 | "", /* reserved */ | |
523 | "", /* reserved */ | |
524 | "Data Link Protocol Error", /* bit 19, fatal */ | |
525 | "", /* reserved */ | |
526 | "Poisoned TLP", /* bit 21, non-fatal */ | |
527 | "", /* reserved */ | |
528 | "Completion Timeout", /* bit 23, non-fatal */ | |
529 | "Completer Abort", /* bit 24, non-fatal */ | |
530 | "Unexpected Completion", /* bit 25, non-fatal */ | |
531 | "Receiver Overflow", /* bit 26, fatal */ | |
532 | "Malformed TLP", /* bit 27, fatal */ | |
533 | "", /* reserved */ | |
534 | "Unsupported Request" /* bit 29, non-fatal */ | |
535 | }; | |
536 | ||
537 | static void do_nsi_error(int fatal, u32 errors) | |
538 | { | |
539 | int i; | |
540 | ||
541 | for (i = 0; i < 30; i++) { | |
542 | if (errors & (1 << i)) | |
543 | printk(KERN_WARNING "%sError %s\n", | |
544 | fatal_message[fatal], nsi_message[i]); | |
545 | } | |
546 | } | |
547 | ||
548 | static inline void nsi_error(int fatal, u32 errors, int *error_found, | |
549 | int handle_error) | |
550 | { | |
551 | *error_found = 1; | |
552 | ||
553 | if (handle_error) | |
554 | do_nsi_error(fatal, errors); | |
555 | } | |
556 | ||
da9bb1d2 | 557 | static char *membuf_message[4] = { |
806c35f5 AC |
558 | "Internal PMWB to DRAM parity", |
559 | "Internal PMWB to System Bus Parity", | |
560 | "Internal System Bus or IO to PMWB Parity", | |
561 | "Internal DRAM to PMWB Parity" | |
562 | }; | |
563 | ||
564 | static void do_membuf_error(u8 errors) | |
565 | { | |
566 | int i; | |
567 | ||
568 | for (i = 0; i < 4; i++) { | |
569 | if (errors & (1 << i)) | |
537fba28 | 570 | e752x_printk(KERN_WARNING, "Non-Fatal Error %s\n", |
052dfb45 | 571 | membuf_message[i]); |
806c35f5 AC |
572 | } |
573 | } | |
574 | ||
575 | static inline void membuf_error(u8 errors, int *error_found, int handle_error) | |
576 | { | |
577 | *error_found = 1; | |
578 | ||
579 | if (handle_error) | |
580 | do_membuf_error(errors); | |
581 | } | |
582 | ||
e009356f | 583 | static char *sysbus_message[10] = { |
806c35f5 AC |
584 | "Addr or Request Parity", |
585 | "Data Strobe Glitch", | |
586 | "Addr Strobe Glitch", | |
587 | "Data Parity", | |
588 | "Addr Above TOM", | |
589 | "Non DRAM Lock Error", | |
590 | "MCERR", "BINIT", | |
591 | "Memory Parity", | |
592 | "IO Subsystem Parity" | |
593 | }; | |
594 | ||
595 | static void do_sysbus_error(int fatal, u32 errors) | |
596 | { | |
597 | int i; | |
598 | ||
599 | for (i = 0; i < 10; i++) { | |
600 | if (errors & (1 << i)) | |
537fba28 | 601 | e752x_printk(KERN_WARNING, "%sError System Bus %s\n", |
052dfb45 | 602 | fatal_message[fatal], sysbus_message[i]); |
806c35f5 AC |
603 | } |
604 | } | |
605 | ||
606 | static inline void sysbus_error(int fatal, u32 errors, int *error_found, | |
203333cb | 607 | int handle_error) |
806c35f5 AC |
608 | { |
609 | *error_found = 1; | |
610 | ||
611 | if (handle_error) | |
612 | do_sysbus_error(fatal, errors); | |
613 | } | |
614 | ||
e7ecd891 | 615 | static void e752x_check_hub_interface(struct e752x_error_info *info, |
052dfb45 | 616 | int *error_found, int handle_error) |
806c35f5 AC |
617 | { |
618 | u8 stat8; | |
619 | ||
620 | //pci_read_config_byte(dev,E752X_HI_FERR,&stat8); | |
e7ecd891 | 621 | |
806c35f5 | 622 | stat8 = info->hi_ferr; |
e7ecd891 | 623 | |
203333cb | 624 | if (stat8 & 0x7f) { /* Error, so process */ |
806c35f5 | 625 | stat8 &= 0x7f; |
e7ecd891 | 626 | |
203333cb | 627 | if (stat8 & 0x2b) |
806c35f5 | 628 | hub_error(1, stat8 & 0x2b, error_found, handle_error); |
e7ecd891 | 629 | |
203333cb | 630 | if (stat8 & 0x54) |
806c35f5 AC |
631 | hub_error(0, stat8 & 0x54, error_found, handle_error); |
632 | } | |
633 | //pci_read_config_byte(dev,E752X_HI_NERR,&stat8); | |
e7ecd891 | 634 | |
806c35f5 | 635 | stat8 = info->hi_nerr; |
e7ecd891 | 636 | |
203333cb | 637 | if (stat8 & 0x7f) { /* Error, so process */ |
806c35f5 | 638 | stat8 &= 0x7f; |
e7ecd891 | 639 | |
806c35f5 AC |
640 | if (stat8 & 0x2b) |
641 | hub_error(1, stat8 & 0x2b, error_found, handle_error); | |
e7ecd891 | 642 | |
203333cb | 643 | if (stat8 & 0x54) |
806c35f5 AC |
644 | hub_error(0, stat8 & 0x54, error_found, handle_error); |
645 | } | |
646 | } | |
647 | ||
5135b797 AK |
648 | static void e752x_check_ns_interface(struct e752x_error_info *info, |
649 | int *error_found, int handle_error) | |
650 | { | |
651 | u32 stat32; | |
652 | ||
653 | stat32 = info->nsi_ferr; | |
654 | if (stat32 & NSI_ERR_MASK) { /* Error, so process */ | |
655 | if (stat32 & NSI_FATAL_MASK) /* check for fatal errors */ | |
656 | nsi_error(1, stat32 & NSI_FATAL_MASK, error_found, | |
657 | handle_error); | |
658 | if (stat32 & NSI_NON_FATAL_MASK) /* check for non-fatal ones */ | |
659 | nsi_error(0, stat32 & NSI_NON_FATAL_MASK, error_found, | |
660 | handle_error); | |
661 | } | |
662 | stat32 = info->nsi_nerr; | |
663 | if (stat32 & NSI_ERR_MASK) { | |
664 | if (stat32 & NSI_FATAL_MASK) | |
665 | nsi_error(1, stat32 & NSI_FATAL_MASK, error_found, | |
666 | handle_error); | |
667 | if (stat32 & NSI_NON_FATAL_MASK) | |
668 | nsi_error(0, stat32 & NSI_NON_FATAL_MASK, error_found, | |
669 | handle_error); | |
670 | } | |
671 | } | |
672 | ||
e7ecd891 | 673 | static void e752x_check_sysbus(struct e752x_error_info *info, |
052dfb45 | 674 | int *error_found, int handle_error) |
806c35f5 AC |
675 | { |
676 | u32 stat32, error32; | |
677 | ||
678 | //pci_read_config_dword(dev,E752X_SYSBUS_FERR,&stat32); | |
679 | stat32 = info->sysbus_ferr + (info->sysbus_nerr << 16); | |
680 | ||
681 | if (stat32 == 0) | |
203333cb | 682 | return; /* no errors */ |
806c35f5 AC |
683 | |
684 | error32 = (stat32 >> 16) & 0x3ff; | |
685 | stat32 = stat32 & 0x3ff; | |
e7ecd891 | 686 | |
203333cb | 687 | if (stat32 & 0x087) |
dfb2a763 | 688 | sysbus_error(1, stat32 & 0x087, error_found, handle_error); |
e7ecd891 | 689 | |
203333cb | 690 | if (stat32 & 0x378) |
dfb2a763 | 691 | sysbus_error(0, stat32 & 0x378, error_found, handle_error); |
e7ecd891 | 692 | |
203333cb | 693 | if (error32 & 0x087) |
dfb2a763 | 694 | sysbus_error(1, error32 & 0x087, error_found, handle_error); |
e7ecd891 | 695 | |
203333cb | 696 | if (error32 & 0x378) |
dfb2a763 | 697 | sysbus_error(0, error32 & 0x378, error_found, handle_error); |
806c35f5 AC |
698 | } |
699 | ||
203333cb | 700 | static void e752x_check_membuf(struct e752x_error_info *info, |
052dfb45 | 701 | int *error_found, int handle_error) |
806c35f5 AC |
702 | { |
703 | u8 stat8; | |
704 | ||
705 | stat8 = info->buf_ferr; | |
e7ecd891 | 706 | |
203333cb | 707 | if (stat8 & 0x0f) { /* Error, so process */ |
806c35f5 AC |
708 | stat8 &= 0x0f; |
709 | membuf_error(stat8, error_found, handle_error); | |
710 | } | |
e7ecd891 | 711 | |
806c35f5 | 712 | stat8 = info->buf_nerr; |
e7ecd891 | 713 | |
203333cb | 714 | if (stat8 & 0x0f) { /* Error, so process */ |
806c35f5 AC |
715 | stat8 &= 0x0f; |
716 | membuf_error(stat8, error_found, handle_error); | |
717 | } | |
718 | } | |
719 | ||
203333cb | 720 | static void e752x_check_dram(struct mem_ctl_info *mci, |
052dfb45 DT |
721 | struct e752x_error_info *info, int *error_found, |
722 | int handle_error) | |
806c35f5 AC |
723 | { |
724 | u16 error_one, error_next; | |
725 | ||
726 | error_one = info->dram_ferr; | |
727 | error_next = info->dram_nerr; | |
728 | ||
729 | /* decode and report errors */ | |
203333cb | 730 | if (error_one & 0x0101) /* check first error correctable */ |
806c35f5 | 731 | process_ce(mci, error_one, info->dram_sec1_add, |
052dfb45 | 732 | info->dram_sec1_syndrome, error_found, handle_error); |
806c35f5 | 733 | |
203333cb | 734 | if (error_next & 0x0101) /* check next error correctable */ |
806c35f5 | 735 | process_ce(mci, error_next, info->dram_sec2_add, |
052dfb45 | 736 | info->dram_sec2_syndrome, error_found, handle_error); |
806c35f5 | 737 | |
203333cb | 738 | if (error_one & 0x4040) |
806c35f5 AC |
739 | process_ue_no_info_wr(mci, error_found, handle_error); |
740 | ||
203333cb | 741 | if (error_next & 0x4040) |
806c35f5 AC |
742 | process_ue_no_info_wr(mci, error_found, handle_error); |
743 | ||
203333cb | 744 | if (error_one & 0x2020) |
806c35f5 | 745 | process_ded_retry(mci, error_one, info->dram_retr_add, |
052dfb45 | 746 | error_found, handle_error); |
806c35f5 | 747 | |
203333cb | 748 | if (error_next & 0x2020) |
806c35f5 | 749 | process_ded_retry(mci, error_next, info->dram_retr_add, |
052dfb45 | 750 | error_found, handle_error); |
806c35f5 | 751 | |
203333cb DJ |
752 | if (error_one & 0x0808) |
753 | process_threshold_ce(mci, error_one, error_found, handle_error); | |
806c35f5 | 754 | |
203333cb | 755 | if (error_next & 0x0808) |
806c35f5 | 756 | process_threshold_ce(mci, error_next, error_found, |
052dfb45 | 757 | handle_error); |
806c35f5 | 758 | |
203333cb | 759 | if (error_one & 0x0606) |
806c35f5 | 760 | process_ue(mci, error_one, info->dram_ded_add, |
052dfb45 | 761 | info->dram_scrb_add, error_found, handle_error); |
806c35f5 | 762 | |
203333cb | 763 | if (error_next & 0x0606) |
806c35f5 | 764 | process_ue(mci, error_next, info->dram_ded_add, |
052dfb45 | 765 | info->dram_scrb_add, error_found, handle_error); |
806c35f5 AC |
766 | } |
767 | ||
203333cb DJ |
768 | static void e752x_get_error_info(struct mem_ctl_info *mci, |
769 | struct e752x_error_info *info) | |
806c35f5 AC |
770 | { |
771 | struct pci_dev *dev; | |
772 | struct e752x_pvt *pvt; | |
773 | ||
774 | memset(info, 0, sizeof(*info)); | |
203333cb | 775 | pvt = (struct e752x_pvt *)mci->pvt_info; |
806c35f5 | 776 | dev = pvt->dev_d0f1; |
806c35f5 AC |
777 | pci_read_config_dword(dev, E752X_FERR_GLOBAL, &info->ferr_global); |
778 | ||
779 | if (info->ferr_global) { | |
5135b797 AK |
780 | if (pvt->dev_info->err_dev == PCI_DEVICE_ID_INTEL_3100_1_ERR) { |
781 | pci_read_config_dword(dev, I3100_NSI_FERR, | |
782 | &info->nsi_ferr); | |
783 | info->hi_ferr = 0; | |
784 | } else { | |
785 | pci_read_config_byte(dev, E752X_HI_FERR, | |
786 | &info->hi_ferr); | |
787 | info->nsi_ferr = 0; | |
788 | } | |
806c35f5 | 789 | pci_read_config_word(dev, E752X_SYSBUS_FERR, |
052dfb45 | 790 | &info->sysbus_ferr); |
806c35f5 | 791 | pci_read_config_byte(dev, E752X_BUF_FERR, &info->buf_ferr); |
203333cb | 792 | pci_read_config_word(dev, E752X_DRAM_FERR, &info->dram_ferr); |
806c35f5 | 793 | pci_read_config_dword(dev, E752X_DRAM_SEC1_ADD, |
052dfb45 | 794 | &info->dram_sec1_add); |
806c35f5 | 795 | pci_read_config_word(dev, E752X_DRAM_SEC1_SYNDROME, |
052dfb45 | 796 | &info->dram_sec1_syndrome); |
806c35f5 | 797 | pci_read_config_dword(dev, E752X_DRAM_DED_ADD, |
052dfb45 | 798 | &info->dram_ded_add); |
806c35f5 | 799 | pci_read_config_dword(dev, E752X_DRAM_SCRB_ADD, |
052dfb45 | 800 | &info->dram_scrb_add); |
806c35f5 | 801 | pci_read_config_dword(dev, E752X_DRAM_RETR_ADD, |
052dfb45 | 802 | &info->dram_retr_add); |
806c35f5 | 803 | |
5135b797 | 804 | /* ignore the reserved bits just in case */ |
806c35f5 AC |
805 | if (info->hi_ferr & 0x7f) |
806 | pci_write_config_byte(dev, E752X_HI_FERR, | |
052dfb45 | 807 | info->hi_ferr); |
806c35f5 | 808 | |
5135b797 AK |
809 | if (info->nsi_ferr & NSI_ERR_MASK) |
810 | pci_write_config_dword(dev, I3100_NSI_FERR, | |
811 | info->nsi_ferr); | |
812 | ||
806c35f5 AC |
813 | if (info->sysbus_ferr) |
814 | pci_write_config_word(dev, E752X_SYSBUS_FERR, | |
052dfb45 | 815 | info->sysbus_ferr); |
806c35f5 AC |
816 | |
817 | if (info->buf_ferr & 0x0f) | |
818 | pci_write_config_byte(dev, E752X_BUF_FERR, | |
052dfb45 | 819 | info->buf_ferr); |
806c35f5 AC |
820 | |
821 | if (info->dram_ferr) | |
822 | pci_write_bits16(pvt->bridge_ck, E752X_DRAM_FERR, | |
203333cb | 823 | info->dram_ferr, info->dram_ferr); |
806c35f5 AC |
824 | |
825 | pci_write_config_dword(dev, E752X_FERR_GLOBAL, | |
052dfb45 | 826 | info->ferr_global); |
806c35f5 AC |
827 | } |
828 | ||
829 | pci_read_config_dword(dev, E752X_NERR_GLOBAL, &info->nerr_global); | |
830 | ||
831 | if (info->nerr_global) { | |
5135b797 AK |
832 | if (pvt->dev_info->err_dev == PCI_DEVICE_ID_INTEL_3100_1_ERR) { |
833 | pci_read_config_dword(dev, I3100_NSI_NERR, | |
834 | &info->nsi_nerr); | |
835 | info->hi_nerr = 0; | |
836 | } else { | |
837 | pci_read_config_byte(dev, E752X_HI_NERR, | |
838 | &info->hi_nerr); | |
839 | info->nsi_nerr = 0; | |
840 | } | |
806c35f5 | 841 | pci_read_config_word(dev, E752X_SYSBUS_NERR, |
052dfb45 | 842 | &info->sysbus_nerr); |
806c35f5 | 843 | pci_read_config_byte(dev, E752X_BUF_NERR, &info->buf_nerr); |
203333cb | 844 | pci_read_config_word(dev, E752X_DRAM_NERR, &info->dram_nerr); |
806c35f5 | 845 | pci_read_config_dword(dev, E752X_DRAM_SEC2_ADD, |
052dfb45 | 846 | &info->dram_sec2_add); |
806c35f5 | 847 | pci_read_config_word(dev, E752X_DRAM_SEC2_SYNDROME, |
052dfb45 | 848 | &info->dram_sec2_syndrome); |
806c35f5 AC |
849 | |
850 | if (info->hi_nerr & 0x7f) | |
851 | pci_write_config_byte(dev, E752X_HI_NERR, | |
052dfb45 | 852 | info->hi_nerr); |
806c35f5 | 853 | |
5135b797 AK |
854 | if (info->nsi_nerr & NSI_ERR_MASK) |
855 | pci_write_config_dword(dev, I3100_NSI_NERR, | |
856 | info->nsi_nerr); | |
857 | ||
806c35f5 AC |
858 | if (info->sysbus_nerr) |
859 | pci_write_config_word(dev, E752X_SYSBUS_NERR, | |
052dfb45 | 860 | info->sysbus_nerr); |
806c35f5 AC |
861 | |
862 | if (info->buf_nerr & 0x0f) | |
863 | pci_write_config_byte(dev, E752X_BUF_NERR, | |
052dfb45 | 864 | info->buf_nerr); |
806c35f5 AC |
865 | |
866 | if (info->dram_nerr) | |
867 | pci_write_bits16(pvt->bridge_ck, E752X_DRAM_NERR, | |
203333cb | 868 | info->dram_nerr, info->dram_nerr); |
806c35f5 AC |
869 | |
870 | pci_write_config_dword(dev, E752X_NERR_GLOBAL, | |
052dfb45 | 871 | info->nerr_global); |
806c35f5 AC |
872 | } |
873 | } | |
874 | ||
203333cb | 875 | static int e752x_process_error_info(struct mem_ctl_info *mci, |
052dfb45 DT |
876 | struct e752x_error_info *info, |
877 | int handle_errors) | |
806c35f5 AC |
878 | { |
879 | u32 error32, stat32; | |
880 | int error_found; | |
881 | ||
882 | error_found = 0; | |
883 | error32 = (info->ferr_global >> 18) & 0x3ff; | |
884 | stat32 = (info->ferr_global >> 4) & 0x7ff; | |
885 | ||
886 | if (error32) | |
887 | global_error(1, error32, &error_found, handle_errors); | |
888 | ||
889 | if (stat32) | |
890 | global_error(0, stat32, &error_found, handle_errors); | |
891 | ||
892 | error32 = (info->nerr_global >> 18) & 0x3ff; | |
893 | stat32 = (info->nerr_global >> 4) & 0x7ff; | |
894 | ||
895 | if (error32) | |
896 | global_error(1, error32, &error_found, handle_errors); | |
897 | ||
898 | if (stat32) | |
899 | global_error(0, stat32, &error_found, handle_errors); | |
900 | ||
901 | e752x_check_hub_interface(info, &error_found, handle_errors); | |
5135b797 | 902 | e752x_check_ns_interface(info, &error_found, handle_errors); |
806c35f5 AC |
903 | e752x_check_sysbus(info, &error_found, handle_errors); |
904 | e752x_check_membuf(info, &error_found, handle_errors); | |
905 | e752x_check_dram(mci, info, &error_found, handle_errors); | |
906 | return error_found; | |
907 | } | |
908 | ||
909 | static void e752x_check(struct mem_ctl_info *mci) | |
910 | { | |
911 | struct e752x_error_info info; | |
e7ecd891 | 912 | |
537fba28 | 913 | debugf3("%s()\n", __func__); |
806c35f5 AC |
914 | e752x_get_error_info(mci, &info); |
915 | e752x_process_error_info(mci, &info, 1); | |
916 | } | |
917 | ||
13189525 DT |
918 | /* Return 1 if dual channel mode is active. Else return 0. */ |
919 | static inline int dual_channel_active(u16 ddrcsr) | |
920 | { | |
921 | return (((ddrcsr >> 12) & 3) == 3); | |
922 | } | |
923 | ||
7297c261 MG |
924 | /* Remap csrow index numbers if map_type is "reverse" |
925 | */ | |
926 | static inline int remap_csrow_index(struct mem_ctl_info *mci, int index) | |
927 | { | |
928 | struct e752x_pvt *pvt = mci->pvt_info; | |
929 | ||
930 | if (!pvt->map_type) | |
931 | return (7 - index); | |
932 | ||
933 | return (index); | |
934 | } | |
935 | ||
13189525 | 936 | static void e752x_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev, |
052dfb45 | 937 | u16 ddrcsr) |
13189525 DT |
938 | { |
939 | struct csrow_info *csrow; | |
940 | unsigned long last_cumul_size; | |
941 | int index, mem_dev, drc_chan; | |
203333cb DJ |
942 | int drc_drbg; /* DRB granularity 0=64mb, 1=128mb */ |
943 | int drc_ddim; /* DRAM Data Integrity Mode 0=none, 2=edac */ | |
13189525 DT |
944 | u8 value; |
945 | u32 dra, drc, cumul_size; | |
946 | ||
9962fd01 | 947 | dra = 0; |
203333cb | 948 | for (index = 0; index < 4; index++) { |
9962fd01 | 949 | u8 dra_reg; |
203333cb | 950 | pci_read_config_byte(pdev, E752X_DRA + index, &dra_reg); |
9962fd01 BP |
951 | dra |= dra_reg << (index * 8); |
952 | } | |
13189525 DT |
953 | pci_read_config_dword(pdev, E752X_DRC, &drc); |
954 | drc_chan = dual_channel_active(ddrcsr); | |
203333cb | 955 | drc_drbg = drc_chan + 1; /* 128 in dual mode, 64 in single */ |
13189525 DT |
956 | drc_ddim = (drc >> 20) & 0x3; |
957 | ||
958 | /* The dram row boundary (DRB) reg values are boundary address for | |
959 | * each DRAM row with a granularity of 64 or 128MB (single/dual | |
960 | * channel operation). DRB regs are cumulative; therefore DRB7 will | |
961 | * contain the total memory contained in all eight rows. | |
962 | */ | |
963 | for (last_cumul_size = index = 0; index < mci->nr_csrows; index++) { | |
964 | /* mem_dev 0=x8, 1=x4 */ | |
965 | mem_dev = (dra >> (index * 4 + 2)) & 0x3; | |
7297c261 | 966 | csrow = &mci->csrows[remap_csrow_index(mci, index)]; |
13189525 DT |
967 | |
968 | mem_dev = (mem_dev == 2); | |
969 | pci_read_config_byte(pdev, E752X_DRB + index, &value); | |
970 | /* convert a 128 or 64 MiB DRB to a page size. */ | |
971 | cumul_size = value << (25 + drc_drbg - PAGE_SHIFT); | |
972 | debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index, | |
973 | cumul_size); | |
974 | if (cumul_size == last_cumul_size) | |
975 | continue; /* not populated */ | |
976 | ||
977 | csrow->first_page = last_cumul_size; | |
978 | csrow->last_page = cumul_size - 1; | |
979 | csrow->nr_pages = cumul_size - last_cumul_size; | |
980 | last_cumul_size = cumul_size; | |
981 | csrow->grain = 1 << 12; /* 4KiB - resolution of CELOG */ | |
982 | csrow->mtype = MEM_RDDR; /* only one type supported */ | |
983 | csrow->dtype = mem_dev ? DEV_X4 : DEV_X8; | |
984 | ||
985 | /* | |
986 | * if single channel or x8 devices then SECDED | |
987 | * if dual channel and x4 then S4ECD4ED | |
988 | */ | |
989 | if (drc_ddim) { | |
990 | if (drc_chan && mem_dev) { | |
991 | csrow->edac_mode = EDAC_S4ECD4ED; | |
992 | mci->edac_cap |= EDAC_FLAG_S4ECD4ED; | |
993 | } else { | |
994 | csrow->edac_mode = EDAC_SECDED; | |
995 | mci->edac_cap |= EDAC_FLAG_SECDED; | |
996 | } | |
997 | } else | |
998 | csrow->edac_mode = EDAC_NONE; | |
999 | } | |
1000 | } | |
1001 | ||
1002 | static void e752x_init_mem_map_table(struct pci_dev *pdev, | |
052dfb45 | 1003 | struct e752x_pvt *pvt) |
806c35f5 | 1004 | { |
806c35f5 | 1005 | int index; |
7297c261 | 1006 | u8 value, last, row; |
13189525 DT |
1007 | |
1008 | last = 0; | |
1009 | row = 0; | |
1010 | ||
1011 | for (index = 0; index < 8; index += 2) { | |
1012 | pci_read_config_byte(pdev, E752X_DRB + index, &value); | |
1013 | /* test if there is a dimm in this slot */ | |
1014 | if (value == last) { | |
1015 | /* no dimm in the slot, so flag it as empty */ | |
1016 | pvt->map[index] = 0xff; | |
1017 | pvt->map[index + 1] = 0xff; | |
203333cb | 1018 | } else { /* there is a dimm in the slot */ |
13189525 DT |
1019 | pvt->map[index] = row; |
1020 | row++; | |
1021 | last = value; | |
1022 | /* test the next value to see if the dimm is double | |
1023 | * sided | |
1024 | */ | |
1025 | pci_read_config_byte(pdev, E752X_DRB + index + 1, | |
052dfb45 DT |
1026 | &value); |
1027 | ||
1028 | /* the dimm is single sided, so flag as empty */ | |
1029 | /* this is a double sided dimm to save the next row #*/ | |
1030 | pvt->map[index + 1] = (value == last) ? 0xff : row; | |
13189525 DT |
1031 | row++; |
1032 | last = value; | |
1033 | } | |
1034 | } | |
13189525 DT |
1035 | } |
1036 | ||
1037 | /* Return 0 on success or 1 on failure. */ | |
1038 | static int e752x_get_devs(struct pci_dev *pdev, int dev_idx, | |
052dfb45 | 1039 | struct e752x_pvt *pvt) |
13189525 DT |
1040 | { |
1041 | struct pci_dev *dev; | |
1042 | ||
1043 | pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL, | |
10d33e9c | 1044 | pvt->dev_info->err_dev, pvt->bridge_ck); |
13189525 DT |
1045 | |
1046 | if (pvt->bridge_ck == NULL) | |
1047 | pvt->bridge_ck = pci_scan_single_device(pdev->bus, | |
1048 | PCI_DEVFN(0, 1)); | |
1049 | ||
1050 | if (pvt->bridge_ck == NULL) { | |
1051 | e752x_printk(KERN_ERR, "error reporting device not found:" | |
052dfb45 DT |
1052 | "vendor %x device 0x%x (broken BIOS?)\n", |
1053 | PCI_VENDOR_ID_INTEL, e752x_devs[dev_idx].err_dev); | |
13189525 DT |
1054 | return 1; |
1055 | } | |
1056 | ||
10d33e9c DT |
1057 | dev = pci_get_device(PCI_VENDOR_ID_INTEL, |
1058 | e752x_devs[dev_idx].ctl_dev, | |
1059 | NULL); | |
13189525 DT |
1060 | |
1061 | if (dev == NULL) | |
1062 | goto fail; | |
1063 | ||
1064 | pvt->dev_d0f0 = dev; | |
1065 | pvt->dev_d0f1 = pci_dev_get(pvt->bridge_ck); | |
1066 | ||
1067 | return 0; | |
1068 | ||
052dfb45 | 1069 | fail: |
13189525 DT |
1070 | pci_dev_put(pvt->bridge_ck); |
1071 | return 1; | |
1072 | } | |
1073 | ||
94ee1cf5 PT |
1074 | /* Setup system bus parity mask register. |
1075 | * Sysbus parity supported on: | |
1076 | * e7320/e7520/e7525 + Xeon | |
1077 | * i3100 + Xeon/Celeron | |
1078 | * Sysbus parity not supported on: | |
1079 | * i3100 + Pentium M/Celeron M/Core Duo/Core2 Duo | |
1080 | */ | |
1081 | static void e752x_init_sysbus_parity_mask(struct e752x_pvt *pvt) | |
1082 | { | |
1083 | char *cpu_id = cpu_data(0).x86_model_id; | |
1084 | struct pci_dev *dev = pvt->dev_d0f1; | |
1085 | int enable = 1; | |
1086 | ||
98a1708d | 1087 | /* Allow module parameter override, else see if CPU supports parity */ |
94ee1cf5 PT |
1088 | if (sysbus_parity != -1) { |
1089 | enable = sysbus_parity; | |
1090 | } else if (cpu_id[0] && | |
1091 | ((strstr(cpu_id, "Pentium") && strstr(cpu_id, " M ")) || | |
1092 | (strstr(cpu_id, "Celeron") && strstr(cpu_id, " M ")) || | |
1093 | (strstr(cpu_id, "Core") && strstr(cpu_id, "Duo")))) { | |
1094 | e752x_printk(KERN_INFO, "System Bus Parity not " | |
1095 | "supported by CPU, disabling\n"); | |
1096 | enable = 0; | |
1097 | } | |
1098 | ||
1099 | if (enable) | |
1100 | pci_write_config_word(dev, E752X_SYSBUS_ERRMASK, 0x0000); | |
1101 | else | |
1102 | pci_write_config_word(dev, E752X_SYSBUS_ERRMASK, 0x0309); | |
1103 | } | |
1104 | ||
13189525 DT |
1105 | static void e752x_init_error_reporting_regs(struct e752x_pvt *pvt) |
1106 | { | |
1107 | struct pci_dev *dev; | |
1108 | ||
1109 | dev = pvt->dev_d0f1; | |
1110 | /* Turn off error disable & SMI in case the BIOS turned it on */ | |
5135b797 AK |
1111 | if (pvt->dev_info->err_dev == PCI_DEVICE_ID_INTEL_3100_1_ERR) { |
1112 | pci_write_config_dword(dev, I3100_NSI_EMASK, 0); | |
1113 | pci_write_config_dword(dev, I3100_NSI_SMICMD, 0); | |
1114 | } else { | |
1115 | pci_write_config_byte(dev, E752X_HI_ERRMASK, 0x00); | |
1116 | pci_write_config_byte(dev, E752X_HI_SMICMD, 0x00); | |
1117 | } | |
94ee1cf5 PT |
1118 | |
1119 | e752x_init_sysbus_parity_mask(pvt); | |
1120 | ||
13189525 DT |
1121 | pci_write_config_word(dev, E752X_SYSBUS_SMICMD, 0x00); |
1122 | pci_write_config_byte(dev, E752X_BUF_ERRMASK, 0x00); | |
1123 | pci_write_config_byte(dev, E752X_BUF_SMICMD, 0x00); | |
1124 | pci_write_config_byte(dev, E752X_DRAM_ERRMASK, 0x00); | |
1125 | pci_write_config_byte(dev, E752X_DRAM_SMICMD, 0x00); | |
1126 | } | |
1127 | ||
1128 | static int e752x_probe1(struct pci_dev *pdev, int dev_idx) | |
1129 | { | |
3847bccc | 1130 | u16 pci_data; |
806c35f5 | 1131 | u8 stat8; |
13189525 DT |
1132 | struct mem_ctl_info *mci; |
1133 | struct e752x_pvt *pvt; | |
806c35f5 | 1134 | u16 ddrcsr; |
203333cb | 1135 | int drc_chan; /* Number of channels 0=1chan,1=2chan */ |
749ede57 | 1136 | struct e752x_error_info discard; |
806c35f5 | 1137 | |
537fba28 | 1138 | debugf0("%s(): mci\n", __func__); |
806c35f5 AC |
1139 | debugf0("Starting Probe1\n"); |
1140 | ||
96941026 | 1141 | /* check to see if device 0 function 1 is enabled; if it isn't, we |
1142 | * assume the BIOS has reserved it for a reason and is expecting | |
1143 | * exclusive access, we take care not to violate that assumption and | |
1144 | * fail the probe. */ | |
806c35f5 | 1145 | pci_read_config_byte(pdev, E752X_DEVPRES1, &stat8); |
96941026 | 1146 | if (!force_function_unhide && !(stat8 & (1 << 5))) { |
1147 | printk(KERN_INFO "Contact your BIOS vendor to see if the " | |
052dfb45 | 1148 | "E752x error registers can be safely un-hidden\n"); |
f9b5a5d1 | 1149 | return -ENODEV; |
96941026 | 1150 | } |
806c35f5 AC |
1151 | stat8 |= (1 << 5); |
1152 | pci_write_config_byte(pdev, E752X_DEVPRES1, stat8); | |
1153 | ||
806c35f5 AC |
1154 | pci_read_config_word(pdev, E752X_DDRCSR, &ddrcsr); |
1155 | /* FIXME: should check >>12 or 0xf, true for all? */ | |
1156 | /* Dual channel = 1, Single channel = 0 */ | |
13189525 | 1157 | drc_chan = dual_channel_active(ddrcsr); |
806c35f5 | 1158 | |
b8f6f975 | 1159 | mci = edac_mc_alloc(sizeof(*pvt), E752X_NR_CSROWS, drc_chan + 1, 0); |
806c35f5 AC |
1160 | |
1161 | if (mci == NULL) { | |
13189525 | 1162 | return -ENOMEM; |
806c35f5 AC |
1163 | } |
1164 | ||
537fba28 | 1165 | debugf3("%s(): init mci\n", __func__); |
806c35f5 | 1166 | mci->mtype_cap = MEM_FLAG_RDDR; |
5135b797 AK |
1167 | /* 3100 IMCH supports SECDEC only */ |
1168 | mci->edac_ctl_cap = (dev_idx == I3100) ? EDAC_FLAG_SECDED : | |
1169 | (EDAC_FLAG_NONE | EDAC_FLAG_SECDED | EDAC_FLAG_S4ECD4ED); | |
806c35f5 | 1170 | /* FIXME - what if different memory types are in different csrows? */ |
680cbbbb | 1171 | mci->mod_name = EDAC_MOD_STR; |
37f04581 DT |
1172 | mci->mod_ver = E752X_REVISION; |
1173 | mci->dev = &pdev->dev; | |
806c35f5 | 1174 | |
537fba28 | 1175 | debugf3("%s(): init pvt\n", __func__); |
203333cb | 1176 | pvt = (struct e752x_pvt *)mci->pvt_info; |
806c35f5 | 1177 | pvt->dev_info = &e752x_devs[dev_idx]; |
13189525 | 1178 | pvt->mc_symmetric = ((ddrcsr & 0x10) != 0); |
e7ecd891 | 1179 | |
13189525 DT |
1180 | if (e752x_get_devs(pdev, dev_idx, pvt)) { |
1181 | edac_mc_free(mci); | |
1182 | return -ENODEV; | |
806c35f5 | 1183 | } |
806c35f5 | 1184 | |
537fba28 | 1185 | debugf3("%s(): more mci init\n", __func__); |
806c35f5 | 1186 | mci->ctl_name = pvt->dev_info->ctl_name; |
c4192705 | 1187 | mci->dev_name = pci_name(pdev); |
806c35f5 AC |
1188 | mci->edac_check = e752x_check; |
1189 | mci->ctl_page_to_phys = ctl_page_to_phys; | |
1190 | ||
7297c261 MG |
1191 | /* set the map type. 1 = normal, 0 = reversed |
1192 | * Must be set before e752x_init_csrows in case csrow mapping | |
1193 | * is reversed. | |
1194 | */ | |
37f04581 | 1195 | pci_read_config_byte(pdev, E752X_DRM, &stat8); |
806c35f5 AC |
1196 | pvt->map_type = ((stat8 & 0x0f) > ((stat8 >> 4) & 0x0f)); |
1197 | ||
7297c261 MG |
1198 | e752x_init_csrows(mci, pdev, ddrcsr); |
1199 | e752x_init_mem_map_table(pdev, pvt); | |
1200 | ||
5135b797 AK |
1201 | if (dev_idx == I3100) |
1202 | mci->edac_cap = EDAC_FLAG_SECDED; /* the only mode supported */ | |
1203 | else | |
1204 | mci->edac_cap |= EDAC_FLAG_NONE; | |
537fba28 | 1205 | debugf3("%s(): tolm, remapbase, remaplimit\n", __func__); |
e7ecd891 | 1206 | |
806c35f5 | 1207 | /* load the top of low memory, remap base, and remap limit vars */ |
37f04581 | 1208 | pci_read_config_word(pdev, E752X_TOLM, &pci_data); |
806c35f5 | 1209 | pvt->tolm = ((u32) pci_data) << 4; |
37f04581 | 1210 | pci_read_config_word(pdev, E752X_REMAPBASE, &pci_data); |
806c35f5 | 1211 | pvt->remapbase = ((u32) pci_data) << 14; |
37f04581 | 1212 | pci_read_config_word(pdev, E752X_REMAPLIMIT, &pci_data); |
806c35f5 | 1213 | pvt->remaplimit = ((u32) pci_data) << 14; |
537fba28 | 1214 | e752x_printk(KERN_INFO, |
052dfb45 DT |
1215 | "tolm = %x, remapbase = %x, remaplimit = %x\n", |
1216 | pvt->tolm, pvt->remapbase, pvt->remaplimit); | |
806c35f5 | 1217 | |
2d7bbb91 DT |
1218 | /* Here we assume that we will never see multiple instances of this |
1219 | * type of memory controller. The ID is therefore hardcoded to 0. | |
1220 | */ | |
b8f6f975 | 1221 | if (edac_mc_add_mc(mci)) { |
537fba28 | 1222 | debugf3("%s(): failed edac_mc_add_mc()\n", __func__); |
806c35f5 AC |
1223 | goto fail; |
1224 | } | |
1225 | ||
13189525 | 1226 | e752x_init_error_reporting_regs(pvt); |
203333cb | 1227 | e752x_get_error_info(mci, &discard); /* clear other MCH errors */ |
806c35f5 | 1228 | |
91b99041 DJ |
1229 | /* allocating generic PCI control info */ |
1230 | e752x_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR); | |
1231 | if (!e752x_pci) { | |
1232 | printk(KERN_WARNING | |
052dfb45 | 1233 | "%s(): Unable to create PCI control\n", __func__); |
91b99041 | 1234 | printk(KERN_WARNING |
052dfb45 DT |
1235 | "%s(): PCI error report via EDAC not setup\n", |
1236 | __func__); | |
91b99041 DJ |
1237 | } |
1238 | ||
806c35f5 | 1239 | /* get this far and it's successful */ |
537fba28 | 1240 | debugf3("%s(): success\n", __func__); |
806c35f5 AC |
1241 | return 0; |
1242 | ||
052dfb45 | 1243 | fail: |
13189525 DT |
1244 | pci_dev_put(pvt->dev_d0f0); |
1245 | pci_dev_put(pvt->dev_d0f1); | |
1246 | pci_dev_put(pvt->bridge_ck); | |
1247 | edac_mc_free(mci); | |
e7ecd891 | 1248 | |
13189525 | 1249 | return -ENODEV; |
806c35f5 AC |
1250 | } |
1251 | ||
1252 | /* returns count (>= 0), or negative on error */ | |
1253 | static int __devinit e752x_init_one(struct pci_dev *pdev, | |
052dfb45 | 1254 | const struct pci_device_id *ent) |
806c35f5 | 1255 | { |
537fba28 | 1256 | debugf0("%s()\n", __func__); |
806c35f5 AC |
1257 | |
1258 | /* wake up and enable device */ | |
203333cb | 1259 | if (pci_enable_device(pdev) < 0) |
806c35f5 | 1260 | return -EIO; |
e7ecd891 | 1261 | |
806c35f5 AC |
1262 | return e752x_probe1(pdev, ent->driver_data); |
1263 | } | |
1264 | ||
806c35f5 AC |
1265 | static void __devexit e752x_remove_one(struct pci_dev *pdev) |
1266 | { | |
1267 | struct mem_ctl_info *mci; | |
1268 | struct e752x_pvt *pvt; | |
1269 | ||
537fba28 | 1270 | debugf0("%s()\n", __func__); |
806c35f5 | 1271 | |
91b99041 DJ |
1272 | if (e752x_pci) |
1273 | edac_pci_release_generic_ctl(e752x_pci); | |
1274 | ||
37f04581 | 1275 | if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL) |
806c35f5 AC |
1276 | return; |
1277 | ||
203333cb | 1278 | pvt = (struct e752x_pvt *)mci->pvt_info; |
806c35f5 AC |
1279 | pci_dev_put(pvt->dev_d0f0); |
1280 | pci_dev_put(pvt->dev_d0f1); | |
1281 | pci_dev_put(pvt->bridge_ck); | |
1282 | edac_mc_free(mci); | |
1283 | } | |
1284 | ||
806c35f5 | 1285 | static const struct pci_device_id e752x_pci_tbl[] __devinitdata = { |
e7ecd891 | 1286 | { |
203333cb DJ |
1287 | PCI_VEND_DEV(INTEL, 7520_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
1288 | E7520}, | |
e7ecd891 | 1289 | { |
203333cb DJ |
1290 | PCI_VEND_DEV(INTEL, 7525_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
1291 | E7525}, | |
e7ecd891 | 1292 | { |
203333cb DJ |
1293 | PCI_VEND_DEV(INTEL, 7320_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
1294 | E7320}, | |
5135b797 AK |
1295 | { |
1296 | PCI_VEND_DEV(INTEL, 3100_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1297 | I3100}, | |
e7ecd891 | 1298 | { |
203333cb DJ |
1299 | 0, |
1300 | } /* 0 terminated list. */ | |
806c35f5 AC |
1301 | }; |
1302 | ||
1303 | MODULE_DEVICE_TABLE(pci, e752x_pci_tbl); | |
1304 | ||
806c35f5 | 1305 | static struct pci_driver e752x_driver = { |
680cbbbb | 1306 | .name = EDAC_MOD_STR, |
0d38b049 RD |
1307 | .probe = e752x_init_one, |
1308 | .remove = __devexit_p(e752x_remove_one), | |
1309 | .id_table = e752x_pci_tbl, | |
806c35f5 AC |
1310 | }; |
1311 | ||
da9bb1d2 | 1312 | static int __init e752x_init(void) |
806c35f5 AC |
1313 | { |
1314 | int pci_rc; | |
1315 | ||
537fba28 | 1316 | debugf3("%s()\n", __func__); |
c3c52bce HM |
1317 | |
1318 | /* Ensure that the OPSTATE is set correctly for POLL or NMI */ | |
1319 | opstate_init(); | |
1320 | ||
806c35f5 AC |
1321 | pci_rc = pci_register_driver(&e752x_driver); |
1322 | return (pci_rc < 0) ? pci_rc : 0; | |
1323 | } | |
1324 | ||
806c35f5 AC |
1325 | static void __exit e752x_exit(void) |
1326 | { | |
537fba28 | 1327 | debugf3("%s()\n", __func__); |
806c35f5 AC |
1328 | pci_unregister_driver(&e752x_driver); |
1329 | } | |
1330 | ||
806c35f5 AC |
1331 | module_init(e752x_init); |
1332 | module_exit(e752x_exit); | |
1333 | ||
1334 | MODULE_LICENSE("GPL"); | |
1335 | MODULE_AUTHOR("Linux Networx (http://lnxi.com) Tom Zimmerman\n"); | |
5135b797 | 1336 | MODULE_DESCRIPTION("MC support for Intel e752x/3100 memory controllers"); |
96941026 | 1337 | |
1338 | module_param(force_function_unhide, int, 0444); | |
1339 | MODULE_PARM_DESC(force_function_unhide, "if BIOS sets Dev0:Fun1 up as hidden:" | |
10d33e9c DT |
1340 | " 1=force unhide and hope BIOS doesn't fight driver for " |
1341 | "Dev0:Fun1 access"); | |
c3c52bce | 1342 | |
c0d12172 DJ |
1343 | module_param(edac_op_state, int, 0444); |
1344 | MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); | |
94ee1cf5 PT |
1345 | |
1346 | module_param(sysbus_parity, int, 0444); | |
1347 | MODULE_PARM_DESC(sysbus_parity, "0=disable system bus parity checking," | |
1348 | " 1=enable system bus parity checking, default=auto-detect"); | |
10d33e9c DT |
1349 | module_param(report_non_memory_errors, int, 0644); |
1350 | MODULE_PARM_DESC(report_non_memory_errors, "0=disable non-memory error " | |
1351 | "reporting, 1=enable non-memory error reporting"); |