Commit | Line | Data |
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806c35f5 AC |
1 | /* |
2 | * Intel e7xxx Memory Controller kernel module | |
3 | * (C) 2003 Linux Networx (http://lnxi.com) | |
4 | * This file may be distributed under the terms of the | |
5 | * GNU General Public License. | |
6 | * | |
7 | * See "enum e7xxx_chips" below for supported chipsets | |
8 | * | |
9 | * Written by Thayne Harbaugh | |
10 | * Based on work by Dan Hollis <goemon at anime dot net> and others. | |
11 | * http://www.anime.net/~goemon/linux-ecc/ | |
12 | * | |
13 | * Contributors: | |
e7ecd891 DP |
14 | * Eric Biederman (Linux Networx) |
15 | * Tom Zimmerman (Linux Networx) | |
16 | * Jim Garlick (Lawrence Livermore National Labs) | |
806c35f5 AC |
17 | * Dave Peterson (Lawrence Livermore National Labs) |
18 | * That One Guy (Some other place) | |
19 | * Wang Zhenyu (intel.com) | |
20 | * | |
21 | * $Id: edac_e7xxx.c,v 1.5.2.9 2005/10/05 00:43:44 dsp_llnl Exp $ | |
22 | * | |
23 | */ | |
24 | ||
806c35f5 AC |
25 | #include <linux/module.h> |
26 | #include <linux/init.h> | |
27 | #include <linux/pci.h> | |
28 | #include <linux/pci_ids.h> | |
c0d12172 | 29 | #include <linux/edac.h> |
20bcb7a8 | 30 | #include "edac_core.h" |
806c35f5 | 31 | |
152ba394 | 32 | #define E7XXX_REVISION " Ver: 2.0.2" |
929a40ec | 33 | #define EDAC_MOD_STR "e7xxx_edac" |
37f04581 | 34 | |
537fba28 | 35 | #define e7xxx_printk(level, fmt, arg...) \ |
e7ecd891 | 36 | edac_printk(level, "e7xxx", fmt, ##arg) |
537fba28 DP |
37 | |
38 | #define e7xxx_mc_printk(mci, level, fmt, arg...) \ | |
e7ecd891 | 39 | edac_mc_chipset_printk(mci, level, "e7xxx", fmt, ##arg) |
537fba28 | 40 | |
806c35f5 AC |
41 | #ifndef PCI_DEVICE_ID_INTEL_7205_0 |
42 | #define PCI_DEVICE_ID_INTEL_7205_0 0x255d | |
43 | #endif /* PCI_DEVICE_ID_INTEL_7205_0 */ | |
44 | ||
45 | #ifndef PCI_DEVICE_ID_INTEL_7205_1_ERR | |
46 | #define PCI_DEVICE_ID_INTEL_7205_1_ERR 0x2551 | |
47 | #endif /* PCI_DEVICE_ID_INTEL_7205_1_ERR */ | |
48 | ||
49 | #ifndef PCI_DEVICE_ID_INTEL_7500_0 | |
50 | #define PCI_DEVICE_ID_INTEL_7500_0 0x2540 | |
51 | #endif /* PCI_DEVICE_ID_INTEL_7500_0 */ | |
52 | ||
53 | #ifndef PCI_DEVICE_ID_INTEL_7500_1_ERR | |
54 | #define PCI_DEVICE_ID_INTEL_7500_1_ERR 0x2541 | |
55 | #endif /* PCI_DEVICE_ID_INTEL_7500_1_ERR */ | |
56 | ||
57 | #ifndef PCI_DEVICE_ID_INTEL_7501_0 | |
58 | #define PCI_DEVICE_ID_INTEL_7501_0 0x254c | |
59 | #endif /* PCI_DEVICE_ID_INTEL_7501_0 */ | |
60 | ||
61 | #ifndef PCI_DEVICE_ID_INTEL_7501_1_ERR | |
62 | #define PCI_DEVICE_ID_INTEL_7501_1_ERR 0x2541 | |
63 | #endif /* PCI_DEVICE_ID_INTEL_7501_1_ERR */ | |
64 | ||
65 | #ifndef PCI_DEVICE_ID_INTEL_7505_0 | |
66 | #define PCI_DEVICE_ID_INTEL_7505_0 0x2550 | |
67 | #endif /* PCI_DEVICE_ID_INTEL_7505_0 */ | |
68 | ||
69 | #ifndef PCI_DEVICE_ID_INTEL_7505_1_ERR | |
70 | #define PCI_DEVICE_ID_INTEL_7505_1_ERR 0x2551 | |
71 | #endif /* PCI_DEVICE_ID_INTEL_7505_1_ERR */ | |
72 | ||
806c35f5 AC |
73 | #define E7XXX_NR_CSROWS 8 /* number of csrows */ |
74 | #define E7XXX_NR_DIMMS 8 /* FIXME - is this correct? */ | |
75 | ||
806c35f5 AC |
76 | /* E7XXX register addresses - device 0 function 0 */ |
77 | #define E7XXX_DRB 0x60 /* DRAM row boundary register (8b) */ | |
78 | #define E7XXX_DRA 0x70 /* DRAM row attribute register (8b) */ | |
79 | /* | |
80 | * 31 Device width row 7 0=x8 1=x4 | |
81 | * 27 Device width row 6 | |
82 | * 23 Device width row 5 | |
83 | * 19 Device width row 4 | |
84 | * 15 Device width row 3 | |
85 | * 11 Device width row 2 | |
86 | * 7 Device width row 1 | |
87 | * 3 Device width row 0 | |
88 | */ | |
89 | #define E7XXX_DRC 0x7C /* DRAM controller mode reg (32b) */ | |
90 | /* | |
91 | * 22 Number channels 0=1,1=2 | |
92 | * 19:18 DRB Granularity 32/64MB | |
93 | */ | |
94 | #define E7XXX_TOLM 0xC4 /* DRAM top of low memory reg (16b) */ | |
95 | #define E7XXX_REMAPBASE 0xC6 /* DRAM remap base address reg (16b) */ | |
96 | #define E7XXX_REMAPLIMIT 0xC8 /* DRAM remap limit address reg (16b) */ | |
97 | ||
98 | /* E7XXX register addresses - device 0 function 1 */ | |
99 | #define E7XXX_DRAM_FERR 0x80 /* DRAM first error register (8b) */ | |
100 | #define E7XXX_DRAM_NERR 0x82 /* DRAM next error register (8b) */ | |
101 | #define E7XXX_DRAM_CELOG_ADD 0xA0 /* DRAM first correctable memory */ | |
102 | /* error address register (32b) */ | |
103 | /* | |
104 | * 31:28 Reserved | |
105 | * 27:6 CE address (4k block 33:12) | |
106 | * 5:0 Reserved | |
107 | */ | |
108 | #define E7XXX_DRAM_UELOG_ADD 0xB0 /* DRAM first uncorrectable memory */ | |
109 | /* error address register (32b) */ | |
110 | /* | |
111 | * 31:28 Reserved | |
112 | * 27:6 CE address (4k block 33:12) | |
113 | * 5:0 Reserved | |
114 | */ | |
115 | #define E7XXX_DRAM_CELOG_SYNDROME 0xD0 /* DRAM first correctable memory */ | |
116 | /* error syndrome register (16b) */ | |
117 | ||
118 | enum e7xxx_chips { | |
119 | E7500 = 0, | |
120 | E7501, | |
121 | E7505, | |
122 | E7205, | |
123 | }; | |
124 | ||
806c35f5 AC |
125 | struct e7xxx_pvt { |
126 | struct pci_dev *bridge_ck; | |
127 | u32 tolm; | |
128 | u32 remapbase; | |
129 | u32 remaplimit; | |
130 | const struct e7xxx_dev_info *dev_info; | |
131 | }; | |
132 | ||
806c35f5 AC |
133 | struct e7xxx_dev_info { |
134 | u16 err_dev; | |
135 | const char *ctl_name; | |
136 | }; | |
137 | ||
806c35f5 AC |
138 | struct e7xxx_error_info { |
139 | u8 dram_ferr; | |
140 | u8 dram_nerr; | |
141 | u32 dram_celog_add; | |
142 | u16 dram_celog_syndrome; | |
143 | u32 dram_uelog_add; | |
144 | }; | |
145 | ||
456a2f95 DJ |
146 | static struct edac_pci_ctl_info *e7xxx_pci; |
147 | ||
806c35f5 AC |
148 | static const struct e7xxx_dev_info e7xxx_devs[] = { |
149 | [E7500] = { | |
052dfb45 DT |
150 | .err_dev = PCI_DEVICE_ID_INTEL_7500_1_ERR, |
151 | .ctl_name = "E7500"}, | |
806c35f5 | 152 | [E7501] = { |
052dfb45 DT |
153 | .err_dev = PCI_DEVICE_ID_INTEL_7501_1_ERR, |
154 | .ctl_name = "E7501"}, | |
806c35f5 | 155 | [E7505] = { |
052dfb45 DT |
156 | .err_dev = PCI_DEVICE_ID_INTEL_7505_1_ERR, |
157 | .ctl_name = "E7505"}, | |
806c35f5 | 158 | [E7205] = { |
052dfb45 DT |
159 | .err_dev = PCI_DEVICE_ID_INTEL_7205_1_ERR, |
160 | .ctl_name = "E7205"}, | |
806c35f5 AC |
161 | }; |
162 | ||
806c35f5 AC |
163 | /* FIXME - is this valid for both SECDED and S4ECD4ED? */ |
164 | static inline int e7xxx_find_channel(u16 syndrome) | |
165 | { | |
537fba28 | 166 | debugf3("%s()\n", __func__); |
806c35f5 AC |
167 | |
168 | if ((syndrome & 0xff00) == 0) | |
169 | return 0; | |
e7ecd891 | 170 | |
806c35f5 AC |
171 | if ((syndrome & 0x00ff) == 0) |
172 | return 1; | |
e7ecd891 | 173 | |
806c35f5 AC |
174 | if ((syndrome & 0xf000) == 0 || (syndrome & 0x0f00) == 0) |
175 | return 0; | |
e7ecd891 | 176 | |
806c35f5 AC |
177 | return 1; |
178 | } | |
179 | ||
e7ecd891 | 180 | static unsigned long ctl_page_to_phys(struct mem_ctl_info *mci, |
052dfb45 | 181 | unsigned long page) |
806c35f5 AC |
182 | { |
183 | u32 remap; | |
849a4c37 | 184 | struct e7xxx_pvt *pvt = (struct e7xxx_pvt *)mci->pvt_info; |
806c35f5 | 185 | |
537fba28 | 186 | debugf3("%s()\n", __func__); |
806c35f5 AC |
187 | |
188 | if ((page < pvt->tolm) || | |
052dfb45 | 189 | ((page >= 0x100000) && (page < pvt->remapbase))) |
806c35f5 | 190 | return page; |
e7ecd891 | 191 | |
806c35f5 | 192 | remap = (page - pvt->tolm) + pvt->remapbase; |
e7ecd891 | 193 | |
806c35f5 AC |
194 | if (remap < pvt->remaplimit) |
195 | return remap; | |
e7ecd891 | 196 | |
537fba28 | 197 | e7xxx_printk(KERN_ERR, "Invalid page %lx - out of range\n", page); |
806c35f5 AC |
198 | return pvt->tolm - 1; |
199 | } | |
200 | ||
849a4c37 | 201 | static void process_ce(struct mem_ctl_info *mci, struct e7xxx_error_info *info) |
806c35f5 AC |
202 | { |
203 | u32 error_1b, page; | |
204 | u16 syndrome; | |
205 | int row; | |
206 | int channel; | |
207 | ||
537fba28 | 208 | debugf3("%s()\n", __func__); |
806c35f5 AC |
209 | /* read the error address */ |
210 | error_1b = info->dram_celog_add; | |
211 | /* FIXME - should use PAGE_SHIFT */ | |
849a4c37 | 212 | page = error_1b >> 6; /* convert the address to 4k page */ |
806c35f5 AC |
213 | /* read the syndrome */ |
214 | syndrome = info->dram_celog_syndrome; | |
215 | /* FIXME - check for -1 */ | |
216 | row = edac_mc_find_csrow_by_page(mci, page); | |
217 | /* convert syndrome to channel */ | |
218 | channel = e7xxx_find_channel(syndrome); | |
e7ecd891 | 219 | edac_mc_handle_ce(mci, page, 0, syndrome, row, channel, "e7xxx CE"); |
806c35f5 AC |
220 | } |
221 | ||
806c35f5 AC |
222 | static void process_ce_no_info(struct mem_ctl_info *mci) |
223 | { | |
537fba28 | 224 | debugf3("%s()\n", __func__); |
806c35f5 AC |
225 | edac_mc_handle_ce_no_info(mci, "e7xxx CE log register overflow"); |
226 | } | |
227 | ||
849a4c37 | 228 | static void process_ue(struct mem_ctl_info *mci, struct e7xxx_error_info *info) |
806c35f5 AC |
229 | { |
230 | u32 error_2b, block_page; | |
231 | int row; | |
232 | ||
537fba28 | 233 | debugf3("%s()\n", __func__); |
806c35f5 AC |
234 | /* read the error address */ |
235 | error_2b = info->dram_uelog_add; | |
236 | /* FIXME - should use PAGE_SHIFT */ | |
849a4c37 | 237 | block_page = error_2b >> 6; /* convert to 4k address */ |
806c35f5 AC |
238 | row = edac_mc_find_csrow_by_page(mci, block_page); |
239 | edac_mc_handle_ue(mci, block_page, 0, row, "e7xxx UE"); | |
240 | } | |
241 | ||
806c35f5 AC |
242 | static void process_ue_no_info(struct mem_ctl_info *mci) |
243 | { | |
537fba28 | 244 | debugf3("%s()\n", __func__); |
806c35f5 AC |
245 | edac_mc_handle_ue_no_info(mci, "e7xxx UE log register overflow"); |
246 | } | |
247 | ||
849a4c37 DJ |
248 | static void e7xxx_get_error_info(struct mem_ctl_info *mci, |
249 | struct e7xxx_error_info *info) | |
806c35f5 AC |
250 | { |
251 | struct e7xxx_pvt *pvt; | |
252 | ||
849a4c37 DJ |
253 | pvt = (struct e7xxx_pvt *)mci->pvt_info; |
254 | pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_FERR, &info->dram_ferr); | |
255 | pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_NERR, &info->dram_nerr); | |
806c35f5 AC |
256 | |
257 | if ((info->dram_ferr & 1) || (info->dram_nerr & 1)) { | |
258 | pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_CELOG_ADD, | |
052dfb45 | 259 | &info->dram_celog_add); |
806c35f5 | 260 | pci_read_config_word(pvt->bridge_ck, |
052dfb45 DT |
261 | E7XXX_DRAM_CELOG_SYNDROME, |
262 | &info->dram_celog_syndrome); | |
806c35f5 AC |
263 | } |
264 | ||
265 | if ((info->dram_ferr & 2) || (info->dram_nerr & 2)) | |
266 | pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_UELOG_ADD, | |
052dfb45 | 267 | &info->dram_uelog_add); |
806c35f5 AC |
268 | |
269 | if (info->dram_ferr & 3) | |
e7ecd891 | 270 | pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_FERR, 0x03, 0x03); |
806c35f5 AC |
271 | |
272 | if (info->dram_nerr & 3) | |
e7ecd891 | 273 | pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_NERR, 0x03, 0x03); |
806c35f5 AC |
274 | } |
275 | ||
849a4c37 | 276 | static int e7xxx_process_error_info(struct mem_ctl_info *mci, |
052dfb45 DT |
277 | struct e7xxx_error_info *info, |
278 | int handle_errors) | |
806c35f5 AC |
279 | { |
280 | int error_found; | |
281 | ||
282 | error_found = 0; | |
283 | ||
284 | /* decode and report errors */ | |
285 | if (info->dram_ferr & 1) { /* check first error correctable */ | |
286 | error_found = 1; | |
287 | ||
288 | if (handle_errors) | |
289 | process_ce(mci, info); | |
290 | } | |
291 | ||
292 | if (info->dram_ferr & 2) { /* check first error uncorrectable */ | |
293 | error_found = 1; | |
294 | ||
295 | if (handle_errors) | |
296 | process_ue(mci, info); | |
297 | } | |
298 | ||
299 | if (info->dram_nerr & 1) { /* check next error correctable */ | |
300 | error_found = 1; | |
301 | ||
302 | if (handle_errors) { | |
303 | if (info->dram_ferr & 1) | |
304 | process_ce_no_info(mci); | |
305 | else | |
306 | process_ce(mci, info); | |
307 | } | |
308 | } | |
309 | ||
310 | if (info->dram_nerr & 2) { /* check next error uncorrectable */ | |
311 | error_found = 1; | |
312 | ||
313 | if (handle_errors) { | |
314 | if (info->dram_ferr & 2) | |
315 | process_ue_no_info(mci); | |
316 | else | |
317 | process_ue(mci, info); | |
318 | } | |
319 | } | |
320 | ||
321 | return error_found; | |
322 | } | |
323 | ||
806c35f5 AC |
324 | static void e7xxx_check(struct mem_ctl_info *mci) |
325 | { | |
326 | struct e7xxx_error_info info; | |
327 | ||
537fba28 | 328 | debugf3("%s()\n", __func__); |
806c35f5 AC |
329 | e7xxx_get_error_info(mci, &info); |
330 | e7xxx_process_error_info(mci, &info, 1); | |
331 | } | |
332 | ||
13189525 DT |
333 | /* Return 1 if dual channel mode is active. Else return 0. */ |
334 | static inline int dual_channel_active(u32 drc, int dev_idx) | |
806c35f5 | 335 | { |
13189525 DT |
336 | return (dev_idx == E7501) ? ((drc >> 22) & 0x1) : 1; |
337 | } | |
806c35f5 | 338 | |
13189525 DT |
339 | /* Return DRB granularity (0=32mb, 1=64mb). */ |
340 | static inline int drb_granularity(u32 drc, int dev_idx) | |
341 | { | |
806c35f5 | 342 | /* only e7501 can be single channel */ |
13189525 DT |
343 | return (dev_idx == E7501) ? ((drc >> 18) & 0x3) : 1; |
344 | } | |
e7ecd891 | 345 | |
13189525 | 346 | static void e7xxx_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev, |
052dfb45 | 347 | int dev_idx, u32 drc) |
13189525 DT |
348 | { |
349 | unsigned long last_cumul_size; | |
084a4fcc | 350 | int index, j; |
13189525 | 351 | u8 value; |
a895bf8b | 352 | u32 dra, cumul_size, nr_pages; |
13189525 DT |
353 | int drc_chan, drc_drbg, drc_ddim, mem_dev; |
354 | struct csrow_info *csrow; | |
084a4fcc | 355 | struct dimm_info *dimm; |
806c35f5 | 356 | |
806c35f5 | 357 | pci_read_config_dword(pdev, E7XXX_DRA, &dra); |
13189525 DT |
358 | drc_chan = dual_channel_active(drc, dev_idx); |
359 | drc_drbg = drb_granularity(drc, dev_idx); | |
360 | drc_ddim = (drc >> 20) & 0x3; | |
361 | last_cumul_size = 0; | |
806c35f5 | 362 | |
13189525 | 363 | /* The dram row boundary (DRB) reg values are boundary address |
806c35f5 AC |
364 | * for each DRAM row with a granularity of 32 or 64MB (single/dual |
365 | * channel operation). DRB regs are cumulative; therefore DRB7 will | |
366 | * contain the total memory contained in all eight rows. | |
367 | */ | |
13189525 | 368 | for (index = 0; index < mci->nr_csrows; index++) { |
806c35f5 | 369 | /* mem_dev 0=x8, 1=x4 */ |
13189525 DT |
370 | mem_dev = (dra >> (index * 4 + 3)) & 0x1; |
371 | csrow = &mci->csrows[index]; | |
806c35f5 | 372 | |
37f04581 | 373 | pci_read_config_byte(pdev, E7XXX_DRB + index, &value); |
806c35f5 AC |
374 | /* convert a 64 or 32 MiB DRB to a page size. */ |
375 | cumul_size = value << (25 + drc_drbg - PAGE_SHIFT); | |
537fba28 DP |
376 | debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index, |
377 | cumul_size); | |
806c35f5 | 378 | if (cumul_size == last_cumul_size) |
13189525 | 379 | continue; /* not populated */ |
806c35f5 AC |
380 | |
381 | csrow->first_page = last_cumul_size; | |
382 | csrow->last_page = cumul_size - 1; | |
a895bf8b | 383 | nr_pages = cumul_size - last_cumul_size; |
806c35f5 | 384 | last_cumul_size = cumul_size; |
084a4fcc MCC |
385 | |
386 | for (j = 0; j < drc_chan + 1; j++) { | |
387 | dimm = csrow->channels[j].dimm; | |
388 | ||
a895bf8b | 389 | dimm->nr_pages = nr_pages / (drc_chan + 1); |
084a4fcc MCC |
390 | dimm->grain = 1 << 12; /* 4KiB - resolution of CELOG */ |
391 | dimm->mtype = MEM_RDDR; /* only one type supported */ | |
392 | dimm->dtype = mem_dev ? DEV_X4 : DEV_X8; | |
393 | ||
394 | /* | |
395 | * if single channel or x8 devices then SECDED | |
396 | * if dual channel and x4 then S4ECD4ED | |
397 | */ | |
398 | if (drc_ddim) { | |
399 | if (drc_chan && mem_dev) { | |
400 | dimm->edac_mode = EDAC_S4ECD4ED; | |
401 | mci->edac_cap |= EDAC_FLAG_S4ECD4ED; | |
402 | } else { | |
403 | dimm->edac_mode = EDAC_SECDED; | |
404 | mci->edac_cap |= EDAC_FLAG_SECDED; | |
405 | } | |
406 | } else | |
407 | dimm->edac_mode = EDAC_NONE; | |
408 | } | |
806c35f5 | 409 | } |
13189525 | 410 | } |
806c35f5 | 411 | |
13189525 DT |
412 | static int e7xxx_probe1(struct pci_dev *pdev, int dev_idx) |
413 | { | |
414 | u16 pci_data; | |
415 | struct mem_ctl_info *mci = NULL; | |
416 | struct e7xxx_pvt *pvt = NULL; | |
417 | u32 drc; | |
418 | int drc_chan; | |
419 | struct e7xxx_error_info discard; | |
420 | ||
421 | debugf0("%s(): mci\n", __func__); | |
c0d12172 | 422 | |
13189525 DT |
423 | pci_read_config_dword(pdev, E7XXX_DRC, &drc); |
424 | ||
425 | drc_chan = dual_channel_active(drc, dev_idx); | |
b8f6f975 | 426 | mci = edac_mc_alloc(sizeof(*pvt), E7XXX_NR_CSROWS, drc_chan + 1, 0); |
13189525 DT |
427 | |
428 | if (mci == NULL) | |
429 | return -ENOMEM; | |
806c35f5 | 430 | |
13189525 DT |
431 | debugf3("%s(): init mci\n", __func__); |
432 | mci->mtype_cap = MEM_FLAG_RDDR; | |
433 | mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED | | |
052dfb45 | 434 | EDAC_FLAG_S4ECD4ED; |
13189525 DT |
435 | /* FIXME - what if different memory types are in different csrows? */ |
436 | mci->mod_name = EDAC_MOD_STR; | |
437 | mci->mod_ver = E7XXX_REVISION; | |
438 | mci->dev = &pdev->dev; | |
439 | debugf3("%s(): init pvt\n", __func__); | |
849a4c37 | 440 | pvt = (struct e7xxx_pvt *)mci->pvt_info; |
13189525 DT |
441 | pvt->dev_info = &e7xxx_devs[dev_idx]; |
442 | pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL, | |
849a4c37 | 443 | pvt->dev_info->err_dev, pvt->bridge_ck); |
13189525 DT |
444 | |
445 | if (!pvt->bridge_ck) { | |
446 | e7xxx_printk(KERN_ERR, "error reporting device not found:" | |
052dfb45 DT |
447 | "vendor %x device 0x%x (broken BIOS?)\n", |
448 | PCI_VENDOR_ID_INTEL, e7xxx_devs[dev_idx].err_dev); | |
13189525 DT |
449 | goto fail0; |
450 | } | |
451 | ||
452 | debugf3("%s(): more mci init\n", __func__); | |
453 | mci->ctl_name = pvt->dev_info->ctl_name; | |
c4192705 | 454 | mci->dev_name = pci_name(pdev); |
13189525 DT |
455 | mci->edac_check = e7xxx_check; |
456 | mci->ctl_page_to_phys = ctl_page_to_phys; | |
457 | e7xxx_init_csrows(mci, pdev, dev_idx, drc); | |
458 | mci->edac_cap |= EDAC_FLAG_NONE; | |
537fba28 | 459 | debugf3("%s(): tolm, remapbase, remaplimit\n", __func__); |
806c35f5 | 460 | /* load the top of low memory, remap base, and remap limit vars */ |
37f04581 | 461 | pci_read_config_word(pdev, E7XXX_TOLM, &pci_data); |
806c35f5 | 462 | pvt->tolm = ((u32) pci_data) << 4; |
37f04581 | 463 | pci_read_config_word(pdev, E7XXX_REMAPBASE, &pci_data); |
806c35f5 | 464 | pvt->remapbase = ((u32) pci_data) << 14; |
37f04581 | 465 | pci_read_config_word(pdev, E7XXX_REMAPLIMIT, &pci_data); |
806c35f5 | 466 | pvt->remaplimit = ((u32) pci_data) << 14; |
537fba28 | 467 | e7xxx_printk(KERN_INFO, |
052dfb45 DT |
468 | "tolm = %x, remapbase = %x, remaplimit = %x\n", pvt->tolm, |
469 | pvt->remapbase, pvt->remaplimit); | |
806c35f5 AC |
470 | |
471 | /* clear any pending errors, or initial state bits */ | |
749ede57 | 472 | e7xxx_get_error_info(mci, &discard); |
806c35f5 | 473 | |
2d7bbb91 DT |
474 | /* Here we assume that we will never see multiple instances of this |
475 | * type of memory controller. The ID is therefore hardcoded to 0. | |
476 | */ | |
b8f6f975 | 477 | if (edac_mc_add_mc(mci)) { |
537fba28 | 478 | debugf3("%s(): failed edac_mc_add_mc()\n", __func__); |
13189525 | 479 | goto fail1; |
806c35f5 AC |
480 | } |
481 | ||
456a2f95 DJ |
482 | /* allocating generic PCI control info */ |
483 | e7xxx_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR); | |
484 | if (!e7xxx_pci) { | |
485 | printk(KERN_WARNING | |
486 | "%s(): Unable to create PCI control\n", | |
487 | __func__); | |
488 | printk(KERN_WARNING | |
489 | "%s(): PCI error report via EDAC not setup\n", | |
490 | __func__); | |
491 | } | |
492 | ||
806c35f5 | 493 | /* get this far and it's successful */ |
537fba28 | 494 | debugf3("%s(): success\n", __func__); |
806c35f5 AC |
495 | return 0; |
496 | ||
052dfb45 | 497 | fail1: |
13189525 DT |
498 | pci_dev_put(pvt->bridge_ck); |
499 | ||
052dfb45 | 500 | fail0: |
13189525 | 501 | edac_mc_free(mci); |
806c35f5 | 502 | |
13189525 | 503 | return -ENODEV; |
806c35f5 AC |
504 | } |
505 | ||
506 | /* returns count (>= 0), or negative on error */ | |
e7ecd891 | 507 | static int __devinit e7xxx_init_one(struct pci_dev *pdev, |
052dfb45 | 508 | const struct pci_device_id *ent) |
806c35f5 | 509 | { |
537fba28 | 510 | debugf0("%s()\n", __func__); |
806c35f5 AC |
511 | |
512 | /* wake up and enable device */ | |
513 | return pci_enable_device(pdev) ? | |
052dfb45 | 514 | -EIO : e7xxx_probe1(pdev, ent->driver_data); |
806c35f5 AC |
515 | } |
516 | ||
806c35f5 AC |
517 | static void __devexit e7xxx_remove_one(struct pci_dev *pdev) |
518 | { | |
519 | struct mem_ctl_info *mci; | |
520 | struct e7xxx_pvt *pvt; | |
521 | ||
537fba28 | 522 | debugf0("%s()\n", __func__); |
806c35f5 | 523 | |
456a2f95 DJ |
524 | if (e7xxx_pci) |
525 | edac_pci_release_generic_ctl(e7xxx_pci); | |
526 | ||
37f04581 | 527 | if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL) |
18dbc337 DP |
528 | return; |
529 | ||
849a4c37 | 530 | pvt = (struct e7xxx_pvt *)mci->pvt_info; |
18dbc337 DP |
531 | pci_dev_put(pvt->bridge_ck); |
532 | edac_mc_free(mci); | |
806c35f5 AC |
533 | } |
534 | ||
36c46f31 | 535 | static DEFINE_PCI_DEVICE_TABLE(e7xxx_pci_tbl) = { |
e7ecd891 | 536 | { |
849a4c37 DJ |
537 | PCI_VEND_DEV(INTEL, 7205_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
538 | E7205}, | |
e7ecd891 | 539 | { |
849a4c37 DJ |
540 | PCI_VEND_DEV(INTEL, 7500_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
541 | E7500}, | |
e7ecd891 | 542 | { |
849a4c37 DJ |
543 | PCI_VEND_DEV(INTEL, 7501_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
544 | E7501}, | |
e7ecd891 | 545 | { |
849a4c37 DJ |
546 | PCI_VEND_DEV(INTEL, 7505_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
547 | E7505}, | |
e7ecd891 | 548 | { |
849a4c37 DJ |
549 | 0, |
550 | } /* 0 terminated list. */ | |
806c35f5 AC |
551 | }; |
552 | ||
553 | MODULE_DEVICE_TABLE(pci, e7xxx_pci_tbl); | |
554 | ||
806c35f5 | 555 | static struct pci_driver e7xxx_driver = { |
680cbbbb | 556 | .name = EDAC_MOD_STR, |
806c35f5 AC |
557 | .probe = e7xxx_init_one, |
558 | .remove = __devexit_p(e7xxx_remove_one), | |
559 | .id_table = e7xxx_pci_tbl, | |
560 | }; | |
561 | ||
da9bb1d2 | 562 | static int __init e7xxx_init(void) |
806c35f5 | 563 | { |
c3c52bce HM |
564 | /* Ensure that the OPSTATE is set correctly for POLL or NMI */ |
565 | opstate_init(); | |
566 | ||
806c35f5 AC |
567 | return pci_register_driver(&e7xxx_driver); |
568 | } | |
569 | ||
806c35f5 AC |
570 | static void __exit e7xxx_exit(void) |
571 | { | |
572 | pci_unregister_driver(&e7xxx_driver); | |
573 | } | |
574 | ||
575 | module_init(e7xxx_init); | |
576 | module_exit(e7xxx_exit); | |
577 | ||
806c35f5 AC |
578 | MODULE_LICENSE("GPL"); |
579 | MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh et al\n" | |
052dfb45 | 580 | "Based on.work by Dan Hollis et al"); |
806c35f5 | 581 | MODULE_DESCRIPTION("MC support for Intel e7xxx memory controllers"); |
c0d12172 DJ |
582 | module_param(edac_op_state, int, 0444); |
583 | MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); |