[deliverable/linux.git] / drivers / edac / edac_core.h

/*
 * Defines, structures, APIs for edac_core module
 *
 * (C) 2007 Linux Networx (http://lnxi.com)
 * This file may be distributed under the terms of the
 * GNU General Public License.
 *
 * Written by Thayne Harbaugh
 * Based on work by Dan Hollis <goemon at anime dot net> and others.
 *	http://www.anime.net/~goemon/linux-ecc/
 *
 * NMI handling support added by
 *     Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>
 *
 * Refactored for multi-source files:
 *	Doug Thompson <norsk5@xmission.com>
 *
 */

#ifndef _EDAC_CORE_H_
#define _EDAC_CORE_H_

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/smp.h>
#include <linux/pci.h>
#include <linux/time.h>
#include <linux/nmi.h>
#include <linux/rcupdate.h>
#include <linux/completion.h>
#include <linux/kobject.h>
#include <linux/platform_device.h>
#include <linux/sysdev.h>
#include <linux/workqueue.h>
#include <linux/edac.h>

#define EDAC_DEVICE_NAME_LEN	31
#define EDAC_ATTRIB_VALUE_LEN	15

#if PAGE_SHIFT < 20
#define PAGES_TO_MiB(pages)	((pages) >> (20 - PAGE_SHIFT))
#define MiB_TO_PAGES(mb)	((mb) << (20 - PAGE_SHIFT))
#else				/* PAGE_SHIFT > 20 */
#define PAGES_TO_MiB(pages)	((pages) << (PAGE_SHIFT - 20))
#define MiB_TO_PAGES(mb)	((mb) >> (PAGE_SHIFT - 20))
#endif

#define edac_printk(level, prefix, fmt, arg...) \
	printk(level "EDAC " prefix ": " fmt, ##arg)

#define edac_mc_printk(mci, level, fmt, arg...) \
	printk(level "EDAC MC%d: " fmt, mci->mc_idx, ##arg)

#define edac_mc_chipset_printk(mci, level, prefix, fmt, arg...) \
	printk(level "EDAC " prefix " MC%d: " fmt, mci->mc_idx, ##arg)

#define edac_device_printk(ctl, level, fmt, arg...) \
	printk(level "EDAC DEVICE%d: " fmt, ctl->dev_idx, ##arg)

#define edac_pci_printk(ctl, level, fmt, arg...) \
	printk(level "EDAC PCI%d: " fmt, ctl->pci_idx, ##arg)

/* prefixes for edac_printk() and edac_mc_printk() */
#define EDAC_MC "MC"
#define EDAC_PCI "PCI"
#define EDAC_DEBUG "DEBUG"

extern const char *edac_mem_types[];

#ifdef CONFIG_EDAC_DEBUG
extern int edac_debug_level;

#define edac_debug_printk(level, fmt, arg...)                           \
	do {                                                            \
		if (level <= edac_debug_level)                          \
			edac_printk(KERN_DEBUG, EDAC_DEBUG,		\
				    "%s: " fmt, __func__, ##arg);	\
	} while (0)

#define debugf0( ... ) edac_debug_printk(0, __VA_ARGS__ )
#define debugf1( ... ) edac_debug_printk(1, __VA_ARGS__ )
#define debugf2( ... ) edac_debug_printk(2, __VA_ARGS__ )
#define debugf3( ... ) edac_debug_printk(3, __VA_ARGS__ )
#define debugf4( ... ) edac_debug_printk(4, __VA_ARGS__ )

#else				/* !CONFIG_EDAC_DEBUG */

#define debugf0( ... )
#define debugf1( ... )
#define debugf2( ... )
#define debugf3( ... )
#define debugf4( ... )

#endif				/* !CONFIG_EDAC_DEBUG */

#define PCI_VEND_DEV(vend, dev) PCI_VENDOR_ID_ ## vend, \
	PCI_DEVICE_ID_ ## vend ## _ ## dev

#define edac_dev_name(dev) (dev)->dev_name

/*
 * The following are the structures to provide for a generic
 * or abstract 'edac_device'. This set of structures and the
 * code that implements the APIs for the same, provide for
 * registering EDAC type devices which are NOT standard memory.
 *
 * CPU caches (L1 and L2)
 * DMA engines
 * Core CPU swithces
 * Fabric switch units
 * PCIe interface controllers
 * other EDAC/ECC type devices that can be monitored for
 * errors, etc.
 *
 * It allows for a 2 level set of hiearchry. For example:
 *
 * cache could be composed of L1, L2 and L3 levels of cache.
 * Each CPU core would have its own L1 cache, while sharing
 * L2 and maybe L3 caches.
 *
 * View them arranged, via the sysfs presentation:
 * /sys/devices/system/edac/..
 *
 *	mc/		<existing memory device directory>
 *	cpu/cpu0/..	<L1 and L2 block directory>
 *		/L1-cache/ce_count
 *			 /ue_count
 *		/L2-cache/ce_count
 *			 /ue_count
 *	cpu/cpu1/..	<L1 and L2 block directory>
 *		/L1-cache/ce_count
 *			 /ue_count
 *		/L2-cache/ce_count
 *			 /ue_count
 *	...
 *
 *	the L1 and L2 directories would be "edac_device_block's"
 */

struct edac_device_counter {
	u32 ue_count;
	u32 ce_count;
};

/* forward reference */
struct edac_device_ctl_info;
struct edac_device_block;

/* edac_dev_sysfs_attribute structure
 *	used for driver sysfs attributes in mem_ctl_info
 *	for extra controls and attributes:
 *		like high level error Injection controls
 */
struct edac_dev_sysfs_attribute {
	struct attribute attr;
	ssize_t (*show)(struct edac_device_ctl_info *, char *);
	ssize_t (*store)(struct edac_device_ctl_info *, const char *, size_t);
};

/* edac_dev_sysfs_block_attribute structure
 *
 *	used in leaf 'block' nodes for adding controls/attributes
 *
 *	each block in each instance of the containing control structure
 *	can have an array of the following. The show and store functions
 *	will be filled in with the show/store function in the
 *	low level driver.
 *
 *	The 'value' field will be the actual value field used for
 *	counting
 */
struct edac_dev_sysfs_block_attribute {
	struct attribute attr;
	ssize_t (*show)(struct kobject *, struct attribute *, char *);
	ssize_t (*store)(struct kobject *, struct attribute *,
			const char *, size_t);
	struct edac_device_block *block;

	unsigned int value;
};

/* device block control structure */
struct edac_device_block {
	struct edac_device_instance *instance;	/* Up Pointer */
	char name[EDAC_DEVICE_NAME_LEN + 1];

	struct edac_device_counter counters;	/* basic UE and CE counters */

	int nr_attribs;		/* how many attributes */

	/* this block's attributes, could be NULL */
	struct edac_dev_sysfs_block_attribute *block_attributes;

	/* edac sysfs device control */
	struct kobject kobj;
};

/* device instance control structure */
struct edac_device_instance {
	struct edac_device_ctl_info *ctl;	/* Up pointer */
	char name[EDAC_DEVICE_NAME_LEN + 4];

	struct edac_device_counter counters;	/* instance counters */

	u32 nr_blocks;		/* how many blocks */
	struct edac_device_block *blocks;	/* block array */

	/* edac sysfs device control */
	struct kobject kobj;
};


/*
 * Abstract edac_device control info structure
 *
 */
struct edac_device_ctl_info {
	/* for global list of edac_device_ctl_info structs */
	struct list_head link;

	struct module *owner;	/* Module owner of this control struct */

	int dev_idx;

	/* Per instance controls for this edac_device */
	int log_ue;		/* boolean for logging UEs */
	int log_ce;		/* boolean for logging CEs */
	int panic_on_ue;	/* boolean for panic'ing on an UE */
	unsigned poll_msec;	/* number of milliseconds to poll interval */
	unsigned long delay;	/* number of jiffies for poll_msec */

	/* Additional top controller level attributes, but specified
	 * by the low level driver.
	 *
	 * Set by the low level driver to provide attributes at the
	 * controller level, same level as 'ue_count' and 'ce_count' above.
	 * An array of structures, NULL terminated
	 *
	 * If attributes are desired, then set to array of attributes
	 * If no attributes are desired, leave NULL
	 */
	struct edac_dev_sysfs_attribute *sysfs_attributes;

	/* pointer to main 'edac' class in sysfs */
	struct sysdev_class *edac_class;

	/* the internal state of this controller instance */
	int op_state;
	/* work struct for this instance */
	struct delayed_work work;

	/* pointer to edac polling checking routine:
	 *      If NOT NULL: points to polling check routine
	 *      If NULL: Then assumes INTERRUPT operation, where
	 *              MC driver will receive events
	 */
	void (*edac_check) (struct edac_device_ctl_info * edac_dev);

	struct device *dev;	/* pointer to device structure */

	const char *mod_name;	/* module name */
	const char *ctl_name;	/* edac controller  name */
	const char *dev_name;	/* pci/platform/etc... name */

	void *pvt_info;		/* pointer to 'private driver' info */

	unsigned long start_time;	/* edac_device load start time (jiffies) */

	struct completion removal_complete;

	/* sysfs top name under 'edac' directory
	 * and instance name:
	 *      cpu/cpu0/...
	 *      cpu/cpu1/...
	 *      cpu/cpu2/...
	 *      ...
	 */
	char name[EDAC_DEVICE_NAME_LEN + 1];

	/* Number of instances supported on this control structure
	 * and the array of those instances
	 */
	u32 nr_instances;
	struct edac_device_instance *instances;

	/* Event counters for the this whole EDAC Device */
	struct edac_device_counter counters;

	/* edac sysfs device control for the 'name'
	 * device this structure controls
	 */
	struct kobject kobj;
};

/* To get from the instance's wq to the beginning of the ctl structure */
#define to_edac_mem_ctl_work(w) \
		container_of(w, struct mem_ctl_info, work)

#define to_edac_device_ctl_work(w) \
		container_of(w,struct edac_device_ctl_info,work)

/*
 * The alloc() and free() functions for the 'edac_device' control info
 * structure. A MC driver will allocate one of these for each edac_device
 * it is going to control/register with the EDAC CORE.
 */
extern struct edac_device_ctl_info *edac_device_alloc_ctl_info(
		unsigned sizeof_private,
		char *edac_device_name, unsigned nr_instances,
		char *edac_block_name, unsigned nr_blocks,
		unsigned offset_value,
		struct edac_dev_sysfs_block_attribute *block_attributes,
		unsigned nr_attribs,
		int device_index);

/* The offset value can be:
 *	-1 indicating no offset value
 *	0 for zero-based block numbers
 *	1 for 1-based block number
 *	other for other-based block number
 */
#define	BLOCK_OFFSET_VALUE_OFF	((unsigned) -1)

extern void edac_device_free_ctl_info(struct edac_device_ctl_info *ctl_info);

#ifdef CONFIG_PCI

struct edac_pci_counter {
	atomic_t pe_count;
	atomic_t npe_count;
};

/*
 * Abstract edac_pci control info structure
 *
 */
struct edac_pci_ctl_info {
	/* for global list of edac_pci_ctl_info structs */
	struct list_head link;

	int pci_idx;

	struct sysdev_class *edac_class;	/* pointer to class */

	/* the internal state of this controller instance */
	int op_state;
	/* work struct for this instance */
	struct delayed_work work;

	/* pointer to edac polling checking routine:
	 *      If NOT NULL: points to polling check routine
	 *      If NULL: Then assumes INTERRUPT operation, where
	 *              MC driver will receive events
	 */
	void (*edac_check) (struct edac_pci_ctl_info * edac_dev);

	struct device *dev;	/* pointer to device structure */

	const char *mod_name;	/* module name */
	const char *ctl_name;	/* edac controller  name */
	const char *dev_name;	/* pci/platform/etc... name */

	void *pvt_info;		/* pointer to 'private driver' info */

	unsigned long start_time;	/* edac_pci load start time (jiffies) */

	struct completion complete;

	/* sysfs top name under 'edac' directory
	 * and instance name:
	 *      cpu/cpu0/...
	 *      cpu/cpu1/...
	 *      cpu/cpu2/...
	 *      ...
	 */
	char name[EDAC_DEVICE_NAME_LEN + 1];

	/* Event counters for the this whole EDAC Device */
	struct edac_pci_counter counters;

	/* edac sysfs device control for the 'name'
	 * device this structure controls
	 */
	struct kobject kobj;
	struct completion kobj_complete;
};

#define to_edac_pci_ctl_work(w) \
		container_of(w, struct edac_pci_ctl_info,work)

/* write all or some bits in a byte-register*/
static inline void pci_write_bits8(struct pci_dev *pdev, int offset, u8 value,
				   u8 mask)
{
	if (mask != 0xff) {
		u8 buf;

		pci_read_config_byte(pdev, offset, &buf);
		value &= mask;
		buf &= ~mask;
		value |= buf;
	}

	pci_write_config_byte(pdev, offset, value);
}

/* write all or some bits in a word-register*/
static inline void pci_write_bits16(struct pci_dev *pdev, int offset,
				    u16 value, u16 mask)
{
	if (mask != 0xffff) {
		u16 buf;

		pci_read_config_word(pdev, offset, &buf);
		value &= mask;
		buf &= ~mask;
		value |= buf;
	}

	pci_write_config_word(pdev, offset, value);
}

/*
 * pci_write_bits32
 *
 * edac local routine to do pci_write_config_dword, but adds
 * a mask parameter. If mask is all ones, ignore the mask.
 * Otherwise utilize the mask to isolate specified bits
 *
 * write all or some bits in a dword-register
 */
static inline void pci_write_bits32(struct pci_dev *pdev, int offset,
				    u32 value, u32 mask)
{
	if (mask != 0xffffffff) {
		u32 buf;

		pci_read_config_dword(pdev, offset, &buf);
		value &= mask;
		buf &= ~mask;
		value |= buf;
	}

	pci_write_config_dword(pdev, offset, value);
}

#endif				/* CONFIG_PCI */

extern struct mem_ctl_info *edac_mc_alloc(unsigned sz_pvt, unsigned nr_csrows,
					  unsigned nr_chans, int edac_index);
extern int edac_mc_add_mc(struct mem_ctl_info *mci);
extern void edac_mc_free(struct mem_ctl_info *mci);
extern struct mem_ctl_info *edac_mc_find(int idx);
extern struct mem_ctl_info *find_mci_by_dev(struct device *dev);
extern struct mem_ctl_info *edac_mc_del_mc(struct device *dev);
extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci,
				      unsigned long page);

/*
 * The no info errors are used when error overflows are reported.
 * There are a limited number of error logging registers that can
 * be exausted.  When all registers are exhausted and an additional
 * error occurs then an error overflow register records that an
 * error occurred and the type of error, but doesn't have any
 * further information.  The ce/ue versions make for cleaner
 * reporting logic and function interface - reduces conditional
 * statement clutter and extra function arguments.
 */
extern void edac_mc_handle_ce(struct mem_ctl_info *mci,
			      unsigned long page_frame_number,
			      unsigned long offset_in_page,
			      unsigned long syndrome, int row, int channel,
			      const char *msg);
extern void edac_mc_handle_ce_no_info(struct mem_ctl_info *mci,
				      const char *msg);
extern void edac_mc_handle_ue(struct mem_ctl_info *mci,
			      unsigned long page_frame_number,
			      unsigned long offset_in_page, int row,
			      const char *msg);
extern void edac_mc_handle_ue_no_info(struct mem_ctl_info *mci,
				      const char *msg);
extern void edac_mc_handle_fbd_ue(struct mem_ctl_info *mci, unsigned int csrow,
				  unsigned int channel0, unsigned int channel1,
				  char *msg);
extern void edac_mc_handle_fbd_ce(struct mem_ctl_info *mci, unsigned int csrow,
				  unsigned int channel, char *msg);

/*
 * edac_device APIs
 */
extern int edac_device_add_device(struct edac_device_ctl_info *edac_dev);
extern struct edac_device_ctl_info *edac_device_del_device(struct device *dev);
extern void edac_device_handle_ue(struct edac_device_ctl_info *edac_dev,
				int inst_nr, int block_nr, const char *msg);
extern void edac_device_handle_ce(struct edac_device_ctl_info *edac_dev,
				int inst_nr, int block_nr, const char *msg);
extern int edac_device_alloc_index(void);

/*
 * edac_pci APIs
 */
extern struct edac_pci_ctl_info *edac_pci_alloc_ctl_info(unsigned int sz_pvt,
				const char *edac_pci_name);

extern void edac_pci_free_ctl_info(struct edac_pci_ctl_info *pci);

extern void edac_pci_reset_delay_period(struct edac_pci_ctl_info *pci,
				unsigned long value);

extern int edac_pci_alloc_index(void);
extern int edac_pci_add_device(struct edac_pci_ctl_info *pci, int edac_idx);
extern struct edac_pci_ctl_info *edac_pci_del_device(struct device *dev);

extern struct edac_pci_ctl_info *edac_pci_create_generic_ctl(
				struct device *dev,
				const char *mod_name);

extern void edac_pci_release_generic_ctl(struct edac_pci_ctl_info *pci);
extern int edac_pci_create_sysfs(struct edac_pci_ctl_info *pci);
extern void edac_pci_remove_sysfs(struct edac_pci_ctl_info *pci);

/*
 * edac misc APIs
 */
extern char *edac_op_state_to_string(int op_state);

#endif				/* _EDAC_CORE_H_ */
Commit	Line	Data
7c9281d7 DT	1	/*
	2	* Defines, structures, APIs for edac_core module
	3	*
	4	* (C) 2007 Linux Networx (http://lnxi.com)
	5	* This file may be distributed under the terms of the
	6	* GNU General Public License.
	7	*
	8	* Written by Thayne Harbaugh
	9	* Based on work by Dan Hollis <goemon at anime dot net> and others.
	10	* http://www.anime.net/~goemon/linux-ecc/
	11	*
	12	* NMI handling support added by
	13	* Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>
	14	*
	15	* Refactored for multi-source files:
	16	* Doug Thompson <norsk5@xmission.com>
	17	*
	18	*/
	19
	20	#ifndef _EDAC_CORE_H_
	21	#define _EDAC_CORE_H_
	22
	23	#include <linux/kernel.h>
	24	#include <linux/types.h>
	25	#include <linux/module.h>
	26	#include <linux/spinlock.h>
	27	#include <linux/smp.h>
	28	#include <linux/pci.h>
	29	#include <linux/time.h>
	30	#include <linux/nmi.h>
	31	#include <linux/rcupdate.h>
	32	#include <linux/completion.h>
	33	#include <linux/kobject.h>
	34	#include <linux/platform_device.h>
e27e3dac DT	35	#include <linux/sysdev.h>
e27e3dac DT	36	#include <linux/workqueue.h>
ddeb3547	37	#include <linux/edac.h>
7c9281d7	38
e27e3dac DT	39	#define EDAC_DEVICE_NAME_LEN 31
e27e3dac DT	40	#define EDAC_ATTRIB_VALUE_LEN 15
7c9281d7 DT	41
7c9281d7 DT	42	#if PAGE_SHIFT < 20
76f04f25 AK	43	#define PAGES_TO_MiB(pages) ((pages) >> (20 - PAGE_SHIFT))
76f04f25 AK	44	#define MiB_TO_PAGES(mb) ((mb) << (20 - PAGE_SHIFT))
7c9281d7	45	#else /* PAGE_SHIFT > 20 */
76f04f25	46	#define PAGES_TO_MiB(pages) ((pages) << (PAGE_SHIFT - 20))
e9144601	47	#define MiB_TO_PAGES(mb) ((mb) >> (PAGE_SHIFT - 20))
7c9281d7 DT	48	#endif
	49
	50	#define edac_printk(level, prefix, fmt, arg...) \
	51	printk(level "EDAC " prefix ": " fmt, ##arg)
	52
	53	#define edac_mc_printk(mci, level, fmt, arg...) \
	54	printk(level "EDAC MC%d: " fmt, mci->mc_idx, ##arg)
	55
	56	#define edac_mc_chipset_printk(mci, level, prefix, fmt, arg...) \
	57	printk(level "EDAC " prefix " MC%d: " fmt, mci->mc_idx, ##arg)
	58
e27e3dac DT	59	#define edac_device_printk(ctl, level, fmt, arg...) \
	60	printk(level "EDAC DEVICE%d: " fmt, ctl->dev_idx, ##arg)
	61
91b99041 DJ	62	#define edac_pci_printk(ctl, level, fmt, arg...) \
	63	printk(level "EDAC PCI%d: " fmt, ctl->pci_idx, ##arg)
	64
7c9281d7 DT	65	/* prefixes for edac_printk() and edac_mc_printk() */
	66	#define EDAC_MC "MC"
	67	#define EDAC_PCI "PCI"
	68	#define EDAC_DEBUG "DEBUG"
	69
24f9a7fe BP	70	extern const char *edac_mem_types[];
24f9a7fe BP	71
7c9281d7 DT	72	#ifdef CONFIG_EDAC_DEBUG
	73	extern int edac_debug_level;
	74
d357cbb4 BP	75	#define edac_debug_printk(level, fmt, arg...) \
	76	do { \
	77	if (level <= edac_debug_level) \
	78	edac_printk(KERN_DEBUG, EDAC_DEBUG, \
	79	"%s: " fmt, __func__, ##arg); \
cc18e3cd	80	} while (0)
7c9281d7 DT	81
	82	#define debugf0( ... ) edac_debug_printk(0, __VA_ARGS__ )
	83	#define debugf1( ... ) edac_debug_printk(1, __VA_ARGS__ )
	84	#define debugf2( ... ) edac_debug_printk(2, __VA_ARGS__ )
	85	#define debugf3( ... ) edac_debug_printk(3, __VA_ARGS__ )
	86	#define debugf4( ... ) edac_debug_printk(4, __VA_ARGS__ )
	87
079708b9	88	#else /* !CONFIG_EDAC_DEBUG */
7c9281d7 DT	89
	90	#define debugf0( ... )
	91	#define debugf1( ... )
	92	#define debugf2( ... )
	93	#define debugf3( ... )
	94	#define debugf4( ... )
	95
079708b9	96	#endif /* !CONFIG_EDAC_DEBUG */
7c9281d7	97
7c9281d7 DT	98	#define PCI_VEND_DEV(vend, dev) PCI_VENDOR_ID_ ## vend, \
	99	PCI_DEVICE_ID_ ## vend ## _ ## dev
	100
17aa7e03	101	#define edac_dev_name(dev) (dev)->dev_name
7c9281d7	102
e27e3dac	103	/*
42a8e397	104	* The following are the structures to provide for a generic
e27e3dac DT	105	* or abstract 'edac_device'. This set of structures and the
	106	* code that implements the APIs for the same, provide for
	107	* registering EDAC type devices which are NOT standard memory.
	108	*
	109	* CPU caches (L1 and L2)
	110	* DMA engines
	111	* Core CPU swithces
	112	* Fabric switch units
	113	* PCIe interface controllers
	114	* other EDAC/ECC type devices that can be monitored for
	115	* errors, etc.
	116	*
	117	* It allows for a 2 level set of hiearchry. For example:
	118	*
	119	* cache could be composed of L1, L2 and L3 levels of cache.
	120	* Each CPU core would have its own L1 cache, while sharing
	121	* L2 and maybe L3 caches.
	122	*
	123	* View them arranged, via the sysfs presentation:
	124	* /sys/devices/system/edac/..
	125	*
	126	* mc/ <existing memory device directory>
	127	* cpu/cpu0/.. <L1 and L2 block directory>
	128	* /L1-cache/ce_count
	129	* /ue_count
	130	* /L2-cache/ce_count
	131	* /ue_count
	132	* cpu/cpu1/.. <L1 and L2 block directory>
	133	* /L1-cache/ce_count
	134	* /ue_count
	135	* /L2-cache/ce_count
	136	* /ue_count
	137	* ...
	138	*
	139	* the L1 and L2 directories would be "edac_device_block's"
	140	*/
	141
	142	struct edac_device_counter {
079708b9 DT	143	u32 ue_count;
079708b9 DT	144	u32 ce_count;
e27e3dac DT	145	};
e27e3dac DT	146
fd309a9d DT	147	/* forward reference */
	148	struct edac_device_ctl_info;
	149	struct edac_device_block;
e27e3dac	150
fd309a9d DT	151	/* edac_dev_sysfs_attribute structure
	152	* used for driver sysfs attributes in mem_ctl_info
	153	* for extra controls and attributes:
	154	* like high level error Injection controls
	155	*/
	156	struct edac_dev_sysfs_attribute {
	157	struct attribute attr;
	158	ssize_t (show)(struct edac_device_ctl_info , char *);
	159	ssize_t (store)(struct edac_device_ctl_info , const char *, size_t);
e27e3dac DT	160	};
e27e3dac DT	161
fd309a9d	162	/* edac_dev_sysfs_block_attribute structure
b2a4ac0c	163	*
fd309a9d	164	* used in leaf 'block' nodes for adding controls/attributes
b2a4ac0c DT	165	*
	166	* each block in each instance of the containing control structure
	167	* can have an array of the following. The show and store functions
	168	* will be filled in with the show/store function in the
	169	* low level driver.
	170	*
	171	* The 'value' field will be the actual value field used for
	172	* counting
e27e3dac	173	*/
fd309a9d DT	174	struct edac_dev_sysfs_block_attribute {
	175	struct attribute attr;
	176	ssize_t (show)(struct kobject , struct attribute , char );
	177	ssize_t (store)(struct kobject , struct attribute *,
	178	const char *, size_t);
	179	struct edac_device_block *block;
	180
fd309a9d	181	unsigned int value;
e27e3dac DT	182	};
	183
	184	/* device block control structure */
	185	struct edac_device_block {
	186	struct edac_device_instance instance; / Up Pointer */
079708b9	187	char name[EDAC_DEVICE_NAME_LEN + 1];
e27e3dac DT	188
	189	struct edac_device_counter counters; /* basic UE and CE counters */
	190
079708b9	191	int nr_attribs; /* how many attributes */
fd309a9d DT	192
	193	/* this block's attributes, could be NULL */
	194	struct edac_dev_sysfs_block_attribute *block_attributes;
e27e3dac DT	195
	196	/* edac sysfs device control */
	197	struct kobject kobj;
e27e3dac DT	198	};
	199
	200	/* device instance control structure */
	201	struct edac_device_instance {
	202	struct edac_device_ctl_info ctl; / Up pointer */
	203	char name[EDAC_DEVICE_NAME_LEN + 4];
	204
	205	struct edac_device_counter counters; /* instance counters */
	206
079708b9	207	u32 nr_blocks; /* how many blocks */
e27e3dac DT	208	struct edac_device_block blocks; / block array */
	209
	210	/* edac sysfs device control */
	211	struct kobject kobj;
e27e3dac DT	212	};
e27e3dac DT	213
42a8e397	214
e27e3dac DT	215	/*
	216	* Abstract edac_device control info structure
	217	*
	218	*/
	219	struct edac_device_ctl_info {
	220	/* for global list of edac_device_ctl_info structs */
	221	struct list_head link;
	222
1c3631ff DT	223	struct module owner; / Module owner of this control struct */
1c3631ff DT	224
e27e3dac DT	225	int dev_idx;
	226
	227	/* Per instance controls for this edac_device */
	228	int log_ue; /* boolean for logging UEs */
	229	int log_ce; /* boolean for logging CEs */
	230	int panic_on_ue; /* boolean for panic'ing on an UE */
	231	unsigned poll_msec; /* number of milliseconds to poll interval */
	232	unsigned long delay; /* number of jiffies for poll_msec */
	233
42a8e397 DT	234	/* Additional top controller level attributes, but specified
	235	* by the low level driver.
	236	*
	237	* Set by the low level driver to provide attributes at the
	238	* controller level, same level as 'ue_count' and 'ce_count' above.
	239	* An array of structures, NULL terminated
	240	*
	241	* If attributes are desired, then set to array of attributes
	242	* If no attributes are desired, leave NULL
	243	*/
	244	struct edac_dev_sysfs_attribute *sysfs_attributes;
	245
	246	/* pointer to main 'edac' class in sysfs */
	247	struct sysdev_class *edac_class;
e27e3dac DT	248
	249	/* the internal state of this controller instance */
	250	int op_state;
e27e3dac	251	/* work struct for this instance */
e27e3dac	252	struct delayed_work work;
e27e3dac DT	253
e27e3dac DT	254	/* pointer to edac polling checking routine:
079708b9 DT	255	* If NOT NULL: points to polling check routine
	256	* If NULL: Then assumes INTERRUPT operation, where
	257	* MC driver will receive events
e27e3dac DT	258	*/
	259	void (edac_check) (struct edac_device_ctl_info edac_dev);
	260
	261	struct device dev; / pointer to device structure */
	262
	263	const char mod_name; / module name */
	264	const char ctl_name; / edac controller name */
c4192705	265	const char dev_name; / pci/platform/etc... name */
e27e3dac DT	266
	267	void pvt_info; / pointer to 'private driver' info */
	268
079708b9	269	unsigned long start_time; /* edac_device load start time (jiffies) */
e27e3dac	270
1c3631ff	271	struct completion removal_complete;
e27e3dac DT	272
	273	/* sysfs top name under 'edac' directory
	274	* and instance name:
079708b9 DT	275	* cpu/cpu0/...
	276	* cpu/cpu1/...
	277	* cpu/cpu2/...
	278	* ...
e27e3dac DT	279	*/
	280	char name[EDAC_DEVICE_NAME_LEN + 1];
	281
	282	/* Number of instances supported on this control structure
	283	* and the array of those instances
	284	*/
	285	u32 nr_instances;
	286	struct edac_device_instance *instances;
	287
	288	/* Event counters for the this whole EDAC Device */
	289	struct edac_device_counter counters;
	290
	291	/* edac sysfs device control for the 'name'
	292	* device this structure controls
	293	*/
	294	struct kobject kobj;
e27e3dac DT	295	};
	296
	297	/* To get from the instance's wq to the beginning of the ctl structure */
81d87cb1 DJ	298	#define to_edac_mem_ctl_work(w) \
	299	container_of(w, struct mem_ctl_info, work)
	300
e27e3dac DT	301	#define to_edac_device_ctl_work(w) \
	302	container_of(w,struct edac_device_ctl_info,work)
	303
e27e3dac DT	304	/*
	305	* The alloc() and free() functions for the 'edac_device' control info
	306	* structure. A MC driver will allocate one of these for each edac_device
	307	* it is going to control/register with the EDAC CORE.
	308	*/
	309	extern struct edac_device_ctl_info *edac_device_alloc_ctl_info(
079708b9	310	unsigned sizeof_private,
fd309a9d DT	311	char *edac_device_name, unsigned nr_instances,
fd309a9d DT	312	char *edac_block_name, unsigned nr_blocks,
079708b9	313	unsigned offset_value,
fd309a9d	314	struct edac_dev_sysfs_block_attribute *block_attributes,
d45e7823 DT	315	unsigned nr_attribs,
d45e7823 DT	316	int device_index);
e27e3dac DT	317
	318	/* The offset value can be:
	319	* -1 indicating no offset value
	320	* 0 for zero-based block numbers
	321	* 1 for 1-based block number
	322	* other for other-based block number
	323	*/
	324	#define BLOCK_OFFSET_VALUE_OFF ((unsigned) -1)
	325
079708b9	326	extern void edac_device_free_ctl_info(struct edac_device_ctl_info *ctl_info);
e27e3dac	327
7c9281d7 DT	328	#ifdef CONFIG_PCI
7c9281d7 DT	329
91b99041	330	struct edac_pci_counter {
079708b9 DT	331	atomic_t pe_count;
079708b9 DT	332	atomic_t npe_count;
91b99041 DJ	333	};
	334
	335	/*
	336	* Abstract edac_pci control info structure
	337	*
	338	*/
	339	struct edac_pci_ctl_info {
	340	/* for global list of edac_pci_ctl_info structs */
	341	struct list_head link;
	342
	343	int pci_idx;
	344
91b99041 DJ	345	struct sysdev_class edac_class; / pointer to class */
	346
	347	/* the internal state of this controller instance */
	348	int op_state;
	349	/* work struct for this instance */
91b99041	350	struct delayed_work work;
91b99041 DJ	351
91b99041 DJ	352	/* pointer to edac polling checking routine:
079708b9 DT	353	* If NOT NULL: points to polling check routine
	354	* If NULL: Then assumes INTERRUPT operation, where
	355	* MC driver will receive events
91b99041 DJ	356	*/
	357	void (edac_check) (struct edac_pci_ctl_info edac_dev);
	358
	359	struct device dev; / pointer to device structure */
	360
	361	const char mod_name; / module name */
	362	const char ctl_name; / edac controller name */
	363	const char dev_name; / pci/platform/etc... name */
	364
	365	void pvt_info; / pointer to 'private driver' info */
	366
079708b9	367	unsigned long start_time; /* edac_pci load start time (jiffies) */
91b99041	368
91b99041 DJ	369	struct completion complete;
	370
	371	/* sysfs top name under 'edac' directory
	372	* and instance name:
079708b9 DT	373	* cpu/cpu0/...
	374	* cpu/cpu1/...
	375	* cpu/cpu2/...
	376	* ...
91b99041 DJ	377	*/
	378	char name[EDAC_DEVICE_NAME_LEN + 1];
	379
	380	/* Event counters for the this whole EDAC Device */
	381	struct edac_pci_counter counters;
	382
	383	/* edac sysfs device control for the 'name'
	384	* device this structure controls
	385	*/
	386	struct kobject kobj;
	387	struct completion kobj_complete;
	388	};
	389
	390	#define to_edac_pci_ctl_work(w) \
	391	container_of(w, struct edac_pci_ctl_info,work)
	392
7c9281d7 DT	393	/* write all or some bits in a byte-register*/
7c9281d7 DT	394	static inline void pci_write_bits8(struct pci_dev *pdev, int offset, u8 value,
079708b9	395	u8 mask)
7c9281d7 DT	396	{
	397	if (mask != 0xff) {
	398	u8 buf;
	399
	400	pci_read_config_byte(pdev, offset, &buf);
	401	value &= mask;
	402	buf &= ~mask;
	403	value \|= buf;
	404	}
	405
	406	pci_write_config_byte(pdev, offset, value);
	407	}
	408
	409	/* write all or some bits in a word-register*/
	410	static inline void pci_write_bits16(struct pci_dev *pdev, int offset,
079708b9	411	u16 value, u16 mask)
7c9281d7 DT	412	{
	413	if (mask != 0xffff) {
	414	u16 buf;
	415
	416	pci_read_config_word(pdev, offset, &buf);
	417	value &= mask;
	418	buf &= ~mask;
	419	value \|= buf;
	420	}
	421
	422	pci_write_config_word(pdev, offset, value);
	423	}
	424
e6da46b2 JH	425	/*
	426	* pci_write_bits32
	427	*
	428	* edac local routine to do pci_write_config_dword, but adds
	429	* a mask parameter. If mask is all ones, ignore the mask.
	430	* Otherwise utilize the mask to isolate specified bits
	431	*
	432	* write all or some bits in a dword-register
	433	*/
7c9281d7	434	static inline void pci_write_bits32(struct pci_dev *pdev, int offset,
079708b9	435	u32 value, u32 mask)
7c9281d7	436	{
e6da46b2	437	if (mask != 0xffffffff) {
7c9281d7 DT	438	u32 buf;
	439
	440	pci_read_config_dword(pdev, offset, &buf);
	441	value &= mask;
	442	buf &= ~mask;
	443	value \|= buf;
	444	}
	445
	446	pci_write_config_dword(pdev, offset, value);
	447	}
	448
079708b9	449	#endif /* CONFIG_PCI */
7c9281d7	450
b8f6f975 DT	451	extern struct mem_ctl_info *edac_mc_alloc(unsigned sz_pvt, unsigned nr_csrows,
	452	unsigned nr_chans, int edac_index);
	453	extern int edac_mc_add_mc(struct mem_ctl_info *mci);
	454	extern void edac_mc_free(struct mem_ctl_info *mci);
079708b9	455	extern struct mem_ctl_info *edac_mc_find(int idx);
939747bd	456	extern struct mem_ctl_info find_mci_by_dev(struct device dev);
079708b9	457	extern struct mem_ctl_info edac_mc_del_mc(struct device dev);
7c9281d7	458	extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci,
079708b9	459	unsigned long page);
7c9281d7 DT	460
	461	/*
	462	* The no info errors are used when error overflows are reported.
	463	* There are a limited number of error logging registers that can
	464	* be exausted. When all registers are exhausted and an additional
	465	* error occurs then an error overflow register records that an
25985edc	466	* error occurred and the type of error, but doesn't have any
7c9281d7 DT	467	* further information. The ce/ue versions make for cleaner
	468	* reporting logic and function interface - reduces conditional
	469	* statement clutter and extra function arguments.
	470	*/
	471	extern void edac_mc_handle_ce(struct mem_ctl_info *mci,
079708b9 DT	472	unsigned long page_frame_number,
	473	unsigned long offset_in_page,
	474	unsigned long syndrome, int row, int channel,
	475	const char *msg);
7c9281d7	476	extern void edac_mc_handle_ce_no_info(struct mem_ctl_info *mci,
079708b9	477	const char *msg);
7c9281d7	478	extern void edac_mc_handle_ue(struct mem_ctl_info *mci,
079708b9 DT	479	unsigned long page_frame_number,
	480	unsigned long offset_in_page, int row,
	481	const char *msg);
7c9281d7	482	extern void edac_mc_handle_ue_no_info(struct mem_ctl_info *mci,
079708b9 DT	483	const char *msg);
	484	extern void edac_mc_handle_fbd_ue(struct mem_ctl_info *mci, unsigned int csrow,
	485	unsigned int channel0, unsigned int channel1,
	486	char *msg);
	487	extern void edac_mc_handle_fbd_ce(struct mem_ctl_info *mci, unsigned int csrow,
	488	unsigned int channel, char *msg);
7c9281d7 DT	489
7c9281d7 DT	490	/*
e27e3dac	491	* edac_device APIs
7c9281d7	492	*/
d45e7823	493	extern int edac_device_add_device(struct edac_device_ctl_info *edac_dev);
079708b9	494	extern struct edac_device_ctl_info edac_device_del_device(struct device dev);
e27e3dac	495	extern void edac_device_handle_ue(struct edac_device_ctl_info *edac_dev,
b8f6f975	496	int inst_nr, int block_nr, const char *msg);
e27e3dac	497	extern void edac_device_handle_ce(struct edac_device_ctl_info *edac_dev,
b8f6f975	498	int inst_nr, int block_nr, const char *msg);
1dc9b70d	499	extern int edac_device_alloc_index(void);
e27e3dac	500
91b99041 DJ	501	/*
	502	* edac_pci APIs
	503	*/
b8f6f975 DT	504	extern struct edac_pci_ctl_info *edac_pci_alloc_ctl_info(unsigned int sz_pvt,
b8f6f975 DT	505	const char *edac_pci_name);
91b99041 DJ	506
	507	extern void edac_pci_free_ctl_info(struct edac_pci_ctl_info *pci);
	508
b8f6f975 DT	509	extern void edac_pci_reset_delay_period(struct edac_pci_ctl_info *pci,
b8f6f975 DT	510	unsigned long value);
91b99041	511
8641a384	512	extern int edac_pci_alloc_index(void);
91b99041	513	extern int edac_pci_add_device(struct edac_pci_ctl_info *pci, int edac_idx);
079708b9	514	extern struct edac_pci_ctl_info edac_pci_del_device(struct device dev);
91b99041	515
b8f6f975 DT	516	extern struct edac_pci_ctl_info *edac_pci_create_generic_ctl(
	517	struct device *dev,
	518	const char *mod_name);
91b99041 DJ	519
	520	extern void edac_pci_release_generic_ctl(struct edac_pci_ctl_info *pci);
	521	extern int edac_pci_create_sysfs(struct edac_pci_ctl_info *pci);
	522	extern void edac_pci_remove_sysfs(struct edac_pci_ctl_info *pci);
	523
	524	/*
	525	* edac misc APIs
	526	*/
494d0d55	527	extern char *edac_op_state_to_string(int op_state);
7c9281d7 DT	528
7c9281d7 DT	529	#endif /* _EDAC_CORE_H_ */