Commit | Line | Data |
---|---|---|
da9bb1d2 AC |
1 | /* |
2 | * edac_mc kernel module | |
49c0dab7 | 3 | * (C) 2005, 2006 Linux Networx (http://lnxi.com) |
da9bb1d2 AC |
4 | * This file may be distributed under the terms of the |
5 | * GNU General Public License. | |
6 | * | |
7 | * Written by Thayne Harbaugh | |
8 | * Based on work by Dan Hollis <goemon at anime dot net> and others. | |
9 | * http://www.anime.net/~goemon/linux-ecc/ | |
10 | * | |
11 | * Modified by Dave Peterson and Doug Thompson | |
12 | * | |
13 | */ | |
14 | ||
da9bb1d2 AC |
15 | #include <linux/module.h> |
16 | #include <linux/proc_fs.h> | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/types.h> | |
19 | #include <linux/smp.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/sysctl.h> | |
22 | #include <linux/highmem.h> | |
23 | #include <linux/timer.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/jiffies.h> | |
26 | #include <linux/spinlock.h> | |
27 | #include <linux/list.h> | |
da9bb1d2 | 28 | #include <linux/ctype.h> |
c0d12172 | 29 | #include <linux/edac.h> |
53f2d028 | 30 | #include <linux/bitops.h> |
da9bb1d2 AC |
31 | #include <asm/uaccess.h> |
32 | #include <asm/page.h> | |
33 | #include <asm/edac.h> | |
20bcb7a8 | 34 | #include "edac_core.h" |
7c9281d7 | 35 | #include "edac_module.h" |
53f2d028 MCC |
36 | #include <ras/ras_event.h> |
37 | ||
da9bb1d2 | 38 | /* lock to memory controller's control array */ |
63b7df91 | 39 | static DEFINE_MUTEX(mem_ctls_mutex); |
ff6ac2a6 | 40 | static LIST_HEAD(mc_devices); |
da9bb1d2 | 41 | |
80cc7d87 MCC |
42 | /* |
43 | * Used to lock EDAC MC to just one module, avoiding two drivers e. g. | |
44 | * apei/ghes and i7core_edac to be used at the same time. | |
45 | */ | |
46 | static void const *edac_mc_owner; | |
47 | ||
88d84ac9 BP |
48 | static struct bus_type mc_bus[EDAC_MAX_MCS]; |
49 | ||
6e84d359 MCC |
50 | unsigned edac_dimm_info_location(struct dimm_info *dimm, char *buf, |
51 | unsigned len) | |
52 | { | |
53 | struct mem_ctl_info *mci = dimm->mci; | |
54 | int i, n, count = 0; | |
55 | char *p = buf; | |
56 | ||
57 | for (i = 0; i < mci->n_layers; i++) { | |
58 | n = snprintf(p, len, "%s %d ", | |
59 | edac_layer_name[mci->layers[i].type], | |
60 | dimm->location[i]); | |
61 | p += n; | |
62 | len -= n; | |
63 | count += n; | |
64 | if (!len) | |
65 | break; | |
66 | } | |
67 | ||
68 | return count; | |
69 | } | |
70 | ||
da9bb1d2 AC |
71 | #ifdef CONFIG_EDAC_DEBUG |
72 | ||
a4b4be3f | 73 | static void edac_mc_dump_channel(struct rank_info *chan) |
da9bb1d2 | 74 | { |
6e84d359 MCC |
75 | edac_dbg(4, " channel->chan_idx = %d\n", chan->chan_idx); |
76 | edac_dbg(4, " channel = %p\n", chan); | |
77 | edac_dbg(4, " channel->csrow = %p\n", chan->csrow); | |
78 | edac_dbg(4, " channel->dimm = %p\n", chan->dimm); | |
4275be63 MCC |
79 | } |
80 | ||
6e84d359 | 81 | static void edac_mc_dump_dimm(struct dimm_info *dimm, int number) |
4275be63 | 82 | { |
6e84d359 MCC |
83 | char location[80]; |
84 | ||
85 | edac_dimm_info_location(dimm, location, sizeof(location)); | |
86 | ||
87 | edac_dbg(4, "%s%i: %smapped as virtual row %d, chan %d\n", | |
9713faec | 88 | dimm->mci->csbased ? "rank" : "dimm", |
6e84d359 MCC |
89 | number, location, dimm->csrow, dimm->cschannel); |
90 | edac_dbg(4, " dimm = %p\n", dimm); | |
91 | edac_dbg(4, " dimm->label = '%s'\n", dimm->label); | |
92 | edac_dbg(4, " dimm->nr_pages = 0x%x\n", dimm->nr_pages); | |
93 | edac_dbg(4, " dimm->grain = %d\n", dimm->grain); | |
94 | edac_dbg(4, " dimm->nr_pages = 0x%x\n", dimm->nr_pages); | |
da9bb1d2 AC |
95 | } |
96 | ||
2da1c119 | 97 | static void edac_mc_dump_csrow(struct csrow_info *csrow) |
da9bb1d2 | 98 | { |
6e84d359 MCC |
99 | edac_dbg(4, "csrow->csrow_idx = %d\n", csrow->csrow_idx); |
100 | edac_dbg(4, " csrow = %p\n", csrow); | |
101 | edac_dbg(4, " csrow->first_page = 0x%lx\n", csrow->first_page); | |
102 | edac_dbg(4, " csrow->last_page = 0x%lx\n", csrow->last_page); | |
103 | edac_dbg(4, " csrow->page_mask = 0x%lx\n", csrow->page_mask); | |
104 | edac_dbg(4, " csrow->nr_channels = %d\n", csrow->nr_channels); | |
105 | edac_dbg(4, " csrow->channels = %p\n", csrow->channels); | |
106 | edac_dbg(4, " csrow->mci = %p\n", csrow->mci); | |
da9bb1d2 AC |
107 | } |
108 | ||
2da1c119 | 109 | static void edac_mc_dump_mci(struct mem_ctl_info *mci) |
da9bb1d2 | 110 | { |
956b9ba1 JP |
111 | edac_dbg(3, "\tmci = %p\n", mci); |
112 | edac_dbg(3, "\tmci->mtype_cap = %lx\n", mci->mtype_cap); | |
113 | edac_dbg(3, "\tmci->edac_ctl_cap = %lx\n", mci->edac_ctl_cap); | |
114 | edac_dbg(3, "\tmci->edac_cap = %lx\n", mci->edac_cap); | |
115 | edac_dbg(4, "\tmci->edac_check = %p\n", mci->edac_check); | |
116 | edac_dbg(3, "\tmci->nr_csrows = %d, csrows = %p\n", | |
117 | mci->nr_csrows, mci->csrows); | |
118 | edac_dbg(3, "\tmci->nr_dimms = %d, dimms = %p\n", | |
119 | mci->tot_dimms, mci->dimms); | |
120 | edac_dbg(3, "\tdev = %p\n", mci->pdev); | |
121 | edac_dbg(3, "\tmod_name:ctl_name = %s:%s\n", | |
122 | mci->mod_name, mci->ctl_name); | |
123 | edac_dbg(3, "\tpvt_info = %p\n\n", mci->pvt_info); | |
da9bb1d2 AC |
124 | } |
125 | ||
24f9a7fe BP |
126 | #endif /* CONFIG_EDAC_DEBUG */ |
127 | ||
f4ce6eca | 128 | const char * const edac_mem_types[] = { |
4cfc3a40 BP |
129 | [MEM_EMPTY] = "Empty csrow", |
130 | [MEM_RESERVED] = "Reserved csrow type", | |
131 | [MEM_UNKNOWN] = "Unknown csrow type", | |
132 | [MEM_FPM] = "Fast page mode RAM", | |
133 | [MEM_EDO] = "Extended data out RAM", | |
134 | [MEM_BEDO] = "Burst Extended data out RAM", | |
135 | [MEM_SDR] = "Single data rate SDRAM", | |
136 | [MEM_RDR] = "Registered single data rate SDRAM", | |
137 | [MEM_DDR] = "Double data rate SDRAM", | |
138 | [MEM_RDDR] = "Registered Double data rate SDRAM", | |
139 | [MEM_RMBS] = "Rambus DRAM", | |
140 | [MEM_DDR2] = "Unbuffered DDR2 RAM", | |
141 | [MEM_FB_DDR2] = "Fully buffered DDR2", | |
142 | [MEM_RDDR2] = "Registered DDR2 RAM", | |
143 | [MEM_XDR] = "Rambus XDR", | |
144 | [MEM_DDR3] = "Unbuffered DDR3 RAM", | |
145 | [MEM_RDDR3] = "Registered DDR3 RAM", | |
146 | [MEM_LRDDR3] = "Load-Reduced DDR3 RAM", | |
147 | [MEM_DDR4] = "Unbuffered DDR4 RAM", | |
148 | [MEM_RDDR4] = "Registered DDR4 RAM", | |
239642fe BP |
149 | }; |
150 | EXPORT_SYMBOL_GPL(edac_mem_types); | |
151 | ||
93e4fe64 MCC |
152 | /** |
153 | * edac_align_ptr - Prepares the pointer offsets for a single-shot allocation | |
154 | * @p: pointer to a pointer with the memory offset to be used. At | |
155 | * return, this will be incremented to point to the next offset | |
156 | * @size: Size of the data structure to be reserved | |
157 | * @n_elems: Number of elements that should be reserved | |
da9bb1d2 AC |
158 | * |
159 | * If 'size' is a constant, the compiler will optimize this whole function | |
93e4fe64 MCC |
160 | * down to either a no-op or the addition of a constant to the value of '*p'. |
161 | * | |
162 | * The 'p' pointer is absolutely needed to keep the proper advancing | |
163 | * further in memory to the proper offsets when allocating the struct along | |
164 | * with its embedded structs, as edac_device_alloc_ctl_info() does it | |
165 | * above, for example. | |
166 | * | |
167 | * At return, the pointer 'p' will be incremented to be used on a next call | |
168 | * to this function. | |
da9bb1d2 | 169 | */ |
93e4fe64 | 170 | void *edac_align_ptr(void **p, unsigned size, int n_elems) |
da9bb1d2 AC |
171 | { |
172 | unsigned align, r; | |
93e4fe64 | 173 | void *ptr = *p; |
da9bb1d2 | 174 | |
93e4fe64 MCC |
175 | *p += size * n_elems; |
176 | ||
177 | /* | |
178 | * 'p' can possibly be an unaligned item X such that sizeof(X) is | |
179 | * 'size'. Adjust 'p' so that its alignment is at least as | |
180 | * stringent as what the compiler would provide for X and return | |
181 | * the aligned result. | |
182 | * Here we assume that the alignment of a "long long" is the most | |
da9bb1d2 AC |
183 | * stringent alignment that the compiler will ever provide by default. |
184 | * As far as I know, this is a reasonable assumption. | |
185 | */ | |
186 | if (size > sizeof(long)) | |
187 | align = sizeof(long long); | |
188 | else if (size > sizeof(int)) | |
189 | align = sizeof(long); | |
190 | else if (size > sizeof(short)) | |
191 | align = sizeof(int); | |
192 | else if (size > sizeof(char)) | |
193 | align = sizeof(short); | |
194 | else | |
079708b9 | 195 | return (char *)ptr; |
da9bb1d2 | 196 | |
8447c4d1 | 197 | r = (unsigned long)p % align; |
da9bb1d2 AC |
198 | |
199 | if (r == 0) | |
079708b9 | 200 | return (char *)ptr; |
da9bb1d2 | 201 | |
93e4fe64 MCC |
202 | *p += align - r; |
203 | ||
7391c6dc | 204 | return (void *)(((unsigned long)ptr) + align - r); |
da9bb1d2 AC |
205 | } |
206 | ||
faa2ad09 SR |
207 | static void _edac_mc_free(struct mem_ctl_info *mci) |
208 | { | |
209 | int i, chn, row; | |
210 | struct csrow_info *csr; | |
211 | const unsigned int tot_dimms = mci->tot_dimms; | |
212 | const unsigned int tot_channels = mci->num_cschannel; | |
213 | const unsigned int tot_csrows = mci->nr_csrows; | |
214 | ||
215 | if (mci->dimms) { | |
216 | for (i = 0; i < tot_dimms; i++) | |
217 | kfree(mci->dimms[i]); | |
218 | kfree(mci->dimms); | |
219 | } | |
220 | if (mci->csrows) { | |
221 | for (row = 0; row < tot_csrows; row++) { | |
222 | csr = mci->csrows[row]; | |
223 | if (csr) { | |
224 | if (csr->channels) { | |
225 | for (chn = 0; chn < tot_channels; chn++) | |
226 | kfree(csr->channels[chn]); | |
227 | kfree(csr->channels); | |
228 | } | |
229 | kfree(csr); | |
230 | } | |
231 | } | |
232 | kfree(mci->csrows); | |
233 | } | |
234 | kfree(mci); | |
235 | } | |
236 | ||
da9bb1d2 | 237 | /** |
4275be63 MCC |
238 | * edac_mc_alloc: Allocate and partially fill a struct mem_ctl_info structure |
239 | * @mc_num: Memory controller number | |
240 | * @n_layers: Number of MC hierarchy layers | |
241 | * layers: Describes each layer as seen by the Memory Controller | |
242 | * @size_pvt: size of private storage needed | |
243 | * | |
da9bb1d2 AC |
244 | * |
245 | * Everything is kmalloc'ed as one big chunk - more efficient. | |
246 | * Only can be used if all structures have the same lifetime - otherwise | |
247 | * you have to allocate and initialize your own structures. | |
248 | * | |
249 | * Use edac_mc_free() to free mc structures allocated by this function. | |
250 | * | |
4275be63 MCC |
251 | * NOTE: drivers handle multi-rank memories in different ways: in some |
252 | * drivers, one multi-rank memory stick is mapped as one entry, while, in | |
253 | * others, a single multi-rank memory stick would be mapped into several | |
254 | * entries. Currently, this function will allocate multiple struct dimm_info | |
255 | * on such scenarios, as grouping the multiple ranks require drivers change. | |
256 | * | |
da9bb1d2 | 257 | * Returns: |
ca0907b9 MCC |
258 | * On failure: NULL |
259 | * On success: struct mem_ctl_info pointer | |
da9bb1d2 | 260 | */ |
ca0907b9 MCC |
261 | struct mem_ctl_info *edac_mc_alloc(unsigned mc_num, |
262 | unsigned n_layers, | |
263 | struct edac_mc_layer *layers, | |
264 | unsigned sz_pvt) | |
da9bb1d2 AC |
265 | { |
266 | struct mem_ctl_info *mci; | |
4275be63 | 267 | struct edac_mc_layer *layer; |
de3910eb MCC |
268 | struct csrow_info *csr; |
269 | struct rank_info *chan; | |
a7d7d2e1 | 270 | struct dimm_info *dimm; |
4275be63 MCC |
271 | u32 *ce_per_layer[EDAC_MAX_LAYERS], *ue_per_layer[EDAC_MAX_LAYERS]; |
272 | unsigned pos[EDAC_MAX_LAYERS]; | |
4275be63 MCC |
273 | unsigned size, tot_dimms = 1, count = 1; |
274 | unsigned tot_csrows = 1, tot_channels = 1, tot_errcount = 0; | |
5926ff50 | 275 | void *pvt, *p, *ptr = NULL; |
de3910eb | 276 | int i, j, row, chn, n, len, off; |
4275be63 MCC |
277 | bool per_rank = false; |
278 | ||
279 | BUG_ON(n_layers > EDAC_MAX_LAYERS || n_layers == 0); | |
280 | /* | |
281 | * Calculate the total amount of dimms and csrows/cschannels while | |
282 | * in the old API emulation mode | |
283 | */ | |
284 | for (i = 0; i < n_layers; i++) { | |
285 | tot_dimms *= layers[i].size; | |
286 | if (layers[i].is_virt_csrow) | |
287 | tot_csrows *= layers[i].size; | |
288 | else | |
289 | tot_channels *= layers[i].size; | |
290 | ||
291 | if (layers[i].type == EDAC_MC_LAYER_CHIP_SELECT) | |
292 | per_rank = true; | |
293 | } | |
da9bb1d2 AC |
294 | |
295 | /* Figure out the offsets of the various items from the start of an mc | |
296 | * structure. We want the alignment of each item to be at least as | |
297 | * stringent as what the compiler would provide if we could simply | |
298 | * hardcode everything into a single struct. | |
299 | */ | |
93e4fe64 | 300 | mci = edac_align_ptr(&ptr, sizeof(*mci), 1); |
4275be63 | 301 | layer = edac_align_ptr(&ptr, sizeof(*layer), n_layers); |
4275be63 MCC |
302 | for (i = 0; i < n_layers; i++) { |
303 | count *= layers[i].size; | |
956b9ba1 | 304 | edac_dbg(4, "errcount layer %d size %d\n", i, count); |
4275be63 MCC |
305 | ce_per_layer[i] = edac_align_ptr(&ptr, sizeof(u32), count); |
306 | ue_per_layer[i] = edac_align_ptr(&ptr, sizeof(u32), count); | |
307 | tot_errcount += 2 * count; | |
308 | } | |
309 | ||
956b9ba1 | 310 | edac_dbg(4, "allocating %d error counters\n", tot_errcount); |
93e4fe64 | 311 | pvt = edac_align_ptr(&ptr, sz_pvt, 1); |
079708b9 | 312 | size = ((unsigned long)pvt) + sz_pvt; |
da9bb1d2 | 313 | |
956b9ba1 JP |
314 | edac_dbg(1, "allocating %u bytes for mci data (%d %s, %d csrows/channels)\n", |
315 | size, | |
316 | tot_dimms, | |
317 | per_rank ? "ranks" : "dimms", | |
318 | tot_csrows * tot_channels); | |
de3910eb | 319 | |
8096cfaf DT |
320 | mci = kzalloc(size, GFP_KERNEL); |
321 | if (mci == NULL) | |
da9bb1d2 AC |
322 | return NULL; |
323 | ||
324 | /* Adjust pointers so they point within the memory we just allocated | |
325 | * rather than an imaginary chunk of memory located at address 0. | |
326 | */ | |
4275be63 | 327 | layer = (struct edac_mc_layer *)(((char *)mci) + ((unsigned long)layer)); |
4275be63 MCC |
328 | for (i = 0; i < n_layers; i++) { |
329 | mci->ce_per_layer[i] = (u32 *)((char *)mci + ((unsigned long)ce_per_layer[i])); | |
330 | mci->ue_per_layer[i] = (u32 *)((char *)mci + ((unsigned long)ue_per_layer[i])); | |
331 | } | |
079708b9 | 332 | pvt = sz_pvt ? (((char *)mci) + ((unsigned long)pvt)) : NULL; |
da9bb1d2 | 333 | |
b8f6f975 | 334 | /* setup index and various internal pointers */ |
4275be63 | 335 | mci->mc_idx = mc_num; |
4275be63 | 336 | mci->tot_dimms = tot_dimms; |
da9bb1d2 | 337 | mci->pvt_info = pvt; |
4275be63 MCC |
338 | mci->n_layers = n_layers; |
339 | mci->layers = layer; | |
340 | memcpy(mci->layers, layers, sizeof(*layer) * n_layers); | |
341 | mci->nr_csrows = tot_csrows; | |
342 | mci->num_cschannel = tot_channels; | |
9713faec | 343 | mci->csbased = per_rank; |
da9bb1d2 | 344 | |
a7d7d2e1 | 345 | /* |
de3910eb | 346 | * Alocate and fill the csrow/channels structs |
a7d7d2e1 | 347 | */ |
d3d09e18 | 348 | mci->csrows = kcalloc(tot_csrows, sizeof(*mci->csrows), GFP_KERNEL); |
de3910eb MCC |
349 | if (!mci->csrows) |
350 | goto error; | |
4275be63 | 351 | for (row = 0; row < tot_csrows; row++) { |
de3910eb MCC |
352 | csr = kzalloc(sizeof(**mci->csrows), GFP_KERNEL); |
353 | if (!csr) | |
354 | goto error; | |
355 | mci->csrows[row] = csr; | |
4275be63 MCC |
356 | csr->csrow_idx = row; |
357 | csr->mci = mci; | |
358 | csr->nr_channels = tot_channels; | |
d3d09e18 | 359 | csr->channels = kcalloc(tot_channels, sizeof(*csr->channels), |
de3910eb MCC |
360 | GFP_KERNEL); |
361 | if (!csr->channels) | |
362 | goto error; | |
4275be63 MCC |
363 | |
364 | for (chn = 0; chn < tot_channels; chn++) { | |
de3910eb MCC |
365 | chan = kzalloc(sizeof(**csr->channels), GFP_KERNEL); |
366 | if (!chan) | |
367 | goto error; | |
368 | csr->channels[chn] = chan; | |
da9bb1d2 | 369 | chan->chan_idx = chn; |
4275be63 MCC |
370 | chan->csrow = csr; |
371 | } | |
372 | } | |
373 | ||
374 | /* | |
de3910eb | 375 | * Allocate and fill the dimm structs |
4275be63 | 376 | */ |
d3d09e18 | 377 | mci->dimms = kcalloc(tot_dimms, sizeof(*mci->dimms), GFP_KERNEL); |
de3910eb MCC |
378 | if (!mci->dimms) |
379 | goto error; | |
380 | ||
4275be63 MCC |
381 | memset(&pos, 0, sizeof(pos)); |
382 | row = 0; | |
383 | chn = 0; | |
4275be63 | 384 | for (i = 0; i < tot_dimms; i++) { |
de3910eb MCC |
385 | chan = mci->csrows[row]->channels[chn]; |
386 | off = EDAC_DIMM_OFF(layer, n_layers, pos[0], pos[1], pos[2]); | |
387 | if (off < 0 || off >= tot_dimms) { | |
388 | edac_mc_printk(mci, KERN_ERR, "EDAC core bug: EDAC_DIMM_OFF is trying to do an illegal data access\n"); | |
389 | goto error; | |
390 | } | |
4275be63 | 391 | |
de3910eb | 392 | dimm = kzalloc(sizeof(**mci->dimms), GFP_KERNEL); |
08a4a136 DC |
393 | if (!dimm) |
394 | goto error; | |
de3910eb | 395 | mci->dimms[off] = dimm; |
4275be63 | 396 | dimm->mci = mci; |
4275be63 | 397 | |
5926ff50 MCC |
398 | /* |
399 | * Copy DIMM location and initialize it. | |
400 | */ | |
401 | len = sizeof(dimm->label); | |
402 | p = dimm->label; | |
403 | n = snprintf(p, len, "mc#%u", mc_num); | |
404 | p += n; | |
405 | len -= n; | |
406 | for (j = 0; j < n_layers; j++) { | |
407 | n = snprintf(p, len, "%s#%u", | |
408 | edac_layer_name[layers[j].type], | |
409 | pos[j]); | |
410 | p += n; | |
411 | len -= n; | |
4275be63 MCC |
412 | dimm->location[j] = pos[j]; |
413 | ||
5926ff50 MCC |
414 | if (len <= 0) |
415 | break; | |
416 | } | |
417 | ||
4275be63 MCC |
418 | /* Link it to the csrows old API data */ |
419 | chan->dimm = dimm; | |
420 | dimm->csrow = row; | |
421 | dimm->cschannel = chn; | |
422 | ||
423 | /* Increment csrow location */ | |
24bef66e | 424 | if (layers[0].is_virt_csrow) { |
4275be63 | 425 | chn++; |
24bef66e MCC |
426 | if (chn == tot_channels) { |
427 | chn = 0; | |
428 | row++; | |
429 | } | |
430 | } else { | |
431 | row++; | |
432 | if (row == tot_csrows) { | |
433 | row = 0; | |
434 | chn++; | |
435 | } | |
4275be63 | 436 | } |
a7d7d2e1 | 437 | |
4275be63 MCC |
438 | /* Increment dimm location */ |
439 | for (j = n_layers - 1; j >= 0; j--) { | |
440 | pos[j]++; | |
441 | if (pos[j] < layers[j].size) | |
442 | break; | |
443 | pos[j] = 0; | |
da9bb1d2 AC |
444 | } |
445 | } | |
446 | ||
81d87cb1 | 447 | mci->op_state = OP_ALLOC; |
8096cfaf | 448 | |
da9bb1d2 | 449 | return mci; |
de3910eb MCC |
450 | |
451 | error: | |
faa2ad09 | 452 | _edac_mc_free(mci); |
de3910eb MCC |
453 | |
454 | return NULL; | |
4275be63 | 455 | } |
9110540f | 456 | EXPORT_SYMBOL_GPL(edac_mc_alloc); |
da9bb1d2 | 457 | |
da9bb1d2 | 458 | /** |
8096cfaf DT |
459 | * edac_mc_free |
460 | * 'Free' a previously allocated 'mci' structure | |
da9bb1d2 | 461 | * @mci: pointer to a struct mem_ctl_info structure |
da9bb1d2 AC |
462 | */ |
463 | void edac_mc_free(struct mem_ctl_info *mci) | |
464 | { | |
956b9ba1 | 465 | edac_dbg(1, "\n"); |
bbc560ae | 466 | |
faa2ad09 SR |
467 | /* If we're not yet registered with sysfs free only what was allocated |
468 | * in edac_mc_alloc(). | |
469 | */ | |
470 | if (!device_is_registered(&mci->dev)) { | |
471 | _edac_mc_free(mci); | |
472 | return; | |
473 | } | |
474 | ||
de3910eb | 475 | /* the mci instance is freed here, when the sysfs object is dropped */ |
7a623c03 | 476 | edac_unregister_sysfs(mci); |
da9bb1d2 | 477 | } |
9110540f | 478 | EXPORT_SYMBOL_GPL(edac_mc_free); |
da9bb1d2 | 479 | |
bce19683 | 480 | |
939747bd | 481 | /** |
bce19683 DT |
482 | * find_mci_by_dev |
483 | * | |
484 | * scan list of controllers looking for the one that manages | |
485 | * the 'dev' device | |
939747bd | 486 | * @dev: pointer to a struct device related with the MCI |
bce19683 | 487 | */ |
939747bd | 488 | struct mem_ctl_info *find_mci_by_dev(struct device *dev) |
da9bb1d2 AC |
489 | { |
490 | struct mem_ctl_info *mci; | |
491 | struct list_head *item; | |
492 | ||
956b9ba1 | 493 | edac_dbg(3, "\n"); |
da9bb1d2 AC |
494 | |
495 | list_for_each(item, &mc_devices) { | |
496 | mci = list_entry(item, struct mem_ctl_info, link); | |
497 | ||
fd687502 | 498 | if (mci->pdev == dev) |
da9bb1d2 AC |
499 | return mci; |
500 | } | |
501 | ||
502 | return NULL; | |
503 | } | |
939747bd | 504 | EXPORT_SYMBOL_GPL(find_mci_by_dev); |
da9bb1d2 | 505 | |
81d87cb1 DJ |
506 | /* |
507 | * handler for EDAC to check if NMI type handler has asserted interrupt | |
508 | */ | |
509 | static int edac_mc_assert_error_check_and_clear(void) | |
510 | { | |
66ee2f94 | 511 | int old_state; |
81d87cb1 | 512 | |
079708b9 | 513 | if (edac_op_state == EDAC_OPSTATE_POLL) |
81d87cb1 DJ |
514 | return 1; |
515 | ||
66ee2f94 DJ |
516 | old_state = edac_err_assert; |
517 | edac_err_assert = 0; | |
81d87cb1 | 518 | |
66ee2f94 | 519 | return old_state; |
81d87cb1 DJ |
520 | } |
521 | ||
522 | /* | |
523 | * edac_mc_workq_function | |
524 | * performs the operation scheduled by a workq request | |
525 | */ | |
81d87cb1 DJ |
526 | static void edac_mc_workq_function(struct work_struct *work_req) |
527 | { | |
fbeb4384 | 528 | struct delayed_work *d_work = to_delayed_work(work_req); |
81d87cb1 | 529 | struct mem_ctl_info *mci = to_edac_mem_ctl_work(d_work); |
81d87cb1 DJ |
530 | |
531 | mutex_lock(&mem_ctls_mutex); | |
532 | ||
bf52fa4a DT |
533 | /* if this control struct has movd to offline state, we are done */ |
534 | if (mci->op_state == OP_OFFLINE) { | |
535 | mutex_unlock(&mem_ctls_mutex); | |
536 | return; | |
537 | } | |
538 | ||
81d87cb1 DJ |
539 | /* Only poll controllers that are running polled and have a check */ |
540 | if (edac_mc_assert_error_check_and_clear() && (mci->edac_check != NULL)) | |
541 | mci->edac_check(mci); | |
542 | ||
81d87cb1 DJ |
543 | mutex_unlock(&mem_ctls_mutex); |
544 | ||
545 | /* Reschedule */ | |
4de78c68 | 546 | queue_delayed_work(edac_workqueue, &mci->work, |
052dfb45 | 547 | msecs_to_jiffies(edac_mc_get_poll_msec())); |
81d87cb1 DJ |
548 | } |
549 | ||
550 | /* | |
551 | * edac_mc_workq_setup | |
552 | * initialize a workq item for this mci | |
553 | * passing in the new delay period in msec | |
bf52fa4a DT |
554 | * |
555 | * locking model: | |
556 | * | |
557 | * called with the mem_ctls_mutex held | |
81d87cb1 | 558 | */ |
cb6ef42e BP |
559 | static void edac_mc_workq_setup(struct mem_ctl_info *mci, unsigned msec, |
560 | bool init) | |
81d87cb1 | 561 | { |
956b9ba1 | 562 | edac_dbg(0, "\n"); |
81d87cb1 | 563 | |
bf52fa4a DT |
564 | /* if this instance is not in the POLL state, then simply return */ |
565 | if (mci->op_state != OP_RUNNING_POLL) | |
566 | return; | |
567 | ||
cb6ef42e BP |
568 | if (init) |
569 | INIT_DELAYED_WORK(&mci->work, edac_mc_workq_function); | |
570 | ||
41f63c53 | 571 | mod_delayed_work(edac_workqueue, &mci->work, msecs_to_jiffies(msec)); |
81d87cb1 DJ |
572 | } |
573 | ||
574 | /* | |
575 | * edac_mc_workq_teardown | |
576 | * stop the workq processing on this mci | |
bf52fa4a DT |
577 | * |
578 | * locking model: | |
579 | * | |
580 | * called WITHOUT lock held | |
81d87cb1 | 581 | */ |
bf52fa4a | 582 | static void edac_mc_workq_teardown(struct mem_ctl_info *mci) |
81d87cb1 DJ |
583 | { |
584 | int status; | |
585 | ||
00740c58 BP |
586 | if (mci->op_state != OP_RUNNING_POLL) |
587 | return; | |
588 | ||
bce19683 DT |
589 | status = cancel_delayed_work(&mci->work); |
590 | if (status == 0) { | |
956b9ba1 | 591 | edac_dbg(0, "not canceled, flush the queue\n"); |
bf52fa4a | 592 | |
bce19683 DT |
593 | /* workq instance might be running, wait for it */ |
594 | flush_workqueue(edac_workqueue); | |
81d87cb1 DJ |
595 | } |
596 | } | |
597 | ||
598 | /* | |
bce19683 DT |
599 | * edac_mc_reset_delay_period(unsigned long value) |
600 | * | |
601 | * user space has updated our poll period value, need to | |
602 | * reset our workq delays | |
81d87cb1 | 603 | */ |
9da21b15 | 604 | void edac_mc_reset_delay_period(unsigned long value) |
81d87cb1 | 605 | { |
bce19683 DT |
606 | struct mem_ctl_info *mci; |
607 | struct list_head *item; | |
608 | ||
609 | mutex_lock(&mem_ctls_mutex); | |
610 | ||
bce19683 DT |
611 | list_for_each(item, &mc_devices) { |
612 | mci = list_entry(item, struct mem_ctl_info, link); | |
613 | ||
cb6ef42e | 614 | edac_mc_workq_setup(mci, value, false); |
bce19683 | 615 | } |
81d87cb1 DJ |
616 | |
617 | mutex_unlock(&mem_ctls_mutex); | |
618 | } | |
619 | ||
bce19683 DT |
620 | |
621 | ||
2d7bbb91 DT |
622 | /* Return 0 on success, 1 on failure. |
623 | * Before calling this function, caller must | |
624 | * assign a unique value to mci->mc_idx. | |
bf52fa4a DT |
625 | * |
626 | * locking model: | |
627 | * | |
628 | * called with the mem_ctls_mutex lock held | |
2d7bbb91 | 629 | */ |
079708b9 | 630 | static int add_mc_to_global_list(struct mem_ctl_info *mci) |
da9bb1d2 AC |
631 | { |
632 | struct list_head *item, *insert_before; | |
633 | struct mem_ctl_info *p; | |
da9bb1d2 | 634 | |
2d7bbb91 | 635 | insert_before = &mc_devices; |
da9bb1d2 | 636 | |
fd687502 | 637 | p = find_mci_by_dev(mci->pdev); |
bf52fa4a | 638 | if (unlikely(p != NULL)) |
2d7bbb91 | 639 | goto fail0; |
da9bb1d2 | 640 | |
2d7bbb91 DT |
641 | list_for_each(item, &mc_devices) { |
642 | p = list_entry(item, struct mem_ctl_info, link); | |
da9bb1d2 | 643 | |
2d7bbb91 DT |
644 | if (p->mc_idx >= mci->mc_idx) { |
645 | if (unlikely(p->mc_idx == mci->mc_idx)) | |
646 | goto fail1; | |
da9bb1d2 | 647 | |
2d7bbb91 DT |
648 | insert_before = item; |
649 | break; | |
da9bb1d2 | 650 | } |
da9bb1d2 AC |
651 | } |
652 | ||
653 | list_add_tail_rcu(&mci->link, insert_before); | |
c0d12172 | 654 | atomic_inc(&edac_handlers); |
da9bb1d2 | 655 | return 0; |
2d7bbb91 | 656 | |
052dfb45 | 657 | fail0: |
2d7bbb91 | 658 | edac_printk(KERN_WARNING, EDAC_MC, |
fd687502 | 659 | "%s (%s) %s %s already assigned %d\n", dev_name(p->pdev), |
17aa7e03 | 660 | edac_dev_name(mci), p->mod_name, p->ctl_name, p->mc_idx); |
2d7bbb91 DT |
661 | return 1; |
662 | ||
052dfb45 | 663 | fail1: |
2d7bbb91 | 664 | edac_printk(KERN_WARNING, EDAC_MC, |
052dfb45 DT |
665 | "bug in low-level driver: attempt to assign\n" |
666 | " duplicate mc_idx %d in %s()\n", p->mc_idx, __func__); | |
2d7bbb91 | 667 | return 1; |
da9bb1d2 AC |
668 | } |
669 | ||
80cc7d87 | 670 | static int del_mc_from_global_list(struct mem_ctl_info *mci) |
a1d03fcc | 671 | { |
80cc7d87 | 672 | int handlers = atomic_dec_return(&edac_handlers); |
a1d03fcc | 673 | list_del_rcu(&mci->link); |
e2e77098 LJ |
674 | |
675 | /* these are for safe removal of devices from global list while | |
676 | * NMI handlers may be traversing list | |
677 | */ | |
678 | synchronize_rcu(); | |
679 | INIT_LIST_HEAD(&mci->link); | |
80cc7d87 MCC |
680 | |
681 | return handlers; | |
a1d03fcc DP |
682 | } |
683 | ||
5da0831c DT |
684 | /** |
685 | * edac_mc_find: Search for a mem_ctl_info structure whose index is 'idx'. | |
686 | * | |
687 | * If found, return a pointer to the structure. | |
688 | * Else return NULL. | |
689 | * | |
690 | * Caller must hold mem_ctls_mutex. | |
691 | */ | |
079708b9 | 692 | struct mem_ctl_info *edac_mc_find(int idx) |
5da0831c DT |
693 | { |
694 | struct list_head *item; | |
695 | struct mem_ctl_info *mci; | |
696 | ||
697 | list_for_each(item, &mc_devices) { | |
698 | mci = list_entry(item, struct mem_ctl_info, link); | |
699 | ||
700 | if (mci->mc_idx >= idx) { | |
701 | if (mci->mc_idx == idx) | |
702 | return mci; | |
703 | ||
704 | break; | |
705 | } | |
706 | } | |
707 | ||
708 | return NULL; | |
709 | } | |
710 | EXPORT_SYMBOL(edac_mc_find); | |
711 | ||
da9bb1d2 | 712 | /** |
4e8d230d TI |
713 | * edac_mc_add_mc_with_groups: Insert the 'mci' structure into the mci |
714 | * global list and create sysfs entries associated with mci structure | |
da9bb1d2 | 715 | * @mci: pointer to the mci structure to be added to the list |
4e8d230d | 716 | * @groups: optional attribute groups for the driver-specific sysfs entries |
da9bb1d2 AC |
717 | * |
718 | * Return: | |
719 | * 0 Success | |
720 | * !0 Failure | |
721 | */ | |
722 | ||
723 | /* FIXME - should a warning be printed if no error detection? correction? */ | |
4e8d230d TI |
724 | int edac_mc_add_mc_with_groups(struct mem_ctl_info *mci, |
725 | const struct attribute_group **groups) | |
da9bb1d2 | 726 | { |
80cc7d87 | 727 | int ret = -EINVAL; |
956b9ba1 | 728 | edac_dbg(0, "\n"); |
b8f6f975 | 729 | |
88d84ac9 BP |
730 | if (mci->mc_idx >= EDAC_MAX_MCS) { |
731 | pr_warn_once("Too many memory controllers: %d\n", mci->mc_idx); | |
732 | return -ENODEV; | |
733 | } | |
734 | ||
da9bb1d2 AC |
735 | #ifdef CONFIG_EDAC_DEBUG |
736 | if (edac_debug_level >= 3) | |
737 | edac_mc_dump_mci(mci); | |
e7ecd891 | 738 | |
da9bb1d2 AC |
739 | if (edac_debug_level >= 4) { |
740 | int i; | |
741 | ||
742 | for (i = 0; i < mci->nr_csrows; i++) { | |
6e84d359 MCC |
743 | struct csrow_info *csrow = mci->csrows[i]; |
744 | u32 nr_pages = 0; | |
da9bb1d2 | 745 | int j; |
e7ecd891 | 746 | |
6e84d359 MCC |
747 | for (j = 0; j < csrow->nr_channels; j++) |
748 | nr_pages += csrow->channels[j]->dimm->nr_pages; | |
749 | if (!nr_pages) | |
750 | continue; | |
751 | edac_mc_dump_csrow(csrow); | |
752 | for (j = 0; j < csrow->nr_channels; j++) | |
753 | if (csrow->channels[j]->dimm->nr_pages) | |
754 | edac_mc_dump_channel(csrow->channels[j]); | |
da9bb1d2 | 755 | } |
4275be63 | 756 | for (i = 0; i < mci->tot_dimms; i++) |
6e84d359 MCC |
757 | if (mci->dimms[i]->nr_pages) |
758 | edac_mc_dump_dimm(mci->dimms[i], i); | |
da9bb1d2 AC |
759 | } |
760 | #endif | |
63b7df91 | 761 | mutex_lock(&mem_ctls_mutex); |
da9bb1d2 | 762 | |
80cc7d87 MCC |
763 | if (edac_mc_owner && edac_mc_owner != mci->mod_name) { |
764 | ret = -EPERM; | |
765 | goto fail0; | |
766 | } | |
767 | ||
da9bb1d2 | 768 | if (add_mc_to_global_list(mci)) |
028a7b6d | 769 | goto fail0; |
da9bb1d2 AC |
770 | |
771 | /* set load time so that error rate can be tracked */ | |
772 | mci->start_time = jiffies; | |
773 | ||
88d84ac9 BP |
774 | mci->bus = &mc_bus[mci->mc_idx]; |
775 | ||
4e8d230d | 776 | if (edac_create_sysfs_mci_device(mci, groups)) { |
9794f33d | 777 | edac_mc_printk(mci, KERN_WARNING, |
052dfb45 | 778 | "failed to create sysfs device\n"); |
9794f33d | 779 | goto fail1; |
780 | } | |
da9bb1d2 | 781 | |
81d87cb1 DJ |
782 | /* If there IS a check routine, then we are running POLLED */ |
783 | if (mci->edac_check != NULL) { | |
784 | /* This instance is NOW RUNNING */ | |
785 | mci->op_state = OP_RUNNING_POLL; | |
786 | ||
cb6ef42e | 787 | edac_mc_workq_setup(mci, edac_mc_get_poll_msec(), true); |
81d87cb1 DJ |
788 | } else { |
789 | mci->op_state = OP_RUNNING_INTERRUPT; | |
790 | } | |
791 | ||
da9bb1d2 | 792 | /* Report action taken */ |
7270a608 RR |
793 | edac_mc_printk(mci, KERN_INFO, |
794 | "Giving out device to module %s controller %s: DEV %s (%s)\n", | |
795 | mci->mod_name, mci->ctl_name, mci->dev_name, | |
796 | edac_op_state_to_string(mci->op_state)); | |
da9bb1d2 | 797 | |
80cc7d87 MCC |
798 | edac_mc_owner = mci->mod_name; |
799 | ||
63b7df91 | 800 | mutex_unlock(&mem_ctls_mutex); |
028a7b6d | 801 | return 0; |
da9bb1d2 | 802 | |
052dfb45 | 803 | fail1: |
028a7b6d DP |
804 | del_mc_from_global_list(mci); |
805 | ||
052dfb45 | 806 | fail0: |
63b7df91 | 807 | mutex_unlock(&mem_ctls_mutex); |
80cc7d87 | 808 | return ret; |
da9bb1d2 | 809 | } |
4e8d230d | 810 | EXPORT_SYMBOL_GPL(edac_mc_add_mc_with_groups); |
da9bb1d2 | 811 | |
da9bb1d2 | 812 | /** |
472678eb DP |
813 | * edac_mc_del_mc: Remove sysfs entries for specified mci structure and |
814 | * remove mci structure from global list | |
37f04581 | 815 | * @pdev: Pointer to 'struct device' representing mci structure to remove. |
da9bb1d2 | 816 | * |
18dbc337 | 817 | * Return pointer to removed mci structure, or NULL if device not found. |
da9bb1d2 | 818 | */ |
079708b9 | 819 | struct mem_ctl_info *edac_mc_del_mc(struct device *dev) |
da9bb1d2 | 820 | { |
18dbc337 | 821 | struct mem_ctl_info *mci; |
da9bb1d2 | 822 | |
956b9ba1 | 823 | edac_dbg(0, "\n"); |
bf52fa4a | 824 | |
63b7df91 | 825 | mutex_lock(&mem_ctls_mutex); |
18dbc337 | 826 | |
bf52fa4a DT |
827 | /* find the requested mci struct in the global list */ |
828 | mci = find_mci_by_dev(dev); | |
829 | if (mci == NULL) { | |
63b7df91 | 830 | mutex_unlock(&mem_ctls_mutex); |
18dbc337 DP |
831 | return NULL; |
832 | } | |
833 | ||
80cc7d87 MCC |
834 | if (!del_mc_from_global_list(mci)) |
835 | edac_mc_owner = NULL; | |
63b7df91 | 836 | mutex_unlock(&mem_ctls_mutex); |
bf52fa4a | 837 | |
bb31b312 | 838 | /* flush workq processes */ |
bf52fa4a | 839 | edac_mc_workq_teardown(mci); |
bb31b312 BP |
840 | |
841 | /* marking MCI offline */ | |
842 | mci->op_state = OP_OFFLINE; | |
843 | ||
844 | /* remove from sysfs */ | |
bf52fa4a DT |
845 | edac_remove_sysfs_mci_device(mci); |
846 | ||
537fba28 | 847 | edac_printk(KERN_INFO, EDAC_MC, |
052dfb45 | 848 | "Removed device %d for %s %s: DEV %s\n", mci->mc_idx, |
17aa7e03 | 849 | mci->mod_name, mci->ctl_name, edac_dev_name(mci)); |
bf52fa4a | 850 | |
18dbc337 | 851 | return mci; |
da9bb1d2 | 852 | } |
9110540f | 853 | EXPORT_SYMBOL_GPL(edac_mc_del_mc); |
da9bb1d2 | 854 | |
2da1c119 AB |
855 | static void edac_mc_scrub_block(unsigned long page, unsigned long offset, |
856 | u32 size) | |
da9bb1d2 AC |
857 | { |
858 | struct page *pg; | |
859 | void *virt_addr; | |
860 | unsigned long flags = 0; | |
861 | ||
956b9ba1 | 862 | edac_dbg(3, "\n"); |
da9bb1d2 AC |
863 | |
864 | /* ECC error page was not in our memory. Ignore it. */ | |
079708b9 | 865 | if (!pfn_valid(page)) |
da9bb1d2 AC |
866 | return; |
867 | ||
868 | /* Find the actual page structure then map it and fix */ | |
869 | pg = pfn_to_page(page); | |
870 | ||
871 | if (PageHighMem(pg)) | |
872 | local_irq_save(flags); | |
873 | ||
4e5df7ca | 874 | virt_addr = kmap_atomic(pg); |
da9bb1d2 AC |
875 | |
876 | /* Perform architecture specific atomic scrub operation */ | |
877 | atomic_scrub(virt_addr + offset, size); | |
878 | ||
879 | /* Unmap and complete */ | |
4e5df7ca | 880 | kunmap_atomic(virt_addr); |
da9bb1d2 AC |
881 | |
882 | if (PageHighMem(pg)) | |
883 | local_irq_restore(flags); | |
884 | } | |
885 | ||
da9bb1d2 | 886 | /* FIXME - should return -1 */ |
e7ecd891 | 887 | int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci, unsigned long page) |
da9bb1d2 | 888 | { |
de3910eb | 889 | struct csrow_info **csrows = mci->csrows; |
a895bf8b | 890 | int row, i, j, n; |
da9bb1d2 | 891 | |
956b9ba1 | 892 | edac_dbg(1, "MC%d: 0x%lx\n", mci->mc_idx, page); |
da9bb1d2 AC |
893 | row = -1; |
894 | ||
895 | for (i = 0; i < mci->nr_csrows; i++) { | |
de3910eb | 896 | struct csrow_info *csrow = csrows[i]; |
a895bf8b MCC |
897 | n = 0; |
898 | for (j = 0; j < csrow->nr_channels; j++) { | |
de3910eb | 899 | struct dimm_info *dimm = csrow->channels[j]->dimm; |
a895bf8b MCC |
900 | n += dimm->nr_pages; |
901 | } | |
902 | if (n == 0) | |
da9bb1d2 AC |
903 | continue; |
904 | ||
956b9ba1 JP |
905 | edac_dbg(3, "MC%d: first(0x%lx) page(0x%lx) last(0x%lx) mask(0x%lx)\n", |
906 | mci->mc_idx, | |
907 | csrow->first_page, page, csrow->last_page, | |
908 | csrow->page_mask); | |
da9bb1d2 AC |
909 | |
910 | if ((page >= csrow->first_page) && | |
911 | (page <= csrow->last_page) && | |
912 | ((page & csrow->page_mask) == | |
913 | (csrow->first_page & csrow->page_mask))) { | |
914 | row = i; | |
915 | break; | |
916 | } | |
917 | } | |
918 | ||
919 | if (row == -1) | |
537fba28 | 920 | edac_mc_printk(mci, KERN_ERR, |
052dfb45 DT |
921 | "could not look up page error address %lx\n", |
922 | (unsigned long)page); | |
da9bb1d2 AC |
923 | |
924 | return row; | |
925 | } | |
9110540f | 926 | EXPORT_SYMBOL_GPL(edac_mc_find_csrow_by_page); |
da9bb1d2 | 927 | |
4275be63 MCC |
928 | const char *edac_layer_name[] = { |
929 | [EDAC_MC_LAYER_BRANCH] = "branch", | |
930 | [EDAC_MC_LAYER_CHANNEL] = "channel", | |
931 | [EDAC_MC_LAYER_SLOT] = "slot", | |
932 | [EDAC_MC_LAYER_CHIP_SELECT] = "csrow", | |
c66b5a79 | 933 | [EDAC_MC_LAYER_ALL_MEM] = "memory", |
4275be63 MCC |
934 | }; |
935 | EXPORT_SYMBOL_GPL(edac_layer_name); | |
936 | ||
937 | static void edac_inc_ce_error(struct mem_ctl_info *mci, | |
9eb07a7f MCC |
938 | bool enable_per_layer_report, |
939 | const int pos[EDAC_MAX_LAYERS], | |
940 | const u16 count) | |
da9bb1d2 | 941 | { |
4275be63 | 942 | int i, index = 0; |
da9bb1d2 | 943 | |
9eb07a7f | 944 | mci->ce_mc += count; |
da9bb1d2 | 945 | |
4275be63 | 946 | if (!enable_per_layer_report) { |
9eb07a7f | 947 | mci->ce_noinfo_count += count; |
da9bb1d2 AC |
948 | return; |
949 | } | |
e7ecd891 | 950 | |
4275be63 MCC |
951 | for (i = 0; i < mci->n_layers; i++) { |
952 | if (pos[i] < 0) | |
953 | break; | |
954 | index += pos[i]; | |
9eb07a7f | 955 | mci->ce_per_layer[i][index] += count; |
4275be63 MCC |
956 | |
957 | if (i < mci->n_layers - 1) | |
958 | index *= mci->layers[i + 1].size; | |
959 | } | |
960 | } | |
961 | ||
962 | static void edac_inc_ue_error(struct mem_ctl_info *mci, | |
963 | bool enable_per_layer_report, | |
9eb07a7f MCC |
964 | const int pos[EDAC_MAX_LAYERS], |
965 | const u16 count) | |
4275be63 MCC |
966 | { |
967 | int i, index = 0; | |
968 | ||
9eb07a7f | 969 | mci->ue_mc += count; |
4275be63 MCC |
970 | |
971 | if (!enable_per_layer_report) { | |
9eb07a7f | 972 | mci->ce_noinfo_count += count; |
da9bb1d2 AC |
973 | return; |
974 | } | |
975 | ||
4275be63 MCC |
976 | for (i = 0; i < mci->n_layers; i++) { |
977 | if (pos[i] < 0) | |
978 | break; | |
979 | index += pos[i]; | |
9eb07a7f | 980 | mci->ue_per_layer[i][index] += count; |
a7d7d2e1 | 981 | |
4275be63 MCC |
982 | if (i < mci->n_layers - 1) |
983 | index *= mci->layers[i + 1].size; | |
984 | } | |
985 | } | |
da9bb1d2 | 986 | |
4275be63 | 987 | static void edac_ce_error(struct mem_ctl_info *mci, |
9eb07a7f | 988 | const u16 error_count, |
4275be63 MCC |
989 | const int pos[EDAC_MAX_LAYERS], |
990 | const char *msg, | |
991 | const char *location, | |
992 | const char *label, | |
993 | const char *detail, | |
994 | const char *other_detail, | |
995 | const bool enable_per_layer_report, | |
996 | const unsigned long page_frame_number, | |
997 | const unsigned long offset_in_page, | |
53f2d028 | 998 | long grain) |
4275be63 MCC |
999 | { |
1000 | unsigned long remapped_page; | |
f430d570 BP |
1001 | char *msg_aux = ""; |
1002 | ||
1003 | if (*msg) | |
1004 | msg_aux = " "; | |
4275be63 MCC |
1005 | |
1006 | if (edac_mc_get_log_ce()) { | |
1007 | if (other_detail && *other_detail) | |
1008 | edac_mc_printk(mci, KERN_WARNING, | |
f430d570 BP |
1009 | "%d CE %s%son %s (%s %s - %s)\n", |
1010 | error_count, msg, msg_aux, label, | |
1011 | location, detail, other_detail); | |
4275be63 MCC |
1012 | else |
1013 | edac_mc_printk(mci, KERN_WARNING, | |
f430d570 BP |
1014 | "%d CE %s%son %s (%s %s)\n", |
1015 | error_count, msg, msg_aux, label, | |
1016 | location, detail); | |
4275be63 | 1017 | } |
9eb07a7f | 1018 | edac_inc_ce_error(mci, enable_per_layer_report, pos, error_count); |
da9bb1d2 | 1019 | |
aa2064d7 | 1020 | if (mci->scrub_mode == SCRUB_SW_SRC) { |
da9bb1d2 | 1021 | /* |
4275be63 MCC |
1022 | * Some memory controllers (called MCs below) can remap |
1023 | * memory so that it is still available at a different | |
1024 | * address when PCI devices map into memory. | |
1025 | * MC's that can't do this, lose the memory where PCI | |
1026 | * devices are mapped. This mapping is MC-dependent | |
1027 | * and so we call back into the MC driver for it to | |
1028 | * map the MC page to a physical (CPU) page which can | |
1029 | * then be mapped to a virtual page - which can then | |
1030 | * be scrubbed. | |
1031 | */ | |
da9bb1d2 | 1032 | remapped_page = mci->ctl_page_to_phys ? |
052dfb45 DT |
1033 | mci->ctl_page_to_phys(mci, page_frame_number) : |
1034 | page_frame_number; | |
da9bb1d2 | 1035 | |
4275be63 MCC |
1036 | edac_mc_scrub_block(remapped_page, |
1037 | offset_in_page, grain); | |
da9bb1d2 AC |
1038 | } |
1039 | } | |
1040 | ||
4275be63 | 1041 | static void edac_ue_error(struct mem_ctl_info *mci, |
9eb07a7f | 1042 | const u16 error_count, |
4275be63 MCC |
1043 | const int pos[EDAC_MAX_LAYERS], |
1044 | const char *msg, | |
1045 | const char *location, | |
1046 | const char *label, | |
1047 | const char *detail, | |
1048 | const char *other_detail, | |
1049 | const bool enable_per_layer_report) | |
da9bb1d2 | 1050 | { |
f430d570 BP |
1051 | char *msg_aux = ""; |
1052 | ||
1053 | if (*msg) | |
1054 | msg_aux = " "; | |
1055 | ||
4275be63 MCC |
1056 | if (edac_mc_get_log_ue()) { |
1057 | if (other_detail && *other_detail) | |
1058 | edac_mc_printk(mci, KERN_WARNING, | |
f430d570 BP |
1059 | "%d UE %s%son %s (%s %s - %s)\n", |
1060 | error_count, msg, msg_aux, label, | |
1061 | location, detail, other_detail); | |
4275be63 MCC |
1062 | else |
1063 | edac_mc_printk(mci, KERN_WARNING, | |
f430d570 BP |
1064 | "%d UE %s%son %s (%s %s)\n", |
1065 | error_count, msg, msg_aux, label, | |
1066 | location, detail); | |
4275be63 | 1067 | } |
e7ecd891 | 1068 | |
4275be63 MCC |
1069 | if (edac_mc_get_panic_on_ue()) { |
1070 | if (other_detail && *other_detail) | |
f430d570 BP |
1071 | panic("UE %s%son %s (%s%s - %s)\n", |
1072 | msg, msg_aux, label, location, detail, other_detail); | |
4275be63 | 1073 | else |
f430d570 BP |
1074 | panic("UE %s%son %s (%s%s)\n", |
1075 | msg, msg_aux, label, location, detail); | |
4275be63 MCC |
1076 | } |
1077 | ||
9eb07a7f | 1078 | edac_inc_ue_error(mci, enable_per_layer_report, pos, error_count); |
da9bb1d2 AC |
1079 | } |
1080 | ||
e7e24830 MCC |
1081 | /** |
1082 | * edac_raw_mc_handle_error - reports a memory event to userspace without doing | |
1083 | * anything to discover the error location | |
1084 | * | |
1085 | * @type: severity of the error (CE/UE/Fatal) | |
1086 | * @mci: a struct mem_ctl_info pointer | |
1087 | * @e: error description | |
1088 | * | |
1089 | * This raw function is used internally by edac_mc_handle_error(). It should | |
1090 | * only be called directly when the hardware error come directly from BIOS, | |
1091 | * like in the case of APEI GHES driver. | |
1092 | */ | |
1093 | void edac_raw_mc_handle_error(const enum hw_event_mc_err_type type, | |
1094 | struct mem_ctl_info *mci, | |
1095 | struct edac_raw_error_desc *e) | |
1096 | { | |
1097 | char detail[80]; | |
1098 | int pos[EDAC_MAX_LAYERS] = { e->top_layer, e->mid_layer, e->low_layer }; | |
1099 | ||
1100 | /* Memory type dependent details about the error */ | |
1101 | if (type == HW_EVENT_ERR_CORRECTED) { | |
1102 | snprintf(detail, sizeof(detail), | |
1103 | "page:0x%lx offset:0x%lx grain:%ld syndrome:0x%lx", | |
1104 | e->page_frame_number, e->offset_in_page, | |
1105 | e->grain, e->syndrome); | |
1106 | edac_ce_error(mci, e->error_count, pos, e->msg, e->location, e->label, | |
1107 | detail, e->other_detail, e->enable_per_layer_report, | |
1108 | e->page_frame_number, e->offset_in_page, e->grain); | |
1109 | } else { | |
1110 | snprintf(detail, sizeof(detail), | |
1111 | "page:0x%lx offset:0x%lx grain:%ld", | |
1112 | e->page_frame_number, e->offset_in_page, e->grain); | |
1113 | ||
1114 | edac_ue_error(mci, e->error_count, pos, e->msg, e->location, e->label, | |
1115 | detail, e->other_detail, e->enable_per_layer_report); | |
1116 | } | |
1117 | ||
1118 | ||
1119 | } | |
1120 | EXPORT_SYMBOL_GPL(edac_raw_mc_handle_error); | |
53f2d028 MCC |
1121 | |
1122 | /** | |
1123 | * edac_mc_handle_error - reports a memory event to userspace | |
1124 | * | |
1125 | * @type: severity of the error (CE/UE/Fatal) | |
1126 | * @mci: a struct mem_ctl_info pointer | |
9eb07a7f | 1127 | * @error_count: Number of errors of the same type |
53f2d028 MCC |
1128 | * @page_frame_number: mem page where the error occurred |
1129 | * @offset_in_page: offset of the error inside the page | |
1130 | * @syndrome: ECC syndrome | |
1131 | * @top_layer: Memory layer[0] position | |
1132 | * @mid_layer: Memory layer[1] position | |
1133 | * @low_layer: Memory layer[2] position | |
1134 | * @msg: Message meaningful to the end users that | |
1135 | * explains the event | |
1136 | * @other_detail: Technical details about the event that | |
1137 | * may help hardware manufacturers and | |
1138 | * EDAC developers to analyse the event | |
53f2d028 | 1139 | */ |
4275be63 MCC |
1140 | void edac_mc_handle_error(const enum hw_event_mc_err_type type, |
1141 | struct mem_ctl_info *mci, | |
9eb07a7f | 1142 | const u16 error_count, |
4275be63 MCC |
1143 | const unsigned long page_frame_number, |
1144 | const unsigned long offset_in_page, | |
1145 | const unsigned long syndrome, | |
53f2d028 MCC |
1146 | const int top_layer, |
1147 | const int mid_layer, | |
1148 | const int low_layer, | |
4275be63 | 1149 | const char *msg, |
03f7eae8 | 1150 | const char *other_detail) |
da9bb1d2 | 1151 | { |
4275be63 MCC |
1152 | char *p; |
1153 | int row = -1, chan = -1; | |
53f2d028 | 1154 | int pos[EDAC_MAX_LAYERS] = { top_layer, mid_layer, low_layer }; |
c7ef7645 | 1155 | int i, n_labels = 0; |
53f2d028 | 1156 | u8 grain_bits; |
c7ef7645 | 1157 | struct edac_raw_error_desc *e = &mci->error_desc; |
da9bb1d2 | 1158 | |
956b9ba1 | 1159 | edac_dbg(3, "MC%d\n", mci->mc_idx); |
da9bb1d2 | 1160 | |
c7ef7645 MCC |
1161 | /* Fills the error report buffer */ |
1162 | memset(e, 0, sizeof (*e)); | |
1163 | e->error_count = error_count; | |
1164 | e->top_layer = top_layer; | |
1165 | e->mid_layer = mid_layer; | |
1166 | e->low_layer = low_layer; | |
1167 | e->page_frame_number = page_frame_number; | |
1168 | e->offset_in_page = offset_in_page; | |
1169 | e->syndrome = syndrome; | |
1170 | e->msg = msg; | |
1171 | e->other_detail = other_detail; | |
1172 | ||
4275be63 MCC |
1173 | /* |
1174 | * Check if the event report is consistent and if the memory | |
1175 | * location is known. If it is known, enable_per_layer_report will be | |
1176 | * true, the DIMM(s) label info will be filled and the per-layer | |
1177 | * error counters will be incremented. | |
1178 | */ | |
1179 | for (i = 0; i < mci->n_layers; i++) { | |
1180 | if (pos[i] >= (int)mci->layers[i].size) { | |
4275be63 MCC |
1181 | |
1182 | edac_mc_printk(mci, KERN_ERR, | |
1183 | "INTERNAL ERROR: %s value is out of range (%d >= %d)\n", | |
1184 | edac_layer_name[mci->layers[i].type], | |
1185 | pos[i], mci->layers[i].size); | |
1186 | /* | |
1187 | * Instead of just returning it, let's use what's | |
1188 | * known about the error. The increment routines and | |
1189 | * the DIMM filter logic will do the right thing by | |
1190 | * pointing the likely damaged DIMMs. | |
1191 | */ | |
1192 | pos[i] = -1; | |
1193 | } | |
1194 | if (pos[i] >= 0) | |
c7ef7645 | 1195 | e->enable_per_layer_report = true; |
da9bb1d2 AC |
1196 | } |
1197 | ||
4275be63 MCC |
1198 | /* |
1199 | * Get the dimm label/grain that applies to the match criteria. | |
1200 | * As the error algorithm may not be able to point to just one memory | |
1201 | * stick, the logic here will get all possible labels that could | |
1202 | * pottentially be affected by the error. | |
1203 | * On FB-DIMM memory controllers, for uncorrected errors, it is common | |
1204 | * to have only the MC channel and the MC dimm (also called "branch") | |
1205 | * but the channel is not known, as the memory is arranged in pairs, | |
1206 | * where each memory belongs to a separate channel within the same | |
1207 | * branch. | |
1208 | */ | |
c7ef7645 | 1209 | p = e->label; |
4275be63 | 1210 | *p = '\0'; |
4da1b7bf | 1211 | |
4275be63 | 1212 | for (i = 0; i < mci->tot_dimms; i++) { |
de3910eb | 1213 | struct dimm_info *dimm = mci->dimms[i]; |
da9bb1d2 | 1214 | |
53f2d028 | 1215 | if (top_layer >= 0 && top_layer != dimm->location[0]) |
4275be63 | 1216 | continue; |
53f2d028 | 1217 | if (mid_layer >= 0 && mid_layer != dimm->location[1]) |
4275be63 | 1218 | continue; |
53f2d028 | 1219 | if (low_layer >= 0 && low_layer != dimm->location[2]) |
4275be63 | 1220 | continue; |
da9bb1d2 | 1221 | |
4275be63 | 1222 | /* get the max grain, over the error match range */ |
c7ef7645 MCC |
1223 | if (dimm->grain > e->grain) |
1224 | e->grain = dimm->grain; | |
9794f33d | 1225 | |
4275be63 MCC |
1226 | /* |
1227 | * If the error is memory-controller wide, there's no need to | |
1228 | * seek for the affected DIMMs because the whole | |
1229 | * channel/memory controller/... may be affected. | |
1230 | * Also, don't show errors for empty DIMM slots. | |
1231 | */ | |
c7ef7645 MCC |
1232 | if (e->enable_per_layer_report && dimm->nr_pages) { |
1233 | if (n_labels >= EDAC_MAX_LABELS) { | |
1234 | e->enable_per_layer_report = false; | |
1235 | break; | |
1236 | } | |
1237 | n_labels++; | |
1238 | if (p != e->label) { | |
4275be63 MCC |
1239 | strcpy(p, OTHER_LABEL); |
1240 | p += strlen(OTHER_LABEL); | |
1241 | } | |
1242 | strcpy(p, dimm->label); | |
1243 | p += strlen(p); | |
1244 | *p = '\0'; | |
1245 | ||
1246 | /* | |
1247 | * get csrow/channel of the DIMM, in order to allow | |
1248 | * incrementing the compat API counters | |
1249 | */ | |
956b9ba1 | 1250 | edac_dbg(4, "%s csrows map: (%d,%d)\n", |
9713faec | 1251 | mci->csbased ? "rank" : "dimm", |
956b9ba1 | 1252 | dimm->csrow, dimm->cschannel); |
4275be63 MCC |
1253 | if (row == -1) |
1254 | row = dimm->csrow; | |
1255 | else if (row >= 0 && row != dimm->csrow) | |
1256 | row = -2; | |
1257 | ||
1258 | if (chan == -1) | |
1259 | chan = dimm->cschannel; | |
1260 | else if (chan >= 0 && chan != dimm->cschannel) | |
1261 | chan = -2; | |
1262 | } | |
9794f33d | 1263 | } |
1264 | ||
c7ef7645 MCC |
1265 | if (!e->enable_per_layer_report) { |
1266 | strcpy(e->label, "any memory"); | |
4275be63 | 1267 | } else { |
956b9ba1 | 1268 | edac_dbg(4, "csrow/channel to increment: (%d,%d)\n", row, chan); |
c7ef7645 MCC |
1269 | if (p == e->label) |
1270 | strcpy(e->label, "unknown memory"); | |
4275be63 MCC |
1271 | if (type == HW_EVENT_ERR_CORRECTED) { |
1272 | if (row >= 0) { | |
9eb07a7f | 1273 | mci->csrows[row]->ce_count += error_count; |
4275be63 | 1274 | if (chan >= 0) |
9eb07a7f | 1275 | mci->csrows[row]->channels[chan]->ce_count += error_count; |
4275be63 MCC |
1276 | } |
1277 | } else | |
1278 | if (row >= 0) | |
9eb07a7f | 1279 | mci->csrows[row]->ue_count += error_count; |
9794f33d | 1280 | } |
1281 | ||
4275be63 | 1282 | /* Fill the RAM location data */ |
c7ef7645 | 1283 | p = e->location; |
4da1b7bf | 1284 | |
4275be63 MCC |
1285 | for (i = 0; i < mci->n_layers; i++) { |
1286 | if (pos[i] < 0) | |
1287 | continue; | |
9794f33d | 1288 | |
4275be63 MCC |
1289 | p += sprintf(p, "%s:%d ", |
1290 | edac_layer_name[mci->layers[i].type], | |
1291 | pos[i]); | |
9794f33d | 1292 | } |
c7ef7645 | 1293 | if (p > e->location) |
53f2d028 MCC |
1294 | *(p - 1) = '\0'; |
1295 | ||
1296 | /* Report the error via the trace interface */ | |
c7ef7645 MCC |
1297 | grain_bits = fls_long(e->grain) + 1; |
1298 | trace_mc_event(type, e->msg, e->label, e->error_count, | |
1299 | mci->mc_idx, e->top_layer, e->mid_layer, e->low_layer, | |
1300 | PAGES_TO_MiB(e->page_frame_number) | e->offset_in_page, | |
e7e24830 | 1301 | grain_bits, e->syndrome, e->other_detail); |
a7d7d2e1 | 1302 | |
e7e24830 | 1303 | edac_raw_mc_handle_error(type, mci, e); |
9794f33d | 1304 | } |
4275be63 | 1305 | EXPORT_SYMBOL_GPL(edac_mc_handle_error); |