Commit | Line | Data |
---|---|---|
7c9281d7 DT |
1 | /* |
2 | * edac_mc kernel module | |
42a8e397 DT |
3 | * (C) 2005-2007 Linux Networx (http://lnxi.com) |
4 | * | |
7c9281d7 DT |
5 | * This file may be distributed under the terms of the |
6 | * GNU General Public License. | |
7 | * | |
42a8e397 | 8 | * Written Doug Thompson <norsk5@xmission.com> www.softwarebitmaker.com |
7c9281d7 | 9 | * |
e7100478 | 10 | * (c) 2012-2013 - Mauro Carvalho Chehab <mchehab@redhat.com> |
7a623c03 MCC |
11 | * The entire API were re-written, and ported to use struct device |
12 | * | |
7c9281d7 DT |
13 | */ |
14 | ||
7c9281d7 | 15 | #include <linux/ctype.h> |
5a0e3ad6 | 16 | #include <linux/slab.h> |
30e1f7a8 | 17 | #include <linux/edac.h> |
8096cfaf | 18 | #include <linux/bug.h> |
7a623c03 | 19 | #include <linux/pm_runtime.h> |
452a6bf9 | 20 | #include <linux/uaccess.h> |
7c9281d7 | 21 | |
20bcb7a8 | 22 | #include "edac_core.h" |
7c9281d7 DT |
23 | #include "edac_module.h" |
24 | ||
25 | /* MC EDAC Controls, setable by module parameter, and sysfs */ | |
4de78c68 DJ |
26 | static int edac_mc_log_ue = 1; |
27 | static int edac_mc_log_ce = 1; | |
f044091c | 28 | static int edac_mc_panic_on_ue; |
4de78c68 | 29 | static int edac_mc_poll_msec = 1000; |
7c9281d7 DT |
30 | |
31 | /* Getter functions for above */ | |
4de78c68 | 32 | int edac_mc_get_log_ue(void) |
7c9281d7 | 33 | { |
4de78c68 | 34 | return edac_mc_log_ue; |
7c9281d7 DT |
35 | } |
36 | ||
4de78c68 | 37 | int edac_mc_get_log_ce(void) |
7c9281d7 | 38 | { |
4de78c68 | 39 | return edac_mc_log_ce; |
7c9281d7 DT |
40 | } |
41 | ||
4de78c68 | 42 | int edac_mc_get_panic_on_ue(void) |
7c9281d7 | 43 | { |
4de78c68 | 44 | return edac_mc_panic_on_ue; |
7c9281d7 DT |
45 | } |
46 | ||
81d87cb1 DJ |
47 | /* this is temporary */ |
48 | int edac_mc_get_poll_msec(void) | |
49 | { | |
4de78c68 | 50 | return edac_mc_poll_msec; |
7c9281d7 DT |
51 | } |
52 | ||
096846e2 AJ |
53 | static int edac_set_poll_msec(const char *val, struct kernel_param *kp) |
54 | { | |
55 | long l; | |
56 | int ret; | |
57 | ||
58 | if (!val) | |
59 | return -EINVAL; | |
60 | ||
c542b53d JH |
61 | ret = kstrtol(val, 0, &l); |
62 | if (ret) | |
63 | return ret; | |
64 | if ((int)l != l) | |
096846e2 AJ |
65 | return -EINVAL; |
66 | *((int *)kp->arg) = l; | |
67 | ||
68 | /* notify edac_mc engine to reset the poll period */ | |
69 | edac_mc_reset_delay_period(l); | |
70 | ||
71 | return 0; | |
72 | } | |
73 | ||
7c9281d7 | 74 | /* Parameter declarations for above */ |
4de78c68 DJ |
75 | module_param(edac_mc_panic_on_ue, int, 0644); |
76 | MODULE_PARM_DESC(edac_mc_panic_on_ue, "Panic on uncorrected error: 0=off 1=on"); | |
77 | module_param(edac_mc_log_ue, int, 0644); | |
78 | MODULE_PARM_DESC(edac_mc_log_ue, | |
079708b9 | 79 | "Log uncorrectable error to console: 0=off 1=on"); |
4de78c68 DJ |
80 | module_param(edac_mc_log_ce, int, 0644); |
81 | MODULE_PARM_DESC(edac_mc_log_ce, | |
079708b9 | 82 | "Log correctable error to console: 0=off 1=on"); |
096846e2 AJ |
83 | module_param_call(edac_mc_poll_msec, edac_set_poll_msec, param_get_int, |
84 | &edac_mc_poll_msec, 0644); | |
4de78c68 | 85 | MODULE_PARM_DESC(edac_mc_poll_msec, "Polling period in milliseconds"); |
7c9281d7 | 86 | |
de3910eb | 87 | static struct device *mci_pdev; |
7a623c03 | 88 | |
7c9281d7 DT |
89 | /* |
90 | * various constants for Memory Controllers | |
91 | */ | |
8b7719e0 | 92 | static const char * const mem_types[] = { |
7c9281d7 DT |
93 | [MEM_EMPTY] = "Empty", |
94 | [MEM_RESERVED] = "Reserved", | |
95 | [MEM_UNKNOWN] = "Unknown", | |
96 | [MEM_FPM] = "FPM", | |
97 | [MEM_EDO] = "EDO", | |
98 | [MEM_BEDO] = "BEDO", | |
99 | [MEM_SDR] = "Unbuffered-SDR", | |
100 | [MEM_RDR] = "Registered-SDR", | |
101 | [MEM_DDR] = "Unbuffered-DDR", | |
102 | [MEM_RDDR] = "Registered-DDR", | |
1a9b85e6 DJ |
103 | [MEM_RMBS] = "RMBS", |
104 | [MEM_DDR2] = "Unbuffered-DDR2", | |
105 | [MEM_FB_DDR2] = "FullyBuffered-DDR2", | |
1d5f726c | 106 | [MEM_RDDR2] = "Registered-DDR2", |
b1cfebc9 YS |
107 | [MEM_XDR] = "XDR", |
108 | [MEM_DDR3] = "Unbuffered-DDR3", | |
109 | [MEM_RDDR3] = "Registered-DDR3" | |
7c9281d7 DT |
110 | }; |
111 | ||
8b7719e0 | 112 | static const char * const dev_types[] = { |
7c9281d7 DT |
113 | [DEV_UNKNOWN] = "Unknown", |
114 | [DEV_X1] = "x1", | |
115 | [DEV_X2] = "x2", | |
116 | [DEV_X4] = "x4", | |
117 | [DEV_X8] = "x8", | |
118 | [DEV_X16] = "x16", | |
119 | [DEV_X32] = "x32", | |
120 | [DEV_X64] = "x64" | |
121 | }; | |
122 | ||
8b7719e0 | 123 | static const char * const edac_caps[] = { |
7c9281d7 DT |
124 | [EDAC_UNKNOWN] = "Unknown", |
125 | [EDAC_NONE] = "None", | |
126 | [EDAC_RESERVED] = "Reserved", | |
127 | [EDAC_PARITY] = "PARITY", | |
128 | [EDAC_EC] = "EC", | |
129 | [EDAC_SECDED] = "SECDED", | |
130 | [EDAC_S2ECD2ED] = "S2ECD2ED", | |
131 | [EDAC_S4ECD4ED] = "S4ECD4ED", | |
132 | [EDAC_S8ECD8ED] = "S8ECD8ED", | |
133 | [EDAC_S16ECD16ED] = "S16ECD16ED" | |
134 | }; | |
135 | ||
19974710 | 136 | #ifdef CONFIG_EDAC_LEGACY_SYSFS |
7a623c03 MCC |
137 | /* |
138 | * EDAC sysfs CSROW data structures and methods | |
139 | */ | |
140 | ||
141 | #define to_csrow(k) container_of(k, struct csrow_info, dev) | |
142 | ||
143 | /* | |
144 | * We need it to avoid namespace conflicts between the legacy API | |
145 | * and the per-dimm/per-rank one | |
7c9281d7 | 146 | */ |
7a623c03 | 147 | #define DEVICE_ATTR_LEGACY(_name, _mode, _show, _store) \ |
fbe2d361 | 148 | static struct device_attribute dev_attr_legacy_##_name = __ATTR(_name, _mode, _show, _store) |
7a623c03 MCC |
149 | |
150 | struct dev_ch_attribute { | |
151 | struct device_attribute attr; | |
152 | int channel; | |
153 | }; | |
154 | ||
155 | #define DEVICE_CHANNEL(_name, _mode, _show, _store, _var) \ | |
156 | struct dev_ch_attribute dev_attr_legacy_##_name = \ | |
157 | { __ATTR(_name, _mode, _show, _store), (_var) } | |
158 | ||
159 | #define to_channel(k) (container_of(k, struct dev_ch_attribute, attr)->channel) | |
7c9281d7 DT |
160 | |
161 | /* Set of more default csrow<id> attribute show/store functions */ | |
7a623c03 MCC |
162 | static ssize_t csrow_ue_count_show(struct device *dev, |
163 | struct device_attribute *mattr, char *data) | |
7c9281d7 | 164 | { |
7a623c03 MCC |
165 | struct csrow_info *csrow = to_csrow(dev); |
166 | ||
079708b9 | 167 | return sprintf(data, "%u\n", csrow->ue_count); |
7c9281d7 DT |
168 | } |
169 | ||
7a623c03 MCC |
170 | static ssize_t csrow_ce_count_show(struct device *dev, |
171 | struct device_attribute *mattr, char *data) | |
7c9281d7 | 172 | { |
7a623c03 MCC |
173 | struct csrow_info *csrow = to_csrow(dev); |
174 | ||
079708b9 | 175 | return sprintf(data, "%u\n", csrow->ce_count); |
7c9281d7 DT |
176 | } |
177 | ||
7a623c03 MCC |
178 | static ssize_t csrow_size_show(struct device *dev, |
179 | struct device_attribute *mattr, char *data) | |
7c9281d7 | 180 | { |
7a623c03 | 181 | struct csrow_info *csrow = to_csrow(dev); |
a895bf8b MCC |
182 | int i; |
183 | u32 nr_pages = 0; | |
184 | ||
185 | for (i = 0; i < csrow->nr_channels; i++) | |
de3910eb | 186 | nr_pages += csrow->channels[i]->dimm->nr_pages; |
a895bf8b | 187 | return sprintf(data, "%u\n", PAGES_TO_MiB(nr_pages)); |
7c9281d7 DT |
188 | } |
189 | ||
7a623c03 MCC |
190 | static ssize_t csrow_mem_type_show(struct device *dev, |
191 | struct device_attribute *mattr, char *data) | |
7c9281d7 | 192 | { |
7a623c03 MCC |
193 | struct csrow_info *csrow = to_csrow(dev); |
194 | ||
de3910eb | 195 | return sprintf(data, "%s\n", mem_types[csrow->channels[0]->dimm->mtype]); |
7c9281d7 DT |
196 | } |
197 | ||
7a623c03 MCC |
198 | static ssize_t csrow_dev_type_show(struct device *dev, |
199 | struct device_attribute *mattr, char *data) | |
7c9281d7 | 200 | { |
7a623c03 MCC |
201 | struct csrow_info *csrow = to_csrow(dev); |
202 | ||
de3910eb | 203 | return sprintf(data, "%s\n", dev_types[csrow->channels[0]->dimm->dtype]); |
7c9281d7 DT |
204 | } |
205 | ||
7a623c03 MCC |
206 | static ssize_t csrow_edac_mode_show(struct device *dev, |
207 | struct device_attribute *mattr, | |
208 | char *data) | |
7c9281d7 | 209 | { |
7a623c03 MCC |
210 | struct csrow_info *csrow = to_csrow(dev); |
211 | ||
de3910eb | 212 | return sprintf(data, "%s\n", edac_caps[csrow->channels[0]->dimm->edac_mode]); |
7c9281d7 DT |
213 | } |
214 | ||
215 | /* show/store functions for DIMM Label attributes */ | |
7a623c03 MCC |
216 | static ssize_t channel_dimm_label_show(struct device *dev, |
217 | struct device_attribute *mattr, | |
218 | char *data) | |
7c9281d7 | 219 | { |
7a623c03 MCC |
220 | struct csrow_info *csrow = to_csrow(dev); |
221 | unsigned chan = to_channel(mattr); | |
de3910eb | 222 | struct rank_info *rank = csrow->channels[chan]; |
7a623c03 | 223 | |
124682c7 | 224 | /* if field has not been initialized, there is nothing to send */ |
7a623c03 | 225 | if (!rank->dimm->label[0]) |
124682c7 AJ |
226 | return 0; |
227 | ||
228 | return snprintf(data, EDAC_MC_LABEL_LEN, "%s\n", | |
7a623c03 | 229 | rank->dimm->label); |
7c9281d7 DT |
230 | } |
231 | ||
7a623c03 MCC |
232 | static ssize_t channel_dimm_label_store(struct device *dev, |
233 | struct device_attribute *mattr, | |
234 | const char *data, size_t count) | |
7c9281d7 | 235 | { |
7a623c03 MCC |
236 | struct csrow_info *csrow = to_csrow(dev); |
237 | unsigned chan = to_channel(mattr); | |
de3910eb | 238 | struct rank_info *rank = csrow->channels[chan]; |
7a623c03 | 239 | |
7c9281d7 DT |
240 | ssize_t max_size = 0; |
241 | ||
079708b9 | 242 | max_size = min((ssize_t) count, (ssize_t) EDAC_MC_LABEL_LEN - 1); |
7a623c03 MCC |
243 | strncpy(rank->dimm->label, data, max_size); |
244 | rank->dimm->label[max_size] = '\0'; | |
7c9281d7 DT |
245 | |
246 | return max_size; | |
247 | } | |
248 | ||
249 | /* show function for dynamic chX_ce_count attribute */ | |
7a623c03 MCC |
250 | static ssize_t channel_ce_count_show(struct device *dev, |
251 | struct device_attribute *mattr, char *data) | |
7c9281d7 | 252 | { |
7a623c03 MCC |
253 | struct csrow_info *csrow = to_csrow(dev); |
254 | unsigned chan = to_channel(mattr); | |
de3910eb | 255 | struct rank_info *rank = csrow->channels[chan]; |
7a623c03 MCC |
256 | |
257 | return sprintf(data, "%u\n", rank->ce_count); | |
7c9281d7 DT |
258 | } |
259 | ||
7a623c03 MCC |
260 | /* cwrow<id>/attribute files */ |
261 | DEVICE_ATTR_LEGACY(size_mb, S_IRUGO, csrow_size_show, NULL); | |
262 | DEVICE_ATTR_LEGACY(dev_type, S_IRUGO, csrow_dev_type_show, NULL); | |
263 | DEVICE_ATTR_LEGACY(mem_type, S_IRUGO, csrow_mem_type_show, NULL); | |
264 | DEVICE_ATTR_LEGACY(edac_mode, S_IRUGO, csrow_edac_mode_show, NULL); | |
265 | DEVICE_ATTR_LEGACY(ue_count, S_IRUGO, csrow_ue_count_show, NULL); | |
266 | DEVICE_ATTR_LEGACY(ce_count, S_IRUGO, csrow_ce_count_show, NULL); | |
7c9281d7 | 267 | |
7a623c03 MCC |
268 | /* default attributes of the CSROW<id> object */ |
269 | static struct attribute *csrow_attrs[] = { | |
270 | &dev_attr_legacy_dev_type.attr, | |
271 | &dev_attr_legacy_mem_type.attr, | |
272 | &dev_attr_legacy_edac_mode.attr, | |
273 | &dev_attr_legacy_size_mb.attr, | |
274 | &dev_attr_legacy_ue_count.attr, | |
275 | &dev_attr_legacy_ce_count.attr, | |
276 | NULL, | |
277 | }; | |
7c9281d7 | 278 | |
7a623c03 MCC |
279 | static struct attribute_group csrow_attr_grp = { |
280 | .attrs = csrow_attrs, | |
281 | }; | |
7c9281d7 | 282 | |
7a623c03 MCC |
283 | static const struct attribute_group *csrow_attr_groups[] = { |
284 | &csrow_attr_grp, | |
285 | NULL | |
286 | }; | |
7c9281d7 | 287 | |
de3910eb | 288 | static void csrow_attr_release(struct device *dev) |
7c9281d7 | 289 | { |
de3910eb MCC |
290 | struct csrow_info *csrow = container_of(dev, struct csrow_info, dev); |
291 | ||
956b9ba1 | 292 | edac_dbg(1, "Releasing csrow device %s\n", dev_name(dev)); |
de3910eb | 293 | kfree(csrow); |
7c9281d7 DT |
294 | } |
295 | ||
7a623c03 MCC |
296 | static struct device_type csrow_attr_type = { |
297 | .groups = csrow_attr_groups, | |
298 | .release = csrow_attr_release, | |
7c9281d7 DT |
299 | }; |
300 | ||
7a623c03 MCC |
301 | /* |
302 | * possible dynamic channel DIMM Label attribute files | |
303 | * | |
304 | */ | |
7c9281d7 | 305 | |
7a623c03 | 306 | #define EDAC_NR_CHANNELS 6 |
7c9281d7 | 307 | |
7a623c03 | 308 | DEVICE_CHANNEL(ch0_dimm_label, S_IRUGO | S_IWUSR, |
052dfb45 | 309 | channel_dimm_label_show, channel_dimm_label_store, 0); |
7a623c03 | 310 | DEVICE_CHANNEL(ch1_dimm_label, S_IRUGO | S_IWUSR, |
052dfb45 | 311 | channel_dimm_label_show, channel_dimm_label_store, 1); |
7a623c03 | 312 | DEVICE_CHANNEL(ch2_dimm_label, S_IRUGO | S_IWUSR, |
052dfb45 | 313 | channel_dimm_label_show, channel_dimm_label_store, 2); |
7a623c03 | 314 | DEVICE_CHANNEL(ch3_dimm_label, S_IRUGO | S_IWUSR, |
052dfb45 | 315 | channel_dimm_label_show, channel_dimm_label_store, 3); |
7a623c03 | 316 | DEVICE_CHANNEL(ch4_dimm_label, S_IRUGO | S_IWUSR, |
052dfb45 | 317 | channel_dimm_label_show, channel_dimm_label_store, 4); |
7a623c03 | 318 | DEVICE_CHANNEL(ch5_dimm_label, S_IRUGO | S_IWUSR, |
052dfb45 | 319 | channel_dimm_label_show, channel_dimm_label_store, 5); |
7c9281d7 DT |
320 | |
321 | /* Total possible dynamic DIMM Label attribute file table */ | |
7a623c03 MCC |
322 | static struct device_attribute *dynamic_csrow_dimm_attr[] = { |
323 | &dev_attr_legacy_ch0_dimm_label.attr, | |
324 | &dev_attr_legacy_ch1_dimm_label.attr, | |
325 | &dev_attr_legacy_ch2_dimm_label.attr, | |
326 | &dev_attr_legacy_ch3_dimm_label.attr, | |
327 | &dev_attr_legacy_ch4_dimm_label.attr, | |
328 | &dev_attr_legacy_ch5_dimm_label.attr | |
7c9281d7 DT |
329 | }; |
330 | ||
331 | /* possible dynamic channel ce_count attribute files */ | |
c8c64d16 | 332 | DEVICE_CHANNEL(ch0_ce_count, S_IRUGO, |
7a623c03 | 333 | channel_ce_count_show, NULL, 0); |
c8c64d16 | 334 | DEVICE_CHANNEL(ch1_ce_count, S_IRUGO, |
7a623c03 | 335 | channel_ce_count_show, NULL, 1); |
c8c64d16 | 336 | DEVICE_CHANNEL(ch2_ce_count, S_IRUGO, |
7a623c03 | 337 | channel_ce_count_show, NULL, 2); |
c8c64d16 | 338 | DEVICE_CHANNEL(ch3_ce_count, S_IRUGO, |
7a623c03 | 339 | channel_ce_count_show, NULL, 3); |
c8c64d16 | 340 | DEVICE_CHANNEL(ch4_ce_count, S_IRUGO, |
7a623c03 | 341 | channel_ce_count_show, NULL, 4); |
c8c64d16 | 342 | DEVICE_CHANNEL(ch5_ce_count, S_IRUGO, |
7a623c03 | 343 | channel_ce_count_show, NULL, 5); |
7c9281d7 DT |
344 | |
345 | /* Total possible dynamic ce_count attribute file table */ | |
7a623c03 MCC |
346 | static struct device_attribute *dynamic_csrow_ce_count_attr[] = { |
347 | &dev_attr_legacy_ch0_ce_count.attr, | |
348 | &dev_attr_legacy_ch1_ce_count.attr, | |
349 | &dev_attr_legacy_ch2_ce_count.attr, | |
350 | &dev_attr_legacy_ch3_ce_count.attr, | |
351 | &dev_attr_legacy_ch4_ce_count.attr, | |
352 | &dev_attr_legacy_ch5_ce_count.attr | |
7c9281d7 DT |
353 | }; |
354 | ||
e39f4ea9 MCC |
355 | static inline int nr_pages_per_csrow(struct csrow_info *csrow) |
356 | { | |
357 | int chan, nr_pages = 0; | |
358 | ||
359 | for (chan = 0; chan < csrow->nr_channels; chan++) | |
de3910eb | 360 | nr_pages += csrow->channels[chan]->dimm->nr_pages; |
e39f4ea9 MCC |
361 | |
362 | return nr_pages; | |
363 | } | |
364 | ||
7a623c03 MCC |
365 | /* Create a CSROW object under specifed edac_mc_device */ |
366 | static int edac_create_csrow_object(struct mem_ctl_info *mci, | |
367 | struct csrow_info *csrow, int index) | |
7c9281d7 | 368 | { |
7a623c03 | 369 | int err, chan; |
7c9281d7 | 370 | |
7a623c03 MCC |
371 | if (csrow->nr_channels >= EDAC_NR_CHANNELS) |
372 | return -ENODEV; | |
7c9281d7 | 373 | |
7a623c03 | 374 | csrow->dev.type = &csrow_attr_type; |
88d84ac9 | 375 | csrow->dev.bus = mci->bus; |
7a623c03 MCC |
376 | device_initialize(&csrow->dev); |
377 | csrow->dev.parent = &mci->dev; | |
921a6899 | 378 | csrow->mci = mci; |
7a623c03 MCC |
379 | dev_set_name(&csrow->dev, "csrow%d", index); |
380 | dev_set_drvdata(&csrow->dev, csrow); | |
7c9281d7 | 381 | |
956b9ba1 JP |
382 | edac_dbg(0, "creating (virtual) csrow node %s\n", |
383 | dev_name(&csrow->dev)); | |
7c9281d7 | 384 | |
7a623c03 MCC |
385 | err = device_add(&csrow->dev); |
386 | if (err < 0) | |
387 | return err; | |
7c9281d7 | 388 | |
7a623c03 | 389 | for (chan = 0; chan < csrow->nr_channels; chan++) { |
e39f4ea9 | 390 | /* Only expose populated DIMMs */ |
de3910eb | 391 | if (!csrow->channels[chan]->dimm->nr_pages) |
e39f4ea9 | 392 | continue; |
7a623c03 MCC |
393 | err = device_create_file(&csrow->dev, |
394 | dynamic_csrow_dimm_attr[chan]); | |
395 | if (err < 0) | |
396 | goto error; | |
397 | err = device_create_file(&csrow->dev, | |
398 | dynamic_csrow_ce_count_attr[chan]); | |
399 | if (err < 0) { | |
400 | device_remove_file(&csrow->dev, | |
401 | dynamic_csrow_dimm_attr[chan]); | |
402 | goto error; | |
403 | } | |
404 | } | |
8096cfaf | 405 | |
7a623c03 | 406 | return 0; |
8096cfaf | 407 | |
7a623c03 MCC |
408 | error: |
409 | for (--chan; chan >= 0; chan--) { | |
410 | device_remove_file(&csrow->dev, | |
411 | dynamic_csrow_dimm_attr[chan]); | |
412 | device_remove_file(&csrow->dev, | |
413 | dynamic_csrow_ce_count_attr[chan]); | |
414 | } | |
415 | put_device(&csrow->dev); | |
7c9281d7 | 416 | |
7a623c03 MCC |
417 | return err; |
418 | } | |
7c9281d7 DT |
419 | |
420 | /* Create a CSROW object under specifed edac_mc_device */ | |
7a623c03 | 421 | static int edac_create_csrow_objects(struct mem_ctl_info *mci) |
7c9281d7 | 422 | { |
7a623c03 MCC |
423 | int err, i, chan; |
424 | struct csrow_info *csrow; | |
7c9281d7 | 425 | |
7a623c03 | 426 | for (i = 0; i < mci->nr_csrows; i++) { |
de3910eb | 427 | csrow = mci->csrows[i]; |
e39f4ea9 MCC |
428 | if (!nr_pages_per_csrow(csrow)) |
429 | continue; | |
de3910eb | 430 | err = edac_create_csrow_object(mci, mci->csrows[i], i); |
3d958823 MCC |
431 | if (err < 0) { |
432 | edac_dbg(1, | |
433 | "failure: create csrow objects for csrow %d\n", | |
434 | i); | |
7a623c03 | 435 | goto error; |
3d958823 | 436 | } |
7a623c03 MCC |
437 | } |
438 | return 0; | |
8096cfaf | 439 | |
7a623c03 MCC |
440 | error: |
441 | for (--i; i >= 0; i--) { | |
de3910eb | 442 | csrow = mci->csrows[i]; |
e39f4ea9 MCC |
443 | if (!nr_pages_per_csrow(csrow)) |
444 | continue; | |
7a623c03 | 445 | for (chan = csrow->nr_channels - 1; chan >= 0; chan--) { |
de3910eb | 446 | if (!csrow->channels[chan]->dimm->nr_pages) |
e39f4ea9 | 447 | continue; |
7a623c03 MCC |
448 | device_remove_file(&csrow->dev, |
449 | dynamic_csrow_dimm_attr[chan]); | |
450 | device_remove_file(&csrow->dev, | |
451 | dynamic_csrow_ce_count_attr[chan]); | |
452 | } | |
de3910eb | 453 | put_device(&mci->csrows[i]->dev); |
8096cfaf | 454 | } |
7c9281d7 | 455 | |
7a623c03 MCC |
456 | return err; |
457 | } | |
8096cfaf | 458 | |
7a623c03 MCC |
459 | static void edac_delete_csrow_objects(struct mem_ctl_info *mci) |
460 | { | |
461 | int i, chan; | |
462 | struct csrow_info *csrow; | |
8096cfaf | 463 | |
7a623c03 | 464 | for (i = mci->nr_csrows - 1; i >= 0; i--) { |
de3910eb | 465 | csrow = mci->csrows[i]; |
e39f4ea9 MCC |
466 | if (!nr_pages_per_csrow(csrow)) |
467 | continue; | |
7a623c03 | 468 | for (chan = csrow->nr_channels - 1; chan >= 0; chan--) { |
de3910eb | 469 | if (!csrow->channels[chan]->dimm->nr_pages) |
e39f4ea9 | 470 | continue; |
956b9ba1 JP |
471 | edac_dbg(1, "Removing csrow %d channel %d sysfs nodes\n", |
472 | i, chan); | |
7a623c03 MCC |
473 | device_remove_file(&csrow->dev, |
474 | dynamic_csrow_dimm_attr[chan]); | |
475 | device_remove_file(&csrow->dev, | |
476 | dynamic_csrow_ce_count_attr[chan]); | |
7c9281d7 | 477 | } |
44d22e24 | 478 | device_unregister(&mci->csrows[i]->dev); |
7c9281d7 | 479 | } |
7c9281d7 | 480 | } |
19974710 MCC |
481 | #endif |
482 | ||
483 | /* | |
484 | * Per-dimm (or per-rank) devices | |
485 | */ | |
486 | ||
487 | #define to_dimm(k) container_of(k, struct dimm_info, dev) | |
488 | ||
489 | /* show/store functions for DIMM Label attributes */ | |
490 | static ssize_t dimmdev_location_show(struct device *dev, | |
491 | struct device_attribute *mattr, char *data) | |
492 | { | |
493 | struct dimm_info *dimm = to_dimm(dev); | |
19974710 | 494 | |
6e84d359 | 495 | return edac_dimm_info_location(dimm, data, PAGE_SIZE); |
19974710 MCC |
496 | } |
497 | ||
498 | static ssize_t dimmdev_label_show(struct device *dev, | |
499 | struct device_attribute *mattr, char *data) | |
500 | { | |
501 | struct dimm_info *dimm = to_dimm(dev); | |
502 | ||
503 | /* if field has not been initialized, there is nothing to send */ | |
504 | if (!dimm->label[0]) | |
505 | return 0; | |
506 | ||
507 | return snprintf(data, EDAC_MC_LABEL_LEN, "%s\n", dimm->label); | |
508 | } | |
509 | ||
510 | static ssize_t dimmdev_label_store(struct device *dev, | |
511 | struct device_attribute *mattr, | |
512 | const char *data, | |
513 | size_t count) | |
514 | { | |
515 | struct dimm_info *dimm = to_dimm(dev); | |
516 | ||
517 | ssize_t max_size = 0; | |
518 | ||
519 | max_size = min((ssize_t) count, (ssize_t) EDAC_MC_LABEL_LEN - 1); | |
520 | strncpy(dimm->label, data, max_size); | |
521 | dimm->label[max_size] = '\0'; | |
522 | ||
523 | return max_size; | |
524 | } | |
525 | ||
526 | static ssize_t dimmdev_size_show(struct device *dev, | |
527 | struct device_attribute *mattr, char *data) | |
528 | { | |
529 | struct dimm_info *dimm = to_dimm(dev); | |
530 | ||
531 | return sprintf(data, "%u\n", PAGES_TO_MiB(dimm->nr_pages)); | |
532 | } | |
533 | ||
534 | static ssize_t dimmdev_mem_type_show(struct device *dev, | |
535 | struct device_attribute *mattr, char *data) | |
536 | { | |
537 | struct dimm_info *dimm = to_dimm(dev); | |
538 | ||
539 | return sprintf(data, "%s\n", mem_types[dimm->mtype]); | |
540 | } | |
541 | ||
542 | static ssize_t dimmdev_dev_type_show(struct device *dev, | |
543 | struct device_attribute *mattr, char *data) | |
544 | { | |
545 | struct dimm_info *dimm = to_dimm(dev); | |
546 | ||
547 | return sprintf(data, "%s\n", dev_types[dimm->dtype]); | |
548 | } | |
549 | ||
550 | static ssize_t dimmdev_edac_mode_show(struct device *dev, | |
551 | struct device_attribute *mattr, | |
552 | char *data) | |
553 | { | |
554 | struct dimm_info *dimm = to_dimm(dev); | |
555 | ||
556 | return sprintf(data, "%s\n", edac_caps[dimm->edac_mode]); | |
557 | } | |
558 | ||
559 | /* dimm/rank attribute files */ | |
560 | static DEVICE_ATTR(dimm_label, S_IRUGO | S_IWUSR, | |
561 | dimmdev_label_show, dimmdev_label_store); | |
562 | static DEVICE_ATTR(dimm_location, S_IRUGO, dimmdev_location_show, NULL); | |
563 | static DEVICE_ATTR(size, S_IRUGO, dimmdev_size_show, NULL); | |
564 | static DEVICE_ATTR(dimm_mem_type, S_IRUGO, dimmdev_mem_type_show, NULL); | |
565 | static DEVICE_ATTR(dimm_dev_type, S_IRUGO, dimmdev_dev_type_show, NULL); | |
566 | static DEVICE_ATTR(dimm_edac_mode, S_IRUGO, dimmdev_edac_mode_show, NULL); | |
567 | ||
568 | /* attributes of the dimm<id>/rank<id> object */ | |
569 | static struct attribute *dimm_attrs[] = { | |
570 | &dev_attr_dimm_label.attr, | |
571 | &dev_attr_dimm_location.attr, | |
572 | &dev_attr_size.attr, | |
573 | &dev_attr_dimm_mem_type.attr, | |
574 | &dev_attr_dimm_dev_type.attr, | |
575 | &dev_attr_dimm_edac_mode.attr, | |
576 | NULL, | |
577 | }; | |
578 | ||
579 | static struct attribute_group dimm_attr_grp = { | |
580 | .attrs = dimm_attrs, | |
581 | }; | |
582 | ||
583 | static const struct attribute_group *dimm_attr_groups[] = { | |
584 | &dimm_attr_grp, | |
585 | NULL | |
586 | }; | |
587 | ||
de3910eb | 588 | static void dimm_attr_release(struct device *dev) |
19974710 | 589 | { |
de3910eb MCC |
590 | struct dimm_info *dimm = container_of(dev, struct dimm_info, dev); |
591 | ||
956b9ba1 | 592 | edac_dbg(1, "Releasing dimm device %s\n", dev_name(dev)); |
de3910eb | 593 | kfree(dimm); |
19974710 MCC |
594 | } |
595 | ||
596 | static struct device_type dimm_attr_type = { | |
597 | .groups = dimm_attr_groups, | |
598 | .release = dimm_attr_release, | |
599 | }; | |
600 | ||
601 | /* Create a DIMM object under specifed memory controller device */ | |
602 | static int edac_create_dimm_object(struct mem_ctl_info *mci, | |
603 | struct dimm_info *dimm, | |
604 | int index) | |
605 | { | |
606 | int err; | |
607 | dimm->mci = mci; | |
608 | ||
609 | dimm->dev.type = &dimm_attr_type; | |
88d84ac9 | 610 | dimm->dev.bus = mci->bus; |
19974710 MCC |
611 | device_initialize(&dimm->dev); |
612 | ||
613 | dimm->dev.parent = &mci->dev; | |
9713faec | 614 | if (mci->csbased) |
19974710 MCC |
615 | dev_set_name(&dimm->dev, "rank%d", index); |
616 | else | |
617 | dev_set_name(&dimm->dev, "dimm%d", index); | |
618 | dev_set_drvdata(&dimm->dev, dimm); | |
619 | pm_runtime_forbid(&mci->dev); | |
620 | ||
621 | err = device_add(&dimm->dev); | |
622 | ||
956b9ba1 | 623 | edac_dbg(0, "creating rank/dimm device %s\n", dev_name(&dimm->dev)); |
19974710 MCC |
624 | |
625 | return err; | |
626 | } | |
7c9281d7 | 627 | |
7a623c03 MCC |
628 | /* |
629 | * Memory controller device | |
630 | */ | |
631 | ||
632 | #define to_mci(k) container_of(k, struct mem_ctl_info, dev) | |
7c9281d7 | 633 | |
7a623c03 MCC |
634 | static ssize_t mci_reset_counters_store(struct device *dev, |
635 | struct device_attribute *mattr, | |
079708b9 | 636 | const char *data, size_t count) |
7c9281d7 | 637 | { |
7a623c03 MCC |
638 | struct mem_ctl_info *mci = to_mci(dev); |
639 | int cnt, row, chan, i; | |
5926ff50 MCC |
640 | mci->ue_mc = 0; |
641 | mci->ce_mc = 0; | |
7a623c03 MCC |
642 | mci->ue_noinfo_count = 0; |
643 | mci->ce_noinfo_count = 0; | |
7c9281d7 DT |
644 | |
645 | for (row = 0; row < mci->nr_csrows; row++) { | |
de3910eb | 646 | struct csrow_info *ri = mci->csrows[row]; |
7c9281d7 DT |
647 | |
648 | ri->ue_count = 0; | |
649 | ri->ce_count = 0; | |
650 | ||
651 | for (chan = 0; chan < ri->nr_channels; chan++) | |
de3910eb | 652 | ri->channels[chan]->ce_count = 0; |
7c9281d7 DT |
653 | } |
654 | ||
7a623c03 MCC |
655 | cnt = 1; |
656 | for (i = 0; i < mci->n_layers; i++) { | |
657 | cnt *= mci->layers[i].size; | |
658 | memset(mci->ce_per_layer[i], 0, cnt * sizeof(u32)); | |
659 | memset(mci->ue_per_layer[i], 0, cnt * sizeof(u32)); | |
660 | } | |
661 | ||
7c9281d7 DT |
662 | mci->start_time = jiffies; |
663 | return count; | |
664 | } | |
665 | ||
39094443 BP |
666 | /* Memory scrubbing interface: |
667 | * | |
668 | * A MC driver can limit the scrubbing bandwidth based on the CPU type. | |
669 | * Therefore, ->set_sdram_scrub_rate should be made to return the actual | |
670 | * bandwidth that is accepted or 0 when scrubbing is to be disabled. | |
671 | * | |
672 | * Negative value still means that an error has occurred while setting | |
673 | * the scrub rate. | |
674 | */ | |
7a623c03 MCC |
675 | static ssize_t mci_sdram_scrub_rate_store(struct device *dev, |
676 | struct device_attribute *mattr, | |
eba042a8 | 677 | const char *data, size_t count) |
7c9281d7 | 678 | { |
7a623c03 | 679 | struct mem_ctl_info *mci = to_mci(dev); |
eba042a8 | 680 | unsigned long bandwidth = 0; |
39094443 | 681 | int new_bw = 0; |
7c9281d7 | 682 | |
c7f62fc8 | 683 | if (kstrtoul(data, 10, &bandwidth) < 0) |
eba042a8 | 684 | return -EINVAL; |
7c9281d7 | 685 | |
39094443 | 686 | new_bw = mci->set_sdram_scrub_rate(mci, bandwidth); |
4949603a MT |
687 | if (new_bw < 0) { |
688 | edac_printk(KERN_WARNING, EDAC_MC, | |
689 | "Error setting scrub rate to: %lu\n", bandwidth); | |
690 | return -EINVAL; | |
7c9281d7 | 691 | } |
39094443 | 692 | |
4949603a | 693 | return count; |
7c9281d7 DT |
694 | } |
695 | ||
39094443 BP |
696 | /* |
697 | * ->get_sdram_scrub_rate() return value semantics same as above. | |
698 | */ | |
7a623c03 MCC |
699 | static ssize_t mci_sdram_scrub_rate_show(struct device *dev, |
700 | struct device_attribute *mattr, | |
701 | char *data) | |
7c9281d7 | 702 | { |
7a623c03 | 703 | struct mem_ctl_info *mci = to_mci(dev); |
39094443 | 704 | int bandwidth = 0; |
eba042a8 | 705 | |
39094443 BP |
706 | bandwidth = mci->get_sdram_scrub_rate(mci); |
707 | if (bandwidth < 0) { | |
eba042a8 | 708 | edac_printk(KERN_DEBUG, EDAC_MC, "Error reading scrub rate\n"); |
39094443 | 709 | return bandwidth; |
7c9281d7 | 710 | } |
39094443 | 711 | |
39094443 | 712 | return sprintf(data, "%d\n", bandwidth); |
7c9281d7 DT |
713 | } |
714 | ||
715 | /* default attribute files for the MCI object */ | |
7a623c03 MCC |
716 | static ssize_t mci_ue_count_show(struct device *dev, |
717 | struct device_attribute *mattr, | |
718 | char *data) | |
7c9281d7 | 719 | { |
7a623c03 MCC |
720 | struct mem_ctl_info *mci = to_mci(dev); |
721 | ||
5926ff50 | 722 | return sprintf(data, "%d\n", mci->ue_mc); |
7c9281d7 DT |
723 | } |
724 | ||
7a623c03 MCC |
725 | static ssize_t mci_ce_count_show(struct device *dev, |
726 | struct device_attribute *mattr, | |
727 | char *data) | |
7c9281d7 | 728 | { |
7a623c03 MCC |
729 | struct mem_ctl_info *mci = to_mci(dev); |
730 | ||
5926ff50 | 731 | return sprintf(data, "%d\n", mci->ce_mc); |
7c9281d7 DT |
732 | } |
733 | ||
7a623c03 MCC |
734 | static ssize_t mci_ce_noinfo_show(struct device *dev, |
735 | struct device_attribute *mattr, | |
736 | char *data) | |
7c9281d7 | 737 | { |
7a623c03 MCC |
738 | struct mem_ctl_info *mci = to_mci(dev); |
739 | ||
079708b9 | 740 | return sprintf(data, "%d\n", mci->ce_noinfo_count); |
7c9281d7 DT |
741 | } |
742 | ||
7a623c03 MCC |
743 | static ssize_t mci_ue_noinfo_show(struct device *dev, |
744 | struct device_attribute *mattr, | |
745 | char *data) | |
7c9281d7 | 746 | { |
7a623c03 MCC |
747 | struct mem_ctl_info *mci = to_mci(dev); |
748 | ||
079708b9 | 749 | return sprintf(data, "%d\n", mci->ue_noinfo_count); |
7c9281d7 DT |
750 | } |
751 | ||
7a623c03 MCC |
752 | static ssize_t mci_seconds_show(struct device *dev, |
753 | struct device_attribute *mattr, | |
754 | char *data) | |
7c9281d7 | 755 | { |
7a623c03 MCC |
756 | struct mem_ctl_info *mci = to_mci(dev); |
757 | ||
079708b9 | 758 | return sprintf(data, "%ld\n", (jiffies - mci->start_time) / HZ); |
7c9281d7 DT |
759 | } |
760 | ||
7a623c03 MCC |
761 | static ssize_t mci_ctl_name_show(struct device *dev, |
762 | struct device_attribute *mattr, | |
763 | char *data) | |
7c9281d7 | 764 | { |
7a623c03 MCC |
765 | struct mem_ctl_info *mci = to_mci(dev); |
766 | ||
079708b9 | 767 | return sprintf(data, "%s\n", mci->ctl_name); |
7c9281d7 DT |
768 | } |
769 | ||
7a623c03 MCC |
770 | static ssize_t mci_size_mb_show(struct device *dev, |
771 | struct device_attribute *mattr, | |
772 | char *data) | |
7c9281d7 | 773 | { |
7a623c03 | 774 | struct mem_ctl_info *mci = to_mci(dev); |
a895bf8b | 775 | int total_pages = 0, csrow_idx, j; |
7c9281d7 | 776 | |
a895bf8b | 777 | for (csrow_idx = 0; csrow_idx < mci->nr_csrows; csrow_idx++) { |
de3910eb | 778 | struct csrow_info *csrow = mci->csrows[csrow_idx]; |
7c9281d7 | 779 | |
1eef1282 MCC |
780 | for (j = 0; j < csrow->nr_channels; j++) { |
781 | struct dimm_info *dimm = csrow->channels[j]->dimm; | |
3c062276 | 782 | |
1eef1282 | 783 | total_pages += dimm->nr_pages; |
a895bf8b | 784 | } |
7c9281d7 DT |
785 | } |
786 | ||
079708b9 | 787 | return sprintf(data, "%u\n", PAGES_TO_MiB(total_pages)); |
7c9281d7 DT |
788 | } |
789 | ||
8ad6c78a MCC |
790 | static ssize_t mci_max_location_show(struct device *dev, |
791 | struct device_attribute *mattr, | |
792 | char *data) | |
793 | { | |
794 | struct mem_ctl_info *mci = to_mci(dev); | |
795 | int i; | |
796 | char *p = data; | |
797 | ||
798 | for (i = 0; i < mci->n_layers; i++) { | |
799 | p += sprintf(p, "%s %d ", | |
800 | edac_layer_name[mci->layers[i].type], | |
801 | mci->layers[i].size - 1); | |
802 | } | |
803 | ||
804 | return p - data; | |
805 | } | |
806 | ||
452a6bf9 MCC |
807 | #ifdef CONFIG_EDAC_DEBUG |
808 | static ssize_t edac_fake_inject_write(struct file *file, | |
809 | const char __user *data, | |
810 | size_t count, loff_t *ppos) | |
811 | { | |
812 | struct device *dev = file->private_data; | |
813 | struct mem_ctl_info *mci = to_mci(dev); | |
814 | static enum hw_event_mc_err_type type; | |
38ced28b MCC |
815 | u16 errcount = mci->fake_inject_count; |
816 | ||
817 | if (!errcount) | |
818 | errcount = 1; | |
452a6bf9 MCC |
819 | |
820 | type = mci->fake_inject_ue ? HW_EVENT_ERR_UNCORRECTED | |
821 | : HW_EVENT_ERR_CORRECTED; | |
822 | ||
823 | printk(KERN_DEBUG | |
38ced28b MCC |
824 | "Generating %d %s fake error%s to %d.%d.%d to test core handling. NOTE: this won't test the driver-specific decoding logic.\n", |
825 | errcount, | |
452a6bf9 | 826 | (type == HW_EVENT_ERR_UNCORRECTED) ? "UE" : "CE", |
38ced28b | 827 | errcount > 1 ? "s" : "", |
452a6bf9 MCC |
828 | mci->fake_inject_layer[0], |
829 | mci->fake_inject_layer[1], | |
830 | mci->fake_inject_layer[2] | |
831 | ); | |
38ced28b | 832 | edac_mc_handle_error(type, mci, errcount, 0, 0, 0, |
452a6bf9 MCC |
833 | mci->fake_inject_layer[0], |
834 | mci->fake_inject_layer[1], | |
835 | mci->fake_inject_layer[2], | |
03f7eae8 | 836 | "FAKE ERROR", "for EDAC testing only"); |
452a6bf9 MCC |
837 | |
838 | return count; | |
839 | } | |
840 | ||
452a6bf9 | 841 | static const struct file_operations debug_fake_inject_fops = { |
db7312a2 | 842 | .open = simple_open, |
452a6bf9 MCC |
843 | .write = edac_fake_inject_write, |
844 | .llseek = generic_file_llseek, | |
845 | }; | |
846 | #endif | |
847 | ||
7c9281d7 | 848 | /* default Control file */ |
7a623c03 | 849 | DEVICE_ATTR(reset_counters, S_IWUSR, NULL, mci_reset_counters_store); |
7c9281d7 DT |
850 | |
851 | /* default Attribute files */ | |
7a623c03 MCC |
852 | DEVICE_ATTR(mc_name, S_IRUGO, mci_ctl_name_show, NULL); |
853 | DEVICE_ATTR(size_mb, S_IRUGO, mci_size_mb_show, NULL); | |
854 | DEVICE_ATTR(seconds_since_reset, S_IRUGO, mci_seconds_show, NULL); | |
855 | DEVICE_ATTR(ue_noinfo_count, S_IRUGO, mci_ue_noinfo_show, NULL); | |
856 | DEVICE_ATTR(ce_noinfo_count, S_IRUGO, mci_ce_noinfo_show, NULL); | |
857 | DEVICE_ATTR(ue_count, S_IRUGO, mci_ue_count_show, NULL); | |
858 | DEVICE_ATTR(ce_count, S_IRUGO, mci_ce_count_show, NULL); | |
8ad6c78a | 859 | DEVICE_ATTR(max_location, S_IRUGO, mci_max_location_show, NULL); |
7c9281d7 DT |
860 | |
861 | /* memory scrubber attribute file */ | |
e7100478 | 862 | DEVICE_ATTR(sdram_scrub_rate, 0, NULL, NULL); |
7c9281d7 | 863 | |
7a623c03 MCC |
864 | static struct attribute *mci_attrs[] = { |
865 | &dev_attr_reset_counters.attr, | |
866 | &dev_attr_mc_name.attr, | |
867 | &dev_attr_size_mb.attr, | |
868 | &dev_attr_seconds_since_reset.attr, | |
869 | &dev_attr_ue_noinfo_count.attr, | |
870 | &dev_attr_ce_noinfo_count.attr, | |
871 | &dev_attr_ue_count.attr, | |
872 | &dev_attr_ce_count.attr, | |
8ad6c78a | 873 | &dev_attr_max_location.attr, |
7c9281d7 DT |
874 | NULL |
875 | }; | |
876 | ||
7a623c03 MCC |
877 | static struct attribute_group mci_attr_grp = { |
878 | .attrs = mci_attrs, | |
cc301b3a MCC |
879 | }; |
880 | ||
7a623c03 MCC |
881 | static const struct attribute_group *mci_attr_groups[] = { |
882 | &mci_attr_grp, | |
883 | NULL | |
cc301b3a MCC |
884 | }; |
885 | ||
de3910eb | 886 | static void mci_attr_release(struct device *dev) |
42a8e397 | 887 | { |
de3910eb MCC |
888 | struct mem_ctl_info *mci = container_of(dev, struct mem_ctl_info, dev); |
889 | ||
956b9ba1 | 890 | edac_dbg(1, "Releasing csrow device %s\n", dev_name(dev)); |
de3910eb | 891 | kfree(mci); |
42a8e397 DT |
892 | } |
893 | ||
7a623c03 MCC |
894 | static struct device_type mci_attr_type = { |
895 | .groups = mci_attr_groups, | |
896 | .release = mci_attr_release, | |
897 | }; | |
8096cfaf | 898 | |
452a6bf9 | 899 | #ifdef CONFIG_EDAC_DEBUG |
e7930ba4 RH |
900 | static struct dentry *edac_debugfs; |
901 | ||
902 | int __init edac_debugfs_init(void) | |
903 | { | |
904 | edac_debugfs = debugfs_create_dir("edac", NULL); | |
905 | if (IS_ERR(edac_debugfs)) { | |
906 | edac_debugfs = NULL; | |
907 | return -ENOMEM; | |
908 | } | |
909 | return 0; | |
910 | } | |
911 | ||
912 | void __exit edac_debugfs_exit(void) | |
913 | { | |
914 | debugfs_remove(edac_debugfs); | |
915 | } | |
916 | ||
452a6bf9 MCC |
917 | int edac_create_debug_nodes(struct mem_ctl_info *mci) |
918 | { | |
919 | struct dentry *d, *parent; | |
920 | char name[80]; | |
921 | int i; | |
922 | ||
e7930ba4 RH |
923 | if (!edac_debugfs) |
924 | return -ENODEV; | |
925 | ||
926 | d = debugfs_create_dir(mci->dev.kobj.name, edac_debugfs); | |
452a6bf9 MCC |
927 | if (!d) |
928 | return -ENOMEM; | |
929 | parent = d; | |
930 | ||
931 | for (i = 0; i < mci->n_layers; i++) { | |
932 | sprintf(name, "fake_inject_%s", | |
933 | edac_layer_name[mci->layers[i].type]); | |
934 | d = debugfs_create_u8(name, S_IRUGO | S_IWUSR, parent, | |
935 | &mci->fake_inject_layer[i]); | |
936 | if (!d) | |
937 | goto nomem; | |
938 | } | |
939 | ||
940 | d = debugfs_create_bool("fake_inject_ue", S_IRUGO | S_IWUSR, parent, | |
941 | &mci->fake_inject_ue); | |
942 | if (!d) | |
943 | goto nomem; | |
944 | ||
38ced28b MCC |
945 | d = debugfs_create_u16("fake_inject_count", S_IRUGO | S_IWUSR, parent, |
946 | &mci->fake_inject_count); | |
947 | if (!d) | |
948 | goto nomem; | |
949 | ||
452a6bf9 MCC |
950 | d = debugfs_create_file("fake_inject", S_IWUSR, parent, |
951 | &mci->dev, | |
952 | &debug_fake_inject_fops); | |
953 | if (!d) | |
954 | goto nomem; | |
955 | ||
e7930ba4 | 956 | mci->debugfs = parent; |
452a6bf9 MCC |
957 | return 0; |
958 | nomem: | |
959 | debugfs_remove(mci->debugfs); | |
960 | return -ENOMEM; | |
961 | } | |
962 | #endif | |
963 | ||
7c9281d7 DT |
964 | /* |
965 | * Create a new Memory Controller kobject instance, | |
966 | * mc<id> under the 'mc' directory | |
967 | * | |
968 | * Return: | |
969 | * 0 Success | |
970 | * !0 Failure | |
971 | */ | |
972 | int edac_create_sysfs_mci_device(struct mem_ctl_info *mci) | |
973 | { | |
7a623c03 | 974 | int i, err; |
7c9281d7 | 975 | |
de3910eb MCC |
976 | /* |
977 | * The memory controller needs its own bus, in order to avoid | |
978 | * namespace conflicts at /sys/bus/edac. | |
979 | */ | |
88d84ac9 BP |
980 | mci->bus->name = kasprintf(GFP_KERNEL, "mc%d", mci->mc_idx); |
981 | if (!mci->bus->name) | |
de3910eb | 982 | return -ENOMEM; |
88d84ac9 BP |
983 | |
984 | edac_dbg(0, "creating bus %s\n", mci->bus->name); | |
985 | ||
986 | err = bus_register(mci->bus); | |
de3910eb MCC |
987 | if (err < 0) |
988 | return err; | |
7c9281d7 | 989 | |
7a623c03 | 990 | /* get the /sys/devices/system/edac subsys reference */ |
7a623c03 MCC |
991 | mci->dev.type = &mci_attr_type; |
992 | device_initialize(&mci->dev); | |
7c9281d7 | 993 | |
de3910eb | 994 | mci->dev.parent = mci_pdev; |
88d84ac9 | 995 | mci->dev.bus = mci->bus; |
7a623c03 MCC |
996 | dev_set_name(&mci->dev, "mc%d", mci->mc_idx); |
997 | dev_set_drvdata(&mci->dev, mci); | |
998 | pm_runtime_forbid(&mci->dev); | |
999 | ||
956b9ba1 | 1000 | edac_dbg(0, "creating device %s\n", dev_name(&mci->dev)); |
7a623c03 MCC |
1001 | err = device_add(&mci->dev); |
1002 | if (err < 0) { | |
3d958823 | 1003 | edac_dbg(1, "failure: create device %s\n", dev_name(&mci->dev)); |
88d84ac9 BP |
1004 | bus_unregister(mci->bus); |
1005 | kfree(mci->bus->name); | |
7a623c03 | 1006 | return err; |
42a8e397 DT |
1007 | } |
1008 | ||
e7100478 MCC |
1009 | if (mci->set_sdram_scrub_rate || mci->get_sdram_scrub_rate) { |
1010 | if (mci->get_sdram_scrub_rate) { | |
1011 | dev_attr_sdram_scrub_rate.attr.mode |= S_IRUGO; | |
1012 | dev_attr_sdram_scrub_rate.show = &mci_sdram_scrub_rate_show; | |
1013 | } | |
1014 | if (mci->set_sdram_scrub_rate) { | |
1015 | dev_attr_sdram_scrub_rate.attr.mode |= S_IWUSR; | |
1016 | dev_attr_sdram_scrub_rate.store = &mci_sdram_scrub_rate_store; | |
1017 | } | |
1018 | err = device_create_file(&mci->dev, | |
1019 | &dev_attr_sdram_scrub_rate); | |
1020 | if (err) { | |
1021 | edac_dbg(1, "failure: create sdram_scrub_rate\n"); | |
1022 | goto fail2; | |
1023 | } | |
1024 | } | |
7a623c03 MCC |
1025 | /* |
1026 | * Create the dimm/rank devices | |
7c9281d7 | 1027 | */ |
7a623c03 | 1028 | for (i = 0; i < mci->tot_dimms; i++) { |
de3910eb | 1029 | struct dimm_info *dimm = mci->dimms[i]; |
7a623c03 MCC |
1030 | /* Only expose populated DIMMs */ |
1031 | if (dimm->nr_pages == 0) | |
1032 | continue; | |
1033 | #ifdef CONFIG_EDAC_DEBUG | |
956b9ba1 | 1034 | edac_dbg(1, "creating dimm%d, located at ", i); |
7a623c03 MCC |
1035 | if (edac_debug_level >= 1) { |
1036 | int lay; | |
1037 | for (lay = 0; lay < mci->n_layers; lay++) | |
1038 | printk(KERN_CONT "%s %d ", | |
1039 | edac_layer_name[mci->layers[lay].type], | |
1040 | dimm->location[lay]); | |
1041 | printk(KERN_CONT "\n"); | |
7c9281d7 | 1042 | } |
7a623c03 | 1043 | #endif |
19974710 MCC |
1044 | err = edac_create_dimm_object(mci, dimm, i); |
1045 | if (err) { | |
956b9ba1 | 1046 | edac_dbg(1, "failure: create dimm %d obj\n", i); |
19974710 MCC |
1047 | goto fail; |
1048 | } | |
7c9281d7 DT |
1049 | } |
1050 | ||
19974710 | 1051 | #ifdef CONFIG_EDAC_LEGACY_SYSFS |
7a623c03 MCC |
1052 | err = edac_create_csrow_objects(mci); |
1053 | if (err < 0) | |
1054 | goto fail; | |
19974710 | 1055 | #endif |
7a623c03 | 1056 | |
452a6bf9 MCC |
1057 | #ifdef CONFIG_EDAC_DEBUG |
1058 | edac_create_debug_nodes(mci); | |
1059 | #endif | |
7c9281d7 DT |
1060 | return 0; |
1061 | ||
7a623c03 | 1062 | fail: |
079708b9 | 1063 | for (i--; i >= 0; i--) { |
de3910eb | 1064 | struct dimm_info *dimm = mci->dimms[i]; |
7a623c03 MCC |
1065 | if (dimm->nr_pages == 0) |
1066 | continue; | |
44d22e24 | 1067 | device_unregister(&dimm->dev); |
7c9281d7 | 1068 | } |
e7100478 | 1069 | fail2: |
44d22e24 | 1070 | device_unregister(&mci->dev); |
88d84ac9 BP |
1071 | bus_unregister(mci->bus); |
1072 | kfree(mci->bus->name); | |
7c9281d7 DT |
1073 | return err; |
1074 | } | |
1075 | ||
1076 | /* | |
1077 | * remove a Memory Controller instance | |
1078 | */ | |
1079 | void edac_remove_sysfs_mci_device(struct mem_ctl_info *mci) | |
1080 | { | |
7a623c03 | 1081 | int i; |
7c9281d7 | 1082 | |
956b9ba1 | 1083 | edac_dbg(0, "\n"); |
7c9281d7 | 1084 | |
452a6bf9 MCC |
1085 | #ifdef CONFIG_EDAC_DEBUG |
1086 | debugfs_remove(mci->debugfs); | |
1087 | #endif | |
19974710 | 1088 | #ifdef CONFIG_EDAC_LEGACY_SYSFS |
7a623c03 | 1089 | edac_delete_csrow_objects(mci); |
19974710 | 1090 | #endif |
7c9281d7 | 1091 | |
7a623c03 | 1092 | for (i = 0; i < mci->tot_dimms; i++) { |
de3910eb | 1093 | struct dimm_info *dimm = mci->dimms[i]; |
7a623c03 MCC |
1094 | if (dimm->nr_pages == 0) |
1095 | continue; | |
956b9ba1 | 1096 | edac_dbg(0, "removing device %s\n", dev_name(&dimm->dev)); |
44d22e24 | 1097 | device_unregister(&dimm->dev); |
6fe1108f | 1098 | } |
7c9281d7 | 1099 | } |
8096cfaf | 1100 | |
7a623c03 MCC |
1101 | void edac_unregister_sysfs(struct mem_ctl_info *mci) |
1102 | { | |
956b9ba1 | 1103 | edac_dbg(1, "Unregistering device %s\n", dev_name(&mci->dev)); |
44d22e24 | 1104 | device_unregister(&mci->dev); |
88d84ac9 BP |
1105 | bus_unregister(mci->bus); |
1106 | kfree(mci->bus->name); | |
7a623c03 | 1107 | } |
8096cfaf | 1108 | |
de3910eb | 1109 | static void mc_attr_release(struct device *dev) |
7a623c03 | 1110 | { |
de3910eb MCC |
1111 | /* |
1112 | * There's no container structure here, as this is just the mci | |
1113 | * parent device, used to create the /sys/devices/mc sysfs node. | |
1114 | * So, there are no attributes on it. | |
1115 | */ | |
956b9ba1 | 1116 | edac_dbg(1, "Releasing device %s\n", dev_name(dev)); |
de3910eb | 1117 | kfree(dev); |
7a623c03 | 1118 | } |
8096cfaf | 1119 | |
7a623c03 MCC |
1120 | static struct device_type mc_attr_type = { |
1121 | .release = mc_attr_release, | |
1122 | }; | |
8096cfaf | 1123 | /* |
7a623c03 | 1124 | * Init/exit code for the module. Basically, creates/removes /sys/class/rc |
8096cfaf | 1125 | */ |
7a623c03 | 1126 | int __init edac_mc_sysfs_init(void) |
8096cfaf | 1127 | { |
fe5ff8b8 | 1128 | struct bus_type *edac_subsys; |
7a623c03 | 1129 | int err; |
8096cfaf | 1130 | |
fe5ff8b8 KS |
1131 | /* get the /sys/devices/system/edac subsys reference */ |
1132 | edac_subsys = edac_get_sysfs_subsys(); | |
1133 | if (edac_subsys == NULL) { | |
956b9ba1 | 1134 | edac_dbg(1, "no edac_subsys\n"); |
2d56b109 DK |
1135 | err = -EINVAL; |
1136 | goto out; | |
8096cfaf DT |
1137 | } |
1138 | ||
de3910eb | 1139 | mci_pdev = kzalloc(sizeof(*mci_pdev), GFP_KERNEL); |
2d56b109 DK |
1140 | if (!mci_pdev) { |
1141 | err = -ENOMEM; | |
1142 | goto out_put_sysfs; | |
1143 | } | |
de3910eb MCC |
1144 | |
1145 | mci_pdev->bus = edac_subsys; | |
1146 | mci_pdev->type = &mc_attr_type; | |
1147 | device_initialize(mci_pdev); | |
1148 | dev_set_name(mci_pdev, "mc"); | |
8096cfaf | 1149 | |
de3910eb | 1150 | err = device_add(mci_pdev); |
7a623c03 | 1151 | if (err < 0) |
2d56b109 | 1152 | goto out_dev_free; |
8096cfaf | 1153 | |
956b9ba1 | 1154 | edac_dbg(0, "device %s created\n", dev_name(mci_pdev)); |
de3910eb | 1155 | |
8096cfaf | 1156 | return 0; |
2d56b109 DK |
1157 | |
1158 | out_dev_free: | |
1159 | kfree(mci_pdev); | |
1160 | out_put_sysfs: | |
1161 | edac_put_sysfs_subsys(); | |
1162 | out: | |
1163 | return err; | |
8096cfaf DT |
1164 | } |
1165 | ||
7a623c03 | 1166 | void __exit edac_mc_sysfs_exit(void) |
8096cfaf | 1167 | { |
44d22e24 | 1168 | device_unregister(mci_pdev); |
fe5ff8b8 | 1169 | edac_put_sysfs_subsys(); |
8096cfaf | 1170 | } |