Commit | Line | Data |
---|---|---|
7c9281d7 DT |
1 | /* |
2 | * edac_mc kernel module | |
42a8e397 DT |
3 | * (C) 2005-2007 Linux Networx (http://lnxi.com) |
4 | * | |
7c9281d7 DT |
5 | * This file may be distributed under the terms of the |
6 | * GNU General Public License. | |
7 | * | |
42a8e397 | 8 | * Written Doug Thompson <norsk5@xmission.com> www.softwarebitmaker.com |
7c9281d7 | 9 | * |
37e59f87 | 10 | * (c) 2012-2013 - Mauro Carvalho Chehab |
7a623c03 MCC |
11 | * The entire API were re-written, and ported to use struct device |
12 | * | |
7c9281d7 DT |
13 | */ |
14 | ||
7c9281d7 | 15 | #include <linux/ctype.h> |
5a0e3ad6 | 16 | #include <linux/slab.h> |
30e1f7a8 | 17 | #include <linux/edac.h> |
8096cfaf | 18 | #include <linux/bug.h> |
7a623c03 | 19 | #include <linux/pm_runtime.h> |
452a6bf9 | 20 | #include <linux/uaccess.h> |
7c9281d7 | 21 | |
20bcb7a8 | 22 | #include "edac_core.h" |
7c9281d7 DT |
23 | #include "edac_module.h" |
24 | ||
25 | /* MC EDAC Controls, setable by module parameter, and sysfs */ | |
4de78c68 DJ |
26 | static int edac_mc_log_ue = 1; |
27 | static int edac_mc_log_ce = 1; | |
f044091c | 28 | static int edac_mc_panic_on_ue; |
4de78c68 | 29 | static int edac_mc_poll_msec = 1000; |
7c9281d7 DT |
30 | |
31 | /* Getter functions for above */ | |
4de78c68 | 32 | int edac_mc_get_log_ue(void) |
7c9281d7 | 33 | { |
4de78c68 | 34 | return edac_mc_log_ue; |
7c9281d7 DT |
35 | } |
36 | ||
4de78c68 | 37 | int edac_mc_get_log_ce(void) |
7c9281d7 | 38 | { |
4de78c68 | 39 | return edac_mc_log_ce; |
7c9281d7 DT |
40 | } |
41 | ||
4de78c68 | 42 | int edac_mc_get_panic_on_ue(void) |
7c9281d7 | 43 | { |
4de78c68 | 44 | return edac_mc_panic_on_ue; |
7c9281d7 DT |
45 | } |
46 | ||
81d87cb1 DJ |
47 | /* this is temporary */ |
48 | int edac_mc_get_poll_msec(void) | |
49 | { | |
4de78c68 | 50 | return edac_mc_poll_msec; |
7c9281d7 DT |
51 | } |
52 | ||
096846e2 AJ |
53 | static int edac_set_poll_msec(const char *val, struct kernel_param *kp) |
54 | { | |
9da21b15 | 55 | unsigned long l; |
096846e2 AJ |
56 | int ret; |
57 | ||
58 | if (!val) | |
59 | return -EINVAL; | |
60 | ||
9da21b15 | 61 | ret = kstrtoul(val, 0, &l); |
c542b53d JH |
62 | if (ret) |
63 | return ret; | |
9da21b15 BP |
64 | |
65 | if (l < 1000) | |
096846e2 | 66 | return -EINVAL; |
9da21b15 BP |
67 | |
68 | *((unsigned long *)kp->arg) = l; | |
096846e2 AJ |
69 | |
70 | /* notify edac_mc engine to reset the poll period */ | |
71 | edac_mc_reset_delay_period(l); | |
72 | ||
73 | return 0; | |
74 | } | |
75 | ||
7c9281d7 | 76 | /* Parameter declarations for above */ |
4de78c68 DJ |
77 | module_param(edac_mc_panic_on_ue, int, 0644); |
78 | MODULE_PARM_DESC(edac_mc_panic_on_ue, "Panic on uncorrected error: 0=off 1=on"); | |
79 | module_param(edac_mc_log_ue, int, 0644); | |
80 | MODULE_PARM_DESC(edac_mc_log_ue, | |
079708b9 | 81 | "Log uncorrectable error to console: 0=off 1=on"); |
4de78c68 DJ |
82 | module_param(edac_mc_log_ce, int, 0644); |
83 | MODULE_PARM_DESC(edac_mc_log_ce, | |
079708b9 | 84 | "Log correctable error to console: 0=off 1=on"); |
096846e2 AJ |
85 | module_param_call(edac_mc_poll_msec, edac_set_poll_msec, param_get_int, |
86 | &edac_mc_poll_msec, 0644); | |
4de78c68 | 87 | MODULE_PARM_DESC(edac_mc_poll_msec, "Polling period in milliseconds"); |
7c9281d7 | 88 | |
de3910eb | 89 | static struct device *mci_pdev; |
7a623c03 | 90 | |
7c9281d7 DT |
91 | /* |
92 | * various constants for Memory Controllers | |
93 | */ | |
8b7719e0 | 94 | static const char * const mem_types[] = { |
7c9281d7 DT |
95 | [MEM_EMPTY] = "Empty", |
96 | [MEM_RESERVED] = "Reserved", | |
97 | [MEM_UNKNOWN] = "Unknown", | |
98 | [MEM_FPM] = "FPM", | |
99 | [MEM_EDO] = "EDO", | |
100 | [MEM_BEDO] = "BEDO", | |
101 | [MEM_SDR] = "Unbuffered-SDR", | |
102 | [MEM_RDR] = "Registered-SDR", | |
103 | [MEM_DDR] = "Unbuffered-DDR", | |
104 | [MEM_RDDR] = "Registered-DDR", | |
1a9b85e6 DJ |
105 | [MEM_RMBS] = "RMBS", |
106 | [MEM_DDR2] = "Unbuffered-DDR2", | |
107 | [MEM_FB_DDR2] = "FullyBuffered-DDR2", | |
1d5f726c | 108 | [MEM_RDDR2] = "Registered-DDR2", |
b1cfebc9 YS |
109 | [MEM_XDR] = "XDR", |
110 | [MEM_DDR3] = "Unbuffered-DDR3", | |
7b827835 AR |
111 | [MEM_RDDR3] = "Registered-DDR3", |
112 | [MEM_DDR4] = "Unbuffered-DDR4", | |
113 | [MEM_RDDR4] = "Registered-DDR4" | |
7c9281d7 DT |
114 | }; |
115 | ||
8b7719e0 | 116 | static const char * const dev_types[] = { |
7c9281d7 DT |
117 | [DEV_UNKNOWN] = "Unknown", |
118 | [DEV_X1] = "x1", | |
119 | [DEV_X2] = "x2", | |
120 | [DEV_X4] = "x4", | |
121 | [DEV_X8] = "x8", | |
122 | [DEV_X16] = "x16", | |
123 | [DEV_X32] = "x32", | |
124 | [DEV_X64] = "x64" | |
125 | }; | |
126 | ||
8b7719e0 | 127 | static const char * const edac_caps[] = { |
7c9281d7 DT |
128 | [EDAC_UNKNOWN] = "Unknown", |
129 | [EDAC_NONE] = "None", | |
130 | [EDAC_RESERVED] = "Reserved", | |
131 | [EDAC_PARITY] = "PARITY", | |
132 | [EDAC_EC] = "EC", | |
133 | [EDAC_SECDED] = "SECDED", | |
134 | [EDAC_S2ECD2ED] = "S2ECD2ED", | |
135 | [EDAC_S4ECD4ED] = "S4ECD4ED", | |
136 | [EDAC_S8ECD8ED] = "S8ECD8ED", | |
137 | [EDAC_S16ECD16ED] = "S16ECD16ED" | |
138 | }; | |
139 | ||
19974710 | 140 | #ifdef CONFIG_EDAC_LEGACY_SYSFS |
7a623c03 MCC |
141 | /* |
142 | * EDAC sysfs CSROW data structures and methods | |
143 | */ | |
144 | ||
145 | #define to_csrow(k) container_of(k, struct csrow_info, dev) | |
146 | ||
147 | /* | |
148 | * We need it to avoid namespace conflicts between the legacy API | |
149 | * and the per-dimm/per-rank one | |
7c9281d7 | 150 | */ |
7a623c03 | 151 | #define DEVICE_ATTR_LEGACY(_name, _mode, _show, _store) \ |
fbe2d361 | 152 | static struct device_attribute dev_attr_legacy_##_name = __ATTR(_name, _mode, _show, _store) |
7a623c03 MCC |
153 | |
154 | struct dev_ch_attribute { | |
155 | struct device_attribute attr; | |
156 | int channel; | |
157 | }; | |
158 | ||
159 | #define DEVICE_CHANNEL(_name, _mode, _show, _store, _var) \ | |
f11135d8 | 160 | static struct dev_ch_attribute dev_attr_legacy_##_name = \ |
7a623c03 MCC |
161 | { __ATTR(_name, _mode, _show, _store), (_var) } |
162 | ||
163 | #define to_channel(k) (container_of(k, struct dev_ch_attribute, attr)->channel) | |
7c9281d7 DT |
164 | |
165 | /* Set of more default csrow<id> attribute show/store functions */ | |
7a623c03 MCC |
166 | static ssize_t csrow_ue_count_show(struct device *dev, |
167 | struct device_attribute *mattr, char *data) | |
7c9281d7 | 168 | { |
7a623c03 MCC |
169 | struct csrow_info *csrow = to_csrow(dev); |
170 | ||
079708b9 | 171 | return sprintf(data, "%u\n", csrow->ue_count); |
7c9281d7 DT |
172 | } |
173 | ||
7a623c03 MCC |
174 | static ssize_t csrow_ce_count_show(struct device *dev, |
175 | struct device_attribute *mattr, char *data) | |
7c9281d7 | 176 | { |
7a623c03 MCC |
177 | struct csrow_info *csrow = to_csrow(dev); |
178 | ||
079708b9 | 179 | return sprintf(data, "%u\n", csrow->ce_count); |
7c9281d7 DT |
180 | } |
181 | ||
7a623c03 MCC |
182 | static ssize_t csrow_size_show(struct device *dev, |
183 | struct device_attribute *mattr, char *data) | |
7c9281d7 | 184 | { |
7a623c03 | 185 | struct csrow_info *csrow = to_csrow(dev); |
a895bf8b MCC |
186 | int i; |
187 | u32 nr_pages = 0; | |
188 | ||
189 | for (i = 0; i < csrow->nr_channels; i++) | |
de3910eb | 190 | nr_pages += csrow->channels[i]->dimm->nr_pages; |
a895bf8b | 191 | return sprintf(data, "%u\n", PAGES_TO_MiB(nr_pages)); |
7c9281d7 DT |
192 | } |
193 | ||
7a623c03 MCC |
194 | static ssize_t csrow_mem_type_show(struct device *dev, |
195 | struct device_attribute *mattr, char *data) | |
7c9281d7 | 196 | { |
7a623c03 MCC |
197 | struct csrow_info *csrow = to_csrow(dev); |
198 | ||
de3910eb | 199 | return sprintf(data, "%s\n", mem_types[csrow->channels[0]->dimm->mtype]); |
7c9281d7 DT |
200 | } |
201 | ||
7a623c03 MCC |
202 | static ssize_t csrow_dev_type_show(struct device *dev, |
203 | struct device_attribute *mattr, char *data) | |
7c9281d7 | 204 | { |
7a623c03 MCC |
205 | struct csrow_info *csrow = to_csrow(dev); |
206 | ||
de3910eb | 207 | return sprintf(data, "%s\n", dev_types[csrow->channels[0]->dimm->dtype]); |
7c9281d7 DT |
208 | } |
209 | ||
7a623c03 MCC |
210 | static ssize_t csrow_edac_mode_show(struct device *dev, |
211 | struct device_attribute *mattr, | |
212 | char *data) | |
7c9281d7 | 213 | { |
7a623c03 MCC |
214 | struct csrow_info *csrow = to_csrow(dev); |
215 | ||
de3910eb | 216 | return sprintf(data, "%s\n", edac_caps[csrow->channels[0]->dimm->edac_mode]); |
7c9281d7 DT |
217 | } |
218 | ||
219 | /* show/store functions for DIMM Label attributes */ | |
7a623c03 MCC |
220 | static ssize_t channel_dimm_label_show(struct device *dev, |
221 | struct device_attribute *mattr, | |
222 | char *data) | |
7c9281d7 | 223 | { |
7a623c03 MCC |
224 | struct csrow_info *csrow = to_csrow(dev); |
225 | unsigned chan = to_channel(mattr); | |
de3910eb | 226 | struct rank_info *rank = csrow->channels[chan]; |
7a623c03 | 227 | |
124682c7 | 228 | /* if field has not been initialized, there is nothing to send */ |
7a623c03 | 229 | if (!rank->dimm->label[0]) |
124682c7 AJ |
230 | return 0; |
231 | ||
232 | return snprintf(data, EDAC_MC_LABEL_LEN, "%s\n", | |
7a623c03 | 233 | rank->dimm->label); |
7c9281d7 DT |
234 | } |
235 | ||
7a623c03 MCC |
236 | static ssize_t channel_dimm_label_store(struct device *dev, |
237 | struct device_attribute *mattr, | |
238 | const char *data, size_t count) | |
7c9281d7 | 239 | { |
7a623c03 MCC |
240 | struct csrow_info *csrow = to_csrow(dev); |
241 | unsigned chan = to_channel(mattr); | |
de3910eb | 242 | struct rank_info *rank = csrow->channels[chan]; |
7a623c03 | 243 | |
7c9281d7 DT |
244 | ssize_t max_size = 0; |
245 | ||
079708b9 | 246 | max_size = min((ssize_t) count, (ssize_t) EDAC_MC_LABEL_LEN - 1); |
7a623c03 MCC |
247 | strncpy(rank->dimm->label, data, max_size); |
248 | rank->dimm->label[max_size] = '\0'; | |
7c9281d7 DT |
249 | |
250 | return max_size; | |
251 | } | |
252 | ||
253 | /* show function for dynamic chX_ce_count attribute */ | |
7a623c03 MCC |
254 | static ssize_t channel_ce_count_show(struct device *dev, |
255 | struct device_attribute *mattr, char *data) | |
7c9281d7 | 256 | { |
7a623c03 MCC |
257 | struct csrow_info *csrow = to_csrow(dev); |
258 | unsigned chan = to_channel(mattr); | |
de3910eb | 259 | struct rank_info *rank = csrow->channels[chan]; |
7a623c03 MCC |
260 | |
261 | return sprintf(data, "%u\n", rank->ce_count); | |
7c9281d7 DT |
262 | } |
263 | ||
7a623c03 MCC |
264 | /* cwrow<id>/attribute files */ |
265 | DEVICE_ATTR_LEGACY(size_mb, S_IRUGO, csrow_size_show, NULL); | |
266 | DEVICE_ATTR_LEGACY(dev_type, S_IRUGO, csrow_dev_type_show, NULL); | |
267 | DEVICE_ATTR_LEGACY(mem_type, S_IRUGO, csrow_mem_type_show, NULL); | |
268 | DEVICE_ATTR_LEGACY(edac_mode, S_IRUGO, csrow_edac_mode_show, NULL); | |
269 | DEVICE_ATTR_LEGACY(ue_count, S_IRUGO, csrow_ue_count_show, NULL); | |
270 | DEVICE_ATTR_LEGACY(ce_count, S_IRUGO, csrow_ce_count_show, NULL); | |
7c9281d7 | 271 | |
7a623c03 MCC |
272 | /* default attributes of the CSROW<id> object */ |
273 | static struct attribute *csrow_attrs[] = { | |
274 | &dev_attr_legacy_dev_type.attr, | |
275 | &dev_attr_legacy_mem_type.attr, | |
276 | &dev_attr_legacy_edac_mode.attr, | |
277 | &dev_attr_legacy_size_mb.attr, | |
278 | &dev_attr_legacy_ue_count.attr, | |
279 | &dev_attr_legacy_ce_count.attr, | |
280 | NULL, | |
281 | }; | |
7c9281d7 | 282 | |
7a623c03 MCC |
283 | static struct attribute_group csrow_attr_grp = { |
284 | .attrs = csrow_attrs, | |
285 | }; | |
7c9281d7 | 286 | |
7a623c03 MCC |
287 | static const struct attribute_group *csrow_attr_groups[] = { |
288 | &csrow_attr_grp, | |
289 | NULL | |
290 | }; | |
7c9281d7 | 291 | |
de3910eb | 292 | static void csrow_attr_release(struct device *dev) |
7c9281d7 | 293 | { |
de3910eb MCC |
294 | struct csrow_info *csrow = container_of(dev, struct csrow_info, dev); |
295 | ||
956b9ba1 | 296 | edac_dbg(1, "Releasing csrow device %s\n", dev_name(dev)); |
de3910eb | 297 | kfree(csrow); |
7c9281d7 DT |
298 | } |
299 | ||
7a623c03 MCC |
300 | static struct device_type csrow_attr_type = { |
301 | .groups = csrow_attr_groups, | |
302 | .release = csrow_attr_release, | |
7c9281d7 DT |
303 | }; |
304 | ||
7a623c03 MCC |
305 | /* |
306 | * possible dynamic channel DIMM Label attribute files | |
307 | * | |
308 | */ | |
7c9281d7 | 309 | |
7a623c03 | 310 | #define EDAC_NR_CHANNELS 6 |
7c9281d7 | 311 | |
7a623c03 | 312 | DEVICE_CHANNEL(ch0_dimm_label, S_IRUGO | S_IWUSR, |
052dfb45 | 313 | channel_dimm_label_show, channel_dimm_label_store, 0); |
7a623c03 | 314 | DEVICE_CHANNEL(ch1_dimm_label, S_IRUGO | S_IWUSR, |
052dfb45 | 315 | channel_dimm_label_show, channel_dimm_label_store, 1); |
7a623c03 | 316 | DEVICE_CHANNEL(ch2_dimm_label, S_IRUGO | S_IWUSR, |
052dfb45 | 317 | channel_dimm_label_show, channel_dimm_label_store, 2); |
7a623c03 | 318 | DEVICE_CHANNEL(ch3_dimm_label, S_IRUGO | S_IWUSR, |
052dfb45 | 319 | channel_dimm_label_show, channel_dimm_label_store, 3); |
7a623c03 | 320 | DEVICE_CHANNEL(ch4_dimm_label, S_IRUGO | S_IWUSR, |
052dfb45 | 321 | channel_dimm_label_show, channel_dimm_label_store, 4); |
7a623c03 | 322 | DEVICE_CHANNEL(ch5_dimm_label, S_IRUGO | S_IWUSR, |
052dfb45 | 323 | channel_dimm_label_show, channel_dimm_label_store, 5); |
7c9281d7 DT |
324 | |
325 | /* Total possible dynamic DIMM Label attribute file table */ | |
2c1946b6 TI |
326 | static struct attribute *dynamic_csrow_dimm_attr[] = { |
327 | &dev_attr_legacy_ch0_dimm_label.attr.attr, | |
328 | &dev_attr_legacy_ch1_dimm_label.attr.attr, | |
329 | &dev_attr_legacy_ch2_dimm_label.attr.attr, | |
330 | &dev_attr_legacy_ch3_dimm_label.attr.attr, | |
331 | &dev_attr_legacy_ch4_dimm_label.attr.attr, | |
332 | &dev_attr_legacy_ch5_dimm_label.attr.attr, | |
333 | NULL | |
7c9281d7 DT |
334 | }; |
335 | ||
336 | /* possible dynamic channel ce_count attribute files */ | |
c8c64d16 | 337 | DEVICE_CHANNEL(ch0_ce_count, S_IRUGO, |
7a623c03 | 338 | channel_ce_count_show, NULL, 0); |
c8c64d16 | 339 | DEVICE_CHANNEL(ch1_ce_count, S_IRUGO, |
7a623c03 | 340 | channel_ce_count_show, NULL, 1); |
c8c64d16 | 341 | DEVICE_CHANNEL(ch2_ce_count, S_IRUGO, |
7a623c03 | 342 | channel_ce_count_show, NULL, 2); |
c8c64d16 | 343 | DEVICE_CHANNEL(ch3_ce_count, S_IRUGO, |
7a623c03 | 344 | channel_ce_count_show, NULL, 3); |
c8c64d16 | 345 | DEVICE_CHANNEL(ch4_ce_count, S_IRUGO, |
7a623c03 | 346 | channel_ce_count_show, NULL, 4); |
c8c64d16 | 347 | DEVICE_CHANNEL(ch5_ce_count, S_IRUGO, |
7a623c03 | 348 | channel_ce_count_show, NULL, 5); |
7c9281d7 DT |
349 | |
350 | /* Total possible dynamic ce_count attribute file table */ | |
2c1946b6 TI |
351 | static struct attribute *dynamic_csrow_ce_count_attr[] = { |
352 | &dev_attr_legacy_ch0_ce_count.attr.attr, | |
353 | &dev_attr_legacy_ch1_ce_count.attr.attr, | |
354 | &dev_attr_legacy_ch2_ce_count.attr.attr, | |
355 | &dev_attr_legacy_ch3_ce_count.attr.attr, | |
356 | &dev_attr_legacy_ch4_ce_count.attr.attr, | |
357 | &dev_attr_legacy_ch5_ce_count.attr.attr, | |
358 | NULL | |
359 | }; | |
360 | ||
361 | static umode_t csrow_dev_is_visible(struct kobject *kobj, | |
362 | struct attribute *attr, int idx) | |
363 | { | |
364 | struct device *dev = kobj_to_dev(kobj); | |
365 | struct csrow_info *csrow = container_of(dev, struct csrow_info, dev); | |
366 | ||
367 | if (idx >= csrow->nr_channels) | |
368 | return 0; | |
369 | /* Only expose populated DIMMs */ | |
370 | if (!csrow->channels[idx]->dimm->nr_pages) | |
371 | return 0; | |
372 | return attr->mode; | |
373 | } | |
374 | ||
375 | ||
376 | static const struct attribute_group csrow_dev_dimm_group = { | |
377 | .attrs = dynamic_csrow_dimm_attr, | |
378 | .is_visible = csrow_dev_is_visible, | |
379 | }; | |
380 | ||
381 | static const struct attribute_group csrow_dev_ce_count_group = { | |
382 | .attrs = dynamic_csrow_ce_count_attr, | |
383 | .is_visible = csrow_dev_is_visible, | |
384 | }; | |
385 | ||
386 | static const struct attribute_group *csrow_dev_groups[] = { | |
387 | &csrow_dev_dimm_group, | |
388 | &csrow_dev_ce_count_group, | |
389 | NULL | |
7c9281d7 DT |
390 | }; |
391 | ||
e39f4ea9 MCC |
392 | static inline int nr_pages_per_csrow(struct csrow_info *csrow) |
393 | { | |
394 | int chan, nr_pages = 0; | |
395 | ||
396 | for (chan = 0; chan < csrow->nr_channels; chan++) | |
de3910eb | 397 | nr_pages += csrow->channels[chan]->dimm->nr_pages; |
e39f4ea9 MCC |
398 | |
399 | return nr_pages; | |
400 | } | |
401 | ||
7a623c03 MCC |
402 | /* Create a CSROW object under specifed edac_mc_device */ |
403 | static int edac_create_csrow_object(struct mem_ctl_info *mci, | |
404 | struct csrow_info *csrow, int index) | |
7c9281d7 | 405 | { |
50043e25 | 406 | if (csrow->nr_channels > EDAC_NR_CHANNELS) |
7a623c03 | 407 | return -ENODEV; |
7c9281d7 | 408 | |
7a623c03 | 409 | csrow->dev.type = &csrow_attr_type; |
88d84ac9 | 410 | csrow->dev.bus = mci->bus; |
2c1946b6 | 411 | csrow->dev.groups = csrow_dev_groups; |
7a623c03 MCC |
412 | device_initialize(&csrow->dev); |
413 | csrow->dev.parent = &mci->dev; | |
921a6899 | 414 | csrow->mci = mci; |
7a623c03 MCC |
415 | dev_set_name(&csrow->dev, "csrow%d", index); |
416 | dev_set_drvdata(&csrow->dev, csrow); | |
7c9281d7 | 417 | |
956b9ba1 JP |
418 | edac_dbg(0, "creating (virtual) csrow node %s\n", |
419 | dev_name(&csrow->dev)); | |
7c9281d7 | 420 | |
2c1946b6 | 421 | return device_add(&csrow->dev); |
7a623c03 | 422 | } |
7c9281d7 DT |
423 | |
424 | /* Create a CSROW object under specifed edac_mc_device */ | |
7a623c03 | 425 | static int edac_create_csrow_objects(struct mem_ctl_info *mci) |
7c9281d7 | 426 | { |
2c1946b6 | 427 | int err, i; |
7a623c03 | 428 | struct csrow_info *csrow; |
7c9281d7 | 429 | |
7a623c03 | 430 | for (i = 0; i < mci->nr_csrows; i++) { |
de3910eb | 431 | csrow = mci->csrows[i]; |
e39f4ea9 MCC |
432 | if (!nr_pages_per_csrow(csrow)) |
433 | continue; | |
de3910eb | 434 | err = edac_create_csrow_object(mci, mci->csrows[i], i); |
3d958823 MCC |
435 | if (err < 0) { |
436 | edac_dbg(1, | |
437 | "failure: create csrow objects for csrow %d\n", | |
438 | i); | |
7a623c03 | 439 | goto error; |
3d958823 | 440 | } |
7a623c03 MCC |
441 | } |
442 | return 0; | |
8096cfaf | 443 | |
7a623c03 MCC |
444 | error: |
445 | for (--i; i >= 0; i--) { | |
de3910eb | 446 | csrow = mci->csrows[i]; |
e39f4ea9 MCC |
447 | if (!nr_pages_per_csrow(csrow)) |
448 | continue; | |
de3910eb | 449 | put_device(&mci->csrows[i]->dev); |
8096cfaf | 450 | } |
7c9281d7 | 451 | |
7a623c03 MCC |
452 | return err; |
453 | } | |
8096cfaf | 454 | |
7a623c03 MCC |
455 | static void edac_delete_csrow_objects(struct mem_ctl_info *mci) |
456 | { | |
2c1946b6 | 457 | int i; |
7a623c03 | 458 | struct csrow_info *csrow; |
8096cfaf | 459 | |
7a623c03 | 460 | for (i = mci->nr_csrows - 1; i >= 0; i--) { |
de3910eb | 461 | csrow = mci->csrows[i]; |
e39f4ea9 MCC |
462 | if (!nr_pages_per_csrow(csrow)) |
463 | continue; | |
44d22e24 | 464 | device_unregister(&mci->csrows[i]->dev); |
7c9281d7 | 465 | } |
7c9281d7 | 466 | } |
19974710 MCC |
467 | #endif |
468 | ||
469 | /* | |
470 | * Per-dimm (or per-rank) devices | |
471 | */ | |
472 | ||
473 | #define to_dimm(k) container_of(k, struct dimm_info, dev) | |
474 | ||
475 | /* show/store functions for DIMM Label attributes */ | |
476 | static ssize_t dimmdev_location_show(struct device *dev, | |
477 | struct device_attribute *mattr, char *data) | |
478 | { | |
479 | struct dimm_info *dimm = to_dimm(dev); | |
19974710 | 480 | |
6e84d359 | 481 | return edac_dimm_info_location(dimm, data, PAGE_SIZE); |
19974710 MCC |
482 | } |
483 | ||
484 | static ssize_t dimmdev_label_show(struct device *dev, | |
485 | struct device_attribute *mattr, char *data) | |
486 | { | |
487 | struct dimm_info *dimm = to_dimm(dev); | |
488 | ||
489 | /* if field has not been initialized, there is nothing to send */ | |
490 | if (!dimm->label[0]) | |
491 | return 0; | |
492 | ||
493 | return snprintf(data, EDAC_MC_LABEL_LEN, "%s\n", dimm->label); | |
494 | } | |
495 | ||
496 | static ssize_t dimmdev_label_store(struct device *dev, | |
497 | struct device_attribute *mattr, | |
498 | const char *data, | |
499 | size_t count) | |
500 | { | |
501 | struct dimm_info *dimm = to_dimm(dev); | |
502 | ||
503 | ssize_t max_size = 0; | |
504 | ||
505 | max_size = min((ssize_t) count, (ssize_t) EDAC_MC_LABEL_LEN - 1); | |
506 | strncpy(dimm->label, data, max_size); | |
507 | dimm->label[max_size] = '\0'; | |
508 | ||
509 | return max_size; | |
510 | } | |
511 | ||
512 | static ssize_t dimmdev_size_show(struct device *dev, | |
513 | struct device_attribute *mattr, char *data) | |
514 | { | |
515 | struct dimm_info *dimm = to_dimm(dev); | |
516 | ||
517 | return sprintf(data, "%u\n", PAGES_TO_MiB(dimm->nr_pages)); | |
518 | } | |
519 | ||
520 | static ssize_t dimmdev_mem_type_show(struct device *dev, | |
521 | struct device_attribute *mattr, char *data) | |
522 | { | |
523 | struct dimm_info *dimm = to_dimm(dev); | |
524 | ||
525 | return sprintf(data, "%s\n", mem_types[dimm->mtype]); | |
526 | } | |
527 | ||
528 | static ssize_t dimmdev_dev_type_show(struct device *dev, | |
529 | struct device_attribute *mattr, char *data) | |
530 | { | |
531 | struct dimm_info *dimm = to_dimm(dev); | |
532 | ||
533 | return sprintf(data, "%s\n", dev_types[dimm->dtype]); | |
534 | } | |
535 | ||
536 | static ssize_t dimmdev_edac_mode_show(struct device *dev, | |
537 | struct device_attribute *mattr, | |
538 | char *data) | |
539 | { | |
540 | struct dimm_info *dimm = to_dimm(dev); | |
541 | ||
542 | return sprintf(data, "%s\n", edac_caps[dimm->edac_mode]); | |
543 | } | |
544 | ||
545 | /* dimm/rank attribute files */ | |
546 | static DEVICE_ATTR(dimm_label, S_IRUGO | S_IWUSR, | |
547 | dimmdev_label_show, dimmdev_label_store); | |
548 | static DEVICE_ATTR(dimm_location, S_IRUGO, dimmdev_location_show, NULL); | |
549 | static DEVICE_ATTR(size, S_IRUGO, dimmdev_size_show, NULL); | |
550 | static DEVICE_ATTR(dimm_mem_type, S_IRUGO, dimmdev_mem_type_show, NULL); | |
551 | static DEVICE_ATTR(dimm_dev_type, S_IRUGO, dimmdev_dev_type_show, NULL); | |
552 | static DEVICE_ATTR(dimm_edac_mode, S_IRUGO, dimmdev_edac_mode_show, NULL); | |
553 | ||
554 | /* attributes of the dimm<id>/rank<id> object */ | |
555 | static struct attribute *dimm_attrs[] = { | |
556 | &dev_attr_dimm_label.attr, | |
557 | &dev_attr_dimm_location.attr, | |
558 | &dev_attr_size.attr, | |
559 | &dev_attr_dimm_mem_type.attr, | |
560 | &dev_attr_dimm_dev_type.attr, | |
561 | &dev_attr_dimm_edac_mode.attr, | |
562 | NULL, | |
563 | }; | |
564 | ||
565 | static struct attribute_group dimm_attr_grp = { | |
566 | .attrs = dimm_attrs, | |
567 | }; | |
568 | ||
569 | static const struct attribute_group *dimm_attr_groups[] = { | |
570 | &dimm_attr_grp, | |
571 | NULL | |
572 | }; | |
573 | ||
de3910eb | 574 | static void dimm_attr_release(struct device *dev) |
19974710 | 575 | { |
de3910eb MCC |
576 | struct dimm_info *dimm = container_of(dev, struct dimm_info, dev); |
577 | ||
956b9ba1 | 578 | edac_dbg(1, "Releasing dimm device %s\n", dev_name(dev)); |
de3910eb | 579 | kfree(dimm); |
19974710 MCC |
580 | } |
581 | ||
582 | static struct device_type dimm_attr_type = { | |
583 | .groups = dimm_attr_groups, | |
584 | .release = dimm_attr_release, | |
585 | }; | |
586 | ||
587 | /* Create a DIMM object under specifed memory controller device */ | |
588 | static int edac_create_dimm_object(struct mem_ctl_info *mci, | |
589 | struct dimm_info *dimm, | |
590 | int index) | |
591 | { | |
592 | int err; | |
593 | dimm->mci = mci; | |
594 | ||
595 | dimm->dev.type = &dimm_attr_type; | |
88d84ac9 | 596 | dimm->dev.bus = mci->bus; |
19974710 MCC |
597 | device_initialize(&dimm->dev); |
598 | ||
599 | dimm->dev.parent = &mci->dev; | |
9713faec | 600 | if (mci->csbased) |
19974710 MCC |
601 | dev_set_name(&dimm->dev, "rank%d", index); |
602 | else | |
603 | dev_set_name(&dimm->dev, "dimm%d", index); | |
604 | dev_set_drvdata(&dimm->dev, dimm); | |
605 | pm_runtime_forbid(&mci->dev); | |
606 | ||
607 | err = device_add(&dimm->dev); | |
608 | ||
956b9ba1 | 609 | edac_dbg(0, "creating rank/dimm device %s\n", dev_name(&dimm->dev)); |
19974710 MCC |
610 | |
611 | return err; | |
612 | } | |
7c9281d7 | 613 | |
7a623c03 MCC |
614 | /* |
615 | * Memory controller device | |
616 | */ | |
617 | ||
618 | #define to_mci(k) container_of(k, struct mem_ctl_info, dev) | |
7c9281d7 | 619 | |
7a623c03 MCC |
620 | static ssize_t mci_reset_counters_store(struct device *dev, |
621 | struct device_attribute *mattr, | |
079708b9 | 622 | const char *data, size_t count) |
7c9281d7 | 623 | { |
7a623c03 MCC |
624 | struct mem_ctl_info *mci = to_mci(dev); |
625 | int cnt, row, chan, i; | |
5926ff50 MCC |
626 | mci->ue_mc = 0; |
627 | mci->ce_mc = 0; | |
7a623c03 MCC |
628 | mci->ue_noinfo_count = 0; |
629 | mci->ce_noinfo_count = 0; | |
7c9281d7 DT |
630 | |
631 | for (row = 0; row < mci->nr_csrows; row++) { | |
de3910eb | 632 | struct csrow_info *ri = mci->csrows[row]; |
7c9281d7 DT |
633 | |
634 | ri->ue_count = 0; | |
635 | ri->ce_count = 0; | |
636 | ||
637 | for (chan = 0; chan < ri->nr_channels; chan++) | |
de3910eb | 638 | ri->channels[chan]->ce_count = 0; |
7c9281d7 DT |
639 | } |
640 | ||
7a623c03 MCC |
641 | cnt = 1; |
642 | for (i = 0; i < mci->n_layers; i++) { | |
643 | cnt *= mci->layers[i].size; | |
644 | memset(mci->ce_per_layer[i], 0, cnt * sizeof(u32)); | |
645 | memset(mci->ue_per_layer[i], 0, cnt * sizeof(u32)); | |
646 | } | |
647 | ||
7c9281d7 DT |
648 | mci->start_time = jiffies; |
649 | return count; | |
650 | } | |
651 | ||
39094443 BP |
652 | /* Memory scrubbing interface: |
653 | * | |
654 | * A MC driver can limit the scrubbing bandwidth based on the CPU type. | |
655 | * Therefore, ->set_sdram_scrub_rate should be made to return the actual | |
656 | * bandwidth that is accepted or 0 when scrubbing is to be disabled. | |
657 | * | |
658 | * Negative value still means that an error has occurred while setting | |
659 | * the scrub rate. | |
660 | */ | |
7a623c03 MCC |
661 | static ssize_t mci_sdram_scrub_rate_store(struct device *dev, |
662 | struct device_attribute *mattr, | |
eba042a8 | 663 | const char *data, size_t count) |
7c9281d7 | 664 | { |
7a623c03 | 665 | struct mem_ctl_info *mci = to_mci(dev); |
eba042a8 | 666 | unsigned long bandwidth = 0; |
39094443 | 667 | int new_bw = 0; |
7c9281d7 | 668 | |
c7f62fc8 | 669 | if (kstrtoul(data, 10, &bandwidth) < 0) |
eba042a8 | 670 | return -EINVAL; |
7c9281d7 | 671 | |
39094443 | 672 | new_bw = mci->set_sdram_scrub_rate(mci, bandwidth); |
4949603a MT |
673 | if (new_bw < 0) { |
674 | edac_printk(KERN_WARNING, EDAC_MC, | |
675 | "Error setting scrub rate to: %lu\n", bandwidth); | |
676 | return -EINVAL; | |
7c9281d7 | 677 | } |
39094443 | 678 | |
4949603a | 679 | return count; |
7c9281d7 DT |
680 | } |
681 | ||
39094443 BP |
682 | /* |
683 | * ->get_sdram_scrub_rate() return value semantics same as above. | |
684 | */ | |
7a623c03 MCC |
685 | static ssize_t mci_sdram_scrub_rate_show(struct device *dev, |
686 | struct device_attribute *mattr, | |
687 | char *data) | |
7c9281d7 | 688 | { |
7a623c03 | 689 | struct mem_ctl_info *mci = to_mci(dev); |
39094443 | 690 | int bandwidth = 0; |
eba042a8 | 691 | |
39094443 BP |
692 | bandwidth = mci->get_sdram_scrub_rate(mci); |
693 | if (bandwidth < 0) { | |
eba042a8 | 694 | edac_printk(KERN_DEBUG, EDAC_MC, "Error reading scrub rate\n"); |
39094443 | 695 | return bandwidth; |
7c9281d7 | 696 | } |
39094443 | 697 | |
39094443 | 698 | return sprintf(data, "%d\n", bandwidth); |
7c9281d7 DT |
699 | } |
700 | ||
701 | /* default attribute files for the MCI object */ | |
7a623c03 MCC |
702 | static ssize_t mci_ue_count_show(struct device *dev, |
703 | struct device_attribute *mattr, | |
704 | char *data) | |
7c9281d7 | 705 | { |
7a623c03 MCC |
706 | struct mem_ctl_info *mci = to_mci(dev); |
707 | ||
5926ff50 | 708 | return sprintf(data, "%d\n", mci->ue_mc); |
7c9281d7 DT |
709 | } |
710 | ||
7a623c03 MCC |
711 | static ssize_t mci_ce_count_show(struct device *dev, |
712 | struct device_attribute *mattr, | |
713 | char *data) | |
7c9281d7 | 714 | { |
7a623c03 MCC |
715 | struct mem_ctl_info *mci = to_mci(dev); |
716 | ||
5926ff50 | 717 | return sprintf(data, "%d\n", mci->ce_mc); |
7c9281d7 DT |
718 | } |
719 | ||
7a623c03 MCC |
720 | static ssize_t mci_ce_noinfo_show(struct device *dev, |
721 | struct device_attribute *mattr, | |
722 | char *data) | |
7c9281d7 | 723 | { |
7a623c03 MCC |
724 | struct mem_ctl_info *mci = to_mci(dev); |
725 | ||
079708b9 | 726 | return sprintf(data, "%d\n", mci->ce_noinfo_count); |
7c9281d7 DT |
727 | } |
728 | ||
7a623c03 MCC |
729 | static ssize_t mci_ue_noinfo_show(struct device *dev, |
730 | struct device_attribute *mattr, | |
731 | char *data) | |
7c9281d7 | 732 | { |
7a623c03 MCC |
733 | struct mem_ctl_info *mci = to_mci(dev); |
734 | ||
079708b9 | 735 | return sprintf(data, "%d\n", mci->ue_noinfo_count); |
7c9281d7 DT |
736 | } |
737 | ||
7a623c03 MCC |
738 | static ssize_t mci_seconds_show(struct device *dev, |
739 | struct device_attribute *mattr, | |
740 | char *data) | |
7c9281d7 | 741 | { |
7a623c03 MCC |
742 | struct mem_ctl_info *mci = to_mci(dev); |
743 | ||
079708b9 | 744 | return sprintf(data, "%ld\n", (jiffies - mci->start_time) / HZ); |
7c9281d7 DT |
745 | } |
746 | ||
7a623c03 MCC |
747 | static ssize_t mci_ctl_name_show(struct device *dev, |
748 | struct device_attribute *mattr, | |
749 | char *data) | |
7c9281d7 | 750 | { |
7a623c03 MCC |
751 | struct mem_ctl_info *mci = to_mci(dev); |
752 | ||
079708b9 | 753 | return sprintf(data, "%s\n", mci->ctl_name); |
7c9281d7 DT |
754 | } |
755 | ||
7a623c03 MCC |
756 | static ssize_t mci_size_mb_show(struct device *dev, |
757 | struct device_attribute *mattr, | |
758 | char *data) | |
7c9281d7 | 759 | { |
7a623c03 | 760 | struct mem_ctl_info *mci = to_mci(dev); |
a895bf8b | 761 | int total_pages = 0, csrow_idx, j; |
7c9281d7 | 762 | |
a895bf8b | 763 | for (csrow_idx = 0; csrow_idx < mci->nr_csrows; csrow_idx++) { |
de3910eb | 764 | struct csrow_info *csrow = mci->csrows[csrow_idx]; |
7c9281d7 | 765 | |
1eef1282 MCC |
766 | for (j = 0; j < csrow->nr_channels; j++) { |
767 | struct dimm_info *dimm = csrow->channels[j]->dimm; | |
3c062276 | 768 | |
1eef1282 | 769 | total_pages += dimm->nr_pages; |
a895bf8b | 770 | } |
7c9281d7 DT |
771 | } |
772 | ||
079708b9 | 773 | return sprintf(data, "%u\n", PAGES_TO_MiB(total_pages)); |
7c9281d7 DT |
774 | } |
775 | ||
8ad6c78a MCC |
776 | static ssize_t mci_max_location_show(struct device *dev, |
777 | struct device_attribute *mattr, | |
778 | char *data) | |
779 | { | |
780 | struct mem_ctl_info *mci = to_mci(dev); | |
781 | int i; | |
782 | char *p = data; | |
783 | ||
784 | for (i = 0; i < mci->n_layers; i++) { | |
785 | p += sprintf(p, "%s %d ", | |
786 | edac_layer_name[mci->layers[i].type], | |
787 | mci->layers[i].size - 1); | |
788 | } | |
789 | ||
790 | return p - data; | |
791 | } | |
792 | ||
452a6bf9 MCC |
793 | #ifdef CONFIG_EDAC_DEBUG |
794 | static ssize_t edac_fake_inject_write(struct file *file, | |
795 | const char __user *data, | |
796 | size_t count, loff_t *ppos) | |
797 | { | |
798 | struct device *dev = file->private_data; | |
799 | struct mem_ctl_info *mci = to_mci(dev); | |
800 | static enum hw_event_mc_err_type type; | |
38ced28b MCC |
801 | u16 errcount = mci->fake_inject_count; |
802 | ||
803 | if (!errcount) | |
804 | errcount = 1; | |
452a6bf9 MCC |
805 | |
806 | type = mci->fake_inject_ue ? HW_EVENT_ERR_UNCORRECTED | |
807 | : HW_EVENT_ERR_CORRECTED; | |
808 | ||
809 | printk(KERN_DEBUG | |
38ced28b MCC |
810 | "Generating %d %s fake error%s to %d.%d.%d to test core handling. NOTE: this won't test the driver-specific decoding logic.\n", |
811 | errcount, | |
452a6bf9 | 812 | (type == HW_EVENT_ERR_UNCORRECTED) ? "UE" : "CE", |
38ced28b | 813 | errcount > 1 ? "s" : "", |
452a6bf9 MCC |
814 | mci->fake_inject_layer[0], |
815 | mci->fake_inject_layer[1], | |
816 | mci->fake_inject_layer[2] | |
817 | ); | |
38ced28b | 818 | edac_mc_handle_error(type, mci, errcount, 0, 0, 0, |
452a6bf9 MCC |
819 | mci->fake_inject_layer[0], |
820 | mci->fake_inject_layer[1], | |
821 | mci->fake_inject_layer[2], | |
03f7eae8 | 822 | "FAKE ERROR", "for EDAC testing only"); |
452a6bf9 MCC |
823 | |
824 | return count; | |
825 | } | |
826 | ||
452a6bf9 | 827 | static const struct file_operations debug_fake_inject_fops = { |
db7312a2 | 828 | .open = simple_open, |
452a6bf9 MCC |
829 | .write = edac_fake_inject_write, |
830 | .llseek = generic_file_llseek, | |
831 | }; | |
832 | #endif | |
833 | ||
7c9281d7 | 834 | /* default Control file */ |
f11135d8 | 835 | static DEVICE_ATTR(reset_counters, S_IWUSR, NULL, mci_reset_counters_store); |
7c9281d7 DT |
836 | |
837 | /* default Attribute files */ | |
f11135d8 BP |
838 | static DEVICE_ATTR(mc_name, S_IRUGO, mci_ctl_name_show, NULL); |
839 | static DEVICE_ATTR(size_mb, S_IRUGO, mci_size_mb_show, NULL); | |
840 | static DEVICE_ATTR(seconds_since_reset, S_IRUGO, mci_seconds_show, NULL); | |
841 | static DEVICE_ATTR(ue_noinfo_count, S_IRUGO, mci_ue_noinfo_show, NULL); | |
842 | static DEVICE_ATTR(ce_noinfo_count, S_IRUGO, mci_ce_noinfo_show, NULL); | |
843 | static DEVICE_ATTR(ue_count, S_IRUGO, mci_ue_count_show, NULL); | |
844 | static DEVICE_ATTR(ce_count, S_IRUGO, mci_ce_count_show, NULL); | |
845 | static DEVICE_ATTR(max_location, S_IRUGO, mci_max_location_show, NULL); | |
7c9281d7 DT |
846 | |
847 | /* memory scrubber attribute file */ | |
2c1946b6 TI |
848 | DEVICE_ATTR(sdram_scrub_rate, 0, mci_sdram_scrub_rate_show, |
849 | mci_sdram_scrub_rate_store); /* umode set later in is_visible */ | |
7c9281d7 | 850 | |
7a623c03 MCC |
851 | static struct attribute *mci_attrs[] = { |
852 | &dev_attr_reset_counters.attr, | |
853 | &dev_attr_mc_name.attr, | |
854 | &dev_attr_size_mb.attr, | |
855 | &dev_attr_seconds_since_reset.attr, | |
856 | &dev_attr_ue_noinfo_count.attr, | |
857 | &dev_attr_ce_noinfo_count.attr, | |
858 | &dev_attr_ue_count.attr, | |
859 | &dev_attr_ce_count.attr, | |
8ad6c78a | 860 | &dev_attr_max_location.attr, |
2c1946b6 | 861 | &dev_attr_sdram_scrub_rate.attr, |
7c9281d7 DT |
862 | NULL |
863 | }; | |
864 | ||
2c1946b6 TI |
865 | static umode_t mci_attr_is_visible(struct kobject *kobj, |
866 | struct attribute *attr, int idx) | |
867 | { | |
868 | struct device *dev = kobj_to_dev(kobj); | |
869 | struct mem_ctl_info *mci = to_mci(dev); | |
870 | umode_t mode = 0; | |
871 | ||
872 | if (attr != &dev_attr_sdram_scrub_rate.attr) | |
873 | return attr->mode; | |
874 | if (mci->get_sdram_scrub_rate) | |
875 | mode |= S_IRUGO; | |
876 | if (mci->set_sdram_scrub_rate) | |
877 | mode |= S_IWUSR; | |
878 | return mode; | |
879 | } | |
880 | ||
7a623c03 MCC |
881 | static struct attribute_group mci_attr_grp = { |
882 | .attrs = mci_attrs, | |
2c1946b6 | 883 | .is_visible = mci_attr_is_visible, |
cc301b3a MCC |
884 | }; |
885 | ||
7a623c03 MCC |
886 | static const struct attribute_group *mci_attr_groups[] = { |
887 | &mci_attr_grp, | |
888 | NULL | |
cc301b3a MCC |
889 | }; |
890 | ||
de3910eb | 891 | static void mci_attr_release(struct device *dev) |
42a8e397 | 892 | { |
de3910eb MCC |
893 | struct mem_ctl_info *mci = container_of(dev, struct mem_ctl_info, dev); |
894 | ||
956b9ba1 | 895 | edac_dbg(1, "Releasing csrow device %s\n", dev_name(dev)); |
de3910eb | 896 | kfree(mci); |
42a8e397 DT |
897 | } |
898 | ||
7a623c03 MCC |
899 | static struct device_type mci_attr_type = { |
900 | .groups = mci_attr_groups, | |
901 | .release = mci_attr_release, | |
902 | }; | |
8096cfaf | 903 | |
452a6bf9 | 904 | #ifdef CONFIG_EDAC_DEBUG |
e7930ba4 RH |
905 | static struct dentry *edac_debugfs; |
906 | ||
907 | int __init edac_debugfs_init(void) | |
908 | { | |
909 | edac_debugfs = debugfs_create_dir("edac", NULL); | |
910 | if (IS_ERR(edac_debugfs)) { | |
911 | edac_debugfs = NULL; | |
912 | return -ENOMEM; | |
913 | } | |
914 | return 0; | |
915 | } | |
916 | ||
c6b97bcf | 917 | void edac_debugfs_exit(void) |
e7930ba4 RH |
918 | { |
919 | debugfs_remove(edac_debugfs); | |
920 | } | |
921 | ||
95285933 | 922 | static int edac_create_debug_nodes(struct mem_ctl_info *mci) |
452a6bf9 MCC |
923 | { |
924 | struct dentry *d, *parent; | |
925 | char name[80]; | |
926 | int i; | |
927 | ||
e7930ba4 RH |
928 | if (!edac_debugfs) |
929 | return -ENODEV; | |
930 | ||
931 | d = debugfs_create_dir(mci->dev.kobj.name, edac_debugfs); | |
452a6bf9 MCC |
932 | if (!d) |
933 | return -ENOMEM; | |
934 | parent = d; | |
935 | ||
936 | for (i = 0; i < mci->n_layers; i++) { | |
937 | sprintf(name, "fake_inject_%s", | |
938 | edac_layer_name[mci->layers[i].type]); | |
939 | d = debugfs_create_u8(name, S_IRUGO | S_IWUSR, parent, | |
940 | &mci->fake_inject_layer[i]); | |
941 | if (!d) | |
942 | goto nomem; | |
943 | } | |
944 | ||
945 | d = debugfs_create_bool("fake_inject_ue", S_IRUGO | S_IWUSR, parent, | |
946 | &mci->fake_inject_ue); | |
947 | if (!d) | |
948 | goto nomem; | |
949 | ||
38ced28b MCC |
950 | d = debugfs_create_u16("fake_inject_count", S_IRUGO | S_IWUSR, parent, |
951 | &mci->fake_inject_count); | |
952 | if (!d) | |
953 | goto nomem; | |
954 | ||
452a6bf9 MCC |
955 | d = debugfs_create_file("fake_inject", S_IWUSR, parent, |
956 | &mci->dev, | |
957 | &debug_fake_inject_fops); | |
958 | if (!d) | |
959 | goto nomem; | |
960 | ||
e7930ba4 | 961 | mci->debugfs = parent; |
452a6bf9 MCC |
962 | return 0; |
963 | nomem: | |
964 | debugfs_remove(mci->debugfs); | |
965 | return -ENOMEM; | |
966 | } | |
967 | #endif | |
968 | ||
7c9281d7 DT |
969 | /* |
970 | * Create a new Memory Controller kobject instance, | |
971 | * mc<id> under the 'mc' directory | |
972 | * | |
973 | * Return: | |
974 | * 0 Success | |
975 | * !0 Failure | |
976 | */ | |
4e8d230d TI |
977 | int edac_create_sysfs_mci_device(struct mem_ctl_info *mci, |
978 | const struct attribute_group **groups) | |
7c9281d7 | 979 | { |
7a623c03 | 980 | int i, err; |
7c9281d7 | 981 | |
de3910eb MCC |
982 | /* |
983 | * The memory controller needs its own bus, in order to avoid | |
984 | * namespace conflicts at /sys/bus/edac. | |
985 | */ | |
88d84ac9 BP |
986 | mci->bus->name = kasprintf(GFP_KERNEL, "mc%d", mci->mc_idx); |
987 | if (!mci->bus->name) | |
de3910eb | 988 | return -ENOMEM; |
88d84ac9 BP |
989 | |
990 | edac_dbg(0, "creating bus %s\n", mci->bus->name); | |
991 | ||
992 | err = bus_register(mci->bus); | |
de3910eb | 993 | if (err < 0) |
1bf1950c | 994 | goto fail_free_name; |
7c9281d7 | 995 | |
7a623c03 | 996 | /* get the /sys/devices/system/edac subsys reference */ |
7a623c03 MCC |
997 | mci->dev.type = &mci_attr_type; |
998 | device_initialize(&mci->dev); | |
7c9281d7 | 999 | |
de3910eb | 1000 | mci->dev.parent = mci_pdev; |
88d84ac9 | 1001 | mci->dev.bus = mci->bus; |
4e8d230d | 1002 | mci->dev.groups = groups; |
7a623c03 MCC |
1003 | dev_set_name(&mci->dev, "mc%d", mci->mc_idx); |
1004 | dev_set_drvdata(&mci->dev, mci); | |
1005 | pm_runtime_forbid(&mci->dev); | |
1006 | ||
956b9ba1 | 1007 | edac_dbg(0, "creating device %s\n", dev_name(&mci->dev)); |
7a623c03 MCC |
1008 | err = device_add(&mci->dev); |
1009 | if (err < 0) { | |
3d958823 | 1010 | edac_dbg(1, "failure: create device %s\n", dev_name(&mci->dev)); |
1bf1950c | 1011 | goto fail_unregister_bus; |
42a8e397 DT |
1012 | } |
1013 | ||
7a623c03 MCC |
1014 | /* |
1015 | * Create the dimm/rank devices | |
7c9281d7 | 1016 | */ |
7a623c03 | 1017 | for (i = 0; i < mci->tot_dimms; i++) { |
de3910eb | 1018 | struct dimm_info *dimm = mci->dimms[i]; |
7a623c03 | 1019 | /* Only expose populated DIMMs */ |
1bf1950c | 1020 | if (!dimm->nr_pages) |
7a623c03 | 1021 | continue; |
1bf1950c | 1022 | |
7a623c03 | 1023 | #ifdef CONFIG_EDAC_DEBUG |
956b9ba1 | 1024 | edac_dbg(1, "creating dimm%d, located at ", i); |
7a623c03 MCC |
1025 | if (edac_debug_level >= 1) { |
1026 | int lay; | |
1027 | for (lay = 0; lay < mci->n_layers; lay++) | |
1028 | printk(KERN_CONT "%s %d ", | |
1029 | edac_layer_name[mci->layers[lay].type], | |
1030 | dimm->location[lay]); | |
1031 | printk(KERN_CONT "\n"); | |
7c9281d7 | 1032 | } |
7a623c03 | 1033 | #endif |
19974710 MCC |
1034 | err = edac_create_dimm_object(mci, dimm, i); |
1035 | if (err) { | |
956b9ba1 | 1036 | edac_dbg(1, "failure: create dimm %d obj\n", i); |
1bf1950c | 1037 | goto fail_unregister_dimm; |
19974710 | 1038 | } |
7c9281d7 DT |
1039 | } |
1040 | ||
19974710 | 1041 | #ifdef CONFIG_EDAC_LEGACY_SYSFS |
7a623c03 MCC |
1042 | err = edac_create_csrow_objects(mci); |
1043 | if (err < 0) | |
1bf1950c | 1044 | goto fail_unregister_dimm; |
19974710 | 1045 | #endif |
7a623c03 | 1046 | |
452a6bf9 MCC |
1047 | #ifdef CONFIG_EDAC_DEBUG |
1048 | edac_create_debug_nodes(mci); | |
1049 | #endif | |
7c9281d7 DT |
1050 | return 0; |
1051 | ||
1bf1950c | 1052 | fail_unregister_dimm: |
079708b9 | 1053 | for (i--; i >= 0; i--) { |
de3910eb | 1054 | struct dimm_info *dimm = mci->dimms[i]; |
1bf1950c | 1055 | if (!dimm->nr_pages) |
7a623c03 | 1056 | continue; |
1bf1950c | 1057 | |
44d22e24 | 1058 | device_unregister(&dimm->dev); |
7c9281d7 | 1059 | } |
44d22e24 | 1060 | device_unregister(&mci->dev); |
1bf1950c | 1061 | fail_unregister_bus: |
88d84ac9 | 1062 | bus_unregister(mci->bus); |
1bf1950c | 1063 | fail_free_name: |
88d84ac9 | 1064 | kfree(mci->bus->name); |
7c9281d7 DT |
1065 | return err; |
1066 | } | |
1067 | ||
1068 | /* | |
1069 | * remove a Memory Controller instance | |
1070 | */ | |
1071 | void edac_remove_sysfs_mci_device(struct mem_ctl_info *mci) | |
1072 | { | |
7a623c03 | 1073 | int i; |
7c9281d7 | 1074 | |
956b9ba1 | 1075 | edac_dbg(0, "\n"); |
7c9281d7 | 1076 | |
452a6bf9 MCC |
1077 | #ifdef CONFIG_EDAC_DEBUG |
1078 | debugfs_remove(mci->debugfs); | |
1079 | #endif | |
19974710 | 1080 | #ifdef CONFIG_EDAC_LEGACY_SYSFS |
7a623c03 | 1081 | edac_delete_csrow_objects(mci); |
19974710 | 1082 | #endif |
7c9281d7 | 1083 | |
7a623c03 | 1084 | for (i = 0; i < mci->tot_dimms; i++) { |
de3910eb | 1085 | struct dimm_info *dimm = mci->dimms[i]; |
7a623c03 MCC |
1086 | if (dimm->nr_pages == 0) |
1087 | continue; | |
956b9ba1 | 1088 | edac_dbg(0, "removing device %s\n", dev_name(&dimm->dev)); |
44d22e24 | 1089 | device_unregister(&dimm->dev); |
6fe1108f | 1090 | } |
7c9281d7 | 1091 | } |
8096cfaf | 1092 | |
7a623c03 MCC |
1093 | void edac_unregister_sysfs(struct mem_ctl_info *mci) |
1094 | { | |
956b9ba1 | 1095 | edac_dbg(1, "Unregistering device %s\n", dev_name(&mci->dev)); |
44d22e24 | 1096 | device_unregister(&mci->dev); |
88d84ac9 BP |
1097 | bus_unregister(mci->bus); |
1098 | kfree(mci->bus->name); | |
7a623c03 | 1099 | } |
8096cfaf | 1100 | |
de3910eb | 1101 | static void mc_attr_release(struct device *dev) |
7a623c03 | 1102 | { |
de3910eb MCC |
1103 | /* |
1104 | * There's no container structure here, as this is just the mci | |
1105 | * parent device, used to create the /sys/devices/mc sysfs node. | |
1106 | * So, there are no attributes on it. | |
1107 | */ | |
956b9ba1 | 1108 | edac_dbg(1, "Releasing device %s\n", dev_name(dev)); |
de3910eb | 1109 | kfree(dev); |
7a623c03 | 1110 | } |
8096cfaf | 1111 | |
7a623c03 MCC |
1112 | static struct device_type mc_attr_type = { |
1113 | .release = mc_attr_release, | |
1114 | }; | |
8096cfaf | 1115 | /* |
7a623c03 | 1116 | * Init/exit code for the module. Basically, creates/removes /sys/class/rc |
8096cfaf | 1117 | */ |
7a623c03 | 1118 | int __init edac_mc_sysfs_init(void) |
8096cfaf | 1119 | { |
fe5ff8b8 | 1120 | struct bus_type *edac_subsys; |
7a623c03 | 1121 | int err; |
8096cfaf | 1122 | |
fe5ff8b8 KS |
1123 | /* get the /sys/devices/system/edac subsys reference */ |
1124 | edac_subsys = edac_get_sysfs_subsys(); | |
1125 | if (edac_subsys == NULL) { | |
956b9ba1 | 1126 | edac_dbg(1, "no edac_subsys\n"); |
2d56b109 DK |
1127 | err = -EINVAL; |
1128 | goto out; | |
8096cfaf DT |
1129 | } |
1130 | ||
de3910eb | 1131 | mci_pdev = kzalloc(sizeof(*mci_pdev), GFP_KERNEL); |
2d56b109 DK |
1132 | if (!mci_pdev) { |
1133 | err = -ENOMEM; | |
1134 | goto out_put_sysfs; | |
1135 | } | |
de3910eb MCC |
1136 | |
1137 | mci_pdev->bus = edac_subsys; | |
1138 | mci_pdev->type = &mc_attr_type; | |
1139 | device_initialize(mci_pdev); | |
1140 | dev_set_name(mci_pdev, "mc"); | |
8096cfaf | 1141 | |
de3910eb | 1142 | err = device_add(mci_pdev); |
7a623c03 | 1143 | if (err < 0) |
2d56b109 | 1144 | goto out_dev_free; |
8096cfaf | 1145 | |
956b9ba1 | 1146 | edac_dbg(0, "device %s created\n", dev_name(mci_pdev)); |
de3910eb | 1147 | |
8096cfaf | 1148 | return 0; |
2d56b109 DK |
1149 | |
1150 | out_dev_free: | |
1151 | kfree(mci_pdev); | |
1152 | out_put_sysfs: | |
1153 | edac_put_sysfs_subsys(); | |
1154 | out: | |
1155 | return err; | |
8096cfaf DT |
1156 | } |
1157 | ||
c6b97bcf | 1158 | void edac_mc_sysfs_exit(void) |
8096cfaf | 1159 | { |
44d22e24 | 1160 | device_unregister(mci_pdev); |
fe5ff8b8 | 1161 | edac_put_sysfs_subsys(); |
8096cfaf | 1162 | } |