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535c6a53 JU |
1 | /* |
2 | * Intel 3000/3010 Memory Controller kernel module | |
3 | * Copyright (C) 2007 Akamai Technologies, Inc. | |
4 | * Shamelessly copied from: | |
5 | * Intel D82875P Memory Controller kernel module | |
6 | * (C) 2003 Linux Networx (http://lnxi.com) | |
7 | * | |
8 | * This file may be distributed under the terms of the | |
9 | * GNU General Public License. | |
10 | */ | |
11 | ||
12 | #include <linux/module.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/pci.h> | |
15 | #include <linux/pci_ids.h> | |
16 | #include <linux/slab.h> | |
17 | #include "edac_core.h" | |
18 | ||
19 | #define I3000_REVISION "1.1" | |
20 | ||
21 | #define EDAC_MOD_STR "i3000_edac" | |
22 | ||
23 | #define I3000_RANKS 8 | |
24 | #define I3000_RANKS_PER_CHANNEL 4 | |
25 | #define I3000_CHANNELS 2 | |
26 | ||
27 | /* Intel 3000 register addresses - device 0 function 0 - DRAM Controller */ | |
28 | ||
29 | #define I3000_MCHBAR 0x44 /* MCH Memory Mapped Register BAR */ | |
30 | #define I3000_MCHBAR_MASK 0xffffc000 | |
31 | #define I3000_MMR_WINDOW_SIZE 16384 | |
32 | ||
33 | #define I3000_EDEAP 0x70 /* Extended DRAM Error Address Pointer (8b) | |
34 | * | |
35 | * 7:1 reserved | |
36 | * 0 bit 32 of address | |
37 | */ | |
38 | #define I3000_DEAP 0x58 /* DRAM Error Address Pointer (32b) | |
39 | * | |
40 | * 31:7 address | |
41 | * 6:1 reserved | |
42 | * 0 Error channel 0/1 | |
43 | */ | |
44 | #define I3000_DEAP_GRAIN (1 << 7) | |
45 | #define I3000_DEAP_PFN(edeap, deap) ((((edeap) & 1) << (32 - PAGE_SHIFT)) | \ | |
46 | ((deap) >> PAGE_SHIFT)) | |
47 | #define I3000_DEAP_OFFSET(deap) ((deap) & ~(I3000_DEAP_GRAIN-1) & ~PAGE_MASK) | |
48 | #define I3000_DEAP_CHANNEL(deap) ((deap) & 1) | |
49 | ||
50 | #define I3000_DERRSYN 0x5c /* DRAM Error Syndrome (8b) | |
51 | * | |
52 | * 7:0 DRAM ECC Syndrome | |
53 | */ | |
54 | ||
55 | #define I3000_ERRSTS 0xc8 /* Error Status Register (16b) | |
56 | * | |
57 | * 15:12 reserved | |
58 | * 11 MCH Thermal Sensor Event for SMI/SCI/SERR | |
59 | * 10 reserved | |
60 | * 9 LOCK to non-DRAM Memory Flag (LCKF) | |
61 | * 8 Received Refresh Timeout Flag (RRTOF) | |
62 | * 7:2 reserved | |
63 | * 1 Multiple-bit DRAM ECC Error Flag (DMERR) | |
64 | * 0 Single-bit DRAM ECC Error Flag (DSERR) | |
65 | */ | |
66 | #define I3000_ERRSTS_BITS 0x0b03 /* bits which indicate errors */ | |
67 | #define I3000_ERRSTS_UE 0x0002 | |
68 | #define I3000_ERRSTS_CE 0x0001 | |
69 | ||
70 | #define I3000_ERRCMD 0xca /* Error Command (16b) | |
71 | * | |
72 | * 15:12 reserved | |
73 | * 11 SERR on MCH Thermal Sensor Event (TSESERR) | |
74 | * 10 reserved | |
75 | * 9 SERR on LOCK to non-DRAM Memory (LCKERR) | |
76 | * 8 SERR on DRAM Refresh Timeout (DRTOERR) | |
77 | * 7:2 reserved | |
78 | * 1 SERR Multiple-Bit DRAM ECC Error (DMERR) | |
79 | * 0 SERR on Single-Bit ECC Error (DSERR) | |
80 | */ | |
81 | ||
82 | /* Intel MMIO register space - device 0 function 0 - MMR space */ | |
83 | ||
84 | #define I3000_DRB_SHIFT 25 /* 32MiB grain */ | |
85 | ||
86 | #define I3000_C0DRB 0x100 /* Channel 0 DRAM Rank Boundary (8b x 4) | |
87 | * | |
88 | * 7:0 Channel 0 DRAM Rank Boundary Address | |
89 | */ | |
90 | #define I3000_C1DRB 0x180 /* Channel 1 DRAM Rank Boundary (8b x 4) | |
91 | * | |
92 | * 7:0 Channel 1 DRAM Rank Boundary Address | |
93 | */ | |
94 | ||
95 | #define I3000_C0DRA 0x108 /* Channel 0 DRAM Rank Attribute (8b x 2) | |
96 | * | |
97 | * 7 reserved | |
98 | * 6:4 DRAM odd Rank Attribute | |
99 | * 3 reserved | |
100 | * 2:0 DRAM even Rank Attribute | |
101 | * | |
102 | * Each attribute defines the page | |
103 | * size of the corresponding rank: | |
104 | * 000: unpopulated | |
105 | * 001: reserved | |
106 | * 010: 4 KB | |
107 | * 011: 8 KB | |
108 | * 100: 16 KB | |
109 | * Others: reserved | |
110 | */ | |
111 | #define I3000_C1DRA 0x188 /* Channel 1 DRAM Rank Attribute (8b x 2) */ | |
112 | #define ODD_RANK_ATTRIB(dra) (((dra) & 0x70) >> 4) | |
113 | #define EVEN_RANK_ATTRIB(dra) ((dra) & 0x07) | |
114 | ||
115 | #define I3000_C0DRC0 0x120 /* DRAM Controller Mode 0 (32b) | |
116 | * | |
117 | * 31:30 reserved | |
118 | * 29 Initialization Complete (IC) | |
119 | * 28:11 reserved | |
120 | * 10:8 Refresh Mode Select (RMS) | |
121 | * 7 reserved | |
122 | * 6:4 Mode Select (SMS) | |
123 | * 3:2 reserved | |
124 | * 1:0 DRAM Type (DT) | |
125 | */ | |
126 | ||
127 | #define I3000_C0DRC1 0x124 /* DRAM Controller Mode 1 (32b) | |
128 | * | |
129 | * 31 Enhanced Addressing Enable (ENHADE) | |
130 | * 30:0 reserved | |
131 | */ | |
132 | ||
535c6a53 JU |
133 | enum i3000p_chips { |
134 | I3000 = 0, | |
135 | }; | |
136 | ||
137 | struct i3000_dev_info { | |
138 | const char *ctl_name; | |
139 | }; | |
140 | ||
141 | struct i3000_error_info { | |
142 | u16 errsts; | |
143 | u8 derrsyn; | |
144 | u8 edeap; | |
145 | u32 deap; | |
146 | u16 errsts2; | |
147 | }; | |
148 | ||
149 | static const struct i3000_dev_info i3000_devs[] = { | |
150 | [I3000] = { | |
36b8289e | 151 | .ctl_name = "i3000"}, |
535c6a53 JU |
152 | }; |
153 | ||
154 | static struct pci_dev *mci_pdev = NULL; | |
155 | static int i3000_registered = 1; | |
156 | ||
157 | static void i3000_get_error_info(struct mem_ctl_info *mci, | |
36b8289e | 158 | struct i3000_error_info *info) |
535c6a53 JU |
159 | { |
160 | struct pci_dev *pdev; | |
161 | ||
162 | pdev = to_pci_dev(mci->dev); | |
163 | ||
164 | /* | |
165 | * This is a mess because there is no atomic way to read all the | |
166 | * registers at once and the registers can transition from CE being | |
167 | * overwritten by UE. | |
168 | */ | |
169 | pci_read_config_word(pdev, I3000_ERRSTS, &info->errsts); | |
170 | if (!(info->errsts & I3000_ERRSTS_BITS)) | |
171 | return; | |
172 | pci_read_config_byte(pdev, I3000_EDEAP, &info->edeap); | |
173 | pci_read_config_dword(pdev, I3000_DEAP, &info->deap); | |
174 | pci_read_config_byte(pdev, I3000_DERRSYN, &info->derrsyn); | |
175 | pci_read_config_word(pdev, I3000_ERRSTS, &info->errsts2); | |
176 | ||
177 | /* | |
178 | * If the error is the same for both reads then the first set | |
179 | * of reads is valid. If there is a change then there is a CE | |
180 | * with no info and the second set of reads is valid and | |
181 | * should be UE info. | |
182 | */ | |
183 | if ((info->errsts ^ info->errsts2) & I3000_ERRSTS_BITS) { | |
36b8289e DJ |
184 | pci_read_config_byte(pdev, I3000_EDEAP, &info->edeap); |
185 | pci_read_config_dword(pdev, I3000_DEAP, &info->deap); | |
186 | pci_read_config_byte(pdev, I3000_DERRSYN, &info->derrsyn); | |
535c6a53 JU |
187 | } |
188 | ||
189 | /* Clear any error bits. | |
190 | * (Yes, we really clear bits by writing 1 to them.) | |
191 | */ | |
36b8289e DJ |
192 | pci_write_bits16(pdev, I3000_ERRSTS, I3000_ERRSTS_BITS, |
193 | I3000_ERRSTS_BITS); | |
535c6a53 JU |
194 | } |
195 | ||
196 | static int i3000_process_error_info(struct mem_ctl_info *mci, | |
36b8289e DJ |
197 | struct i3000_error_info *info, |
198 | int handle_errors) | |
535c6a53 JU |
199 | { |
200 | int row, multi_chan; | |
201 | int pfn, offset, channel; | |
202 | ||
203 | multi_chan = mci->csrows[0].nr_channels - 1; | |
204 | ||
205 | if (!(info->errsts & I3000_ERRSTS_BITS)) | |
206 | return 0; | |
207 | ||
208 | if (!handle_errors) | |
209 | return 1; | |
210 | ||
211 | if ((info->errsts ^ info->errsts2) & I3000_ERRSTS_BITS) { | |
212 | edac_mc_handle_ce_no_info(mci, "UE overwrote CE"); | |
213 | info->errsts = info->errsts2; | |
214 | } | |
215 | ||
216 | pfn = I3000_DEAP_PFN(info->edeap, info->deap); | |
217 | offset = I3000_DEAP_OFFSET(info->deap); | |
218 | channel = I3000_DEAP_CHANNEL(info->deap); | |
219 | ||
220 | row = edac_mc_find_csrow_by_page(mci, pfn); | |
221 | ||
222 | if (info->errsts & I3000_ERRSTS_UE) | |
223 | edac_mc_handle_ue(mci, pfn, offset, row, "i3000 UE"); | |
224 | else | |
225 | edac_mc_handle_ce(mci, pfn, offset, info->derrsyn, row, | |
36b8289e | 226 | multi_chan ? channel : 0, "i3000 CE"); |
535c6a53 JU |
227 | |
228 | return 1; | |
229 | } | |
230 | ||
231 | static void i3000_check(struct mem_ctl_info *mci) | |
232 | { | |
233 | struct i3000_error_info info; | |
234 | ||
235 | debugf1("MC%d: %s()\n", mci->mc_idx, __func__); | |
236 | i3000_get_error_info(mci, &info); | |
237 | i3000_process_error_info(mci, &info, 1); | |
238 | } | |
239 | ||
240 | static int i3000_is_interleaved(const unsigned char *c0dra, | |
241 | const unsigned char *c1dra, | |
242 | const unsigned char *c0drb, | |
243 | const unsigned char *c1drb) | |
244 | { | |
245 | int i; | |
246 | ||
247 | /* If the channels aren't populated identically then | |
248 | * we're not interleaved. | |
249 | */ | |
250 | for (i = 0; i < I3000_RANKS_PER_CHANNEL / 2; i++) | |
251 | if (ODD_RANK_ATTRIB(c0dra[i]) != ODD_RANK_ATTRIB(c1dra[i]) || | |
252 | EVEN_RANK_ATTRIB(c0dra[i]) != EVEN_RANK_ATTRIB(c1dra[i])) | |
253 | return 0; | |
254 | ||
255 | /* If the rank boundaries for the two channels are different | |
256 | * then we're not interleaved. | |
257 | */ | |
258 | for (i = 0; i < I3000_RANKS_PER_CHANNEL; i++) | |
259 | if (c0drb[i] != c1drb[i]) | |
260 | return 0; | |
261 | ||
262 | return 1; | |
263 | } | |
264 | ||
265 | static int i3000_probe1(struct pci_dev *pdev, int dev_idx) | |
266 | { | |
267 | int rc; | |
268 | int i; | |
269 | struct mem_ctl_info *mci = NULL; | |
270 | unsigned long last_cumul_size; | |
271 | int interleaved, nr_channels; | |
272 | unsigned char dra[I3000_RANKS / 2], drb[I3000_RANKS]; | |
273 | unsigned char *c0dra = dra, *c1dra = &dra[I3000_RANKS_PER_CHANNEL / 2]; | |
274 | unsigned char *c0drb = drb, *c1drb = &drb[I3000_RANKS_PER_CHANNEL]; | |
275 | unsigned long mchbar; | |
276 | void *window; | |
277 | ||
278 | debugf0("MC: %s()\n", __func__); | |
279 | ||
36b8289e | 280 | pci_read_config_dword(pdev, I3000_MCHBAR, (u32 *) & mchbar); |
535c6a53 JU |
281 | mchbar &= I3000_MCHBAR_MASK; |
282 | window = ioremap_nocache(mchbar, I3000_MMR_WINDOW_SIZE); | |
283 | if (!window) { | |
36b8289e DJ |
284 | printk(KERN_ERR "i3000: cannot map mmio space at 0x%lx\n", |
285 | mchbar); | |
535c6a53 JU |
286 | return -ENODEV; |
287 | } | |
288 | ||
36b8289e DJ |
289 | c0dra[0] = readb(window + I3000_C0DRA + 0); /* ranks 0,1 */ |
290 | c0dra[1] = readb(window + I3000_C0DRA + 1); /* ranks 2,3 */ | |
291 | c1dra[0] = readb(window + I3000_C1DRA + 0); /* ranks 0,1 */ | |
292 | c1dra[1] = readb(window + I3000_C1DRA + 1); /* ranks 2,3 */ | |
535c6a53 JU |
293 | |
294 | for (i = 0; i < I3000_RANKS_PER_CHANNEL; i++) { | |
295 | c0drb[i] = readb(window + I3000_C0DRB + i); | |
296 | c1drb[i] = readb(window + I3000_C1DRB + i); | |
297 | } | |
298 | ||
299 | iounmap(window); | |
300 | ||
301 | /* Figure out how many channels we have. | |
302 | * | |
303 | * If we have what the datasheet calls "asymmetric channels" | |
304 | * (essentially the same as what was called "virtual single | |
305 | * channel mode" in the i82875) then it's a single channel as | |
306 | * far as EDAC is concerned. | |
307 | */ | |
308 | interleaved = i3000_is_interleaved(c0dra, c1dra, c0drb, c1drb); | |
309 | nr_channels = interleaved ? 2 : 1; | |
310 | mci = edac_mc_alloc(0, I3000_RANKS / nr_channels, nr_channels); | |
311 | if (!mci) | |
312 | return -ENOMEM; | |
313 | ||
314 | debugf3("MC: %s(): init mci\n", __func__); | |
315 | ||
316 | mci->dev = &pdev->dev; | |
317 | mci->mtype_cap = MEM_FLAG_DDR2; | |
318 | ||
319 | mci->edac_ctl_cap = EDAC_FLAG_SECDED; | |
320 | mci->edac_cap = EDAC_FLAG_SECDED; | |
321 | ||
322 | mci->mod_name = EDAC_MOD_STR; | |
323 | mci->mod_ver = I3000_REVISION; | |
324 | mci->ctl_name = i3000_devs[dev_idx].ctl_name; | |
325 | mci->dev_name = pci_name(pdev); | |
326 | mci->edac_check = i3000_check; | |
327 | mci->ctl_page_to_phys = NULL; | |
328 | ||
329 | /* | |
330 | * The dram rank boundary (DRB) reg values are boundary addresses | |
331 | * for each DRAM rank with a granularity of 32MB. DRB regs are | |
332 | * cumulative; the last one will contain the total memory | |
333 | * contained in all ranks. | |
334 | * | |
335 | * If we're in interleaved mode then we're only walking through | |
336 | * the ranks of controller 0, so we double all the values we see. | |
337 | */ | |
338 | for (last_cumul_size = i = 0; i < mci->nr_csrows; i++) { | |
339 | u8 value; | |
340 | u32 cumul_size; | |
341 | struct csrow_info *csrow = &mci->csrows[i]; | |
342 | ||
343 | value = drb[i]; | |
344 | cumul_size = value << (I3000_DRB_SHIFT - PAGE_SHIFT); | |
345 | if (interleaved) | |
346 | cumul_size <<= 1; | |
347 | debugf3("MC: %s(): (%d) cumul_size 0x%x\n", | |
348 | __func__, i, cumul_size); | |
349 | if (cumul_size == last_cumul_size) { | |
350 | csrow->mtype = MEM_EMPTY; | |
351 | continue; | |
352 | } | |
353 | ||
354 | csrow->first_page = last_cumul_size; | |
355 | csrow->last_page = cumul_size - 1; | |
356 | csrow->nr_pages = cumul_size - last_cumul_size; | |
357 | last_cumul_size = cumul_size; | |
358 | csrow->grain = I3000_DEAP_GRAIN; | |
359 | csrow->mtype = MEM_DDR2; | |
360 | csrow->dtype = DEV_UNKNOWN; | |
361 | csrow->edac_mode = EDAC_UNKNOWN; | |
362 | } | |
363 | ||
364 | /* Clear any error bits. | |
365 | * (Yes, we really clear bits by writing 1 to them.) | |
366 | */ | |
36b8289e DJ |
367 | pci_write_bits16(pdev, I3000_ERRSTS, I3000_ERRSTS_BITS, |
368 | I3000_ERRSTS_BITS); | |
535c6a53 JU |
369 | |
370 | rc = -ENODEV; | |
371 | if (edac_mc_add_mc(mci, 0)) { | |
372 | debugf3("MC: %s(): failed edac_mc_add_mc()\n", __func__); | |
373 | goto fail; | |
374 | } | |
375 | ||
376 | /* get this far and it's successful */ | |
377 | debugf3("MC: %s(): success\n", __func__); | |
378 | return 0; | |
379 | ||
380 | fail: | |
381 | if (mci) | |
382 | edac_mc_free(mci); | |
383 | ||
384 | return rc; | |
385 | } | |
386 | ||
387 | /* returns count (>= 0), or negative on error */ | |
388 | static int __devinit i3000_init_one(struct pci_dev *pdev, | |
36b8289e | 389 | const struct pci_device_id *ent) |
535c6a53 JU |
390 | { |
391 | int rc; | |
392 | ||
393 | debugf0("MC: %s()\n", __func__); | |
394 | ||
395 | if (pci_enable_device(pdev) < 0) | |
396 | return -EIO; | |
397 | ||
398 | rc = i3000_probe1(pdev, ent->driver_data); | |
399 | if (mci_pdev == NULL) | |
400 | mci_pdev = pci_dev_get(pdev); | |
401 | ||
402 | return rc; | |
403 | } | |
404 | ||
405 | static void __devexit i3000_remove_one(struct pci_dev *pdev) | |
406 | { | |
407 | struct mem_ctl_info *mci; | |
408 | ||
409 | debugf0("%s()\n", __func__); | |
410 | ||
411 | if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL) | |
412 | return; | |
413 | ||
414 | edac_mc_free(mci); | |
415 | } | |
416 | ||
417 | static const struct pci_device_id i3000_pci_tbl[] __devinitdata = { | |
418 | { | |
36b8289e DJ |
419 | PCI_VEND_DEV(INTEL, 3000_HB), PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
420 | I3000}, | |
535c6a53 | 421 | { |
36b8289e DJ |
422 | 0, |
423 | } /* 0 terminated list. */ | |
535c6a53 JU |
424 | }; |
425 | ||
426 | MODULE_DEVICE_TABLE(pci, i3000_pci_tbl); | |
427 | ||
428 | static struct pci_driver i3000_driver = { | |
429 | .name = EDAC_MOD_STR, | |
430 | .probe = i3000_init_one, | |
431 | .remove = __devexit_p(i3000_remove_one), | |
432 | .id_table = i3000_pci_tbl, | |
433 | }; | |
434 | ||
435 | static int __init i3000_init(void) | |
436 | { | |
437 | int pci_rc; | |
438 | ||
439 | debugf3("MC: %s()\n", __func__); | |
440 | pci_rc = pci_register_driver(&i3000_driver); | |
441 | if (pci_rc < 0) | |
442 | goto fail0; | |
443 | ||
444 | if (mci_pdev == NULL) { | |
445 | i3000_registered = 0; | |
446 | mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL, | |
447 | PCI_DEVICE_ID_INTEL_3000_HB, NULL); | |
448 | if (!mci_pdev) { | |
449 | debugf0("i3000 pci_get_device fail\n"); | |
450 | pci_rc = -ENODEV; | |
451 | goto fail1; | |
452 | } | |
453 | ||
454 | pci_rc = i3000_init_one(mci_pdev, i3000_pci_tbl); | |
455 | if (pci_rc < 0) { | |
456 | debugf0("i3000 init fail\n"); | |
457 | pci_rc = -ENODEV; | |
458 | goto fail1; | |
459 | } | |
460 | } | |
461 | ||
462 | return 0; | |
463 | ||
36b8289e | 464 | fail1: |
535c6a53 JU |
465 | pci_unregister_driver(&i3000_driver); |
466 | ||
36b8289e | 467 | fail0: |
535c6a53 JU |
468 | if (mci_pdev) |
469 | pci_dev_put(mci_pdev); | |
470 | ||
471 | return pci_rc; | |
472 | } | |
473 | ||
474 | static void __exit i3000_exit(void) | |
475 | { | |
476 | debugf3("MC: %s()\n", __func__); | |
477 | ||
478 | pci_unregister_driver(&i3000_driver); | |
479 | if (!i3000_registered) { | |
480 | i3000_remove_one(mci_pdev); | |
481 | pci_dev_put(mci_pdev); | |
482 | } | |
483 | } | |
484 | ||
485 | module_init(i3000_init); | |
486 | module_exit(i3000_exit); | |
487 | ||
488 | MODULE_LICENSE("GPL"); | |
489 | MODULE_AUTHOR("Akamai Technologies Arthur Ulfeldt/Jason Uhlenkott"); | |
490 | MODULE_DESCRIPTION("MC support for Intel 3000 memory hub controllers"); |