[deliverable/linux.git] / drivers / edac / i3200_edac.c

/*
 * Intel 3200/3210 Memory Controller kernel module
 * Copyright (C) 2008-2009 Akamai Technologies, Inc.
 * Portions by Hitoshi Mitake <h.mitake@gmail.com>.
 *
 * This file may be distributed under the terms of the
 * GNU General Public License.
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/edac.h>
#include <linux/io.h>
#include "edac_core.h"

#include <asm-generic/io-64-nonatomic-lo-hi.h>

#define I3200_REVISION        "1.1"

#define EDAC_MOD_STR        "i3200_edac"

#define PCI_DEVICE_ID_INTEL_3200_HB    0x29f0

#define I3200_RANKS		8
#define I3200_RANKS_PER_CHANNEL	4
#define I3200_CHANNELS		2

/* Intel 3200 register addresses - device 0 function 0 - DRAM Controller */

#define I3200_MCHBAR_LOW	0x48	/* MCH Memory Mapped Register BAR */
#define I3200_MCHBAR_HIGH	0x4c
#define I3200_MCHBAR_MASK	0xfffffc000ULL	/* bits 35:14 */
#define I3200_MMR_WINDOW_SIZE	16384

#define I3200_TOM		0xa0	/* Top of Memory (16b)
		 *
		 * 15:10 reserved
		 *  9:0  total populated physical memory
		 */
#define I3200_TOM_MASK		0x3ff	/* bits 9:0 */
#define I3200_TOM_SHIFT		26	/* 64MiB grain */

#define I3200_ERRSTS		0xc8	/* Error Status Register (16b)
		 *
		 * 15    reserved
		 * 14    Isochronous TBWRR Run Behind FIFO Full
		 *       (ITCV)
		 * 13    Isochronous TBWRR Run Behind FIFO Put
		 *       (ITSTV)
		 * 12    reserved
		 * 11    MCH Thermal Sensor Event
		 *       for SMI/SCI/SERR (GTSE)
		 * 10    reserved
		 *  9    LOCK to non-DRAM Memory Flag (LCKF)
		 *  8    reserved
		 *  7    DRAM Throttle Flag (DTF)
		 *  6:2  reserved
		 *  1    Multi-bit DRAM ECC Error Flag (DMERR)
		 *  0    Single-bit DRAM ECC Error Flag (DSERR)
		 */
#define I3200_ERRSTS_UE		0x0002
#define I3200_ERRSTS_CE		0x0001
#define I3200_ERRSTS_BITS	(I3200_ERRSTS_UE | I3200_ERRSTS_CE)


/* Intel  MMIO register space - device 0 function 0 - MMR space */

#define I3200_C0DRB	0x200	/* Channel 0 DRAM Rank Boundary (16b x 4)
		 *
		 * 15:10 reserved
		 *  9:0  Channel 0 DRAM Rank Boundary Address
		 */
#define I3200_C1DRB	0x600	/* Channel 1 DRAM Rank Boundary (16b x 4) */
#define I3200_DRB_MASK	0x3ff	/* bits 9:0 */
#define I3200_DRB_SHIFT	26	/* 64MiB grain */

#define I3200_C0ECCERRLOG	0x280	/* Channel 0 ECC Error Log (64b)
		 *
		 * 63:48 Error Column Address (ERRCOL)
		 * 47:32 Error Row Address (ERRROW)
		 * 31:29 Error Bank Address (ERRBANK)
		 * 28:27 Error Rank Address (ERRRANK)
		 * 26:24 reserved
		 * 23:16 Error Syndrome (ERRSYND)
		 * 15: 2 reserved
		 *    1  Multiple Bit Error Status (MERRSTS)
		 *    0  Correctable Error Status (CERRSTS)
		 */
#define I3200_C1ECCERRLOG		0x680	/* Chan 1 ECC Error Log (64b) */
#define I3200_ECCERRLOG_CE		0x1
#define I3200_ECCERRLOG_UE		0x2
#define I3200_ECCERRLOG_RANK_BITS	0x18000000
#define I3200_ECCERRLOG_RANK_SHIFT	27
#define I3200_ECCERRLOG_SYNDROME_BITS	0xff0000
#define I3200_ECCERRLOG_SYNDROME_SHIFT	16
#define I3200_CAPID0			0xe0	/* P.95 of spec for details */

struct i3200_priv {
	void __iomem *window;
};

static int nr_channels;

static int how_many_channels(struct pci_dev *pdev)
{
	unsigned char capid0_8b; /* 8th byte of CAPID0 */

	pci_read_config_byte(pdev, I3200_CAPID0 + 8, &capid0_8b);
	if (capid0_8b & 0x20) { /* check DCD: Dual Channel Disable */
		debugf0("In single channel mode.\n");
		return 1;
	} else {
		debugf0("In dual channel mode.\n");
		return 2;
	}
}

static unsigned long eccerrlog_syndrome(u64 log)
{
	return (log & I3200_ECCERRLOG_SYNDROME_BITS) >>
		I3200_ECCERRLOG_SYNDROME_SHIFT;
}

static int eccerrlog_row(int channel, u64 log)
{
	u64 rank = ((log & I3200_ECCERRLOG_RANK_BITS) >>
		I3200_ECCERRLOG_RANK_SHIFT);
	return rank | (channel * I3200_RANKS_PER_CHANNEL);
}

enum i3200_chips {
	I3200 = 0,
};

struct i3200_dev_info {
	const char *ctl_name;
};

struct i3200_error_info {
	u16 errsts;
	u16 errsts2;
	u64 eccerrlog[I3200_CHANNELS];
};

static const struct i3200_dev_info i3200_devs[] = {
	[I3200] = {
		.ctl_name = "i3200"
	},
};

static struct pci_dev *mci_pdev;
static int i3200_registered = 1;


static void i3200_clear_error_info(struct mem_ctl_info *mci)
{
	struct pci_dev *pdev;

	pdev = to_pci_dev(mci->dev);

	/*
	 * Clear any error bits.
	 * (Yes, we really clear bits by writing 1 to them.)
	 */
	pci_write_bits16(pdev, I3200_ERRSTS, I3200_ERRSTS_BITS,
		I3200_ERRSTS_BITS);
}

static void i3200_get_and_clear_error_info(struct mem_ctl_info *mci,
		struct i3200_error_info *info)
{
	struct pci_dev *pdev;
	struct i3200_priv *priv = mci->pvt_info;
	void __iomem *window = priv->window;

	pdev = to_pci_dev(mci->dev);

	/*
	 * This is a mess because there is no atomic way to read all the
	 * registers at once and the registers can transition from CE being
	 * overwritten by UE.
	 */
	pci_read_config_word(pdev, I3200_ERRSTS, &info->errsts);
	if (!(info->errsts & I3200_ERRSTS_BITS))
		return;

	info->eccerrlog[0] = readq(window + I3200_C0ECCERRLOG);
	if (nr_channels == 2)
		info->eccerrlog[1] = readq(window + I3200_C1ECCERRLOG);

	pci_read_config_word(pdev, I3200_ERRSTS, &info->errsts2);

	/*
	 * If the error is the same for both reads then the first set
	 * of reads is valid.  If there is a change then there is a CE
	 * with no info and the second set of reads is valid and
	 * should be UE info.
	 */
	if ((info->errsts ^ info->errsts2) & I3200_ERRSTS_BITS) {
		info->eccerrlog[0] = readq(window + I3200_C0ECCERRLOG);
		if (nr_channels == 2)
			info->eccerrlog[1] = readq(window + I3200_C1ECCERRLOG);
	}

	i3200_clear_error_info(mci);
}

static void i3200_process_error_info(struct mem_ctl_info *mci,
		struct i3200_error_info *info)
{
	int channel;
	u64 log;

	if (!(info->errsts & I3200_ERRSTS_BITS))
		return;

	if ((info->errsts ^ info->errsts2) & I3200_ERRSTS_BITS) {
		edac_mc_handle_ce_no_info(mci, "UE overwrote CE");
		info->errsts = info->errsts2;
	}

	for (channel = 0; channel < nr_channels; channel++) {
		log = info->eccerrlog[channel];
		if (log & I3200_ECCERRLOG_UE) {
			edac_mc_handle_ue(mci, 0, 0,
				eccerrlog_row(channel, log),
				"i3200 UE");
		} else if (log & I3200_ECCERRLOG_CE) {
			edac_mc_handle_ce(mci, 0, 0,
				eccerrlog_syndrome(log),
				eccerrlog_row(channel, log), 0,
				"i3200 CE");
		}
	}
}

static void i3200_check(struct mem_ctl_info *mci)
{
	struct i3200_error_info info;

	debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
	i3200_get_and_clear_error_info(mci, &info);
	i3200_process_error_info(mci, &info);
}


void __iomem *i3200_map_mchbar(struct pci_dev *pdev)
{
	union {
		u64 mchbar;
		struct {
			u32 mchbar_low;
			u32 mchbar_high;
		};
	} u;
	void __iomem *window;

	pci_read_config_dword(pdev, I3200_MCHBAR_LOW, &u.mchbar_low);
	pci_read_config_dword(pdev, I3200_MCHBAR_HIGH, &u.mchbar_high);
	u.mchbar &= I3200_MCHBAR_MASK;

	if (u.mchbar != (resource_size_t)u.mchbar) {
		printk(KERN_ERR
			"i3200: mmio space beyond accessible range (0x%llx)\n",
			(unsigned long long)u.mchbar);
		return NULL;
	}

	window = ioremap_nocache(u.mchbar, I3200_MMR_WINDOW_SIZE);
	if (!window)
		printk(KERN_ERR "i3200: cannot map mmio space at 0x%llx\n",
			(unsigned long long)u.mchbar);

	return window;
}


static void i3200_get_drbs(void __iomem *window,
	u16 drbs[I3200_CHANNELS][I3200_RANKS_PER_CHANNEL])
{
	int i;

	for (i = 0; i < I3200_RANKS_PER_CHANNEL; i++) {
		drbs[0][i] = readw(window + I3200_C0DRB + 2*i) & I3200_DRB_MASK;
		drbs[1][i] = readw(window + I3200_C1DRB + 2*i) & I3200_DRB_MASK;
	}
}

static bool i3200_is_stacked(struct pci_dev *pdev,
	u16 drbs[I3200_CHANNELS][I3200_RANKS_PER_CHANNEL])
{
	u16 tom;

	pci_read_config_word(pdev, I3200_TOM, &tom);
	tom &= I3200_TOM_MASK;

	return drbs[I3200_CHANNELS - 1][I3200_RANKS_PER_CHANNEL - 1] == tom;
}

static unsigned long drb_to_nr_pages(
	u16 drbs[I3200_CHANNELS][I3200_RANKS_PER_CHANNEL], bool stacked,
	int channel, int rank)
{
	int n;

	n = drbs[channel][rank];
	if (rank > 0)
		n -= drbs[channel][rank - 1];
	if (stacked && (channel == 1) &&
	drbs[channel][rank] == drbs[channel][I3200_RANKS_PER_CHANNEL - 1])
		n -= drbs[0][I3200_RANKS_PER_CHANNEL - 1];

	n <<= (I3200_DRB_SHIFT - PAGE_SHIFT);
	return n;
}

static int i3200_probe1(struct pci_dev *pdev, int dev_idx)
{
	int rc;
	int i, j;
	struct mem_ctl_info *mci = NULL;
	u16 drbs[I3200_CHANNELS][I3200_RANKS_PER_CHANNEL];
	bool stacked;
	void __iomem *window;
	struct i3200_priv *priv;

	debugf0("MC: %s()\n", __func__);

	window = i3200_map_mchbar(pdev);
	if (!window)
		return -ENODEV;

	i3200_get_drbs(window, drbs);
	nr_channels = how_many_channels(pdev);

	mci = edac_mc_alloc(sizeof(struct i3200_priv), I3200_RANKS,
		nr_channels, 0);
	if (!mci)
		return -ENOMEM;

	debugf3("MC: %s(): init mci\n", __func__);

	mci->dev = &pdev->dev;
	mci->mtype_cap = MEM_FLAG_DDR2;

	mci->edac_ctl_cap = EDAC_FLAG_SECDED;
	mci->edac_cap = EDAC_FLAG_SECDED;

	mci->mod_name = EDAC_MOD_STR;
	mci->mod_ver = I3200_REVISION;
	mci->ctl_name = i3200_devs[dev_idx].ctl_name;
	mci->dev_name = pci_name(pdev);
	mci->edac_check = i3200_check;
	mci->ctl_page_to_phys = NULL;
	priv = mci->pvt_info;
	priv->window = window;

	stacked = i3200_is_stacked(pdev, drbs);

	/*
	 * The dram rank boundary (DRB) reg values are boundary addresses
	 * for each DRAM rank with a granularity of 64MB.  DRB regs are
	 * cumulative; the last one will contain the total memory
	 * contained in all ranks.
	 */
	for (i = 0; i < mci->nr_csrows; i++) {
		unsigned long nr_pages;
		struct csrow_info *csrow = &mci->csrows[i];

		nr_pages = drb_to_nr_pages(drbs, stacked,
			i / I3200_RANKS_PER_CHANNEL,
			i % I3200_RANKS_PER_CHANNEL);

		if (nr_pages == 0)
			continue;

		for (j = 0; j < nr_channels; j++) {
			struct dimm_info *dimm = csrow->channels[j].dimm;

			dimm->nr_pages = nr_pages / nr_channels;
			dimm->grain = nr_pages << PAGE_SHIFT;
			dimm->mtype = MEM_DDR2;
			dimm->dtype = DEV_UNKNOWN;
			dimm->edac_mode = EDAC_UNKNOWN;
		}
	}

	i3200_clear_error_info(mci);

	rc = -ENODEV;
	if (edac_mc_add_mc(mci)) {
		debugf3("MC: %s(): failed edac_mc_add_mc()\n", __func__);
		goto fail;
	}

	/* get this far and it's successful */
	debugf3("MC: %s(): success\n", __func__);
	return 0;

fail:
	iounmap(window);
	if (mci)
		edac_mc_free(mci);

	return rc;
}

static int __devinit i3200_init_one(struct pci_dev *pdev,
		const struct pci_device_id *ent)
{
	int rc;

	debugf0("MC: %s()\n", __func__);

	if (pci_enable_device(pdev) < 0)
		return -EIO;

	rc = i3200_probe1(pdev, ent->driver_data);
	if (!mci_pdev)
		mci_pdev = pci_dev_get(pdev);

	return rc;
}

static void __devexit i3200_remove_one(struct pci_dev *pdev)
{
	struct mem_ctl_info *mci;
	struct i3200_priv *priv;

	debugf0("%s()\n", __func__);

	mci = edac_mc_del_mc(&pdev->dev);
	if (!mci)
		return;

	priv = mci->pvt_info;
	iounmap(priv->window);

	edac_mc_free(mci);
}

static DEFINE_PCI_DEVICE_TABLE(i3200_pci_tbl) = {
	{
		PCI_VEND_DEV(INTEL, 3200_HB), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
		I3200},
	{
		0,
	}            /* 0 terminated list. */
};

MODULE_DEVICE_TABLE(pci, i3200_pci_tbl);

static struct pci_driver i3200_driver = {
	.name = EDAC_MOD_STR,
	.probe = i3200_init_one,
	.remove = __devexit_p(i3200_remove_one),
	.id_table = i3200_pci_tbl,
};

static int __init i3200_init(void)
{
	int pci_rc;

	debugf3("MC: %s()\n", __func__);

	/* Ensure that the OPSTATE is set correctly for POLL or NMI */
	opstate_init();

	pci_rc = pci_register_driver(&i3200_driver);
	if (pci_rc < 0)
		goto fail0;

	if (!mci_pdev) {
		i3200_registered = 0;
		mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
				PCI_DEVICE_ID_INTEL_3200_HB, NULL);
		if (!mci_pdev) {
			debugf0("i3200 pci_get_device fail\n");
			pci_rc = -ENODEV;
			goto fail1;
		}

		pci_rc = i3200_init_one(mci_pdev, i3200_pci_tbl);
		if (pci_rc < 0) {
			debugf0("i3200 init fail\n");
			pci_rc = -ENODEV;
			goto fail1;
		}
	}

	return 0;

fail1:
	pci_unregister_driver(&i3200_driver);

fail0:
	if (mci_pdev)
		pci_dev_put(mci_pdev);

	return pci_rc;
}

static void __exit i3200_exit(void)
{
	debugf3("MC: %s()\n", __func__);

	pci_unregister_driver(&i3200_driver);
	if (!i3200_registered) {
		i3200_remove_one(mci_pdev);
		pci_dev_put(mci_pdev);
	}
}

module_init(i3200_init);
module_exit(i3200_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Akamai Technologies, Inc.");
MODULE_DESCRIPTION("MC support for Intel 3200 memory hub controllers");

module_param(edac_op_state, int, 0444);
MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
Commit	Line	Data
dd8ef1db JU	1	/*
	2	* Intel 3200/3210 Memory Controller kernel module
	3	* Copyright (C) 2008-2009 Akamai Technologies, Inc.
	4	* Portions by Hitoshi Mitake <h.mitake@gmail.com>.
	5	*
	6	* This file may be distributed under the terms of the
	7	* GNU General Public License.
	8	*/
	9
	10	#include <linux/module.h>
	11	#include <linux/init.h>
	12	#include <linux/pci.h>
	13	#include <linux/pci_ids.h>
dd8ef1db JU	14	#include <linux/edac.h>
	15	#include <linux/io.h>
	16	#include "edac_core.h"
	17
797a796a HM	18	#include <asm-generic/io-64-nonatomic-lo-hi.h>
797a796a HM	19
dd8ef1db JU	20	#define I3200_REVISION "1.1"
	21
	22	#define EDAC_MOD_STR "i3200_edac"
	23
	24	#define PCI_DEVICE_ID_INTEL_3200_HB 0x29f0
	25
	26	#define I3200_RANKS 8
	27	#define I3200_RANKS_PER_CHANNEL 4
	28	#define I3200_CHANNELS 2
	29
	30	/* Intel 3200 register addresses - device 0 function 0 - DRAM Controller */
	31
	32	#define I3200_MCHBAR_LOW 0x48 /* MCH Memory Mapped Register BAR */
	33	#define I3200_MCHBAR_HIGH 0x4c
	34	#define I3200_MCHBAR_MASK 0xfffffc000ULL /* bits 35:14 */
	35	#define I3200_MMR_WINDOW_SIZE 16384
	36
	37	#define I3200_TOM 0xa0 /* Top of Memory (16b)
	38	*
	39	* 15:10 reserved
	40	* 9:0 total populated physical memory
	41	*/
	42	#define I3200_TOM_MASK 0x3ff /* bits 9:0 */
	43	#define I3200_TOM_SHIFT 26 /* 64MiB grain */
	44
	45	#define I3200_ERRSTS 0xc8 /* Error Status Register (16b)
	46	*
	47	* 15 reserved
	48	* 14 Isochronous TBWRR Run Behind FIFO Full
	49	* (ITCV)
	50	* 13 Isochronous TBWRR Run Behind FIFO Put
	51	* (ITSTV)
	52	* 12 reserved
	53	* 11 MCH Thermal Sensor Event
	54	* for SMI/SCI/SERR (GTSE)
	55	* 10 reserved
	56	* 9 LOCK to non-DRAM Memory Flag (LCKF)
	57	* 8 reserved
	58	* 7 DRAM Throttle Flag (DTF)
	59	* 6:2 reserved
	60	* 1 Multi-bit DRAM ECC Error Flag (DMERR)
	61	* 0 Single-bit DRAM ECC Error Flag (DSERR)
	62	*/
	63	#define I3200_ERRSTS_UE 0x0002
	64	#define I3200_ERRSTS_CE 0x0001
	65	#define I3200_ERRSTS_BITS (I3200_ERRSTS_UE \| I3200_ERRSTS_CE)
	66
	67
	68	/* Intel MMIO register space - device 0 function 0 - MMR space */
	69
	70	#define I3200_C0DRB 0x200 /* Channel 0 DRAM Rank Boundary (16b x 4)
	71	*
	72	* 15:10 reserved
	73	* 9:0 Channel 0 DRAM Rank Boundary Address
	74	*/
	75	#define I3200_C1DRB 0x600 /* Channel 1 DRAM Rank Boundary (16b x 4) */
	76	#define I3200_DRB_MASK 0x3ff /* bits 9:0 */
	77	#define I3200_DRB_SHIFT 26 /* 64MiB grain */
	78
	79	#define I3200_C0ECCERRLOG 0x280 /* Channel 0 ECC Error Log (64b)
	80	*
	81	* 63:48 Error Column Address (ERRCOL)
	82	* 47:32 Error Row Address (ERRROW)
	83	* 31:29 Error Bank Address (ERRBANK)
84	* 28:27 Error Rank Address (ERRRANK)
85	* 26:24 reserved
86	* 23:16 Error Syndrome (ERRSYND)
87	* 15: 2 reserved
88	* 1 Multiple Bit Error Status (MERRSTS)
89	* 0 Correctable Error Status (CERRSTS)
90	*/
91	#define I3200_C1ECCERRLOG 0x680 /* Chan 1 ECC Error Log (64b) */
92	#define I3200_ECCERRLOG_CE 0x1
93	#define I3200_ECCERRLOG_UE 0x2
94	#define I3200_ECCERRLOG_RANK_BITS 0x18000000
95	#define I3200_ECCERRLOG_RANK_SHIFT 27
96	#define I3200_ECCERRLOG_SYNDROME_BITS 0xff0000
97	#define I3200_ECCERRLOG_SYNDROME_SHIFT 16
98	#define I3200_CAPID0 0xe0 /* P.95 of spec for details */
99
100	struct i3200_priv {
101	void __iomem *window;
102	};
103
104	static int nr_channels;
105
106	static int how_many_channels(struct pci_dev *pdev)
107	{
108	unsigned char capid0_8b; /* 8th byte of CAPID0 */
109
110	pci_read_config_byte(pdev, I3200_CAPID0 + 8, &capid0_8b);
111	if (capid0_8b & 0x20) { /* check DCD: Dual Channel Disable */
112	debugf0("In single channel mode.\n");
113	return 1;
114	} else {
115	debugf0("In dual channel mode.\n");
116	return 2;
117	}
118	}
119
120	static unsigned long eccerrlog_syndrome(u64 log)
121	{
122	return (log & I3200_ECCERRLOG_SYNDROME_BITS) >>
123	I3200_ECCERRLOG_SYNDROME_SHIFT;
124	}
125
126	static int eccerrlog_row(int channel, u64 log)
127	{
128	u64 rank = ((log & I3200_ECCERRLOG_RANK_BITS) >>
129	I3200_ECCERRLOG_RANK_SHIFT);
130	return rank \| (channel * I3200_RANKS_PER_CHANNEL);
131	}
132
133	enum i3200_chips {
134	I3200 = 0,
135	};
136
137	struct i3200_dev_info {
138	const char *ctl_name;
139	};
140
141	struct i3200_error_info {
142	u16 errsts;
143	u16 errsts2;
144	u64 eccerrlog[I3200_CHANNELS];
145	};
146
147	static const struct i3200_dev_info i3200_devs[] = {
148	[I3200] = {
149	.ctl_name = "i3200"
150	},
151	};
152
153	static struct pci_dev *mci_pdev;
154	static int i3200_registered = 1;
155
156
157	static void i3200_clear_error_info(struct mem_ctl_info *mci)
158	{
159	struct pci_dev *pdev;
160
161	pdev = to_pci_dev(mci->dev);
162
163	/*
164	* Clear any error bits.
165	* (Yes, we really clear bits by writing 1 to them.)
166	*/
167	pci_write_bits16(pdev, I3200_ERRSTS, I3200_ERRSTS_BITS,
168	I3200_ERRSTS_BITS);
169	}
170
171	static void i3200_get_and_clear_error_info(struct mem_ctl_info *mci,
172	struct i3200_error_info *info)
173	{
174	struct pci_dev *pdev;
175	struct i3200_priv *priv = mci->pvt_info;
176	void __iomem *window = priv->window;
177
178	pdev = to_pci_dev(mci->dev);
179
180	/*
181	* This is a mess because there is no atomic way to read all the
182	* registers at once and the registers can transition from CE being
183	* overwritten by UE.
184	*/
185	pci_read_config_word(pdev, I3200_ERRSTS, &info->errsts);
186	if (!(info->errsts & I3200_ERRSTS_BITS))
187	return;
188
189	info->eccerrlog[0] = readq(window + I3200_C0ECCERRLOG);
190	if (nr_channels == 2)
191	info->eccerrlog[1] = readq(window + I3200_C1ECCERRLOG);
192
193	pci_read_config_word(pdev, I3200_ERRSTS, &info->errsts2);
194
195	/*
196	* If the error is the same for both reads then the first set
197	* of reads is valid. If there is a change then there is a CE
198	* with no info and the second set of reads is valid and
199	* should be UE info.
200	*/
201	if ((info->errsts ^ info->errsts2) & I3200_ERRSTS_BITS) {
202	info->eccerrlog[0] = readq(window + I3200_C0ECCERRLOG);
203	if (nr_channels == 2)
204	info->eccerrlog[1] = readq(window + I3200_C1ECCERRLOG);
205	}
206
207	i3200_clear_error_info(mci);
208	}
209
210	static void i3200_process_error_info(struct mem_ctl_info *mci,
211	struct i3200_error_info *info)
212	{
213	int channel;
214	u64 log;
215
216	if (!(info->errsts & I3200_ERRSTS_BITS))
217	return;
218
219	if ((info->errsts ^ info->errsts2) & I3200_ERRSTS_BITS) {
220	edac_mc_handle_ce_no_info(mci, "UE overwrote CE");
221	info->errsts = info->errsts2;
222	}
223
224	for (channel = 0; channel < nr_channels; channel++) {
225	log = info->eccerrlog[channel];
226	if (log & I3200_ECCERRLOG_UE) {
227	edac_mc_handle_ue(mci, 0, 0,
228	eccerrlog_row(channel, log),
229	"i3200 UE");
230	} else if (log & I3200_ECCERRLOG_CE) {
231	edac_mc_handle_ce(mci, 0, 0,
232	eccerrlog_syndrome(log),
233	eccerrlog_row(channel, log), 0,
234	"i3200 CE");
235	}
236	}
237	}
238
239	static void i3200_check(struct mem_ctl_info *mci)
240	{
241	struct i3200_error_info info;
242
243	debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
244	i3200_get_and_clear_error_info(mci, &info);
245	i3200_process_error_info(mci, &info);
246	}
247
248
249	void __iomem i3200_map_mchbar(struct pci_dev pdev)
250	{
251	union {
252	u64 mchbar;
253	struct {
254	u32 mchbar_low;
255	u32 mchbar_high;
256	};
257	} u;
258	void __iomem *window;
259
260	pci_read_config_dword(pdev, I3200_MCHBAR_LOW, &u.mchbar_low);
261	pci_read_config_dword(pdev, I3200_MCHBAR_HIGH, &u.mchbar_high);
262	u.mchbar &= I3200_MCHBAR_MASK;
263
264	if (u.mchbar != (resource_size_t)u.mchbar) {
265	printk(KERN_ERR
266	"i3200: mmio space beyond accessible range (0x%llx)\n",
267	(unsigned long long)u.mchbar);
268	return NULL;
269	}
270
271	window = ioremap_nocache(u.mchbar, I3200_MMR_WINDOW_SIZE);
272	if (!window)
273	printk(KERN_ERR "i3200: cannot map mmio space at 0x%llx\n",
274	(unsigned long long)u.mchbar);
275
276	return window;
277	}
278
279
280	static void i3200_get_drbs(void __iomem *window,
281	u16 drbs[I3200_CHANNELS][I3200_RANKS_PER_CHANNEL])
282	{
283	int i;
284
285	for (i = 0; i < I3200_RANKS_PER_CHANNEL; i++) {
286	drbs[0][i] = readw(window + I3200_C0DRB + 2*i) & I3200_DRB_MASK;
287	drbs[1][i] = readw(window + I3200_C1DRB + 2*i) & I3200_DRB_MASK;
288	}
289	}
290
291	static bool i3200_is_stacked(struct pci_dev *pdev,
292	u16 drbs[I3200_CHANNELS][I3200_RANKS_PER_CHANNEL])
293	{
294	u16 tom;
295
296	pci_read_config_word(pdev, I3200_TOM, &tom);
297	tom &= I3200_TOM_MASK;
298
299	return drbs[I3200_CHANNELS - 1][I3200_RANKS_PER_CHANNEL - 1] == tom;
300	}
301
302	static unsigned long drb_to_nr_pages(
303	u16 drbs[I3200_CHANNELS][I3200_RANKS_PER_CHANNEL], bool stacked,
304	int channel, int rank)
305	{
306	int n;
307
308	n = drbs[channel][rank];
309	if (rank > 0)
310	n -= drbs[channel][rank - 1];
311	if (stacked && (channel == 1) &&
312	drbs[channel][rank] == drbs[channel][I3200_RANKS_PER_CHANNEL - 1])
313	n -= drbs[0][I3200_RANKS_PER_CHANNEL - 1];
314
315	n <<= (I3200_DRB_SHIFT - PAGE_SHIFT);
316	return n;
317	}
318
319	static int i3200_probe1(struct pci_dev *pdev, int dev_idx)
320	{
321	int rc;
084a4fcc	322	int i, j;
dd8ef1db	323	struct mem_ctl_info *mci = NULL;
dd8ef1db JU	324	u16 drbs[I3200_CHANNELS][I3200_RANKS_PER_CHANNEL];
	325	bool stacked;
	326	void __iomem *window;
	327	struct i3200_priv *priv;
	328
	329	debugf0("MC: %s()\n", __func__);
	330
	331	window = i3200_map_mchbar(pdev);
	332	if (!window)
	333	return -ENODEV;
	334
	335	i3200_get_drbs(window, drbs);
	336	nr_channels = how_many_channels(pdev);
	337
	338	mci = edac_mc_alloc(sizeof(struct i3200_priv), I3200_RANKS,
	339	nr_channels, 0);
	340	if (!mci)
	341	return -ENOMEM;
	342
	343	debugf3("MC: %s(): init mci\n", __func__);
	344
	345	mci->dev = &pdev->dev;
	346	mci->mtype_cap = MEM_FLAG_DDR2;
	347
	348	mci->edac_ctl_cap = EDAC_FLAG_SECDED;
	349	mci->edac_cap = EDAC_FLAG_SECDED;
	350
	351	mci->mod_name = EDAC_MOD_STR;
	352	mci->mod_ver = I3200_REVISION;
	353	mci->ctl_name = i3200_devs[dev_idx].ctl_name;
	354	mci->dev_name = pci_name(pdev);
	355	mci->edac_check = i3200_check;
	356	mci->ctl_page_to_phys = NULL;
	357	priv = mci->pvt_info;
	358	priv->window = window;
	359
	360	stacked = i3200_is_stacked(pdev, drbs);
	361
	362	/*
	363	* The dram rank boundary (DRB) reg values are boundary addresses
	364	* for each DRAM rank with a granularity of 64MB. DRB regs are
	365	* cumulative; the last one will contain the total memory
	366	* contained in all ranks.
	367	*/
dd8ef1db JU	368	for (i = 0; i < mci->nr_csrows; i++) {
	369	unsigned long nr_pages;
	370	struct csrow_info *csrow = &mci->csrows[i];
	371
	372	nr_pages = drb_to_nr_pages(drbs, stacked,
	373	i / I3200_RANKS_PER_CHANNEL,
	374	i % I3200_RANKS_PER_CHANNEL);
	375
084a4fcc	376	if (nr_pages == 0)
dd8ef1db	377	continue;
dd8ef1db	378
084a4fcc MCC	379	for (j = 0; j < nr_channels; j++) {
	380	struct dimm_info *dimm = csrow->channels[j].dimm;
	381
a895bf8b	382	dimm->nr_pages = nr_pages / nr_channels;
084a4fcc MCC	383	dimm->grain = nr_pages << PAGE_SHIFT;
	384	dimm->mtype = MEM_DDR2;
	385	dimm->dtype = DEV_UNKNOWN;
	386	dimm->edac_mode = EDAC_UNKNOWN;
	387	}
dd8ef1db JU	388	}
	389
	390	i3200_clear_error_info(mci);
	391
	392	rc = -ENODEV;
	393	if (edac_mc_add_mc(mci)) {
	394	debugf3("MC: %s(): failed edac_mc_add_mc()\n", __func__);
	395	goto fail;
	396	}
	397
	398	/* get this far and it's successful */
	399	debugf3("MC: %s(): success\n", __func__);
	400	return 0;
	401
	402	fail:
	403	iounmap(window);
	404	if (mci)
	405	edac_mc_free(mci);
	406
	407	return rc;
	408	}
	409
	410	static int __devinit i3200_init_one(struct pci_dev *pdev,
	411	const struct pci_device_id *ent)
	412	{
	413	int rc;
	414
	415	debugf0("MC: %s()\n", __func__);
	416
	417	if (pci_enable_device(pdev) < 0)
	418	return -EIO;
	419
	420	rc = i3200_probe1(pdev, ent->driver_data);
	421	if (!mci_pdev)
	422	mci_pdev = pci_dev_get(pdev);
	423
	424	return rc;
	425	}
	426
	427	static void __devexit i3200_remove_one(struct pci_dev *pdev)
	428	{
	429	struct mem_ctl_info *mci;
	430	struct i3200_priv *priv;
	431
	432	debugf0("%s()\n", __func__);
	433
	434	mci = edac_mc_del_mc(&pdev->dev);
	435	if (!mci)
	436	return;
	437
	438	priv = mci->pvt_info;
	439	iounmap(priv->window);
	440
	441	edac_mc_free(mci);
	442	}
	443
36c46f31	444	static DEFINE_PCI_DEVICE_TABLE(i3200_pci_tbl) = {
dd8ef1db JU	445	{
	446	PCI_VEND_DEV(INTEL, 3200_HB), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
	447	I3200},
	448	{
	449	0,
	450	} /* 0 terminated list. */
	451	};
	452
	453	MODULE_DEVICE_TABLE(pci, i3200_pci_tbl);
	454
	455	static struct pci_driver i3200_driver = {
	456	.name = EDAC_MOD_STR,
	457	.probe = i3200_init_one,
	458	.remove = __devexit_p(i3200_remove_one),
	459	.id_table = i3200_pci_tbl,
	460	};
	461
	462	static int __init i3200_init(void)
	463	{
	464	int pci_rc;
	465
	466	debugf3("MC: %s()\n", __func__);
	467
	468	/* Ensure that the OPSTATE is set correctly for POLL or NMI */
	469	opstate_init();
	470
	471	pci_rc = pci_register_driver(&i3200_driver);
	472	if (pci_rc < 0)
	473	goto fail0;
	474
	475	if (!mci_pdev) {
	476	i3200_registered = 0;
	477	mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
	478	PCI_DEVICE_ID_INTEL_3200_HB, NULL);
	479	if (!mci_pdev) {
	480	debugf0("i3200 pci_get_device fail\n");
	481	pci_rc = -ENODEV;
	482	goto fail1;
	483	}
	484
	485	pci_rc = i3200_init_one(mci_pdev, i3200_pci_tbl);
	486	if (pci_rc < 0) {
	487	debugf0("i3200 init fail\n");
	488	pci_rc = -ENODEV;
	489	goto fail1;
	490	}
	491	}
	492
	493	return 0;
	494
	495	fail1:
	496	pci_unregister_driver(&i3200_driver);
	497
	498	fail0:
	499	if (mci_pdev)
	500	pci_dev_put(mci_pdev);
	501
	502	return pci_rc;
	503	}
	504
	505	static void __exit i3200_exit(void)
	506	{
	507	debugf3("MC: %s()\n", __func__);
	508
509	pci_unregister_driver(&i3200_driver);
510	if (!i3200_registered) {
511	i3200_remove_one(mci_pdev);
512	pci_dev_put(mci_pdev);
513	}
514	}
515
516	module_init(i3200_init);
517	module_exit(i3200_exit);
518
519	MODULE_LICENSE("GPL");
520	MODULE_AUTHOR("Akamai Technologies, Inc.");
521	MODULE_DESCRIPTION("MC support for Intel 3200 memory hub controllers");
522
523	module_param(edac_op_state, int, 0444);
524	MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");