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52707f91 MCC |
1 | /* Intel i7 core/Nehalem Memory Controller kernel module |
2 | * | |
3 | * This driver supports yhe memory controllers found on the Intel | |
4 | * processor families i7core, i7core 7xx/8xx, i5core, Xeon 35xx, | |
5 | * Xeon 55xx and Xeon 56xx also known as Nehalem, Nehalem-EP, Lynnfield | |
6 | * and Westmere-EP. | |
a0c36a1f MCC |
7 | * |
8 | * This file may be distributed under the terms of the | |
9 | * GNU General Public License version 2 only. | |
10 | * | |
52707f91 | 11 | * Copyright (c) 2009-2010 by: |
a0c36a1f MCC |
12 | * Mauro Carvalho Chehab <mchehab@redhat.com> |
13 | * | |
14 | * Red Hat Inc. http://www.redhat.com | |
15 | * | |
16 | * Forked and adapted from the i5400_edac driver | |
17 | * | |
18 | * Based on the following public Intel datasheets: | |
19 | * Intel Core i7 Processor Extreme Edition and Intel Core i7 Processor | |
20 | * Datasheet, Volume 2: | |
21 | * http://download.intel.com/design/processor/datashts/320835.pdf | |
22 | * Intel Xeon Processor 5500 Series Datasheet Volume 2 | |
23 | * http://www.intel.com/Assets/PDF/datasheet/321322.pdf | |
24 | * also available at: | |
25 | * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf | |
26 | */ | |
27 | ||
a0c36a1f MCC |
28 | #include <linux/module.h> |
29 | #include <linux/init.h> | |
30 | #include <linux/pci.h> | |
31 | #include <linux/pci_ids.h> | |
32 | #include <linux/slab.h> | |
3b918c12 | 33 | #include <linux/delay.h> |
a0c36a1f MCC |
34 | #include <linux/edac.h> |
35 | #include <linux/mmzone.h> | |
d5381642 | 36 | #include <linux/edac_mce.h> |
f4742949 | 37 | #include <linux/smp.h> |
14d2c083 | 38 | #include <asm/processor.h> |
a0c36a1f MCC |
39 | |
40 | #include "edac_core.h" | |
41 | ||
f4742949 MCC |
42 | /* |
43 | * This is used for Nehalem-EP and Nehalem-EX devices, where the non-core | |
44 | * registers start at bus 255, and are not reported by BIOS. | |
45 | * We currently find devices with only 2 sockets. In order to support more QPI | |
46 | * Quick Path Interconnect, just increment this number. | |
47 | */ | |
48 | #define MAX_SOCKET_BUSES 2 | |
49 | ||
50 | ||
a0c36a1f MCC |
51 | /* |
52 | * Alter this version for the module when modifications are made | |
53 | */ | |
54 | #define I7CORE_REVISION " Ver: 1.0.0 " __DATE__ | |
55 | #define EDAC_MOD_STR "i7core_edac" | |
56 | ||
a0c36a1f MCC |
57 | /* |
58 | * Debug macros | |
59 | */ | |
60 | #define i7core_printk(level, fmt, arg...) \ | |
61 | edac_printk(level, "i7core", fmt, ##arg) | |
62 | ||
63 | #define i7core_mc_printk(mci, level, fmt, arg...) \ | |
64 | edac_mc_chipset_printk(mci, level, "i7core", fmt, ##arg) | |
65 | ||
66 | /* | |
67 | * i7core Memory Controller Registers | |
68 | */ | |
69 | ||
e9bd2e73 MCC |
70 | /* OFFSETS for Device 0 Function 0 */ |
71 | ||
72 | #define MC_CFG_CONTROL 0x90 | |
73 | ||
a0c36a1f MCC |
74 | /* OFFSETS for Device 3 Function 0 */ |
75 | ||
76 | #define MC_CONTROL 0x48 | |
77 | #define MC_STATUS 0x4c | |
78 | #define MC_MAX_DOD 0x64 | |
79 | ||
442305b1 MCC |
80 | /* |
81 | * OFFSETS for Device 3 Function 4, as inicated on Xeon 5500 datasheet: | |
82 | * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf | |
83 | */ | |
84 | ||
85 | #define MC_TEST_ERR_RCV1 0x60 | |
86 | #define DIMM2_COR_ERR(r) ((r) & 0x7fff) | |
87 | ||
88 | #define MC_TEST_ERR_RCV0 0x64 | |
89 | #define DIMM1_COR_ERR(r) (((r) >> 16) & 0x7fff) | |
90 | #define DIMM0_COR_ERR(r) ((r) & 0x7fff) | |
91 | ||
b4e8f0b6 MCC |
92 | /* OFFSETS for Device 3 Function 2, as inicated on Xeon 5500 datasheet */ |
93 | #define MC_COR_ECC_CNT_0 0x80 | |
94 | #define MC_COR_ECC_CNT_1 0x84 | |
95 | #define MC_COR_ECC_CNT_2 0x88 | |
96 | #define MC_COR_ECC_CNT_3 0x8c | |
97 | #define MC_COR_ECC_CNT_4 0x90 | |
98 | #define MC_COR_ECC_CNT_5 0x94 | |
99 | ||
100 | #define DIMM_TOP_COR_ERR(r) (((r) >> 16) & 0x7fff) | |
101 | #define DIMM_BOT_COR_ERR(r) ((r) & 0x7fff) | |
102 | ||
103 | ||
a0c36a1f MCC |
104 | /* OFFSETS for Devices 4,5 and 6 Function 0 */ |
105 | ||
0b2b7b7e MCC |
106 | #define MC_CHANNEL_DIMM_INIT_PARAMS 0x58 |
107 | #define THREE_DIMMS_PRESENT (1 << 24) | |
108 | #define SINGLE_QUAD_RANK_PRESENT (1 << 23) | |
109 | #define QUAD_RANK_PRESENT (1 << 22) | |
110 | #define REGISTERED_DIMM (1 << 15) | |
111 | ||
f122a892 MCC |
112 | #define MC_CHANNEL_MAPPER 0x60 |
113 | #define RDLCH(r, ch) ((((r) >> (3 + (ch * 6))) & 0x07) - 1) | |
114 | #define WRLCH(r, ch) ((((r) >> (ch * 6)) & 0x07) - 1) | |
115 | ||
0b2b7b7e MCC |
116 | #define MC_CHANNEL_RANK_PRESENT 0x7c |
117 | #define RANK_PRESENT_MASK 0xffff | |
118 | ||
a0c36a1f | 119 | #define MC_CHANNEL_ADDR_MATCH 0xf0 |
194a40fe MCC |
120 | #define MC_CHANNEL_ERROR_MASK 0xf8 |
121 | #define MC_CHANNEL_ERROR_INJECT 0xfc | |
122 | #define INJECT_ADDR_PARITY 0x10 | |
123 | #define INJECT_ECC 0x08 | |
124 | #define MASK_CACHELINE 0x06 | |
125 | #define MASK_FULL_CACHELINE 0x06 | |
126 | #define MASK_MSB32_CACHELINE 0x04 | |
127 | #define MASK_LSB32_CACHELINE 0x02 | |
128 | #define NO_MASK_CACHELINE 0x00 | |
129 | #define REPEAT_EN 0x01 | |
a0c36a1f | 130 | |
0b2b7b7e | 131 | /* OFFSETS for Devices 4,5 and 6 Function 1 */ |
b990538a | 132 | |
0b2b7b7e MCC |
133 | #define MC_DOD_CH_DIMM0 0x48 |
134 | #define MC_DOD_CH_DIMM1 0x4c | |
135 | #define MC_DOD_CH_DIMM2 0x50 | |
136 | #define RANKOFFSET_MASK ((1 << 12) | (1 << 11) | (1 << 10)) | |
137 | #define RANKOFFSET(x) ((x & RANKOFFSET_MASK) >> 10) | |
138 | #define DIMM_PRESENT_MASK (1 << 9) | |
139 | #define DIMM_PRESENT(x) (((x) & DIMM_PRESENT_MASK) >> 9) | |
854d3349 MCC |
140 | #define MC_DOD_NUMBANK_MASK ((1 << 8) | (1 << 7)) |
141 | #define MC_DOD_NUMBANK(x) (((x) & MC_DOD_NUMBANK_MASK) >> 7) | |
142 | #define MC_DOD_NUMRANK_MASK ((1 << 6) | (1 << 5)) | |
143 | #define MC_DOD_NUMRANK(x) (((x) & MC_DOD_NUMRANK_MASK) >> 5) | |
41fcb7fe | 144 | #define MC_DOD_NUMROW_MASK ((1 << 4) | (1 << 3) | (1 << 2)) |
5566cb7c | 145 | #define MC_DOD_NUMROW(x) (((x) & MC_DOD_NUMROW_MASK) >> 2) |
854d3349 MCC |
146 | #define MC_DOD_NUMCOL_MASK 3 |
147 | #define MC_DOD_NUMCOL(x) ((x) & MC_DOD_NUMCOL_MASK) | |
0b2b7b7e | 148 | |
f122a892 MCC |
149 | #define MC_RANK_PRESENT 0x7c |
150 | ||
0b2b7b7e MCC |
151 | #define MC_SAG_CH_0 0x80 |
152 | #define MC_SAG_CH_1 0x84 | |
153 | #define MC_SAG_CH_2 0x88 | |
154 | #define MC_SAG_CH_3 0x8c | |
155 | #define MC_SAG_CH_4 0x90 | |
156 | #define MC_SAG_CH_5 0x94 | |
157 | #define MC_SAG_CH_6 0x98 | |
158 | #define MC_SAG_CH_7 0x9c | |
159 | ||
160 | #define MC_RIR_LIMIT_CH_0 0x40 | |
161 | #define MC_RIR_LIMIT_CH_1 0x44 | |
162 | #define MC_RIR_LIMIT_CH_2 0x48 | |
163 | #define MC_RIR_LIMIT_CH_3 0x4C | |
164 | #define MC_RIR_LIMIT_CH_4 0x50 | |
165 | #define MC_RIR_LIMIT_CH_5 0x54 | |
166 | #define MC_RIR_LIMIT_CH_6 0x58 | |
167 | #define MC_RIR_LIMIT_CH_7 0x5C | |
168 | #define MC_RIR_LIMIT_MASK ((1 << 10) - 1) | |
169 | ||
170 | #define MC_RIR_WAY_CH 0x80 | |
171 | #define MC_RIR_WAY_OFFSET_MASK (((1 << 14) - 1) & ~0x7) | |
172 | #define MC_RIR_WAY_RANK_MASK 0x7 | |
173 | ||
a0c36a1f MCC |
174 | /* |
175 | * i7core structs | |
176 | */ | |
177 | ||
178 | #define NUM_CHANS 3 | |
442305b1 MCC |
179 | #define MAX_DIMMS 3 /* Max DIMMS per channel */ |
180 | #define MAX_MCR_FUNC 4 | |
181 | #define MAX_CHAN_FUNC 3 | |
a0c36a1f MCC |
182 | |
183 | struct i7core_info { | |
184 | u32 mc_control; | |
185 | u32 mc_status; | |
186 | u32 max_dod; | |
f122a892 | 187 | u32 ch_map; |
a0c36a1f MCC |
188 | }; |
189 | ||
194a40fe MCC |
190 | |
191 | struct i7core_inject { | |
192 | int enable; | |
193 | ||
194 | u32 section; | |
195 | u32 type; | |
196 | u32 eccmask; | |
197 | ||
198 | /* Error address mask */ | |
199 | int channel, dimm, rank, bank, page, col; | |
200 | }; | |
201 | ||
0b2b7b7e | 202 | struct i7core_channel { |
442305b1 MCC |
203 | u32 ranks; |
204 | u32 dimms; | |
0b2b7b7e MCC |
205 | }; |
206 | ||
8f331907 | 207 | struct pci_id_descr { |
66607706 MCC |
208 | int dev; |
209 | int func; | |
210 | int dev_id; | |
de06eeef | 211 | int optional; |
8f331907 MCC |
212 | }; |
213 | ||
bd9e19ca VM |
214 | struct pci_id_table { |
215 | struct pci_id_descr *descr; | |
216 | int n_devs; | |
217 | }; | |
218 | ||
f4742949 MCC |
219 | struct i7core_dev { |
220 | struct list_head list; | |
221 | u8 socket; | |
222 | struct pci_dev **pdev; | |
de06eeef | 223 | int n_devs; |
f4742949 MCC |
224 | struct mem_ctl_info *mci; |
225 | }; | |
226 | ||
a0c36a1f | 227 | struct i7core_pvt { |
f4742949 MCC |
228 | struct pci_dev *pci_noncore; |
229 | struct pci_dev *pci_mcr[MAX_MCR_FUNC + 1]; | |
230 | struct pci_dev *pci_ch[NUM_CHANS][MAX_CHAN_FUNC + 1]; | |
231 | ||
232 | struct i7core_dev *i7core_dev; | |
67166af4 | 233 | |
a0c36a1f | 234 | struct i7core_info info; |
194a40fe | 235 | struct i7core_inject inject; |
f4742949 | 236 | struct i7core_channel channel[NUM_CHANS]; |
67166af4 | 237 | |
f4742949 | 238 | int channels; /* Number of active channels */ |
442305b1 | 239 | |
f4742949 MCC |
240 | int ce_count_available; |
241 | int csrow_map[NUM_CHANS][MAX_DIMMS]; | |
b4e8f0b6 MCC |
242 | |
243 | /* ECC corrected errors counts per udimm */ | |
f4742949 MCC |
244 | unsigned long udimm_ce_count[MAX_DIMMS]; |
245 | int udimm_last_ce_count[MAX_DIMMS]; | |
b4e8f0b6 | 246 | /* ECC corrected errors counts per rdimm */ |
f4742949 MCC |
247 | unsigned long rdimm_ce_count[NUM_CHANS][MAX_DIMMS]; |
248 | int rdimm_last_ce_count[NUM_CHANS][MAX_DIMMS]; | |
442305b1 | 249 | |
f4742949 | 250 | unsigned int is_registered; |
14d2c083 | 251 | |
d5381642 MCC |
252 | /* mcelog glue */ |
253 | struct edac_mce edac_mce; | |
ca9c90ba MCC |
254 | |
255 | /* Fifo double buffers */ | |
d5381642 | 256 | struct mce mce_entry[MCE_LOG_LEN]; |
ca9c90ba MCC |
257 | struct mce mce_outentry[MCE_LOG_LEN]; |
258 | ||
259 | /* Fifo in/out counters */ | |
260 | unsigned mce_in, mce_out; | |
261 | ||
262 | /* Count indicator to show errors not got */ | |
263 | unsigned mce_overrun; | |
a0c36a1f MCC |
264 | }; |
265 | ||
66607706 MCC |
266 | /* Static vars */ |
267 | static LIST_HEAD(i7core_edac_list); | |
268 | static DEFINE_MUTEX(i7core_edac_lock); | |
a0c36a1f | 269 | |
8f331907 MCC |
270 | #define PCI_DESCR(device, function, device_id) \ |
271 | .dev = (device), \ | |
272 | .func = (function), \ | |
273 | .dev_id = (device_id) | |
274 | ||
bd9e19ca | 275 | struct pci_id_descr pci_dev_descr_i7core_nehalem[] = { |
8f331907 MCC |
276 | /* Memory controller */ |
277 | { PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_I7_MCR) }, | |
278 | { PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_I7_MC_TAD) }, | |
de06eeef MCC |
279 | /* Exists only for RDIMM */ |
280 | { PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_I7_MC_RAS), .optional = 1 }, | |
8f331907 MCC |
281 | { PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_I7_MC_TEST) }, |
282 | ||
283 | /* Channel 0 */ | |
284 | { PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH0_CTRL) }, | |
285 | { PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH0_ADDR) }, | |
286 | { PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH0_RANK) }, | |
287 | { PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH0_TC) }, | |
288 | ||
289 | /* Channel 1 */ | |
290 | { PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH1_CTRL) }, | |
291 | { PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH1_ADDR) }, | |
292 | { PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH1_RANK) }, | |
293 | { PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH1_TC) }, | |
294 | ||
295 | /* Channel 2 */ | |
296 | { PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH2_CTRL) }, | |
297 | { PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH2_ADDR) }, | |
298 | { PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH2_RANK) }, | |
299 | { PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH2_TC) }, | |
310cbb72 MCC |
300 | |
301 | /* Generic Non-core registers */ | |
302 | /* | |
303 | * This is the PCI device on i7core and on Xeon 35xx (8086:2c41) | |
304 | * On Xeon 55xx, however, it has a different id (8086:2c40). So, | |
305 | * the probing code needs to test for the other address in case of | |
306 | * failure of this one | |
307 | */ | |
fd382654 | 308 | { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_I7_NONCORE) }, |
310cbb72 | 309 | |
a0c36a1f | 310 | }; |
8f331907 | 311 | |
52a2e4fc MCC |
312 | struct pci_id_descr pci_dev_descr_lynnfield[] = { |
313 | { PCI_DESCR( 3, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR) }, | |
314 | { PCI_DESCR( 3, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD) }, | |
315 | { PCI_DESCR( 3, 4, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST) }, | |
316 | ||
317 | { PCI_DESCR( 4, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL) }, | |
318 | { PCI_DESCR( 4, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR) }, | |
319 | { PCI_DESCR( 4, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK) }, | |
320 | { PCI_DESCR( 4, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC) }, | |
321 | ||
508fa179 MCC |
322 | { PCI_DESCR( 5, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL) }, |
323 | { PCI_DESCR( 5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR) }, | |
324 | { PCI_DESCR( 5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK) }, | |
325 | { PCI_DESCR( 5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC) }, | |
52a2e4fc | 326 | |
f05da2f7 MCC |
327 | /* |
328 | * This is the PCI device has an alternate address on some | |
329 | * processors like Core i7 860 | |
330 | */ | |
52a2e4fc MCC |
331 | { PCI_DESCR( 0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE) }, |
332 | }; | |
333 | ||
bd9e19ca VM |
334 | struct pci_id_descr pci_dev_descr_i7core_westmere[] = { |
335 | /* Memory controller */ | |
336 | { PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR_REV2) }, | |
337 | { PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD_REV2) }, | |
338 | /* Exists only for RDIMM */ | |
339 | { PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_RAS_REV2), .optional = 1 }, | |
340 | { PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST_REV2) }, | |
341 | ||
342 | /* Channel 0 */ | |
343 | { PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL_REV2) }, | |
344 | { PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR_REV2) }, | |
345 | { PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK_REV2) }, | |
346 | { PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC_REV2) }, | |
347 | ||
348 | /* Channel 1 */ | |
349 | { PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL_REV2) }, | |
350 | { PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR_REV2) }, | |
351 | { PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK_REV2) }, | |
352 | { PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC_REV2) }, | |
353 | ||
354 | /* Channel 2 */ | |
355 | { PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_CTRL_REV2) }, | |
356 | { PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_ADDR_REV2) }, | |
357 | { PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_RANK_REV2) }, | |
358 | { PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_TC_REV2) }, | |
359 | ||
360 | /* Generic Non-core registers */ | |
361 | { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_REV2) }, | |
362 | ||
363 | }; | |
364 | ||
365 | #define PCI_ID_TABLE_ENTRY(A) { A, ARRAY_SIZE(A) } | |
366 | struct pci_id_table pci_dev_table[] = { | |
367 | PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_nehalem), | |
368 | PCI_ID_TABLE_ENTRY(pci_dev_descr_lynnfield), | |
369 | PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_westmere), | |
370 | }; | |
371 | ||
8f331907 MCC |
372 | /* |
373 | * pci_device_id table for which devices we are looking for | |
8f331907 MCC |
374 | */ |
375 | static const struct pci_device_id i7core_pci_tbl[] __devinitdata = { | |
d1fd4fb6 | 376 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58_HUB_MGMT)}, |
f05da2f7 | 377 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNNFIELD_QPI_LINK0)}, |
8f331907 MCC |
378 | {0,} /* 0 terminated list. */ |
379 | }; | |
380 | ||
a0c36a1f MCC |
381 | static struct edac_pci_ctl_info *i7core_pci; |
382 | ||
383 | /**************************************************************************** | |
384 | Anciliary status routines | |
385 | ****************************************************************************/ | |
386 | ||
387 | /* MC_CONTROL bits */ | |
ef708b53 MCC |
388 | #define CH_ACTIVE(pvt, ch) ((pvt)->info.mc_control & (1 << (8 + ch))) |
389 | #define ECCx8(pvt) ((pvt)->info.mc_control & (1 << 1)) | |
a0c36a1f MCC |
390 | |
391 | /* MC_STATUS bits */ | |
61053fde | 392 | #define ECC_ENABLED(pvt) ((pvt)->info.mc_status & (1 << 4)) |
ef708b53 | 393 | #define CH_DISABLED(pvt, ch) ((pvt)->info.mc_status & (1 << ch)) |
a0c36a1f MCC |
394 | |
395 | /* MC_MAX_DOD read functions */ | |
854d3349 | 396 | static inline int numdimms(u32 dimms) |
a0c36a1f | 397 | { |
854d3349 | 398 | return (dimms & 0x3) + 1; |
a0c36a1f MCC |
399 | } |
400 | ||
854d3349 | 401 | static inline int numrank(u32 rank) |
a0c36a1f MCC |
402 | { |
403 | static int ranks[4] = { 1, 2, 4, -EINVAL }; | |
404 | ||
854d3349 | 405 | return ranks[rank & 0x3]; |
a0c36a1f MCC |
406 | } |
407 | ||
854d3349 | 408 | static inline int numbank(u32 bank) |
a0c36a1f MCC |
409 | { |
410 | static int banks[4] = { 4, 8, 16, -EINVAL }; | |
411 | ||
854d3349 | 412 | return banks[bank & 0x3]; |
a0c36a1f MCC |
413 | } |
414 | ||
854d3349 | 415 | static inline int numrow(u32 row) |
a0c36a1f MCC |
416 | { |
417 | static int rows[8] = { | |
418 | 1 << 12, 1 << 13, 1 << 14, 1 << 15, | |
419 | 1 << 16, -EINVAL, -EINVAL, -EINVAL, | |
420 | }; | |
421 | ||
854d3349 | 422 | return rows[row & 0x7]; |
a0c36a1f MCC |
423 | } |
424 | ||
854d3349 | 425 | static inline int numcol(u32 col) |
a0c36a1f MCC |
426 | { |
427 | static int cols[8] = { | |
428 | 1 << 10, 1 << 11, 1 << 12, -EINVAL, | |
429 | }; | |
854d3349 | 430 | return cols[col & 0x3]; |
a0c36a1f MCC |
431 | } |
432 | ||
f4742949 | 433 | static struct i7core_dev *get_i7core_dev(u8 socket) |
66607706 MCC |
434 | { |
435 | struct i7core_dev *i7core_dev; | |
436 | ||
437 | list_for_each_entry(i7core_dev, &i7core_edac_list, list) { | |
438 | if (i7core_dev->socket == socket) | |
439 | return i7core_dev; | |
440 | } | |
441 | ||
442 | return NULL; | |
443 | } | |
444 | ||
a0c36a1f MCC |
445 | /**************************************************************************** |
446 | Memory check routines | |
447 | ****************************************************************************/ | |
67166af4 MCC |
448 | static struct pci_dev *get_pdev_slot_func(u8 socket, unsigned slot, |
449 | unsigned func) | |
ef708b53 | 450 | { |
66607706 | 451 | struct i7core_dev *i7core_dev = get_i7core_dev(socket); |
ef708b53 | 452 | int i; |
ef708b53 | 453 | |
66607706 MCC |
454 | if (!i7core_dev) |
455 | return NULL; | |
456 | ||
de06eeef | 457 | for (i = 0; i < i7core_dev->n_devs; i++) { |
66607706 | 458 | if (!i7core_dev->pdev[i]) |
ef708b53 MCC |
459 | continue; |
460 | ||
66607706 MCC |
461 | if (PCI_SLOT(i7core_dev->pdev[i]->devfn) == slot && |
462 | PCI_FUNC(i7core_dev->pdev[i]->devfn) == func) { | |
463 | return i7core_dev->pdev[i]; | |
ef708b53 MCC |
464 | } |
465 | } | |
466 | ||
eb94fc40 MCC |
467 | return NULL; |
468 | } | |
469 | ||
ec6df24c MCC |
470 | /** |
471 | * i7core_get_active_channels() - gets the number of channels and csrows | |
472 | * @socket: Quick Path Interconnect socket | |
473 | * @channels: Number of channels that will be returned | |
474 | * @csrows: Number of csrows found | |
475 | * | |
476 | * Since EDAC core needs to know in advance the number of available channels | |
477 | * and csrows, in order to allocate memory for csrows/channels, it is needed | |
478 | * to run two similar steps. At the first step, implemented on this function, | |
479 | * it checks the number of csrows/channels present at one socket. | |
480 | * this is used in order to properly allocate the size of mci components. | |
481 | * | |
482 | * It should be noticed that none of the current available datasheets explain | |
483 | * or even mention how csrows are seen by the memory controller. So, we need | |
484 | * to add a fake description for csrows. | |
485 | * So, this driver is attributing one DIMM memory for one csrow. | |
486 | */ | |
67166af4 MCC |
487 | static int i7core_get_active_channels(u8 socket, unsigned *channels, |
488 | unsigned *csrows) | |
eb94fc40 MCC |
489 | { |
490 | struct pci_dev *pdev = NULL; | |
491 | int i, j; | |
492 | u32 status, control; | |
493 | ||
494 | *channels = 0; | |
495 | *csrows = 0; | |
496 | ||
67166af4 | 497 | pdev = get_pdev_slot_func(socket, 3, 0); |
b7c76151 | 498 | if (!pdev) { |
67166af4 MCC |
499 | i7core_printk(KERN_ERR, "Couldn't find socket %d fn 3.0!!!\n", |
500 | socket); | |
ef708b53 | 501 | return -ENODEV; |
b7c76151 | 502 | } |
ef708b53 MCC |
503 | |
504 | /* Device 3 function 0 reads */ | |
505 | pci_read_config_dword(pdev, MC_STATUS, &status); | |
506 | pci_read_config_dword(pdev, MC_CONTROL, &control); | |
507 | ||
508 | for (i = 0; i < NUM_CHANS; i++) { | |
eb94fc40 | 509 | u32 dimm_dod[3]; |
ef708b53 MCC |
510 | /* Check if the channel is active */ |
511 | if (!(control & (1 << (8 + i)))) | |
512 | continue; | |
513 | ||
514 | /* Check if the channel is disabled */ | |
41fcb7fe | 515 | if (status & (1 << i)) |
ef708b53 | 516 | continue; |
ef708b53 | 517 | |
67166af4 | 518 | pdev = get_pdev_slot_func(socket, i + 4, 1); |
eb94fc40 | 519 | if (!pdev) { |
67166af4 MCC |
520 | i7core_printk(KERN_ERR, "Couldn't find socket %d " |
521 | "fn %d.%d!!!\n", | |
522 | socket, i + 4, 1); | |
eb94fc40 MCC |
523 | return -ENODEV; |
524 | } | |
525 | /* Devices 4-6 function 1 */ | |
526 | pci_read_config_dword(pdev, | |
527 | MC_DOD_CH_DIMM0, &dimm_dod[0]); | |
528 | pci_read_config_dword(pdev, | |
529 | MC_DOD_CH_DIMM1, &dimm_dod[1]); | |
530 | pci_read_config_dword(pdev, | |
531 | MC_DOD_CH_DIMM2, &dimm_dod[2]); | |
532 | ||
ef708b53 | 533 | (*channels)++; |
eb94fc40 MCC |
534 | |
535 | for (j = 0; j < 3; j++) { | |
536 | if (!DIMM_PRESENT(dimm_dod[j])) | |
537 | continue; | |
538 | (*csrows)++; | |
539 | } | |
ef708b53 MCC |
540 | } |
541 | ||
c77720b9 | 542 | debugf0("Number of active channels on socket %d: %d\n", |
67166af4 | 543 | socket, *channels); |
1c6fed80 | 544 | |
ef708b53 MCC |
545 | return 0; |
546 | } | |
547 | ||
f4742949 | 548 | static int get_dimm_config(struct mem_ctl_info *mci, int *csrow) |
a0c36a1f MCC |
549 | { |
550 | struct i7core_pvt *pvt = mci->pvt_info; | |
1c6fed80 | 551 | struct csrow_info *csr; |
854d3349 | 552 | struct pci_dev *pdev; |
ba6c5c62 | 553 | int i, j; |
5566cb7c | 554 | unsigned long last_page = 0; |
1c6fed80 | 555 | enum edac_type mode; |
854d3349 | 556 | enum mem_type mtype; |
a0c36a1f | 557 | |
854d3349 | 558 | /* Get data from the MC register, function 0 */ |
f4742949 | 559 | pdev = pvt->pci_mcr[0]; |
7dd6953c | 560 | if (!pdev) |
8f331907 MCC |
561 | return -ENODEV; |
562 | ||
f122a892 | 563 | /* Device 3 function 0 reads */ |
7dd6953c MCC |
564 | pci_read_config_dword(pdev, MC_CONTROL, &pvt->info.mc_control); |
565 | pci_read_config_dword(pdev, MC_STATUS, &pvt->info.mc_status); | |
566 | pci_read_config_dword(pdev, MC_MAX_DOD, &pvt->info.max_dod); | |
567 | pci_read_config_dword(pdev, MC_CHANNEL_MAPPER, &pvt->info.ch_map); | |
f122a892 | 568 | |
17cb7b0c | 569 | debugf0("QPI %d control=0x%08x status=0x%08x dod=0x%08x map=0x%08x\n", |
4af91889 | 570 | pvt->i7core_dev->socket, pvt->info.mc_control, pvt->info.mc_status, |
f122a892 | 571 | pvt->info.max_dod, pvt->info.ch_map); |
a0c36a1f | 572 | |
1c6fed80 | 573 | if (ECC_ENABLED(pvt)) { |
41fcb7fe | 574 | debugf0("ECC enabled with x%d SDCC\n", ECCx8(pvt) ? 8 : 4); |
1c6fed80 MCC |
575 | if (ECCx8(pvt)) |
576 | mode = EDAC_S8ECD8ED; | |
577 | else | |
578 | mode = EDAC_S4ECD4ED; | |
579 | } else { | |
a0c36a1f | 580 | debugf0("ECC disabled\n"); |
1c6fed80 MCC |
581 | mode = EDAC_NONE; |
582 | } | |
a0c36a1f MCC |
583 | |
584 | /* FIXME: need to handle the error codes */ | |
17cb7b0c MCC |
585 | debugf0("DOD Max limits: DIMMS: %d, %d-ranked, %d-banked " |
586 | "x%x x 0x%x\n", | |
854d3349 MCC |
587 | numdimms(pvt->info.max_dod), |
588 | numrank(pvt->info.max_dod >> 2), | |
276b824c | 589 | numbank(pvt->info.max_dod >> 4), |
854d3349 MCC |
590 | numrow(pvt->info.max_dod >> 6), |
591 | numcol(pvt->info.max_dod >> 9)); | |
a0c36a1f | 592 | |
0b2b7b7e | 593 | for (i = 0; i < NUM_CHANS; i++) { |
854d3349 | 594 | u32 data, dimm_dod[3], value[8]; |
0b2b7b7e | 595 | |
52a2e4fc MCC |
596 | if (!pvt->pci_ch[i][0]) |
597 | continue; | |
598 | ||
0b2b7b7e MCC |
599 | if (!CH_ACTIVE(pvt, i)) { |
600 | debugf0("Channel %i is not active\n", i); | |
601 | continue; | |
602 | } | |
603 | if (CH_DISABLED(pvt, i)) { | |
604 | debugf0("Channel %i is disabled\n", i); | |
605 | continue; | |
606 | } | |
607 | ||
f122a892 | 608 | /* Devices 4-6 function 0 */ |
f4742949 | 609 | pci_read_config_dword(pvt->pci_ch[i][0], |
0b2b7b7e MCC |
610 | MC_CHANNEL_DIMM_INIT_PARAMS, &data); |
611 | ||
f4742949 | 612 | pvt->channel[i].ranks = (data & QUAD_RANK_PRESENT) ? |
67166af4 | 613 | 4 : 2; |
0b2b7b7e | 614 | |
854d3349 MCC |
615 | if (data & REGISTERED_DIMM) |
616 | mtype = MEM_RDDR3; | |
14d2c083 | 617 | else |
854d3349 MCC |
618 | mtype = MEM_DDR3; |
619 | #if 0 | |
0b2b7b7e MCC |
620 | if (data & THREE_DIMMS_PRESENT) |
621 | pvt->channel[i].dimms = 3; | |
622 | else if (data & SINGLE_QUAD_RANK_PRESENT) | |
623 | pvt->channel[i].dimms = 1; | |
624 | else | |
625 | pvt->channel[i].dimms = 2; | |
854d3349 MCC |
626 | #endif |
627 | ||
628 | /* Devices 4-6 function 1 */ | |
f4742949 | 629 | pci_read_config_dword(pvt->pci_ch[i][1], |
854d3349 | 630 | MC_DOD_CH_DIMM0, &dimm_dod[0]); |
f4742949 | 631 | pci_read_config_dword(pvt->pci_ch[i][1], |
854d3349 | 632 | MC_DOD_CH_DIMM1, &dimm_dod[1]); |
f4742949 | 633 | pci_read_config_dword(pvt->pci_ch[i][1], |
854d3349 | 634 | MC_DOD_CH_DIMM2, &dimm_dod[2]); |
0b2b7b7e | 635 | |
1c6fed80 | 636 | debugf0("Ch%d phy rd%d, wr%d (0x%08x): " |
854d3349 | 637 | "%d ranks, %cDIMMs\n", |
1c6fed80 MCC |
638 | i, |
639 | RDLCH(pvt->info.ch_map, i), WRLCH(pvt->info.ch_map, i), | |
640 | data, | |
f4742949 | 641 | pvt->channel[i].ranks, |
41fcb7fe | 642 | (data & REGISTERED_DIMM) ? 'R' : 'U'); |
854d3349 MCC |
643 | |
644 | for (j = 0; j < 3; j++) { | |
645 | u32 banks, ranks, rows, cols; | |
5566cb7c | 646 | u32 size, npages; |
854d3349 MCC |
647 | |
648 | if (!DIMM_PRESENT(dimm_dod[j])) | |
649 | continue; | |
650 | ||
651 | banks = numbank(MC_DOD_NUMBANK(dimm_dod[j])); | |
652 | ranks = numrank(MC_DOD_NUMRANK(dimm_dod[j])); | |
653 | rows = numrow(MC_DOD_NUMROW(dimm_dod[j])); | |
654 | cols = numcol(MC_DOD_NUMCOL(dimm_dod[j])); | |
655 | ||
5566cb7c MCC |
656 | /* DDR3 has 8 I/O banks */ |
657 | size = (rows * cols * banks * ranks) >> (20 - 3); | |
658 | ||
f4742949 | 659 | pvt->channel[i].dimms++; |
854d3349 | 660 | |
17cb7b0c MCC |
661 | debugf0("\tdimm %d %d Mb offset: %x, " |
662 | "bank: %d, rank: %d, row: %#x, col: %#x\n", | |
663 | j, size, | |
854d3349 MCC |
664 | RANKOFFSET(dimm_dod[j]), |
665 | banks, ranks, rows, cols); | |
666 | ||
eb94fc40 MCC |
667 | #if PAGE_SHIFT > 20 |
668 | npages = size >> (PAGE_SHIFT - 20); | |
669 | #else | |
670 | npages = size << (20 - PAGE_SHIFT); | |
671 | #endif | |
5566cb7c | 672 | |
ba6c5c62 | 673 | csr = &mci->csrows[*csrow]; |
5566cb7c MCC |
674 | csr->first_page = last_page + 1; |
675 | last_page += npages; | |
676 | csr->last_page = last_page; | |
677 | csr->nr_pages = npages; | |
678 | ||
854d3349 | 679 | csr->page_mask = 0; |
eb94fc40 | 680 | csr->grain = 8; |
ba6c5c62 | 681 | csr->csrow_idx = *csrow; |
eb94fc40 MCC |
682 | csr->nr_channels = 1; |
683 | ||
684 | csr->channels[0].chan_idx = i; | |
685 | csr->channels[0].ce_count = 0; | |
854d3349 | 686 | |
f4742949 | 687 | pvt->csrow_map[i][j] = *csrow; |
b4e8f0b6 | 688 | |
854d3349 MCC |
689 | switch (banks) { |
690 | case 4: | |
691 | csr->dtype = DEV_X4; | |
692 | break; | |
693 | case 8: | |
694 | csr->dtype = DEV_X8; | |
695 | break; | |
696 | case 16: | |
697 | csr->dtype = DEV_X16; | |
698 | break; | |
699 | default: | |
700 | csr->dtype = DEV_UNKNOWN; | |
701 | } | |
702 | ||
703 | csr->edac_mode = mode; | |
704 | csr->mtype = mtype; | |
705 | ||
ba6c5c62 | 706 | (*csrow)++; |
854d3349 | 707 | } |
1c6fed80 | 708 | |
854d3349 MCC |
709 | pci_read_config_dword(pdev, MC_SAG_CH_0, &value[0]); |
710 | pci_read_config_dword(pdev, MC_SAG_CH_1, &value[1]); | |
711 | pci_read_config_dword(pdev, MC_SAG_CH_2, &value[2]); | |
712 | pci_read_config_dword(pdev, MC_SAG_CH_3, &value[3]); | |
713 | pci_read_config_dword(pdev, MC_SAG_CH_4, &value[4]); | |
714 | pci_read_config_dword(pdev, MC_SAG_CH_5, &value[5]); | |
715 | pci_read_config_dword(pdev, MC_SAG_CH_6, &value[6]); | |
716 | pci_read_config_dword(pdev, MC_SAG_CH_7, &value[7]); | |
17cb7b0c | 717 | debugf1("\t[%i] DIVBY3\tREMOVED\tOFFSET\n", i); |
854d3349 | 718 | for (j = 0; j < 8; j++) |
17cb7b0c | 719 | debugf1("\t\t%#x\t%#x\t%#x\n", |
854d3349 MCC |
720 | (value[j] >> 27) & 0x1, |
721 | (value[j] >> 24) & 0x7, | |
722 | (value[j] && ((1 << 24) - 1))); | |
0b2b7b7e MCC |
723 | } |
724 | ||
a0c36a1f MCC |
725 | return 0; |
726 | } | |
727 | ||
194a40fe MCC |
728 | /**************************************************************************** |
729 | Error insertion routines | |
730 | ****************************************************************************/ | |
731 | ||
732 | /* The i7core has independent error injection features per channel. | |
733 | However, to have a simpler code, we don't allow enabling error injection | |
734 | on more than one channel. | |
735 | Also, since a change at an inject parameter will be applied only at enable, | |
736 | we're disabling error injection on all write calls to the sysfs nodes that | |
737 | controls the error code injection. | |
738 | */ | |
8f331907 | 739 | static int disable_inject(struct mem_ctl_info *mci) |
194a40fe MCC |
740 | { |
741 | struct i7core_pvt *pvt = mci->pvt_info; | |
742 | ||
743 | pvt->inject.enable = 0; | |
744 | ||
f4742949 | 745 | if (!pvt->pci_ch[pvt->inject.channel][0]) |
8f331907 MCC |
746 | return -ENODEV; |
747 | ||
f4742949 | 748 | pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0], |
4157d9f5 | 749 | MC_CHANNEL_ERROR_INJECT, 0); |
8f331907 MCC |
750 | |
751 | return 0; | |
194a40fe MCC |
752 | } |
753 | ||
754 | /* | |
755 | * i7core inject inject.section | |
756 | * | |
757 | * accept and store error injection inject.section value | |
758 | * bit 0 - refers to the lower 32-byte half cacheline | |
759 | * bit 1 - refers to the upper 32-byte half cacheline | |
760 | */ | |
761 | static ssize_t i7core_inject_section_store(struct mem_ctl_info *mci, | |
762 | const char *data, size_t count) | |
763 | { | |
764 | struct i7core_pvt *pvt = mci->pvt_info; | |
765 | unsigned long value; | |
766 | int rc; | |
767 | ||
768 | if (pvt->inject.enable) | |
41fcb7fe | 769 | disable_inject(mci); |
194a40fe MCC |
770 | |
771 | rc = strict_strtoul(data, 10, &value); | |
772 | if ((rc < 0) || (value > 3)) | |
2068def5 | 773 | return -EIO; |
194a40fe MCC |
774 | |
775 | pvt->inject.section = (u32) value; | |
776 | return count; | |
777 | } | |
778 | ||
779 | static ssize_t i7core_inject_section_show(struct mem_ctl_info *mci, | |
780 | char *data) | |
781 | { | |
782 | struct i7core_pvt *pvt = mci->pvt_info; | |
783 | return sprintf(data, "0x%08x\n", pvt->inject.section); | |
784 | } | |
785 | ||
786 | /* | |
787 | * i7core inject.type | |
788 | * | |
789 | * accept and store error injection inject.section value | |
790 | * bit 0 - repeat enable - Enable error repetition | |
791 | * bit 1 - inject ECC error | |
792 | * bit 2 - inject parity error | |
793 | */ | |
794 | static ssize_t i7core_inject_type_store(struct mem_ctl_info *mci, | |
795 | const char *data, size_t count) | |
796 | { | |
797 | struct i7core_pvt *pvt = mci->pvt_info; | |
798 | unsigned long value; | |
799 | int rc; | |
800 | ||
801 | if (pvt->inject.enable) | |
41fcb7fe | 802 | disable_inject(mci); |
194a40fe MCC |
803 | |
804 | rc = strict_strtoul(data, 10, &value); | |
805 | if ((rc < 0) || (value > 7)) | |
2068def5 | 806 | return -EIO; |
194a40fe MCC |
807 | |
808 | pvt->inject.type = (u32) value; | |
809 | return count; | |
810 | } | |
811 | ||
812 | static ssize_t i7core_inject_type_show(struct mem_ctl_info *mci, | |
813 | char *data) | |
814 | { | |
815 | struct i7core_pvt *pvt = mci->pvt_info; | |
816 | return sprintf(data, "0x%08x\n", pvt->inject.type); | |
817 | } | |
818 | ||
819 | /* | |
820 | * i7core_inject_inject.eccmask_store | |
821 | * | |
822 | * The type of error (UE/CE) will depend on the inject.eccmask value: | |
823 | * Any bits set to a 1 will flip the corresponding ECC bit | |
824 | * Correctable errors can be injected by flipping 1 bit or the bits within | |
825 | * a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or | |
826 | * 23:16 and 31:24). Flipping bits in two symbol pairs will cause an | |
827 | * uncorrectable error to be injected. | |
828 | */ | |
829 | static ssize_t i7core_inject_eccmask_store(struct mem_ctl_info *mci, | |
830 | const char *data, size_t count) | |
831 | { | |
832 | struct i7core_pvt *pvt = mci->pvt_info; | |
833 | unsigned long value; | |
834 | int rc; | |
835 | ||
836 | if (pvt->inject.enable) | |
41fcb7fe | 837 | disable_inject(mci); |
194a40fe MCC |
838 | |
839 | rc = strict_strtoul(data, 10, &value); | |
840 | if (rc < 0) | |
2068def5 | 841 | return -EIO; |
194a40fe MCC |
842 | |
843 | pvt->inject.eccmask = (u32) value; | |
844 | return count; | |
845 | } | |
846 | ||
847 | static ssize_t i7core_inject_eccmask_show(struct mem_ctl_info *mci, | |
848 | char *data) | |
849 | { | |
850 | struct i7core_pvt *pvt = mci->pvt_info; | |
851 | return sprintf(data, "0x%08x\n", pvt->inject.eccmask); | |
852 | } | |
853 | ||
854 | /* | |
855 | * i7core_addrmatch | |
856 | * | |
857 | * The type of error (UE/CE) will depend on the inject.eccmask value: | |
858 | * Any bits set to a 1 will flip the corresponding ECC bit | |
859 | * Correctable errors can be injected by flipping 1 bit or the bits within | |
860 | * a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or | |
861 | * 23:16 and 31:24). Flipping bits in two symbol pairs will cause an | |
862 | * uncorrectable error to be injected. | |
863 | */ | |
194a40fe | 864 | |
a5538e53 MCC |
865 | #define DECLARE_ADDR_MATCH(param, limit) \ |
866 | static ssize_t i7core_inject_store_##param( \ | |
867 | struct mem_ctl_info *mci, \ | |
868 | const char *data, size_t count) \ | |
869 | { \ | |
cc301b3a | 870 | struct i7core_pvt *pvt; \ |
a5538e53 MCC |
871 | long value; \ |
872 | int rc; \ | |
873 | \ | |
cc301b3a MCC |
874 | debugf1("%s()\n", __func__); \ |
875 | pvt = mci->pvt_info; \ | |
876 | \ | |
a5538e53 MCC |
877 | if (pvt->inject.enable) \ |
878 | disable_inject(mci); \ | |
879 | \ | |
4f87fad1 | 880 | if (!strcasecmp(data, "any") || !strcasecmp(data, "any\n"))\ |
a5538e53 MCC |
881 | value = -1; \ |
882 | else { \ | |
883 | rc = strict_strtoul(data, 10, &value); \ | |
884 | if ((rc < 0) || (value >= limit)) \ | |
885 | return -EIO; \ | |
886 | } \ | |
887 | \ | |
888 | pvt->inject.param = value; \ | |
889 | \ | |
890 | return count; \ | |
891 | } \ | |
892 | \ | |
893 | static ssize_t i7core_inject_show_##param( \ | |
894 | struct mem_ctl_info *mci, \ | |
895 | char *data) \ | |
896 | { \ | |
cc301b3a MCC |
897 | struct i7core_pvt *pvt; \ |
898 | \ | |
899 | pvt = mci->pvt_info; \ | |
900 | debugf1("%s() pvt=%p\n", __func__, pvt); \ | |
a5538e53 MCC |
901 | if (pvt->inject.param < 0) \ |
902 | return sprintf(data, "any\n"); \ | |
903 | else \ | |
904 | return sprintf(data, "%d\n", pvt->inject.param);\ | |
194a40fe MCC |
905 | } |
906 | ||
a5538e53 MCC |
907 | #define ATTR_ADDR_MATCH(param) \ |
908 | { \ | |
909 | .attr = { \ | |
910 | .name = #param, \ | |
911 | .mode = (S_IRUGO | S_IWUSR) \ | |
912 | }, \ | |
913 | .show = i7core_inject_show_##param, \ | |
914 | .store = i7core_inject_store_##param, \ | |
915 | } | |
194a40fe | 916 | |
a5538e53 MCC |
917 | DECLARE_ADDR_MATCH(channel, 3); |
918 | DECLARE_ADDR_MATCH(dimm, 3); | |
919 | DECLARE_ADDR_MATCH(rank, 4); | |
920 | DECLARE_ADDR_MATCH(bank, 32); | |
921 | DECLARE_ADDR_MATCH(page, 0x10000); | |
922 | DECLARE_ADDR_MATCH(col, 0x4000); | |
194a40fe | 923 | |
276b824c MCC |
924 | static int write_and_test(struct pci_dev *dev, int where, u32 val) |
925 | { | |
926 | u32 read; | |
927 | int count; | |
928 | ||
4157d9f5 MCC |
929 | debugf0("setting pci %02x:%02x.%x reg=%02x value=%08x\n", |
930 | dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), | |
931 | where, val); | |
932 | ||
276b824c MCC |
933 | for (count = 0; count < 10; count++) { |
934 | if (count) | |
b990538a | 935 | msleep(100); |
276b824c MCC |
936 | pci_write_config_dword(dev, where, val); |
937 | pci_read_config_dword(dev, where, &read); | |
938 | ||
939 | if (read == val) | |
940 | return 0; | |
941 | } | |
942 | ||
4157d9f5 MCC |
943 | i7core_printk(KERN_ERR, "Error during set pci %02x:%02x.%x reg=%02x " |
944 | "write=%08x. Read=%08x\n", | |
945 | dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), | |
946 | where, val, read); | |
276b824c MCC |
947 | |
948 | return -EINVAL; | |
949 | } | |
950 | ||
194a40fe MCC |
951 | /* |
952 | * This routine prepares the Memory Controller for error injection. | |
953 | * The error will be injected when some process tries to write to the | |
954 | * memory that matches the given criteria. | |
955 | * The criteria can be set in terms of a mask where dimm, rank, bank, page | |
956 | * and col can be specified. | |
957 | * A -1 value for any of the mask items will make the MCU to ignore | |
958 | * that matching criteria for error injection. | |
959 | * | |
960 | * It should be noticed that the error will only happen after a write operation | |
961 | * on a memory that matches the condition. if REPEAT_EN is not enabled at | |
962 | * inject mask, then it will produce just one error. Otherwise, it will repeat | |
963 | * until the injectmask would be cleaned. | |
964 | * | |
965 | * FIXME: This routine assumes that MAXNUMDIMMS value of MC_MAX_DOD | |
966 | * is reliable enough to check if the MC is using the | |
967 | * three channels. However, this is not clear at the datasheet. | |
968 | */ | |
969 | static ssize_t i7core_inject_enable_store(struct mem_ctl_info *mci, | |
970 | const char *data, size_t count) | |
971 | { | |
972 | struct i7core_pvt *pvt = mci->pvt_info; | |
973 | u32 injectmask; | |
974 | u64 mask = 0; | |
975 | int rc; | |
976 | long enable; | |
977 | ||
f4742949 | 978 | if (!pvt->pci_ch[pvt->inject.channel][0]) |
8f331907 MCC |
979 | return 0; |
980 | ||
194a40fe MCC |
981 | rc = strict_strtoul(data, 10, &enable); |
982 | if ((rc < 0)) | |
983 | return 0; | |
984 | ||
985 | if (enable) { | |
986 | pvt->inject.enable = 1; | |
987 | } else { | |
988 | disable_inject(mci); | |
989 | return count; | |
990 | } | |
991 | ||
992 | /* Sets pvt->inject.dimm mask */ | |
993 | if (pvt->inject.dimm < 0) | |
486dd09f | 994 | mask |= 1LL << 41; |
194a40fe | 995 | else { |
f4742949 | 996 | if (pvt->channel[pvt->inject.channel].dimms > 2) |
486dd09f | 997 | mask |= (pvt->inject.dimm & 0x3LL) << 35; |
194a40fe | 998 | else |
486dd09f | 999 | mask |= (pvt->inject.dimm & 0x1LL) << 36; |
194a40fe MCC |
1000 | } |
1001 | ||
1002 | /* Sets pvt->inject.rank mask */ | |
1003 | if (pvt->inject.rank < 0) | |
486dd09f | 1004 | mask |= 1LL << 40; |
194a40fe | 1005 | else { |
f4742949 | 1006 | if (pvt->channel[pvt->inject.channel].dimms > 2) |
486dd09f | 1007 | mask |= (pvt->inject.rank & 0x1LL) << 34; |
194a40fe | 1008 | else |
486dd09f | 1009 | mask |= (pvt->inject.rank & 0x3LL) << 34; |
194a40fe MCC |
1010 | } |
1011 | ||
1012 | /* Sets pvt->inject.bank mask */ | |
1013 | if (pvt->inject.bank < 0) | |
486dd09f | 1014 | mask |= 1LL << 39; |
194a40fe | 1015 | else |
486dd09f | 1016 | mask |= (pvt->inject.bank & 0x15LL) << 30; |
194a40fe MCC |
1017 | |
1018 | /* Sets pvt->inject.page mask */ | |
1019 | if (pvt->inject.page < 0) | |
486dd09f | 1020 | mask |= 1LL << 38; |
194a40fe | 1021 | else |
486dd09f | 1022 | mask |= (pvt->inject.page & 0xffff) << 14; |
194a40fe MCC |
1023 | |
1024 | /* Sets pvt->inject.column mask */ | |
1025 | if (pvt->inject.col < 0) | |
486dd09f | 1026 | mask |= 1LL << 37; |
194a40fe | 1027 | else |
486dd09f | 1028 | mask |= (pvt->inject.col & 0x3fff); |
194a40fe | 1029 | |
276b824c MCC |
1030 | /* |
1031 | * bit 0: REPEAT_EN | |
1032 | * bits 1-2: MASK_HALF_CACHELINE | |
1033 | * bit 3: INJECT_ECC | |
1034 | * bit 4: INJECT_ADDR_PARITY | |
1035 | */ | |
1036 | ||
1037 | injectmask = (pvt->inject.type & 1) | | |
1038 | (pvt->inject.section & 0x3) << 1 | | |
1039 | (pvt->inject.type & 0x6) << (3 - 1); | |
1040 | ||
1041 | /* Unlock writes to registers - this register is write only */ | |
f4742949 | 1042 | pci_write_config_dword(pvt->pci_noncore, |
67166af4 | 1043 | MC_CFG_CONTROL, 0x2); |
e9bd2e73 | 1044 | |
f4742949 | 1045 | write_and_test(pvt->pci_ch[pvt->inject.channel][0], |
194a40fe | 1046 | MC_CHANNEL_ADDR_MATCH, mask); |
f4742949 | 1047 | write_and_test(pvt->pci_ch[pvt->inject.channel][0], |
7b029d03 | 1048 | MC_CHANNEL_ADDR_MATCH + 4, mask >> 32L); |
7b029d03 | 1049 | |
f4742949 | 1050 | write_and_test(pvt->pci_ch[pvt->inject.channel][0], |
194a40fe MCC |
1051 | MC_CHANNEL_ERROR_MASK, pvt->inject.eccmask); |
1052 | ||
f4742949 | 1053 | write_and_test(pvt->pci_ch[pvt->inject.channel][0], |
4157d9f5 | 1054 | MC_CHANNEL_ERROR_INJECT, injectmask); |
276b824c | 1055 | |
194a40fe | 1056 | /* |
276b824c MCC |
1057 | * This is something undocumented, based on my tests |
1058 | * Without writing 8 to this register, errors aren't injected. Not sure | |
1059 | * why. | |
194a40fe | 1060 | */ |
f4742949 | 1061 | pci_write_config_dword(pvt->pci_noncore, |
276b824c | 1062 | MC_CFG_CONTROL, 8); |
194a40fe | 1063 | |
41fcb7fe MCC |
1064 | debugf0("Error inject addr match 0x%016llx, ecc 0x%08x," |
1065 | " inject 0x%08x\n", | |
194a40fe MCC |
1066 | mask, pvt->inject.eccmask, injectmask); |
1067 | ||
7b029d03 | 1068 | |
194a40fe MCC |
1069 | return count; |
1070 | } | |
1071 | ||
1072 | static ssize_t i7core_inject_enable_show(struct mem_ctl_info *mci, | |
1073 | char *data) | |
1074 | { | |
1075 | struct i7core_pvt *pvt = mci->pvt_info; | |
7b029d03 MCC |
1076 | u32 injectmask; |
1077 | ||
52a2e4fc MCC |
1078 | if (!pvt->pci_ch[pvt->inject.channel][0]) |
1079 | return 0; | |
1080 | ||
f4742949 | 1081 | pci_read_config_dword(pvt->pci_ch[pvt->inject.channel][0], |
4157d9f5 | 1082 | MC_CHANNEL_ERROR_INJECT, &injectmask); |
7b029d03 MCC |
1083 | |
1084 | debugf0("Inject error read: 0x%018x\n", injectmask); | |
1085 | ||
1086 | if (injectmask & 0x0c) | |
1087 | pvt->inject.enable = 1; | |
1088 | ||
194a40fe MCC |
1089 | return sprintf(data, "%d\n", pvt->inject.enable); |
1090 | } | |
1091 | ||
f338d736 MCC |
1092 | #define DECLARE_COUNTER(param) \ |
1093 | static ssize_t i7core_show_counter_##param( \ | |
1094 | struct mem_ctl_info *mci, \ | |
1095 | char *data) \ | |
1096 | { \ | |
1097 | struct i7core_pvt *pvt = mci->pvt_info; \ | |
1098 | \ | |
1099 | debugf1("%s() \n", __func__); \ | |
1100 | if (!pvt->ce_count_available || (pvt->is_registered)) \ | |
1101 | return sprintf(data, "data unavailable\n"); \ | |
1102 | return sprintf(data, "%lu\n", \ | |
1103 | pvt->udimm_ce_count[param]); \ | |
1104 | } | |
442305b1 | 1105 | |
f338d736 MCC |
1106 | #define ATTR_COUNTER(param) \ |
1107 | { \ | |
1108 | .attr = { \ | |
1109 | .name = __stringify(udimm##param), \ | |
1110 | .mode = (S_IRUGO | S_IWUSR) \ | |
1111 | }, \ | |
1112 | .show = i7core_show_counter_##param \ | |
d88b8507 | 1113 | } |
442305b1 | 1114 | |
f338d736 MCC |
1115 | DECLARE_COUNTER(0); |
1116 | DECLARE_COUNTER(1); | |
1117 | DECLARE_COUNTER(2); | |
442305b1 | 1118 | |
194a40fe MCC |
1119 | /* |
1120 | * Sysfs struct | |
1121 | */ | |
a5538e53 MCC |
1122 | |
1123 | ||
1124 | static struct mcidev_sysfs_attribute i7core_addrmatch_attrs[] = { | |
1125 | ATTR_ADDR_MATCH(channel), | |
1126 | ATTR_ADDR_MATCH(dimm), | |
1127 | ATTR_ADDR_MATCH(rank), | |
1128 | ATTR_ADDR_MATCH(bank), | |
1129 | ATTR_ADDR_MATCH(page), | |
1130 | ATTR_ADDR_MATCH(col), | |
1131 | { .attr = { .name = NULL } } | |
1132 | }; | |
1133 | ||
a5538e53 MCC |
1134 | static struct mcidev_sysfs_group i7core_inject_addrmatch = { |
1135 | .name = "inject_addrmatch", | |
1136 | .mcidev_attr = i7core_addrmatch_attrs, | |
1137 | }; | |
1138 | ||
f338d736 MCC |
1139 | static struct mcidev_sysfs_attribute i7core_udimm_counters_attrs[] = { |
1140 | ATTR_COUNTER(0), | |
1141 | ATTR_COUNTER(1), | |
1142 | ATTR_COUNTER(2), | |
1143 | }; | |
1144 | ||
1145 | static struct mcidev_sysfs_group i7core_udimm_counters = { | |
1146 | .name = "all_channel_counts", | |
1147 | .mcidev_attr = i7core_udimm_counters_attrs, | |
1148 | }; | |
1149 | ||
a5538e53 | 1150 | static struct mcidev_sysfs_attribute i7core_sysfs_attrs[] = { |
194a40fe MCC |
1151 | { |
1152 | .attr = { | |
1153 | .name = "inject_section", | |
1154 | .mode = (S_IRUGO | S_IWUSR) | |
1155 | }, | |
1156 | .show = i7core_inject_section_show, | |
1157 | .store = i7core_inject_section_store, | |
1158 | }, { | |
1159 | .attr = { | |
1160 | .name = "inject_type", | |
1161 | .mode = (S_IRUGO | S_IWUSR) | |
1162 | }, | |
1163 | .show = i7core_inject_type_show, | |
1164 | .store = i7core_inject_type_store, | |
1165 | }, { | |
1166 | .attr = { | |
1167 | .name = "inject_eccmask", | |
1168 | .mode = (S_IRUGO | S_IWUSR) | |
1169 | }, | |
1170 | .show = i7core_inject_eccmask_show, | |
1171 | .store = i7core_inject_eccmask_store, | |
1172 | }, { | |
a5538e53 | 1173 | .grp = &i7core_inject_addrmatch, |
194a40fe MCC |
1174 | }, { |
1175 | .attr = { | |
1176 | .name = "inject_enable", | |
1177 | .mode = (S_IRUGO | S_IWUSR) | |
1178 | }, | |
1179 | .show = i7core_inject_enable_show, | |
1180 | .store = i7core_inject_enable_store, | |
1181 | }, | |
f338d736 | 1182 | { .attr = { .name = NULL } }, /* Reserved for udimm counters */ |
42538680 | 1183 | { .attr = { .name = NULL } } |
194a40fe MCC |
1184 | }; |
1185 | ||
a0c36a1f MCC |
1186 | /**************************************************************************** |
1187 | Device initialization routines: put/get, init/exit | |
1188 | ****************************************************************************/ | |
1189 | ||
1190 | /* | |
1191 | * i7core_put_devices 'put' all the devices that we have | |
1192 | * reserved via 'get' | |
1193 | */ | |
13d6e9b6 | 1194 | static void i7core_put_devices(struct i7core_dev *i7core_dev) |
a0c36a1f | 1195 | { |
13d6e9b6 | 1196 | int i; |
a0c36a1f | 1197 | |
22e6bcbd | 1198 | debugf0(__FILE__ ": %s()\n", __func__); |
de06eeef | 1199 | for (i = 0; i < i7core_dev->n_devs; i++) { |
22e6bcbd MCC |
1200 | struct pci_dev *pdev = i7core_dev->pdev[i]; |
1201 | if (!pdev) | |
1202 | continue; | |
1203 | debugf0("Removing dev %02x:%02x.%d\n", | |
1204 | pdev->bus->number, | |
1205 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); | |
1206 | pci_dev_put(pdev); | |
1207 | } | |
13d6e9b6 | 1208 | kfree(i7core_dev->pdev); |
22e6bcbd | 1209 | list_del(&i7core_dev->list); |
13d6e9b6 MCC |
1210 | kfree(i7core_dev); |
1211 | } | |
66607706 | 1212 | |
13d6e9b6 MCC |
1213 | static void i7core_put_all_devices(void) |
1214 | { | |
42538680 | 1215 | struct i7core_dev *i7core_dev, *tmp; |
13d6e9b6 | 1216 | |
42538680 | 1217 | list_for_each_entry_safe(i7core_dev, tmp, &i7core_edac_list, list) |
13d6e9b6 | 1218 | i7core_put_devices(i7core_dev); |
a0c36a1f MCC |
1219 | } |
1220 | ||
bd9e19ca | 1221 | static void __init i7core_xeon_pci_fixup(struct pci_id_table *table) |
bc2d7245 KM |
1222 | { |
1223 | struct pci_dev *pdev = NULL; | |
1224 | int i; | |
1225 | /* | |
1226 | * On Xeon 55xx, the Intel Quckpath Arch Generic Non-core pci buses | |
1227 | * aren't announced by acpi. So, we need to use a legacy scan probing | |
1228 | * to detect them | |
1229 | */ | |
bd9e19ca VM |
1230 | while (table && table->descr) { |
1231 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, table->descr[0].dev_id, NULL); | |
1232 | if (unlikely(!pdev)) { | |
1233 | for (i = 0; i < MAX_SOCKET_BUSES; i++) | |
1234 | pcibios_scan_specific_bus(255-i); | |
1235 | } | |
bda14289 | 1236 | pci_dev_put(pdev); |
bd9e19ca | 1237 | table++; |
bc2d7245 KM |
1238 | } |
1239 | } | |
1240 | ||
bda14289 MCC |
1241 | static unsigned i7core_pci_lastbus(void) |
1242 | { | |
1243 | int last_bus = 0, bus; | |
1244 | struct pci_bus *b = NULL; | |
1245 | ||
1246 | while ((b = pci_find_next_bus(b)) != NULL) { | |
1247 | bus = b->number; | |
1248 | debugf0("Found bus %d\n", bus); | |
1249 | if (bus > last_bus) | |
1250 | last_bus = bus; | |
1251 | } | |
1252 | ||
1253 | debugf0("Last bus %d\n", last_bus); | |
1254 | ||
1255 | return last_bus; | |
1256 | } | |
1257 | ||
a0c36a1f MCC |
1258 | /* |
1259 | * i7core_get_devices Find and perform 'get' operation on the MCH's | |
1260 | * device/functions we want to reference for this driver | |
1261 | * | |
1262 | * Need to 'get' device 16 func 1 and func 2 | |
1263 | */ | |
de06eeef | 1264 | int i7core_get_onedevice(struct pci_dev **prev, int devno, |
bda14289 MCC |
1265 | struct pci_id_descr *dev_descr, unsigned n_devs, |
1266 | unsigned last_bus) | |
a0c36a1f | 1267 | { |
66607706 MCC |
1268 | struct i7core_dev *i7core_dev; |
1269 | ||
8f331907 | 1270 | struct pci_dev *pdev = NULL; |
67166af4 MCC |
1271 | u8 bus = 0; |
1272 | u8 socket = 0; | |
a0c36a1f | 1273 | |
c77720b9 | 1274 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, |
de06eeef | 1275 | dev_descr->dev_id, *prev); |
c77720b9 | 1276 | |
c77720b9 MCC |
1277 | /* |
1278 | * On Xeon 55xx, the Intel Quckpath Arch Generic Non-core regs | |
1279 | * is at addr 8086:2c40, instead of 8086:2c41. So, we need | |
1280 | * to probe for the alternate address in case of failure | |
1281 | */ | |
de06eeef | 1282 | if (dev_descr->dev_id == PCI_DEVICE_ID_INTEL_I7_NONCORE && !pdev) |
c77720b9 | 1283 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, |
fd382654 | 1284 | PCI_DEVICE_ID_INTEL_I7_NONCORE_ALT, *prev); |
d1fd4fb6 | 1285 | |
bd9e19ca | 1286 | if (dev_descr->dev_id == PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE && !pdev) |
f05da2f7 MCC |
1287 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, |
1288 | PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_ALT, | |
1289 | *prev); | |
1290 | ||
c77720b9 MCC |
1291 | if (!pdev) { |
1292 | if (*prev) { | |
1293 | *prev = pdev; | |
1294 | return 0; | |
d1fd4fb6 MCC |
1295 | } |
1296 | ||
de06eeef | 1297 | if (dev_descr->optional) |
c77720b9 | 1298 | return 0; |
310cbb72 | 1299 | |
bd9e19ca VM |
1300 | if (devno == 0) |
1301 | return -ENODEV; | |
1302 | ||
c77720b9 MCC |
1303 | i7core_printk(KERN_ERR, |
1304 | "Device not found: dev %02x.%d PCI ID %04x:%04x\n", | |
de06eeef MCC |
1305 | dev_descr->dev, dev_descr->func, |
1306 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); | |
67166af4 | 1307 | |
c77720b9 MCC |
1308 | /* End of list, leave */ |
1309 | return -ENODEV; | |
1310 | } | |
1311 | bus = pdev->bus->number; | |
67166af4 | 1312 | |
bda14289 | 1313 | socket = last_bus - bus; |
c77720b9 | 1314 | |
66607706 MCC |
1315 | i7core_dev = get_i7core_dev(socket); |
1316 | if (!i7core_dev) { | |
1317 | i7core_dev = kzalloc(sizeof(*i7core_dev), GFP_KERNEL); | |
1318 | if (!i7core_dev) | |
1319 | return -ENOMEM; | |
de06eeef | 1320 | i7core_dev->pdev = kzalloc(sizeof(*i7core_dev->pdev) * n_devs, |
66607706 | 1321 | GFP_KERNEL); |
2a6fae32 AB |
1322 | if (!i7core_dev->pdev) { |
1323 | kfree(i7core_dev); | |
66607706 | 1324 | return -ENOMEM; |
2a6fae32 | 1325 | } |
66607706 | 1326 | i7core_dev->socket = socket; |
de06eeef | 1327 | i7core_dev->n_devs = n_devs; |
66607706 | 1328 | list_add_tail(&i7core_dev->list, &i7core_edac_list); |
c77720b9 | 1329 | } |
67166af4 | 1330 | |
66607706 | 1331 | if (i7core_dev->pdev[devno]) { |
c77720b9 MCC |
1332 | i7core_printk(KERN_ERR, |
1333 | "Duplicated device for " | |
1334 | "dev %02x:%02x.%d PCI ID %04x:%04x\n", | |
de06eeef MCC |
1335 | bus, dev_descr->dev, dev_descr->func, |
1336 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); | |
c77720b9 MCC |
1337 | pci_dev_put(pdev); |
1338 | return -ENODEV; | |
1339 | } | |
67166af4 | 1340 | |
66607706 | 1341 | i7core_dev->pdev[devno] = pdev; |
c77720b9 MCC |
1342 | |
1343 | /* Sanity check */ | |
de06eeef MCC |
1344 | if (unlikely(PCI_SLOT(pdev->devfn) != dev_descr->dev || |
1345 | PCI_FUNC(pdev->devfn) != dev_descr->func)) { | |
c77720b9 MCC |
1346 | i7core_printk(KERN_ERR, |
1347 | "Device PCI ID %04x:%04x " | |
1348 | "has dev %02x:%02x.%d instead of dev %02x:%02x.%d\n", | |
de06eeef | 1349 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id, |
c77720b9 | 1350 | bus, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), |
de06eeef | 1351 | bus, dev_descr->dev, dev_descr->func); |
c77720b9 MCC |
1352 | return -ENODEV; |
1353 | } | |
ef708b53 | 1354 | |
c77720b9 MCC |
1355 | /* Be sure that the device is enabled */ |
1356 | if (unlikely(pci_enable_device(pdev) < 0)) { | |
1357 | i7core_printk(KERN_ERR, | |
1358 | "Couldn't enable " | |
1359 | "dev %02x:%02x.%d PCI ID %04x:%04x\n", | |
de06eeef MCC |
1360 | bus, dev_descr->dev, dev_descr->func, |
1361 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); | |
c77720b9 MCC |
1362 | return -ENODEV; |
1363 | } | |
ef708b53 | 1364 | |
d4c27795 | 1365 | debugf0("Detected socket %d dev %02x:%02x.%d PCI ID %04x:%04x\n", |
de06eeef MCC |
1366 | socket, bus, dev_descr->dev, |
1367 | dev_descr->func, | |
1368 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); | |
8f331907 | 1369 | |
c77720b9 | 1370 | *prev = pdev; |
ef708b53 | 1371 | |
c77720b9 MCC |
1372 | return 0; |
1373 | } | |
a0c36a1f | 1374 | |
bd9e19ca | 1375 | static int i7core_get_devices(struct pci_id_table *table) |
c77720b9 | 1376 | { |
bda14289 | 1377 | int i, rc, last_bus; |
c77720b9 | 1378 | struct pci_dev *pdev = NULL; |
bd9e19ca VM |
1379 | struct pci_id_descr *dev_descr; |
1380 | ||
bda14289 MCC |
1381 | last_bus = i7core_pci_lastbus(); |
1382 | ||
bd9e19ca VM |
1383 | while (table && table->descr) { |
1384 | dev_descr = table->descr; | |
1385 | for (i = 0; i < table->n_devs; i++) { | |
1386 | pdev = NULL; | |
1387 | do { | |
bda14289 MCC |
1388 | rc = i7core_get_onedevice(&pdev, i, |
1389 | &dev_descr[i], | |
1390 | table->n_devs, | |
1391 | last_bus); | |
bd9e19ca VM |
1392 | if (rc < 0) { |
1393 | if (i == 0) { | |
1394 | i = table->n_devs; | |
1395 | break; | |
1396 | } | |
1397 | i7core_put_all_devices(); | |
1398 | return -ENODEV; | |
1399 | } | |
1400 | } while (pdev); | |
1401 | } | |
1402 | table++; | |
c77720b9 | 1403 | } |
66607706 | 1404 | |
ef708b53 | 1405 | return 0; |
bd9e19ca | 1406 | return 0; |
ef708b53 MCC |
1407 | } |
1408 | ||
f4742949 MCC |
1409 | static int mci_bind_devs(struct mem_ctl_info *mci, |
1410 | struct i7core_dev *i7core_dev) | |
ef708b53 MCC |
1411 | { |
1412 | struct i7core_pvt *pvt = mci->pvt_info; | |
1413 | struct pci_dev *pdev; | |
f4742949 | 1414 | int i, func, slot; |
ef708b53 | 1415 | |
f4742949 MCC |
1416 | /* Associates i7core_dev and mci for future usage */ |
1417 | pvt->i7core_dev = i7core_dev; | |
1418 | i7core_dev->mci = mci; | |
66607706 | 1419 | |
f4742949 | 1420 | pvt->is_registered = 0; |
de06eeef | 1421 | for (i = 0; i < i7core_dev->n_devs; i++) { |
f4742949 MCC |
1422 | pdev = i7core_dev->pdev[i]; |
1423 | if (!pdev) | |
66607706 MCC |
1424 | continue; |
1425 | ||
f4742949 MCC |
1426 | func = PCI_FUNC(pdev->devfn); |
1427 | slot = PCI_SLOT(pdev->devfn); | |
1428 | if (slot == 3) { | |
1429 | if (unlikely(func > MAX_MCR_FUNC)) | |
1430 | goto error; | |
1431 | pvt->pci_mcr[func] = pdev; | |
1432 | } else if (likely(slot >= 4 && slot < 4 + NUM_CHANS)) { | |
1433 | if (unlikely(func > MAX_CHAN_FUNC)) | |
ef708b53 | 1434 | goto error; |
f4742949 MCC |
1435 | pvt->pci_ch[slot - 4][func] = pdev; |
1436 | } else if (!slot && !func) | |
1437 | pvt->pci_noncore = pdev; | |
1438 | else | |
1439 | goto error; | |
ef708b53 | 1440 | |
f4742949 MCC |
1441 | debugf0("Associated fn %d.%d, dev = %p, socket %d\n", |
1442 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), | |
1443 | pdev, i7core_dev->socket); | |
14d2c083 | 1444 | |
f4742949 MCC |
1445 | if (PCI_SLOT(pdev->devfn) == 3 && |
1446 | PCI_FUNC(pdev->devfn) == 2) | |
1447 | pvt->is_registered = 1; | |
a0c36a1f | 1448 | } |
e9bd2e73 | 1449 | |
f338d736 MCC |
1450 | /* |
1451 | * Add extra nodes to count errors on udimm | |
1452 | * For registered memory, this is not needed, since the counters | |
1453 | * are already displayed at the standard locations | |
1454 | */ | |
1455 | if (!pvt->is_registered) | |
1456 | i7core_sysfs_attrs[ARRAY_SIZE(i7core_sysfs_attrs)-2].grp = | |
1457 | &i7core_udimm_counters; | |
1458 | ||
a0c36a1f | 1459 | return 0; |
ef708b53 MCC |
1460 | |
1461 | error: | |
1462 | i7core_printk(KERN_ERR, "Device %d, function %d " | |
1463 | "is out of the expected range\n", | |
1464 | slot, func); | |
1465 | return -EINVAL; | |
a0c36a1f MCC |
1466 | } |
1467 | ||
442305b1 MCC |
1468 | /**************************************************************************** |
1469 | Error check routines | |
1470 | ****************************************************************************/ | |
f4742949 | 1471 | static void i7core_rdimm_update_csrow(struct mem_ctl_info *mci, |
b4e8f0b6 MCC |
1472 | int chan, int dimm, int add) |
1473 | { | |
1474 | char *msg; | |
1475 | struct i7core_pvt *pvt = mci->pvt_info; | |
f4742949 | 1476 | int row = pvt->csrow_map[chan][dimm], i; |
b4e8f0b6 MCC |
1477 | |
1478 | for (i = 0; i < add; i++) { | |
1479 | msg = kasprintf(GFP_KERNEL, "Corrected error " | |
f4742949 MCC |
1480 | "(Socket=%d channel=%d dimm=%d)", |
1481 | pvt->i7core_dev->socket, chan, dimm); | |
b4e8f0b6 MCC |
1482 | |
1483 | edac_mc_handle_fbd_ce(mci, row, 0, msg); | |
1484 | kfree (msg); | |
1485 | } | |
1486 | } | |
1487 | ||
1488 | static void i7core_rdimm_update_ce_count(struct mem_ctl_info *mci, | |
f4742949 | 1489 | int chan, int new0, int new1, int new2) |
b4e8f0b6 MCC |
1490 | { |
1491 | struct i7core_pvt *pvt = mci->pvt_info; | |
1492 | int add0 = 0, add1 = 0, add2 = 0; | |
1493 | /* Updates CE counters if it is not the first time here */ | |
f4742949 | 1494 | if (pvt->ce_count_available) { |
b4e8f0b6 MCC |
1495 | /* Updates CE counters */ |
1496 | ||
f4742949 MCC |
1497 | add2 = new2 - pvt->rdimm_last_ce_count[chan][2]; |
1498 | add1 = new1 - pvt->rdimm_last_ce_count[chan][1]; | |
1499 | add0 = new0 - pvt->rdimm_last_ce_count[chan][0]; | |
b4e8f0b6 MCC |
1500 | |
1501 | if (add2 < 0) | |
1502 | add2 += 0x7fff; | |
f4742949 | 1503 | pvt->rdimm_ce_count[chan][2] += add2; |
b4e8f0b6 MCC |
1504 | |
1505 | if (add1 < 0) | |
1506 | add1 += 0x7fff; | |
f4742949 | 1507 | pvt->rdimm_ce_count[chan][1] += add1; |
b4e8f0b6 MCC |
1508 | |
1509 | if (add0 < 0) | |
1510 | add0 += 0x7fff; | |
f4742949 | 1511 | pvt->rdimm_ce_count[chan][0] += add0; |
b4e8f0b6 | 1512 | } else |
f4742949 | 1513 | pvt->ce_count_available = 1; |
b4e8f0b6 MCC |
1514 | |
1515 | /* Store the new values */ | |
f4742949 MCC |
1516 | pvt->rdimm_last_ce_count[chan][2] = new2; |
1517 | pvt->rdimm_last_ce_count[chan][1] = new1; | |
1518 | pvt->rdimm_last_ce_count[chan][0] = new0; | |
b4e8f0b6 MCC |
1519 | |
1520 | /*updated the edac core */ | |
1521 | if (add0 != 0) | |
f4742949 | 1522 | i7core_rdimm_update_csrow(mci, chan, 0, add0); |
b4e8f0b6 | 1523 | if (add1 != 0) |
f4742949 | 1524 | i7core_rdimm_update_csrow(mci, chan, 1, add1); |
b4e8f0b6 | 1525 | if (add2 != 0) |
f4742949 | 1526 | i7core_rdimm_update_csrow(mci, chan, 2, add2); |
b4e8f0b6 MCC |
1527 | |
1528 | } | |
1529 | ||
f4742949 | 1530 | static void i7core_rdimm_check_mc_ecc_err(struct mem_ctl_info *mci) |
b4e8f0b6 MCC |
1531 | { |
1532 | struct i7core_pvt *pvt = mci->pvt_info; | |
1533 | u32 rcv[3][2]; | |
1534 | int i, new0, new1, new2; | |
1535 | ||
1536 | /*Read DEV 3: FUN 2: MC_COR_ECC_CNT regs directly*/ | |
f4742949 | 1537 | pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_0, |
b4e8f0b6 | 1538 | &rcv[0][0]); |
f4742949 | 1539 | pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_1, |
b4e8f0b6 | 1540 | &rcv[0][1]); |
f4742949 | 1541 | pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_2, |
b4e8f0b6 | 1542 | &rcv[1][0]); |
f4742949 | 1543 | pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_3, |
b4e8f0b6 | 1544 | &rcv[1][1]); |
f4742949 | 1545 | pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_4, |
b4e8f0b6 | 1546 | &rcv[2][0]); |
f4742949 | 1547 | pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_5, |
b4e8f0b6 MCC |
1548 | &rcv[2][1]); |
1549 | for (i = 0 ; i < 3; i++) { | |
1550 | debugf3("MC_COR_ECC_CNT%d = 0x%x; MC_COR_ECC_CNT%d = 0x%x\n", | |
1551 | (i * 2), rcv[i][0], (i * 2) + 1, rcv[i][1]); | |
1552 | /*if the channel has 3 dimms*/ | |
f4742949 | 1553 | if (pvt->channel[i].dimms > 2) { |
b4e8f0b6 MCC |
1554 | new0 = DIMM_BOT_COR_ERR(rcv[i][0]); |
1555 | new1 = DIMM_TOP_COR_ERR(rcv[i][0]); | |
1556 | new2 = DIMM_BOT_COR_ERR(rcv[i][1]); | |
1557 | } else { | |
1558 | new0 = DIMM_TOP_COR_ERR(rcv[i][0]) + | |
1559 | DIMM_BOT_COR_ERR(rcv[i][0]); | |
1560 | new1 = DIMM_TOP_COR_ERR(rcv[i][1]) + | |
1561 | DIMM_BOT_COR_ERR(rcv[i][1]); | |
1562 | new2 = 0; | |
1563 | } | |
1564 | ||
f4742949 | 1565 | i7core_rdimm_update_ce_count(mci, i, new0, new1, new2); |
b4e8f0b6 MCC |
1566 | } |
1567 | } | |
442305b1 MCC |
1568 | |
1569 | /* This function is based on the device 3 function 4 registers as described on: | |
1570 | * Intel Xeon Processor 5500 Series Datasheet Volume 2 | |
1571 | * http://www.intel.com/Assets/PDF/datasheet/321322.pdf | |
1572 | * also available at: | |
1573 | * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf | |
1574 | */ | |
f4742949 | 1575 | static void i7core_udimm_check_mc_ecc_err(struct mem_ctl_info *mci) |
442305b1 MCC |
1576 | { |
1577 | struct i7core_pvt *pvt = mci->pvt_info; | |
1578 | u32 rcv1, rcv0; | |
1579 | int new0, new1, new2; | |
1580 | ||
f4742949 | 1581 | if (!pvt->pci_mcr[4]) { |
b990538a | 1582 | debugf0("%s MCR registers not found\n", __func__); |
442305b1 MCC |
1583 | return; |
1584 | } | |
1585 | ||
b4e8f0b6 | 1586 | /* Corrected test errors */ |
f4742949 MCC |
1587 | pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV1, &rcv1); |
1588 | pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV0, &rcv0); | |
442305b1 MCC |
1589 | |
1590 | /* Store the new values */ | |
1591 | new2 = DIMM2_COR_ERR(rcv1); | |
1592 | new1 = DIMM1_COR_ERR(rcv0); | |
1593 | new0 = DIMM0_COR_ERR(rcv0); | |
1594 | ||
442305b1 | 1595 | /* Updates CE counters if it is not the first time here */ |
f4742949 | 1596 | if (pvt->ce_count_available) { |
442305b1 MCC |
1597 | /* Updates CE counters */ |
1598 | int add0, add1, add2; | |
1599 | ||
f4742949 MCC |
1600 | add2 = new2 - pvt->udimm_last_ce_count[2]; |
1601 | add1 = new1 - pvt->udimm_last_ce_count[1]; | |
1602 | add0 = new0 - pvt->udimm_last_ce_count[0]; | |
442305b1 MCC |
1603 | |
1604 | if (add2 < 0) | |
1605 | add2 += 0x7fff; | |
f4742949 | 1606 | pvt->udimm_ce_count[2] += add2; |
442305b1 MCC |
1607 | |
1608 | if (add1 < 0) | |
1609 | add1 += 0x7fff; | |
f4742949 | 1610 | pvt->udimm_ce_count[1] += add1; |
442305b1 MCC |
1611 | |
1612 | if (add0 < 0) | |
1613 | add0 += 0x7fff; | |
f4742949 | 1614 | pvt->udimm_ce_count[0] += add0; |
b4e8f0b6 MCC |
1615 | |
1616 | if (add0 | add1 | add2) | |
1617 | i7core_printk(KERN_ERR, "New Corrected error(s): " | |
1618 | "dimm0: +%d, dimm1: +%d, dimm2 +%d\n", | |
1619 | add0, add1, add2); | |
442305b1 | 1620 | } else |
f4742949 | 1621 | pvt->ce_count_available = 1; |
442305b1 MCC |
1622 | |
1623 | /* Store the new values */ | |
f4742949 MCC |
1624 | pvt->udimm_last_ce_count[2] = new2; |
1625 | pvt->udimm_last_ce_count[1] = new1; | |
1626 | pvt->udimm_last_ce_count[0] = new0; | |
442305b1 MCC |
1627 | } |
1628 | ||
8a2f118e MCC |
1629 | /* |
1630 | * According with tables E-11 and E-12 of chapter E.3.3 of Intel 64 and IA-32 | |
1631 | * Architectures Software Developer’s Manual Volume 3B. | |
f237fcf2 MCC |
1632 | * Nehalem are defined as family 0x06, model 0x1a |
1633 | * | |
1634 | * The MCA registers used here are the following ones: | |
8a2f118e | 1635 | * struct mce field MCA Register |
f237fcf2 MCC |
1636 | * m->status MSR_IA32_MC8_STATUS |
1637 | * m->addr MSR_IA32_MC8_ADDR | |
1638 | * m->misc MSR_IA32_MC8_MISC | |
8a2f118e MCC |
1639 | * In the case of Nehalem, the error information is masked at .status and .misc |
1640 | * fields | |
1641 | */ | |
d5381642 MCC |
1642 | static void i7core_mce_output_error(struct mem_ctl_info *mci, |
1643 | struct mce *m) | |
1644 | { | |
b4e8f0b6 | 1645 | struct i7core_pvt *pvt = mci->pvt_info; |
a639539f | 1646 | char *type, *optype, *err, *msg; |
8a2f118e | 1647 | unsigned long error = m->status & 0x1ff0000l; |
a639539f | 1648 | u32 optypenum = (m->status >> 4) & 0x07; |
8a2f118e MCC |
1649 | u32 core_err_cnt = (m->status >> 38) && 0x7fff; |
1650 | u32 dimm = (m->misc >> 16) & 0x3; | |
1651 | u32 channel = (m->misc >> 18) & 0x3; | |
1652 | u32 syndrome = m->misc >> 32; | |
1653 | u32 errnum = find_first_bit(&error, 32); | |
b4e8f0b6 | 1654 | int csrow; |
8a2f118e | 1655 | |
c5d34528 MCC |
1656 | if (m->mcgstatus & 1) |
1657 | type = "FATAL"; | |
1658 | else | |
1659 | type = "NON_FATAL"; | |
1660 | ||
a639539f | 1661 | switch (optypenum) { |
b990538a MCC |
1662 | case 0: |
1663 | optype = "generic undef request"; | |
1664 | break; | |
1665 | case 1: | |
1666 | optype = "read error"; | |
1667 | break; | |
1668 | case 2: | |
1669 | optype = "write error"; | |
1670 | break; | |
1671 | case 3: | |
1672 | optype = "addr/cmd error"; | |
1673 | break; | |
1674 | case 4: | |
1675 | optype = "scrubbing error"; | |
1676 | break; | |
1677 | default: | |
1678 | optype = "reserved"; | |
1679 | break; | |
a639539f MCC |
1680 | } |
1681 | ||
8a2f118e MCC |
1682 | switch (errnum) { |
1683 | case 16: | |
1684 | err = "read ECC error"; | |
1685 | break; | |
1686 | case 17: | |
1687 | err = "RAS ECC error"; | |
1688 | break; | |
1689 | case 18: | |
1690 | err = "write parity error"; | |
1691 | break; | |
1692 | case 19: | |
1693 | err = "redundacy loss"; | |
1694 | break; | |
1695 | case 20: | |
1696 | err = "reserved"; | |
1697 | break; | |
1698 | case 21: | |
1699 | err = "memory range error"; | |
1700 | break; | |
1701 | case 22: | |
1702 | err = "RTID out of range"; | |
1703 | break; | |
1704 | case 23: | |
1705 | err = "address parity error"; | |
1706 | break; | |
1707 | case 24: | |
1708 | err = "byte enable parity error"; | |
1709 | break; | |
1710 | default: | |
1711 | err = "unknown"; | |
d5381642 | 1712 | } |
d5381642 | 1713 | |
f237fcf2 | 1714 | /* FIXME: should convert addr into bank and rank information */ |
8a2f118e | 1715 | msg = kasprintf(GFP_ATOMIC, |
f4742949 | 1716 | "%s (addr = 0x%08llx, cpu=%d, Dimm=%d, Channel=%d, " |
a639539f | 1717 | "syndrome=0x%08x, count=%d, Err=%08llx:%08llx (%s: %s))\n", |
f4742949 | 1718 | type, (long long) m->addr, m->cpu, dimm, channel, |
a639539f MCC |
1719 | syndrome, core_err_cnt, (long long)m->status, |
1720 | (long long)m->misc, optype, err); | |
8a2f118e MCC |
1721 | |
1722 | debugf0("%s", msg); | |
d5381642 | 1723 | |
f4742949 | 1724 | csrow = pvt->csrow_map[channel][dimm]; |
b4e8f0b6 | 1725 | |
d5381642 | 1726 | /* Call the helper to output message */ |
b4e8f0b6 MCC |
1727 | if (m->mcgstatus & 1) |
1728 | edac_mc_handle_fbd_ue(mci, csrow, 0, | |
1729 | 0 /* FIXME: should be channel here */, msg); | |
f4742949 | 1730 | else if (!pvt->is_registered) |
b4e8f0b6 MCC |
1731 | edac_mc_handle_fbd_ce(mci, csrow, |
1732 | 0 /* FIXME: should be channel here */, msg); | |
8a2f118e MCC |
1733 | |
1734 | kfree(msg); | |
d5381642 MCC |
1735 | } |
1736 | ||
87d1d272 MCC |
1737 | /* |
1738 | * i7core_check_error Retrieve and process errors reported by the | |
1739 | * hardware. Called by the Core module. | |
1740 | */ | |
1741 | static void i7core_check_error(struct mem_ctl_info *mci) | |
1742 | { | |
d5381642 MCC |
1743 | struct i7core_pvt *pvt = mci->pvt_info; |
1744 | int i; | |
1745 | unsigned count = 0; | |
ca9c90ba | 1746 | struct mce *m; |
d5381642 | 1747 | |
ca9c90ba MCC |
1748 | /* |
1749 | * MCE first step: Copy all mce errors into a temporary buffer | |
1750 | * We use a double buffering here, to reduce the risk of | |
1751 | * loosing an error. | |
1752 | */ | |
1753 | smp_rmb(); | |
321ece4d MCC |
1754 | count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in) |
1755 | % MCE_LOG_LEN; | |
ca9c90ba | 1756 | if (!count) |
8a311e17 | 1757 | goto check_ce_error; |
f4742949 | 1758 | |
ca9c90ba | 1759 | m = pvt->mce_outentry; |
321ece4d MCC |
1760 | if (pvt->mce_in + count > MCE_LOG_LEN) { |
1761 | unsigned l = MCE_LOG_LEN - pvt->mce_in; | |
f4742949 | 1762 | |
ca9c90ba MCC |
1763 | memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * l); |
1764 | smp_wmb(); | |
1765 | pvt->mce_in = 0; | |
1766 | count -= l; | |
1767 | m += l; | |
1768 | } | |
1769 | memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * count); | |
1770 | smp_wmb(); | |
1771 | pvt->mce_in += count; | |
1772 | ||
1773 | smp_rmb(); | |
1774 | if (pvt->mce_overrun) { | |
1775 | i7core_printk(KERN_ERR, "Lost %d memory errors\n", | |
1776 | pvt->mce_overrun); | |
1777 | smp_wmb(); | |
1778 | pvt->mce_overrun = 0; | |
1779 | } | |
d5381642 | 1780 | |
ca9c90ba MCC |
1781 | /* |
1782 | * MCE second step: parse errors and display | |
1783 | */ | |
d5381642 | 1784 | for (i = 0; i < count; i++) |
ca9c90ba | 1785 | i7core_mce_output_error(mci, &pvt->mce_outentry[i]); |
d5381642 | 1786 | |
ca9c90ba MCC |
1787 | /* |
1788 | * Now, let's increment CE error counts | |
1789 | */ | |
8a311e17 | 1790 | check_ce_error: |
f4742949 MCC |
1791 | if (!pvt->is_registered) |
1792 | i7core_udimm_check_mc_ecc_err(mci); | |
1793 | else | |
1794 | i7core_rdimm_check_mc_ecc_err(mci); | |
87d1d272 MCC |
1795 | } |
1796 | ||
d5381642 MCC |
1797 | /* |
1798 | * i7core_mce_check_error Replicates mcelog routine to get errors | |
1799 | * This routine simply queues mcelog errors, and | |
1800 | * return. The error itself should be handled later | |
1801 | * by i7core_check_error. | |
6e103be1 MCC |
1802 | * WARNING: As this routine should be called at NMI time, extra care should |
1803 | * be taken to avoid deadlocks, and to be as fast as possible. | |
d5381642 MCC |
1804 | */ |
1805 | static int i7core_mce_check_error(void *priv, struct mce *mce) | |
1806 | { | |
c5d34528 MCC |
1807 | struct mem_ctl_info *mci = priv; |
1808 | struct i7core_pvt *pvt = mci->pvt_info; | |
d5381642 | 1809 | |
8a2f118e MCC |
1810 | /* |
1811 | * Just let mcelog handle it if the error is | |
1812 | * outside the memory controller | |
1813 | */ | |
1814 | if (((mce->status & 0xffff) >> 7) != 1) | |
1815 | return 0; | |
1816 | ||
f237fcf2 MCC |
1817 | /* Bank 8 registers are the only ones that we know how to handle */ |
1818 | if (mce->bank != 8) | |
1819 | return 0; | |
1820 | ||
3b918c12 | 1821 | #ifdef CONFIG_SMP |
f4742949 | 1822 | /* Only handle if it is the right mc controller */ |
6e103be1 | 1823 | if (cpu_data(mce->cpu).phys_proc_id != pvt->i7core_dev->socket) |
f4742949 | 1824 | return 0; |
3b918c12 | 1825 | #endif |
f4742949 | 1826 | |
ca9c90ba | 1827 | smp_rmb(); |
321ece4d | 1828 | if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) { |
ca9c90ba MCC |
1829 | smp_wmb(); |
1830 | pvt->mce_overrun++; | |
1831 | return 0; | |
d5381642 | 1832 | } |
6e103be1 MCC |
1833 | |
1834 | /* Copy memory error at the ringbuffer */ | |
1835 | memcpy(&pvt->mce_entry[pvt->mce_out], mce, sizeof(*mce)); | |
ca9c90ba | 1836 | smp_wmb(); |
321ece4d | 1837 | pvt->mce_out = (pvt->mce_out + 1) % MCE_LOG_LEN; |
d5381642 | 1838 | |
c5d34528 MCC |
1839 | /* Handle fatal errors immediately */ |
1840 | if (mce->mcgstatus & 1) | |
1841 | i7core_check_error(mci); | |
1842 | ||
d5381642 | 1843 | /* Advice mcelog that the error were handled */ |
8a2f118e | 1844 | return 1; |
d5381642 MCC |
1845 | } |
1846 | ||
f4742949 MCC |
1847 | static int i7core_register_mci(struct i7core_dev *i7core_dev, |
1848 | int num_channels, int num_csrows) | |
a0c36a1f MCC |
1849 | { |
1850 | struct mem_ctl_info *mci; | |
1851 | struct i7core_pvt *pvt; | |
ba6c5c62 | 1852 | int csrow = 0; |
f4742949 | 1853 | int rc; |
a0c36a1f | 1854 | |
a0c36a1f | 1855 | /* allocate a new MC control structure */ |
d4c27795 MCC |
1856 | mci = edac_mc_alloc(sizeof(*pvt), num_csrows, num_channels, |
1857 | i7core_dev->socket); | |
f4742949 MCC |
1858 | if (unlikely(!mci)) |
1859 | return -ENOMEM; | |
a0c36a1f MCC |
1860 | |
1861 | debugf0("MC: " __FILE__ ": %s(): mci = %p\n", __func__, mci); | |
1862 | ||
f4742949 MCC |
1863 | /* record ptr to the generic device */ |
1864 | mci->dev = &i7core_dev->pdev[0]->dev; | |
1865 | ||
a0c36a1f | 1866 | pvt = mci->pvt_info; |
ef708b53 | 1867 | memset(pvt, 0, sizeof(*pvt)); |
67166af4 | 1868 | |
41fcb7fe MCC |
1869 | /* |
1870 | * FIXME: how to handle RDDR3 at MCI level? It is possible to have | |
1871 | * Mixed RDDR3/UDDR3 with Nehalem, provided that they are on different | |
1872 | * memory channels | |
1873 | */ | |
1874 | mci->mtype_cap = MEM_FLAG_DDR3; | |
a0c36a1f MCC |
1875 | mci->edac_ctl_cap = EDAC_FLAG_NONE; |
1876 | mci->edac_cap = EDAC_FLAG_NONE; | |
1877 | mci->mod_name = "i7core_edac.c"; | |
1878 | mci->mod_ver = I7CORE_REVISION; | |
f4742949 MCC |
1879 | mci->ctl_name = kasprintf(GFP_KERNEL, "i7 core #%d", |
1880 | i7core_dev->socket); | |
1881 | mci->dev_name = pci_name(i7core_dev->pdev[0]); | |
a0c36a1f | 1882 | mci->ctl_page_to_phys = NULL; |
a5538e53 | 1883 | mci->mc_driver_sysfs_attributes = i7core_sysfs_attrs; |
87d1d272 MCC |
1884 | /* Set the function pointer to an actual operation function */ |
1885 | mci->edac_check = i7core_check_error; | |
8f331907 | 1886 | |
ef708b53 | 1887 | /* Store pci devices at mci for faster access */ |
f4742949 | 1888 | rc = mci_bind_devs(mci, i7core_dev); |
41fcb7fe | 1889 | if (unlikely(rc < 0)) |
f4742949 | 1890 | goto fail; |
ef708b53 MCC |
1891 | |
1892 | /* Get dimm basic config */ | |
f4742949 | 1893 | get_dimm_config(mci, &csrow); |
ef708b53 | 1894 | |
a0c36a1f | 1895 | /* add this new MC control structure to EDAC's list of MCs */ |
b7c76151 | 1896 | if (unlikely(edac_mc_add_mc(mci))) { |
a0c36a1f MCC |
1897 | debugf0("MC: " __FILE__ |
1898 | ": %s(): failed edac_mc_add_mc()\n", __func__); | |
1899 | /* FIXME: perhaps some code should go here that disables error | |
1900 | * reporting if we just enabled it | |
1901 | */ | |
b7c76151 MCC |
1902 | |
1903 | rc = -EINVAL; | |
f4742949 | 1904 | goto fail; |
a0c36a1f MCC |
1905 | } |
1906 | ||
1907 | /* allocating generic PCI control info */ | |
f4742949 MCC |
1908 | i7core_pci = edac_pci_create_generic_ctl(&i7core_dev->pdev[0]->dev, |
1909 | EDAC_MOD_STR); | |
41fcb7fe | 1910 | if (unlikely(!i7core_pci)) { |
a0c36a1f MCC |
1911 | printk(KERN_WARNING |
1912 | "%s(): Unable to create PCI control\n", | |
1913 | __func__); | |
1914 | printk(KERN_WARNING | |
1915 | "%s(): PCI error report via EDAC not setup\n", | |
1916 | __func__); | |
1917 | } | |
1918 | ||
194a40fe | 1919 | /* Default error mask is any memory */ |
ef708b53 | 1920 | pvt->inject.channel = 0; |
194a40fe MCC |
1921 | pvt->inject.dimm = -1; |
1922 | pvt->inject.rank = -1; | |
1923 | pvt->inject.bank = -1; | |
1924 | pvt->inject.page = -1; | |
1925 | pvt->inject.col = -1; | |
1926 | ||
d5381642 | 1927 | /* Registers on edac_mce in order to receive memory errors */ |
c5d34528 | 1928 | pvt->edac_mce.priv = mci; |
d5381642 | 1929 | pvt->edac_mce.check_error = i7core_mce_check_error; |
d5381642 MCC |
1930 | |
1931 | rc = edac_mce_register(&pvt->edac_mce); | |
b990538a | 1932 | if (unlikely(rc < 0)) { |
d5381642 MCC |
1933 | debugf0("MC: " __FILE__ |
1934 | ": %s(): failed edac_mce_register()\n", __func__); | |
f4742949 MCC |
1935 | } |
1936 | ||
1937 | fail: | |
d4d1ef45 TL |
1938 | if (rc < 0) |
1939 | edac_mc_free(mci); | |
f4742949 MCC |
1940 | return rc; |
1941 | } | |
1942 | ||
1943 | /* | |
1944 | * i7core_probe Probe for ONE instance of device to see if it is | |
1945 | * present. | |
1946 | * return: | |
1947 | * 0 for FOUND a device | |
1948 | * < 0 for error code | |
1949 | */ | |
1950 | static int __devinit i7core_probe(struct pci_dev *pdev, | |
1951 | const struct pci_device_id *id) | |
1952 | { | |
1953 | int dev_idx = id->driver_data; | |
1954 | int rc; | |
1955 | struct i7core_dev *i7core_dev; | |
1956 | ||
1957 | /* | |
d4c27795 | 1958 | * All memory controllers are allocated at the first pass. |
f4742949 MCC |
1959 | */ |
1960 | if (unlikely(dev_idx >= 1)) | |
1961 | return -EINVAL; | |
1962 | ||
1963 | /* get the pci devices we want to reserve for our use */ | |
1964 | mutex_lock(&i7core_edac_lock); | |
de06eeef | 1965 | |
bd9e19ca | 1966 | rc = i7core_get_devices(pci_dev_table); |
f4742949 MCC |
1967 | if (unlikely(rc < 0)) |
1968 | goto fail0; | |
1969 | ||
1970 | list_for_each_entry(i7core_dev, &i7core_edac_list, list) { | |
1971 | int channels; | |
1972 | int csrows; | |
1973 | ||
1974 | /* Check the number of active and not disabled channels */ | |
1975 | rc = i7core_get_active_channels(i7core_dev->socket, | |
1976 | &channels, &csrows); | |
1977 | if (unlikely(rc < 0)) | |
1978 | goto fail1; | |
1979 | ||
d4c27795 MCC |
1980 | rc = i7core_register_mci(i7core_dev, channels, csrows); |
1981 | if (unlikely(rc < 0)) | |
1982 | goto fail1; | |
d5381642 MCC |
1983 | } |
1984 | ||
ef708b53 | 1985 | i7core_printk(KERN_INFO, "Driver loaded.\n"); |
8f331907 | 1986 | |
66607706 | 1987 | mutex_unlock(&i7core_edac_lock); |
a0c36a1f MCC |
1988 | return 0; |
1989 | ||
66607706 | 1990 | fail1: |
13d6e9b6 | 1991 | i7core_put_all_devices(); |
66607706 MCC |
1992 | fail0: |
1993 | mutex_unlock(&i7core_edac_lock); | |
b7c76151 | 1994 | return rc; |
a0c36a1f MCC |
1995 | } |
1996 | ||
1997 | /* | |
1998 | * i7core_remove destructor for one instance of device | |
1999 | * | |
2000 | */ | |
2001 | static void __devexit i7core_remove(struct pci_dev *pdev) | |
2002 | { | |
2003 | struct mem_ctl_info *mci; | |
22e6bcbd | 2004 | struct i7core_dev *i7core_dev, *tmp; |
a0c36a1f MCC |
2005 | |
2006 | debugf0(__FILE__ ": %s()\n", __func__); | |
2007 | ||
2008 | if (i7core_pci) | |
2009 | edac_pci_release_generic_ctl(i7core_pci); | |
2010 | ||
22e6bcbd MCC |
2011 | /* |
2012 | * we have a trouble here: pdev value for removal will be wrong, since | |
2013 | * it will point to the X58 register used to detect that the machine | |
2014 | * is a Nehalem or upper design. However, due to the way several PCI | |
2015 | * devices are grouped together to provide MC functionality, we need | |
2016 | * to use a different method for releasing the devices | |
2017 | */ | |
87d1d272 | 2018 | |
66607706 | 2019 | mutex_lock(&i7core_edac_lock); |
22e6bcbd MCC |
2020 | list_for_each_entry_safe(i7core_dev, tmp, &i7core_edac_list, list) { |
2021 | mci = edac_mc_del_mc(&i7core_dev->pdev[0]->dev); | |
2022 | if (mci) { | |
2023 | struct i7core_pvt *pvt = mci->pvt_info; | |
2024 | ||
2025 | i7core_dev = pvt->i7core_dev; | |
2026 | edac_mce_unregister(&pvt->edac_mce); | |
2027 | kfree(mci->ctl_name); | |
2028 | edac_mc_free(mci); | |
2029 | i7core_put_devices(i7core_dev); | |
2030 | } else { | |
2031 | i7core_printk(KERN_ERR, | |
2032 | "Couldn't find mci for socket %d\n", | |
2033 | i7core_dev->socket); | |
2034 | } | |
2035 | } | |
66607706 | 2036 | mutex_unlock(&i7core_edac_lock); |
a0c36a1f MCC |
2037 | } |
2038 | ||
a0c36a1f MCC |
2039 | MODULE_DEVICE_TABLE(pci, i7core_pci_tbl); |
2040 | ||
2041 | /* | |
2042 | * i7core_driver pci_driver structure for this module | |
2043 | * | |
2044 | */ | |
2045 | static struct pci_driver i7core_driver = { | |
2046 | .name = "i7core_edac", | |
2047 | .probe = i7core_probe, | |
2048 | .remove = __devexit_p(i7core_remove), | |
2049 | .id_table = i7core_pci_tbl, | |
2050 | }; | |
2051 | ||
2052 | /* | |
2053 | * i7core_init Module entry function | |
2054 | * Try to initialize this module for its devices | |
2055 | */ | |
2056 | static int __init i7core_init(void) | |
2057 | { | |
2058 | int pci_rc; | |
2059 | ||
2060 | debugf2("MC: " __FILE__ ": %s()\n", __func__); | |
2061 | ||
2062 | /* Ensure that the OPSTATE is set correctly for POLL or NMI */ | |
2063 | opstate_init(); | |
2064 | ||
bd9e19ca | 2065 | i7core_xeon_pci_fixup(pci_dev_table); |
bc2d7245 | 2066 | |
a0c36a1f MCC |
2067 | pci_rc = pci_register_driver(&i7core_driver); |
2068 | ||
3ef288a9 MCC |
2069 | if (pci_rc >= 0) |
2070 | return 0; | |
2071 | ||
2072 | i7core_printk(KERN_ERR, "Failed to register device with error %d.\n", | |
2073 | pci_rc); | |
2074 | ||
2075 | return pci_rc; | |
a0c36a1f MCC |
2076 | } |
2077 | ||
2078 | /* | |
2079 | * i7core_exit() Module exit function | |
2080 | * Unregister the driver | |
2081 | */ | |
2082 | static void __exit i7core_exit(void) | |
2083 | { | |
2084 | debugf2("MC: " __FILE__ ": %s()\n", __func__); | |
2085 | pci_unregister_driver(&i7core_driver); | |
2086 | } | |
2087 | ||
2088 | module_init(i7core_init); | |
2089 | module_exit(i7core_exit); | |
2090 | ||
2091 | MODULE_LICENSE("GPL"); | |
2092 | MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); | |
2093 | MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)"); | |
2094 | MODULE_DESCRIPTION("MC Driver for Intel i7 Core memory controllers - " | |
2095 | I7CORE_REVISION); | |
2096 | ||
2097 | module_param(edac_op_state, int, 0444); | |
2098 | MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); |