Commit | Line | Data |
---|---|---|
0d88a10e AC |
1 | /* |
2 | * Intel D82875P Memory Controller kernel module | |
3 | * (C) 2003 Linux Networx (http://lnxi.com) | |
4 | * This file may be distributed under the terms of the | |
5 | * GNU General Public License. | |
6 | * | |
7 | * Written by Thayne Harbaugh | |
8 | * Contributors: | |
9 | * Wang Zhenyu at intel.com | |
10 | * | |
11 | * $Id: edac_i82875p.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $ | |
12 | * | |
13 | * Note: E7210 appears same as D82875P - zhenyu.z.wang at intel.com | |
14 | */ | |
15 | ||
0d88a10e AC |
16 | #include <linux/module.h> |
17 | #include <linux/init.h> | |
0d88a10e AC |
18 | #include <linux/pci.h> |
19 | #include <linux/pci_ids.h> | |
0d88a10e | 20 | #include <linux/slab.h> |
0d88a10e AC |
21 | #include "edac_mc.h" |
22 | ||
929a40ec DT |
23 | #define I82875P_REVISION " Ver: 2.0.1 " __DATE__ |
24 | #define EDAC_MOD_STR "i82875p_edac" | |
37f04581 | 25 | |
537fba28 | 26 | #define i82875p_printk(level, fmt, arg...) \ |
e7ecd891 | 27 | edac_printk(level, "i82875p", fmt, ##arg) |
537fba28 DP |
28 | |
29 | #define i82875p_mc_printk(mci, level, fmt, arg...) \ | |
e7ecd891 | 30 | edac_mc_chipset_printk(mci, level, "i82875p", fmt, ##arg) |
537fba28 | 31 | |
0d88a10e AC |
32 | #ifndef PCI_DEVICE_ID_INTEL_82875_0 |
33 | #define PCI_DEVICE_ID_INTEL_82875_0 0x2578 | |
34 | #endif /* PCI_DEVICE_ID_INTEL_82875_0 */ | |
35 | ||
36 | #ifndef PCI_DEVICE_ID_INTEL_82875_6 | |
37 | #define PCI_DEVICE_ID_INTEL_82875_6 0x257e | |
38 | #endif /* PCI_DEVICE_ID_INTEL_82875_6 */ | |
39 | ||
0d88a10e AC |
40 | /* four csrows in dual channel, eight in single channel */ |
41 | #define I82875P_NR_CSROWS(nr_chans) (8/(nr_chans)) | |
42 | ||
0d88a10e AC |
43 | /* Intel 82875p register addresses - device 0 function 0 - DRAM Controller */ |
44 | #define I82875P_EAP 0x58 /* Error Address Pointer (32b) | |
45 | * | |
46 | * 31:12 block address | |
47 | * 11:0 reserved | |
48 | */ | |
49 | ||
50 | #define I82875P_DERRSYN 0x5c /* DRAM Error Syndrome (8b) | |
51 | * | |
52 | * 7:0 DRAM ECC Syndrome | |
53 | */ | |
54 | ||
55 | #define I82875P_DES 0x5d /* DRAM Error Status (8b) | |
56 | * | |
57 | * 7:1 reserved | |
58 | * 0 Error channel 0/1 | |
59 | */ | |
60 | ||
61 | #define I82875P_ERRSTS 0xc8 /* Error Status Register (16b) | |
62 | * | |
63 | * 15:10 reserved | |
64 | * 9 non-DRAM lock error (ndlock) | |
65 | * 8 Sftwr Generated SMI | |
66 | * 7 ECC UE | |
67 | * 6 reserved | |
68 | * 5 MCH detects unimplemented cycle | |
69 | * 4 AGP access outside GA | |
70 | * 3 Invalid AGP access | |
71 | * 2 Invalid GA translation table | |
72 | * 1 Unsupported AGP command | |
73 | * 0 ECC CE | |
74 | */ | |
75 | ||
76 | #define I82875P_ERRCMD 0xca /* Error Command (16b) | |
77 | * | |
78 | * 15:10 reserved | |
79 | * 9 SERR on non-DRAM lock | |
80 | * 8 SERR on ECC UE | |
81 | * 7 SERR on ECC CE | |
82 | * 6 target abort on high exception | |
83 | * 5 detect unimplemented cyc | |
84 | * 4 AGP access outside of GA | |
85 | * 3 SERR on invalid AGP access | |
86 | * 2 invalid translation table | |
87 | * 1 SERR on unsupported AGP command | |
88 | * 0 reserved | |
89 | */ | |
90 | ||
0d88a10e AC |
91 | /* Intel 82875p register addresses - device 6 function 0 - DRAM Controller */ |
92 | #define I82875P_PCICMD6 0x04 /* PCI Command Register (16b) | |
93 | * | |
94 | * 15:10 reserved | |
95 | * 9 fast back-to-back - ro 0 | |
96 | * 8 SERR enable - ro 0 | |
97 | * 7 addr/data stepping - ro 0 | |
98 | * 6 parity err enable - ro 0 | |
99 | * 5 VGA palette snoop - ro 0 | |
100 | * 4 mem wr & invalidate - ro 0 | |
101 | * 3 special cycle - ro 0 | |
102 | * 2 bus master - ro 0 | |
103 | * 1 mem access dev6 - 0(dis),1(en) | |
104 | * 0 IO access dev3 - 0(dis),1(en) | |
105 | */ | |
106 | ||
107 | #define I82875P_BAR6 0x10 /* Mem Delays Base ADDR Reg (32b) | |
108 | * | |
109 | * 31:12 mem base addr [31:12] | |
110 | * 11:4 address mask - ro 0 | |
111 | * 3 prefetchable - ro 0(non),1(pre) | |
112 | * 2:1 mem type - ro 0 | |
113 | * 0 mem space - ro 0 | |
114 | */ | |
115 | ||
116 | /* Intel 82875p MMIO register space - device 0 function 0 - MMR space */ | |
117 | ||
118 | #define I82875P_DRB_SHIFT 26 /* 64MiB grain */ | |
119 | #define I82875P_DRB 0x00 /* DRAM Row Boundary (8b x 8) | |
120 | * | |
121 | * 7 reserved | |
122 | * 6:0 64MiB row boundary addr | |
123 | */ | |
124 | ||
125 | #define I82875P_DRA 0x10 /* DRAM Row Attribute (4b x 8) | |
126 | * | |
127 | * 7 reserved | |
128 | * 6:4 row attr row 1 | |
129 | * 3 reserved | |
130 | * 2:0 row attr row 0 | |
131 | * | |
132 | * 000 = 4KiB | |
133 | * 001 = 8KiB | |
134 | * 010 = 16KiB | |
135 | * 011 = 32KiB | |
136 | */ | |
137 | ||
138 | #define I82875P_DRC 0x68 /* DRAM Controller Mode (32b) | |
139 | * | |
140 | * 31:30 reserved | |
141 | * 29 init complete | |
142 | * 28:23 reserved | |
143 | * 22:21 nr chan 00=1,01=2 | |
144 | * 20 reserved | |
145 | * 19:18 Data Integ Mode 00=none,01=ecc | |
146 | * 17:11 reserved | |
147 | * 10:8 refresh mode | |
148 | * 7 reserved | |
149 | * 6:4 mode select | |
150 | * 3:2 reserved | |
151 | * 1:0 DRAM type 01=DDR | |
152 | */ | |
153 | ||
0d88a10e AC |
154 | enum i82875p_chips { |
155 | I82875P = 0, | |
156 | }; | |
157 | ||
0d88a10e AC |
158 | struct i82875p_pvt { |
159 | struct pci_dev *ovrfl_pdev; | |
6d57348d | 160 | void __iomem *ovrfl_window; |
0d88a10e AC |
161 | }; |
162 | ||
0d88a10e AC |
163 | struct i82875p_dev_info { |
164 | const char *ctl_name; | |
165 | }; | |
166 | ||
0d88a10e AC |
167 | struct i82875p_error_info { |
168 | u16 errsts; | |
169 | u32 eap; | |
170 | u8 des; | |
171 | u8 derrsyn; | |
172 | u16 errsts2; | |
173 | }; | |
174 | ||
0d88a10e AC |
175 | static const struct i82875p_dev_info i82875p_devs[] = { |
176 | [I82875P] = { | |
e7ecd891 DP |
177 | .ctl_name = "i82875p" |
178 | }, | |
0d88a10e AC |
179 | }; |
180 | ||
e7ecd891 DP |
181 | static struct pci_dev *mci_pdev = NULL; /* init dev: in case that AGP code has |
182 | * already registered driver | |
183 | */ | |
184 | ||
0d88a10e AC |
185 | static int i82875p_registered = 1; |
186 | ||
e7ecd891 | 187 | static void i82875p_get_error_info(struct mem_ctl_info *mci, |
0d88a10e AC |
188 | struct i82875p_error_info *info) |
189 | { | |
37f04581 DT |
190 | struct pci_dev *pdev; |
191 | ||
192 | pdev = to_pci_dev(mci->dev); | |
193 | ||
0d88a10e AC |
194 | /* |
195 | * This is a mess because there is no atomic way to read all the | |
196 | * registers at once and the registers can transition from CE being | |
197 | * overwritten by UE. | |
198 | */ | |
37f04581 DT |
199 | pci_read_config_word(pdev, I82875P_ERRSTS, &info->errsts); |
200 | pci_read_config_dword(pdev, I82875P_EAP, &info->eap); | |
201 | pci_read_config_byte(pdev, I82875P_DES, &info->des); | |
202 | pci_read_config_byte(pdev, I82875P_DERRSYN, &info->derrsyn); | |
203 | pci_read_config_word(pdev, I82875P_ERRSTS, &info->errsts2); | |
0d88a10e | 204 | |
37f04581 | 205 | pci_write_bits16(pdev, I82875P_ERRSTS, 0x0081, 0x0081); |
0d88a10e AC |
206 | |
207 | /* | |
208 | * If the error is the same then we can for both reads then | |
209 | * the first set of reads is valid. If there is a change then | |
210 | * there is a CE no info and the second set of reads is valid | |
211 | * and should be UE info. | |
212 | */ | |
213 | if (!(info->errsts2 & 0x0081)) | |
214 | return; | |
e7ecd891 | 215 | |
0d88a10e | 216 | if ((info->errsts ^ info->errsts2) & 0x0081) { |
37f04581 DT |
217 | pci_read_config_dword(pdev, I82875P_EAP, &info->eap); |
218 | pci_read_config_byte(pdev, I82875P_DES, &info->des); | |
219 | pci_read_config_byte(pdev, I82875P_DERRSYN, | |
e7ecd891 | 220 | &info->derrsyn); |
0d88a10e AC |
221 | } |
222 | } | |
223 | ||
e7ecd891 | 224 | static int i82875p_process_error_info(struct mem_ctl_info *mci, |
0d88a10e AC |
225 | struct i82875p_error_info *info, int handle_errors) |
226 | { | |
227 | int row, multi_chan; | |
228 | ||
229 | multi_chan = mci->csrows[0].nr_channels - 1; | |
230 | ||
231 | if (!(info->errsts2 & 0x0081)) | |
232 | return 0; | |
233 | ||
234 | if (!handle_errors) | |
235 | return 1; | |
236 | ||
237 | if ((info->errsts ^ info->errsts2) & 0x0081) { | |
238 | edac_mc_handle_ce_no_info(mci, "UE overwrote CE"); | |
239 | info->errsts = info->errsts2; | |
240 | } | |
241 | ||
242 | info->eap >>= PAGE_SHIFT; | |
243 | row = edac_mc_find_csrow_by_page(mci, info->eap); | |
244 | ||
245 | if (info->errsts & 0x0080) | |
246 | edac_mc_handle_ue(mci, info->eap, 0, row, "i82875p UE"); | |
247 | else | |
248 | edac_mc_handle_ce(mci, info->eap, 0, info->derrsyn, row, | |
e7ecd891 DP |
249 | multi_chan ? (info->des & 0x1) : 0, |
250 | "i82875p CE"); | |
0d88a10e AC |
251 | |
252 | return 1; | |
253 | } | |
254 | ||
0d88a10e AC |
255 | static void i82875p_check(struct mem_ctl_info *mci) |
256 | { | |
257 | struct i82875p_error_info info; | |
258 | ||
537fba28 | 259 | debugf1("MC%d: %s()\n", mci->mc_idx, __func__); |
0d88a10e AC |
260 | i82875p_get_error_info(mci, &info); |
261 | i82875p_process_error_info(mci, &info, 1); | |
262 | } | |
263 | ||
0d88a10e AC |
264 | #ifdef CONFIG_PROC_FS |
265 | extern int pci_proc_attach_device(struct pci_dev *); | |
266 | #endif | |
267 | ||
13189525 DT |
268 | /* Return 0 on success or 1 on failure. */ |
269 | static int i82875p_setup_overfl_dev(struct pci_dev *pdev, | |
270 | struct pci_dev **ovrfl_pdev, void __iomem **ovrfl_window) | |
0d88a10e | 271 | { |
13189525 DT |
272 | struct pci_dev *dev; |
273 | void __iomem *window; | |
0d88a10e | 274 | |
13189525 DT |
275 | *ovrfl_pdev = NULL; |
276 | *ovrfl_window = NULL; | |
277 | dev = pci_get_device(PCI_VEND_DEV(INTEL, 82875_6), NULL); | |
0d88a10e | 278 | |
13189525 DT |
279 | if (dev == NULL) { |
280 | /* Intel tells BIOS developers to hide device 6 which | |
0d88a10e AC |
281 | * configures the overflow device access containing |
282 | * the DRBs - this is where we expose device 6. | |
283 | * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm | |
284 | */ | |
285 | pci_write_bits8(pdev, 0xf4, 0x2, 0x2); | |
13189525 | 286 | dev = pci_scan_single_device(pdev->bus, PCI_DEVFN(6, 0)); |
e7ecd891 | 287 | |
13189525 DT |
288 | if (dev == NULL) |
289 | return 1; | |
0d88a10e | 290 | } |
e7ecd891 | 291 | |
13189525 DT |
292 | *ovrfl_pdev = dev; |
293 | ||
0d88a10e | 294 | #ifdef CONFIG_PROC_FS |
13189525 DT |
295 | if ((dev->procent == NULL) && pci_proc_attach_device(dev)) { |
296 | i82875p_printk(KERN_ERR, "%s(): Failed to attach overflow " | |
297 | "device\n", __func__); | |
298 | return 1; | |
0d88a10e | 299 | } |
13189525 DT |
300 | #endif /* CONFIG_PROC_FS */ |
301 | if (pci_enable_device(dev)) { | |
302 | i82875p_printk(KERN_ERR, "%s(): Failed to enable overflow " | |
303 | "device\n", __func__); | |
304 | return 1; | |
0d88a10e AC |
305 | } |
306 | ||
13189525 | 307 | if (pci_request_regions(dev, pci_name(dev))) { |
0d88a10e | 308 | #ifdef CORRECT_BIOS |
637beb69 | 309 | goto fail0; |
0d88a10e AC |
310 | #endif |
311 | } | |
e7ecd891 | 312 | |
0d88a10e | 313 | /* cache is irrelevant for PCI bus reads/writes */ |
13189525 DT |
314 | window = ioremap_nocache(pci_resource_start(dev, 0), |
315 | pci_resource_len(dev, 0)); | |
0d88a10e | 316 | |
13189525 | 317 | if (window == NULL) { |
537fba28 | 318 | i82875p_printk(KERN_ERR, "%s(): Failed to ioremap bar6\n", |
13189525 | 319 | __func__); |
637beb69 | 320 | goto fail1; |
0d88a10e AC |
321 | } |
322 | ||
13189525 DT |
323 | *ovrfl_window = window; |
324 | return 0; | |
0d88a10e | 325 | |
13189525 DT |
326 | fail1: |
327 | pci_release_regions(dev); | |
0d88a10e | 328 | |
13189525 DT |
329 | #ifdef CORRECT_BIOS |
330 | fail0: | |
331 | pci_disable_device(dev); | |
332 | #endif | |
333 | /* NOTE: the ovrfl proc entry and pci_dev are intentionally left */ | |
334 | return 1; | |
335 | } | |
0d88a10e | 336 | |
0d88a10e | 337 | |
13189525 DT |
338 | /* Return 1 if dual channel mode is active. Else return 0. */ |
339 | static inline int dual_channel_active(u32 drc) | |
340 | { | |
341 | return (drc >> 21) & 0x1; | |
342 | } | |
0d88a10e | 343 | |
13189525 DT |
344 | |
345 | static void i82875p_init_csrows(struct mem_ctl_info *mci, | |
346 | struct pci_dev *pdev, void __iomem *ovrfl_window, u32 drc) | |
347 | { | |
348 | struct csrow_info *csrow; | |
349 | unsigned long last_cumul_size; | |
350 | u8 value; | |
351 | u32 drc_ddim; /* DRAM Data Integrity Mode 0=none,2=edac */ | |
352 | u32 cumul_size; | |
353 | int index; | |
354 | ||
355 | drc_ddim = (drc >> 18) & 0x1; | |
356 | last_cumul_size = 0; | |
357 | ||
358 | /* The dram row boundary (DRB) reg values are boundary address | |
0d88a10e AC |
359 | * for each DRAM row with a granularity of 32 or 64MB (single/dual |
360 | * channel operation). DRB regs are cumulative; therefore DRB7 will | |
361 | * contain the total memory contained in all eight rows. | |
362 | */ | |
13189525 DT |
363 | |
364 | for (index = 0; index < mci->nr_csrows; index++) { | |
365 | csrow = &mci->csrows[index]; | |
0d88a10e AC |
366 | |
367 | value = readb(ovrfl_window + I82875P_DRB + index); | |
368 | cumul_size = value << (I82875P_DRB_SHIFT - PAGE_SHIFT); | |
537fba28 DP |
369 | debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index, |
370 | cumul_size); | |
0d88a10e AC |
371 | if (cumul_size == last_cumul_size) |
372 | continue; /* not populated */ | |
373 | ||
374 | csrow->first_page = last_cumul_size; | |
375 | csrow->last_page = cumul_size - 1; | |
376 | csrow->nr_pages = cumul_size - last_cumul_size; | |
377 | last_cumul_size = cumul_size; | |
13189525 | 378 | csrow->grain = 1 << 12; /* I82875P_EAP has 4KiB reolution */ |
0d88a10e AC |
379 | csrow->mtype = MEM_DDR; |
380 | csrow->dtype = DEV_UNKNOWN; | |
381 | csrow->edac_mode = drc_ddim ? EDAC_SECDED : EDAC_NONE; | |
382 | } | |
13189525 DT |
383 | } |
384 | ||
385 | static int i82875p_probe1(struct pci_dev *pdev, int dev_idx) | |
386 | { | |
387 | int rc = -ENODEV; | |
388 | struct mem_ctl_info *mci; | |
389 | struct i82875p_pvt *pvt; | |
390 | struct pci_dev *ovrfl_pdev; | |
391 | void __iomem *ovrfl_window; | |
392 | u32 drc; | |
393 | u32 nr_chans; | |
394 | struct i82875p_error_info discard; | |
0d88a10e | 395 | |
13189525 DT |
396 | debugf0("%s()\n", __func__); |
397 | ovrfl_pdev = pci_get_device(PCI_VEND_DEV(INTEL, 82875_6), NULL); | |
398 | ||
399 | if (i82875p_setup_overfl_dev(pdev, &ovrfl_pdev, &ovrfl_window)) | |
400 | return -ENODEV; | |
401 | drc = readl(ovrfl_window + I82875P_DRC); | |
402 | nr_chans = dual_channel_active(drc) + 1; | |
403 | mci = edac_mc_alloc(sizeof(*pvt), I82875P_NR_CSROWS(nr_chans), | |
404 | nr_chans); | |
405 | ||
406 | if (!mci) { | |
407 | rc = -ENOMEM; | |
408 | goto fail0; | |
409 | } | |
410 | ||
411 | debugf3("%s(): init mci\n", __func__); | |
412 | mci->dev = &pdev->dev; | |
413 | mci->mtype_cap = MEM_FLAG_DDR; | |
414 | mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; | |
415 | mci->edac_cap = EDAC_FLAG_UNKNOWN; | |
416 | mci->mod_name = EDAC_MOD_STR; | |
417 | mci->mod_ver = I82875P_REVISION; | |
418 | mci->ctl_name = i82875p_devs[dev_idx].ctl_name; | |
419 | mci->edac_check = i82875p_check; | |
420 | mci->ctl_page_to_phys = NULL; | |
421 | debugf3("%s(): init pvt\n", __func__); | |
422 | pvt = (struct i82875p_pvt *) mci->pvt_info; | |
423 | pvt->ovrfl_pdev = ovrfl_pdev; | |
424 | pvt->ovrfl_window = ovrfl_window; | |
425 | i82875p_init_csrows(mci, pdev, ovrfl_window, drc); | |
749ede57 | 426 | i82875p_get_error_info(mci, &discard); /* clear counters */ |
0d88a10e | 427 | |
2d7bbb91 DT |
428 | /* Here we assume that we will never see multiple instances of this |
429 | * type of memory controller. The ID is therefore hardcoded to 0. | |
430 | */ | |
431 | if (edac_mc_add_mc(mci,0)) { | |
537fba28 | 432 | debugf3("%s(): failed edac_mc_add_mc()\n", __func__); |
13189525 | 433 | goto fail1; |
0d88a10e AC |
434 | } |
435 | ||
436 | /* get this far and it's successful */ | |
537fba28 | 437 | debugf3("%s(): success\n", __func__); |
0d88a10e AC |
438 | return 0; |
439 | ||
13189525 | 440 | fail1: |
637beb69 | 441 | edac_mc_free(mci); |
0d88a10e | 442 | |
13189525 | 443 | fail0: |
637beb69 | 444 | iounmap(ovrfl_window); |
637beb69 | 445 | pci_release_regions(ovrfl_pdev); |
0d88a10e | 446 | |
637beb69 | 447 | pci_disable_device(ovrfl_pdev); |
0d88a10e AC |
448 | /* NOTE: the ovrfl proc entry and pci_dev are intentionally left */ |
449 | return rc; | |
450 | } | |
451 | ||
0d88a10e AC |
452 | /* returns count (>= 0), or negative on error */ |
453 | static int __devinit i82875p_init_one(struct pci_dev *pdev, | |
e7ecd891 | 454 | const struct pci_device_id *ent) |
0d88a10e AC |
455 | { |
456 | int rc; | |
457 | ||
537fba28 | 458 | debugf0("%s()\n", __func__); |
537fba28 | 459 | i82875p_printk(KERN_INFO, "i82875p init one\n"); |
e7ecd891 DP |
460 | |
461 | if (pci_enable_device(pdev) < 0) | |
0d88a10e | 462 | return -EIO; |
e7ecd891 | 463 | |
0d88a10e | 464 | rc = i82875p_probe1(pdev, ent->driver_data); |
e7ecd891 | 465 | |
0d88a10e AC |
466 | if (mci_pdev == NULL) |
467 | mci_pdev = pci_dev_get(pdev); | |
e7ecd891 | 468 | |
0d88a10e AC |
469 | return rc; |
470 | } | |
471 | ||
0d88a10e AC |
472 | static void __devexit i82875p_remove_one(struct pci_dev *pdev) |
473 | { | |
474 | struct mem_ctl_info *mci; | |
475 | struct i82875p_pvt *pvt = NULL; | |
476 | ||
537fba28 | 477 | debugf0("%s()\n", __func__); |
0d88a10e | 478 | |
37f04581 | 479 | if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL) |
0d88a10e AC |
480 | return; |
481 | ||
482 | pvt = (struct i82875p_pvt *) mci->pvt_info; | |
e7ecd891 | 483 | |
0d88a10e AC |
484 | if (pvt->ovrfl_window) |
485 | iounmap(pvt->ovrfl_window); | |
486 | ||
487 | if (pvt->ovrfl_pdev) { | |
488 | #ifdef CORRECT_BIOS | |
489 | pci_release_regions(pvt->ovrfl_pdev); | |
490 | #endif /*CORRECT_BIOS */ | |
491 | pci_disable_device(pvt->ovrfl_pdev); | |
492 | pci_dev_put(pvt->ovrfl_pdev); | |
493 | } | |
494 | ||
0d88a10e AC |
495 | edac_mc_free(mci); |
496 | } | |
497 | ||
0d88a10e | 498 | static const struct pci_device_id i82875p_pci_tbl[] __devinitdata = { |
e7ecd891 DP |
499 | { |
500 | PCI_VEND_DEV(INTEL, 82875_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
501 | I82875P | |
502 | }, | |
503 | { | |
504 | 0, | |
505 | } /* 0 terminated list. */ | |
0d88a10e AC |
506 | }; |
507 | ||
508 | MODULE_DEVICE_TABLE(pci, i82875p_pci_tbl); | |
509 | ||
0d88a10e | 510 | static struct pci_driver i82875p_driver = { |
680cbbbb | 511 | .name = EDAC_MOD_STR, |
0d88a10e AC |
512 | .probe = i82875p_init_one, |
513 | .remove = __devexit_p(i82875p_remove_one), | |
514 | .id_table = i82875p_pci_tbl, | |
515 | }; | |
516 | ||
da9bb1d2 | 517 | static int __init i82875p_init(void) |
0d88a10e AC |
518 | { |
519 | int pci_rc; | |
520 | ||
537fba28 | 521 | debugf3("%s()\n", __func__); |
0d88a10e | 522 | pci_rc = pci_register_driver(&i82875p_driver); |
e7ecd891 | 523 | |
0d88a10e | 524 | if (pci_rc < 0) |
637beb69 | 525 | goto fail0; |
e7ecd891 | 526 | |
0d88a10e | 527 | if (mci_pdev == NULL) { |
e7ecd891 DP |
528 | mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL, |
529 | PCI_DEVICE_ID_INTEL_82875_0, NULL); | |
530 | ||
0d88a10e AC |
531 | if (!mci_pdev) { |
532 | debugf0("875p pci_get_device fail\n"); | |
637beb69 DP |
533 | pci_rc = -ENODEV; |
534 | goto fail1; | |
0d88a10e | 535 | } |
e7ecd891 | 536 | |
0d88a10e | 537 | pci_rc = i82875p_init_one(mci_pdev, i82875p_pci_tbl); |
e7ecd891 | 538 | |
0d88a10e AC |
539 | if (pci_rc < 0) { |
540 | debugf0("875p init fail\n"); | |
637beb69 DP |
541 | pci_rc = -ENODEV; |
542 | goto fail1; | |
0d88a10e AC |
543 | } |
544 | } | |
e7ecd891 | 545 | |
0d88a10e | 546 | return 0; |
637beb69 DP |
547 | |
548 | fail1: | |
549 | pci_unregister_driver(&i82875p_driver); | |
550 | ||
551 | fail0: | |
552 | if (mci_pdev != NULL) | |
553 | pci_dev_put(mci_pdev); | |
554 | ||
555 | return pci_rc; | |
0d88a10e AC |
556 | } |
557 | ||
0d88a10e AC |
558 | static void __exit i82875p_exit(void) |
559 | { | |
537fba28 | 560 | debugf3("%s()\n", __func__); |
0d88a10e AC |
561 | |
562 | pci_unregister_driver(&i82875p_driver); | |
e7ecd891 | 563 | |
0d88a10e AC |
564 | if (!i82875p_registered) { |
565 | i82875p_remove_one(mci_pdev); | |
566 | pci_dev_put(mci_pdev); | |
567 | } | |
568 | } | |
569 | ||
0d88a10e AC |
570 | module_init(i82875p_init); |
571 | module_exit(i82875p_exit); | |
572 | ||
0d88a10e AC |
573 | MODULE_LICENSE("GPL"); |
574 | MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh"); | |
575 | MODULE_DESCRIPTION("MC support for Intel 82875 memory hub controllers"); |