Commit | Line | Data |
---|---|---|
b70ef010 | 1 | #include <linux/module.h> |
888ab8e6 BP |
2 | #include <linux/slab.h> |
3 | ||
47ca08a4 | 4 | #include "mce_amd.h" |
b52401ce | 5 | |
888ab8e6 BP |
6 | static struct amd_decoder_ops *fam_ops; |
7 | ||
2be64bfa | 8 | static u8 xec_mask = 0xf; |
5ce88f6e BP |
9 | static u8 nb_err_cpumask = 0xf; |
10 | ||
549d042d | 11 | static bool report_gart_errors; |
b0b07a2b | 12 | static void (*nb_bus_decoder)(int node_id, struct mce *m); |
549d042d BP |
13 | |
14 | void amd_report_gart_errors(bool v) | |
15 | { | |
16 | report_gart_errors = v; | |
17 | } | |
18 | EXPORT_SYMBOL_GPL(amd_report_gart_errors); | |
19 | ||
b0b07a2b | 20 | void amd_register_ecc_decoder(void (*f)(int, struct mce *)) |
549d042d BP |
21 | { |
22 | nb_bus_decoder = f; | |
23 | } | |
24 | EXPORT_SYMBOL_GPL(amd_register_ecc_decoder); | |
25 | ||
b0b07a2b | 26 | void amd_unregister_ecc_decoder(void (*f)(int, struct mce *)) |
549d042d BP |
27 | { |
28 | if (nb_bus_decoder) { | |
29 | WARN_ON(nb_bus_decoder != f); | |
30 | ||
31 | nb_bus_decoder = NULL; | |
32 | } | |
33 | } | |
34 | EXPORT_SYMBOL_GPL(amd_unregister_ecc_decoder); | |
35 | ||
b52401ce DT |
36 | /* |
37 | * string representation for the different MCA reported error types, see F3x48 | |
38 | * or MSR0000_0411. | |
39 | */ | |
6337583d BP |
40 | |
41 | /* transaction type */ | |
ebe2aea8 | 42 | const char * const tt_msgs[] = { "INSN", "DATA", "GEN", "RESV" }; |
b70ef010 | 43 | EXPORT_SYMBOL_GPL(tt_msgs); |
b52401ce | 44 | |
6337583d | 45 | /* cache level */ |
ebe2aea8 | 46 | const char * const ll_msgs[] = { "RESV", "L1", "L2", "L3/GEN" }; |
b70ef010 | 47 | EXPORT_SYMBOL_GPL(ll_msgs); |
b52401ce | 48 | |
6337583d | 49 | /* memory transaction type */ |
ebe2aea8 | 50 | const char * const rrrr_msgs[] = { |
6337583d | 51 | "GEN", "RD", "WR", "DRD", "DWR", "IRD", "PRF", "EV", "SNP" |
b52401ce | 52 | }; |
b70ef010 | 53 | EXPORT_SYMBOL_GPL(rrrr_msgs); |
b52401ce | 54 | |
6337583d | 55 | /* participating processor */ |
ebe2aea8 | 56 | const char * const pp_msgs[] = { "SRC", "RES", "OBS", "GEN" }; |
b70ef010 | 57 | EXPORT_SYMBOL_GPL(pp_msgs); |
b52401ce | 58 | |
6337583d | 59 | /* request timeout */ |
ebe2aea8 | 60 | const char * const to_msgs[] = { "no timeout", "timed out" }; |
b70ef010 | 61 | EXPORT_SYMBOL_GPL(to_msgs); |
b52401ce | 62 | |
6337583d | 63 | /* memory or i/o */ |
ebe2aea8 | 64 | const char * const ii_msgs[] = { "MEM", "RESV", "IO", "GEN" }; |
b70ef010 | 65 | EXPORT_SYMBOL_GPL(ii_msgs); |
b52401ce | 66 | |
980eec8b JS |
67 | /* internal error type */ |
68 | const char * const uu_msgs[] = { "RESV", "RESV", "HWA", "RESV" }; | |
69 | ||
f05c41a9 | 70 | static const char * const f15h_mc1_mce_desc[] = { |
86039cd4 BP |
71 | "UC during a demand linefill from L2", |
72 | "Parity error during data load from IC", | |
73 | "Parity error for IC valid bit", | |
74 | "Main tag parity error", | |
75 | "Parity error in prediction queue", | |
76 | "PFB data/address parity error", | |
77 | "Parity error in the branch status reg", | |
78 | "PFB promotion address error", | |
79 | "Tag error during probe/victimization", | |
80 | "Parity error for IC probe tag valid bit", | |
81 | "PFB non-cacheable bit parity error", | |
82 | "PFB valid bit parity error", /* xec = 0xd */ | |
6c1173a6 | 83 | "Microcode Patch Buffer", /* xec = 010 */ |
86039cd4 BP |
84 | "uop queue", |
85 | "insn buffer", | |
86 | "predecode buffer", | |
87 | "fetch address FIFO" | |
88 | }; | |
89 | ||
f05c41a9 | 90 | static const char * const f15h_mc2_mce_desc[] = { |
70fdb494 BP |
91 | "Fill ECC error on data fills", /* xec = 0x4 */ |
92 | "Fill parity error on insn fills", | |
93 | "Prefetcher request FIFO parity error", | |
94 | "PRQ address parity error", | |
95 | "PRQ data parity error", | |
96 | "WCC Tag ECC error", | |
97 | "WCC Data ECC error", | |
98 | "WCB Data parity error", | |
b64a99c1 | 99 | "VB Data ECC or parity error", |
70fdb494 BP |
100 | "L2 Tag ECC error", /* xec = 0x10 */ |
101 | "Hard L2 Tag ECC error", | |
102 | "Multiple hits on L2 tag", | |
103 | "XAB parity error", | |
104 | "PRB address parity error" | |
105 | }; | |
106 | ||
f05c41a9 | 107 | static const char * const mc4_mce_desc[] = { |
68782673 BP |
108 | "DRAM ECC error detected on the NB", |
109 | "CRC error detected on HT link", | |
110 | "Link-defined sync error packets detected on HT link", | |
111 | "HT Master abort", | |
112 | "HT Target abort", | |
113 | "Invalid GART PTE entry during GART table walk", | |
114 | "Unsupported atomic RMW received from an IO link", | |
115 | "Watchdog timeout due to lack of progress", | |
116 | "DRAM ECC error detected on the NB", | |
117 | "SVM DMA Exclusion Vector error", | |
118 | "HT data error detected on link", | |
119 | "Protocol error (link, L3, probe filter)", | |
120 | "NB internal arrays parity error", | |
121 | "DRAM addr/ctl signals parity error", | |
122 | "IO link transmission error", | |
123 | "L3 data cache ECC error", /* xec = 0x1c */ | |
124 | "L3 cache tag error", | |
125 | "L3 LRU parity bits error", | |
126 | "ECC Error in the Probe Filter directory" | |
127 | }; | |
128 | ||
f05c41a9 | 129 | static const char * const mc5_mce_desc[] = { |
8259a7e5 BP |
130 | "CPU Watchdog timer expire", |
131 | "Wakeup array dest tag", | |
132 | "AG payload array", | |
133 | "EX payload array", | |
134 | "IDRF array", | |
135 | "Retire dispatch queue", | |
136 | "Mapper checkpoint array", | |
137 | "Physical register file EX0 port", | |
138 | "Physical register file EX1 port", | |
139 | "Physical register file AG0 port", | |
140 | "Physical register file AG1 port", | |
141 | "Flag register file", | |
ae615b4b | 142 | "DE error occurred" |
8259a7e5 BP |
143 | }; |
144 | ||
f05c41a9 | 145 | static bool f12h_mc0_mce(u16 ec, u8 xec) |
51966241 | 146 | { |
888ab8e6 | 147 | bool ret = false; |
51966241 | 148 | |
888ab8e6 | 149 | if (MEM_ERROR(ec)) { |
62452882 | 150 | u8 ll = LL(ec); |
888ab8e6 | 151 | ret = true; |
51966241 | 152 | |
888ab8e6 BP |
153 | if (ll == LL_L2) |
154 | pr_cont("during L1 linefill from L2.\n"); | |
155 | else if (ll == LL_L1) | |
62452882 | 156 | pr_cont("Data/Tag %s error.\n", R4_MSG(ec)); |
888ab8e6 BP |
157 | else |
158 | ret = false; | |
159 | } | |
160 | return ret; | |
161 | } | |
51966241 | 162 | |
f05c41a9 | 163 | static bool f10h_mc0_mce(u16 ec, u8 xec) |
9be0bb10 | 164 | { |
62452882 | 165 | if (R4(ec) == R4_GEN && LL(ec) == LL_L1) { |
9be0bb10 BP |
166 | pr_cont("during data scrub.\n"); |
167 | return true; | |
168 | } | |
f05c41a9 | 169 | return f12h_mc0_mce(ec, xec); |
9be0bb10 BP |
170 | } |
171 | ||
f05c41a9 | 172 | static bool k8_mc0_mce(u16 ec, u8 xec) |
888ab8e6 BP |
173 | { |
174 | if (BUS_ERROR(ec)) { | |
175 | pr_cont("during system linefill.\n"); | |
176 | return true; | |
177 | } | |
51966241 | 178 | |
f05c41a9 | 179 | return f10h_mc0_mce(ec, xec); |
888ab8e6 BP |
180 | } |
181 | ||
980eec8b | 182 | static bool cat_mc0_mce(u16 ec, u8 xec) |
888ab8e6 | 183 | { |
62452882 | 184 | u8 r4 = R4(ec); |
888ab8e6 BP |
185 | bool ret = true; |
186 | ||
187 | if (MEM_ERROR(ec)) { | |
188 | ||
62452882 | 189 | if (TT(ec) != TT_DATA || LL(ec) != LL_L1) |
888ab8e6 BP |
190 | return false; |
191 | ||
192 | switch (r4) { | |
193 | case R4_DRD: | |
194 | case R4_DWR: | |
195 | pr_cont("Data/Tag parity error due to %s.\n", | |
196 | (r4 == R4_DRD ? "load/hw prf" : "store")); | |
197 | break; | |
198 | case R4_EVICT: | |
199 | pr_cont("Copyback parity error on a tag miss.\n"); | |
200 | break; | |
201 | case R4_SNOOP: | |
202 | pr_cont("Tag parity error during snoop.\n"); | |
203 | break; | |
204 | default: | |
205 | ret = false; | |
206 | } | |
207 | } else if (BUS_ERROR(ec)) { | |
208 | ||
62452882 | 209 | if ((II(ec) != II_MEM && II(ec) != II_IO) || LL(ec) != LL_LG) |
888ab8e6 BP |
210 | return false; |
211 | ||
212 | pr_cont("System read data error on a "); | |
213 | ||
214 | switch (r4) { | |
215 | case R4_RD: | |
216 | pr_cont("TLB reload.\n"); | |
217 | break; | |
218 | case R4_DWR: | |
219 | pr_cont("store.\n"); | |
220 | break; | |
221 | case R4_DRD: | |
222 | pr_cont("load.\n"); | |
223 | break; | |
224 | default: | |
225 | ret = false; | |
226 | } | |
227 | } else { | |
228 | ret = false; | |
229 | } | |
230 | ||
231 | return ret; | |
232 | } | |
233 | ||
f05c41a9 | 234 | static bool f15h_mc0_mce(u16 ec, u8 xec) |
25a4f8b0 BP |
235 | { |
236 | bool ret = true; | |
237 | ||
238 | if (MEM_ERROR(ec)) { | |
239 | ||
240 | switch (xec) { | |
241 | case 0x0: | |
242 | pr_cont("Data Array access error.\n"); | |
243 | break; | |
244 | ||
245 | case 0x1: | |
246 | pr_cont("UC error during a linefill from L2/NB.\n"); | |
247 | break; | |
248 | ||
249 | case 0x2: | |
250 | case 0x11: | |
251 | pr_cont("STQ access error.\n"); | |
252 | break; | |
253 | ||
254 | case 0x3: | |
255 | pr_cont("SCB access error.\n"); | |
256 | break; | |
257 | ||
258 | case 0x10: | |
259 | pr_cont("Tag error.\n"); | |
260 | break; | |
261 | ||
262 | case 0x12: | |
263 | pr_cont("LDQ access error.\n"); | |
264 | break; | |
265 | ||
266 | default: | |
267 | ret = false; | |
268 | } | |
269 | } else if (BUS_ERROR(ec)) { | |
270 | ||
271 | if (!xec) | |
344f0a06 | 272 | pr_cont("System Read Data Error.\n"); |
25a4f8b0 | 273 | else |
344f0a06 | 274 | pr_cont(" Internal error condition type %d.\n", xec); |
25a4f8b0 BP |
275 | } else |
276 | ret = false; | |
277 | ||
278 | return ret; | |
279 | } | |
280 | ||
f05c41a9 | 281 | static void decode_mc0_mce(struct mce *m) |
888ab8e6 | 282 | { |
62452882 BP |
283 | u16 ec = EC(m->status); |
284 | u8 xec = XEC(m->status, xec_mask); | |
888ab8e6 | 285 | |
f05c41a9 | 286 | pr_emerg(HW_ERR "MC0 Error: "); |
888ab8e6 BP |
287 | |
288 | /* TLB error signatures are the same across families */ | |
289 | if (TLB_ERROR(ec)) { | |
62452882 | 290 | if (TT(ec) == TT_DATA) { |
888ab8e6 | 291 | pr_cont("%s TLB %s.\n", LL_MSG(ec), |
25a4f8b0 BP |
292 | ((xec == 2) ? "locked miss" |
293 | : (xec ? "multimatch" : "parity"))); | |
888ab8e6 BP |
294 | return; |
295 | } | |
f05c41a9 | 296 | } else if (fam_ops->mc0_mce(ec, xec)) |
25a4f8b0 BP |
297 | ; |
298 | else | |
f05c41a9 | 299 | pr_emerg(HW_ERR "Corrupted MC0 MCE info?\n"); |
51966241 BP |
300 | } |
301 | ||
f05c41a9 | 302 | static bool k8_mc1_mce(u16 ec, u8 xec) |
ab5535e7 | 303 | { |
62452882 | 304 | u8 ll = LL(ec); |
dd53bce4 | 305 | bool ret = true; |
ab5535e7 | 306 | |
dd53bce4 BP |
307 | if (!MEM_ERROR(ec)) |
308 | return false; | |
ab5535e7 | 309 | |
dd53bce4 BP |
310 | if (ll == 0x2) |
311 | pr_cont("during a linefill from L2.\n"); | |
312 | else if (ll == 0x1) { | |
62452882 | 313 | switch (R4(ec)) { |
dd53bce4 BP |
314 | case R4_IRD: |
315 | pr_cont("Parity error during data load.\n"); | |
316 | break; | |
ab5535e7 | 317 | |
dd53bce4 BP |
318 | case R4_EVICT: |
319 | pr_cont("Copyback Parity/Victim error.\n"); | |
320 | break; | |
321 | ||
322 | case R4_SNOOP: | |
323 | pr_cont("Tag Snoop error.\n"); | |
324 | break; | |
325 | ||
326 | default: | |
327 | ret = false; | |
328 | break; | |
329 | } | |
ab5535e7 | 330 | } else |
dd53bce4 | 331 | ret = false; |
ab5535e7 | 332 | |
dd53bce4 BP |
333 | return ret; |
334 | } | |
335 | ||
980eec8b | 336 | static bool cat_mc1_mce(u16 ec, u8 xec) |
dd53bce4 | 337 | { |
62452882 | 338 | u8 r4 = R4(ec); |
dd53bce4 | 339 | bool ret = true; |
ab5535e7 | 340 | |
980eec8b JS |
341 | if (!MEM_ERROR(ec)) |
342 | return false; | |
343 | ||
344 | if (TT(ec) != TT_INSTR) | |
345 | return false; | |
346 | ||
347 | if (r4 == R4_IRD) | |
348 | pr_cont("Data/tag array parity error for a tag hit.\n"); | |
349 | else if (r4 == R4_SNOOP) | |
350 | pr_cont("Tag error during snoop/victimization.\n"); | |
351 | else if (xec == 0x0) | |
352 | pr_cont("Tag parity error from victim castout.\n"); | |
353 | else if (xec == 0x2) | |
354 | pr_cont("Microcode patch RAM parity error.\n"); | |
355 | else | |
356 | ret = false; | |
dd53bce4 | 357 | |
dd53bce4 BP |
358 | return ret; |
359 | } | |
360 | ||
f05c41a9 | 361 | static bool f15h_mc1_mce(u16 ec, u8 xec) |
86039cd4 BP |
362 | { |
363 | bool ret = true; | |
364 | ||
365 | if (!MEM_ERROR(ec)) | |
366 | return false; | |
367 | ||
368 | switch (xec) { | |
369 | case 0x0 ... 0xa: | |
f05c41a9 | 370 | pr_cont("%s.\n", f15h_mc1_mce_desc[xec]); |
86039cd4 BP |
371 | break; |
372 | ||
373 | case 0xd: | |
f05c41a9 | 374 | pr_cont("%s.\n", f15h_mc1_mce_desc[xec-2]); |
86039cd4 BP |
375 | break; |
376 | ||
6c1173a6 | 377 | case 0x10: |
f05c41a9 | 378 | pr_cont("%s.\n", f15h_mc1_mce_desc[xec-4]); |
6c1173a6 BP |
379 | break; |
380 | ||
381 | case 0x11 ... 0x14: | |
f05c41a9 | 382 | pr_cont("Decoder %s parity error.\n", f15h_mc1_mce_desc[xec-4]); |
86039cd4 BP |
383 | break; |
384 | ||
385 | default: | |
386 | ret = false; | |
387 | } | |
388 | return ret; | |
389 | } | |
390 | ||
f05c41a9 | 391 | static void decode_mc1_mce(struct mce *m) |
dd53bce4 | 392 | { |
62452882 BP |
393 | u16 ec = EC(m->status); |
394 | u8 xec = XEC(m->status, xec_mask); | |
dd53bce4 | 395 | |
f05c41a9 | 396 | pr_emerg(HW_ERR "MC1 Error: "); |
dd53bce4 BP |
397 | |
398 | if (TLB_ERROR(ec)) | |
399 | pr_cont("%s TLB %s.\n", LL_MSG(ec), | |
400 | (xec ? "multimatch" : "parity error")); | |
401 | else if (BUS_ERROR(ec)) { | |
525906bc | 402 | bool k8 = (boot_cpu_data.x86 == 0xf && (m->status & BIT_64(58))); |
dd53bce4 BP |
403 | |
404 | pr_cont("during %s.\n", (k8 ? "system linefill" : "NB data read")); | |
f05c41a9 | 405 | } else if (fam_ops->mc1_mce(ec, xec)) |
dd53bce4 BP |
406 | ; |
407 | else | |
f05c41a9 | 408 | pr_emerg(HW_ERR "Corrupted MC1 MCE info?\n"); |
ab5535e7 BP |
409 | } |
410 | ||
4a73d3de | 411 | static bool k8_mc2_mce(u16 ec, u8 xec) |
56cad2d6 | 412 | { |
4a73d3de | 413 | bool ret = true; |
56cad2d6 BP |
414 | |
415 | if (xec == 0x1) | |
416 | pr_cont(" in the write data buffers.\n"); | |
417 | else if (xec == 0x3) | |
418 | pr_cont(" in the victim data buffers.\n"); | |
419 | else if (xec == 0x2 && MEM_ERROR(ec)) | |
62452882 | 420 | pr_cont(": %s error in the L2 cache tags.\n", R4_MSG(ec)); |
56cad2d6 BP |
421 | else if (xec == 0x0) { |
422 | if (TLB_ERROR(ec)) | |
423 | pr_cont(": %s error in a Page Descriptor Cache or " | |
424 | "Guest TLB.\n", TT_MSG(ec)); | |
425 | else if (BUS_ERROR(ec)) | |
426 | pr_cont(": %s/ECC error in data read from NB: %s.\n", | |
62452882 | 427 | R4_MSG(ec), PP_MSG(ec)); |
56cad2d6 | 428 | else if (MEM_ERROR(ec)) { |
62452882 | 429 | u8 r4 = R4(ec); |
56cad2d6 | 430 | |
62452882 | 431 | if (r4 >= 0x7) |
56cad2d6 | 432 | pr_cont(": %s error during data copyback.\n", |
62452882 BP |
433 | R4_MSG(ec)); |
434 | else if (r4 <= 0x1) | |
56cad2d6 | 435 | pr_cont(": %s parity/ECC error during data " |
62452882 | 436 | "access from L2.\n", R4_MSG(ec)); |
56cad2d6 | 437 | else |
4a73d3de | 438 | ret = false; |
56cad2d6 | 439 | } else |
4a73d3de | 440 | ret = false; |
56cad2d6 | 441 | } else |
4a73d3de | 442 | ret = false; |
56cad2d6 | 443 | |
4a73d3de | 444 | return ret; |
56cad2d6 BP |
445 | } |
446 | ||
4a73d3de | 447 | static bool f15h_mc2_mce(u16 ec, u8 xec) |
70fdb494 | 448 | { |
4a73d3de | 449 | bool ret = true; |
70fdb494 BP |
450 | |
451 | if (TLB_ERROR(ec)) { | |
452 | if (xec == 0x0) | |
453 | pr_cont("Data parity TLB read error.\n"); | |
454 | else if (xec == 0x1) | |
455 | pr_cont("Poison data provided for TLB fill.\n"); | |
456 | else | |
4a73d3de | 457 | ret = false; |
70fdb494 BP |
458 | } else if (BUS_ERROR(ec)) { |
459 | if (xec > 2) | |
4a73d3de | 460 | ret = false; |
70fdb494 BP |
461 | |
462 | pr_cont("Error during attempted NB data read.\n"); | |
463 | } else if (MEM_ERROR(ec)) { | |
464 | switch (xec) { | |
465 | case 0x4 ... 0xc: | |
f05c41a9 | 466 | pr_cont("%s.\n", f15h_mc2_mce_desc[xec - 0x4]); |
70fdb494 BP |
467 | break; |
468 | ||
469 | case 0x10 ... 0x14: | |
f05c41a9 | 470 | pr_cont("%s.\n", f15h_mc2_mce_desc[xec - 0x7]); |
70fdb494 BP |
471 | break; |
472 | ||
473 | default: | |
4a73d3de | 474 | ret = false; |
70fdb494 BP |
475 | } |
476 | } | |
477 | ||
4a73d3de JS |
478 | return ret; |
479 | } | |
480 | ||
980eec8b JS |
481 | static bool f16h_mc2_mce(u16 ec, u8 xec) |
482 | { | |
483 | u8 r4 = R4(ec); | |
484 | ||
485 | if (!MEM_ERROR(ec)) | |
486 | return false; | |
487 | ||
488 | switch (xec) { | |
489 | case 0x04 ... 0x05: | |
490 | pr_cont("%cBUFF parity error.\n", (r4 == R4_RD) ? 'I' : 'O'); | |
491 | break; | |
492 | ||
493 | case 0x09 ... 0x0b: | |
494 | case 0x0d ... 0x0f: | |
495 | pr_cont("ECC error in L2 tag (%s).\n", | |
496 | ((r4 == R4_GEN) ? "BankReq" : | |
497 | ((r4 == R4_SNOOP) ? "Prb" : "Fill"))); | |
498 | break; | |
499 | ||
500 | case 0x10 ... 0x19: | |
501 | case 0x1b: | |
502 | pr_cont("ECC error in L2 data array (%s).\n", | |
503 | (((r4 == R4_RD) && !(xec & 0x3)) ? "Hit" : | |
504 | ((r4 == R4_GEN) ? "Attr" : | |
505 | ((r4 == R4_EVICT) ? "Vict" : "Fill")))); | |
506 | break; | |
507 | ||
508 | case 0x1c ... 0x1d: | |
509 | case 0x1f: | |
510 | pr_cont("Parity error in L2 attribute bits (%s).\n", | |
511 | ((r4 == R4_RD) ? "Hit" : | |
512 | ((r4 == R4_GEN) ? "Attr" : "Fill"))); | |
513 | break; | |
514 | ||
515 | default: | |
516 | return false; | |
517 | } | |
518 | ||
519 | return true; | |
520 | } | |
521 | ||
4a73d3de JS |
522 | static void decode_mc2_mce(struct mce *m) |
523 | { | |
524 | u16 ec = EC(m->status); | |
525 | u8 xec = XEC(m->status, xec_mask); | |
70fdb494 | 526 | |
4a73d3de JS |
527 | pr_emerg(HW_ERR "MC2 Error: "); |
528 | ||
529 | if (!fam_ops->mc2_mce(ec, xec)) | |
530 | pr_cont(HW_ERR "Corrupted MC2 MCE info?\n"); | |
70fdb494 BP |
531 | } |
532 | ||
f05c41a9 | 533 | static void decode_mc3_mce(struct mce *m) |
f9350efd | 534 | { |
62452882 BP |
535 | u16 ec = EC(m->status); |
536 | u8 xec = XEC(m->status, xec_mask); | |
ded50623 | 537 | |
b18434ca | 538 | if (boot_cpu_data.x86 >= 0x14) { |
f05c41a9 | 539 | pr_emerg("You shouldn't be seeing MC3 MCE on this cpu family," |
ded50623 BP |
540 | " please report on LKML.\n"); |
541 | return; | |
542 | } | |
f9350efd | 543 | |
f05c41a9 | 544 | pr_emerg(HW_ERR "MC3 Error"); |
f9350efd BP |
545 | |
546 | if (xec == 0x0) { | |
62452882 | 547 | u8 r4 = R4(ec); |
f9350efd | 548 | |
ded50623 | 549 | if (!BUS_ERROR(ec) || (r4 != R4_DRD && r4 != R4_DWR)) |
f05c41a9 | 550 | goto wrong_mc3_mce; |
f9350efd | 551 | |
62452882 | 552 | pr_cont(" during %s.\n", R4_MSG(ec)); |
ded50623 | 553 | } else |
f05c41a9 | 554 | goto wrong_mc3_mce; |
ded50623 | 555 | |
f9350efd BP |
556 | return; |
557 | ||
f05c41a9 BP |
558 | wrong_mc3_mce: |
559 | pr_emerg(HW_ERR "Corrupted MC3 MCE info?\n"); | |
f9350efd BP |
560 | } |
561 | ||
f05c41a9 | 562 | static void decode_mc4_mce(struct mce *m) |
5ce88f6e | 563 | { |
68782673 BP |
564 | struct cpuinfo_x86 *c = &boot_cpu_data; |
565 | int node_id = amd_get_nb_id(m->extcpu); | |
566 | u16 ec = EC(m->status); | |
567 | u8 xec = XEC(m->status, 0x1f); | |
568 | u8 offset = 0; | |
5ce88f6e | 569 | |
f05c41a9 | 570 | pr_emerg(HW_ERR "MC4 Error (node %d): ", node_id); |
5ce88f6e | 571 | |
68782673 BP |
572 | switch (xec) { |
573 | case 0x0 ... 0xe: | |
5ce88f6e | 574 | |
68782673 BP |
575 | /* special handling for DRAM ECCs */ |
576 | if (xec == 0x0 || xec == 0x8) { | |
577 | /* no ECCs on F11h */ | |
578 | if (c->x86 == 0x11) | |
f05c41a9 | 579 | goto wrong_mc4_mce; |
5ce88f6e | 580 | |
f05c41a9 | 581 | pr_cont("%s.\n", mc4_mce_desc[xec]); |
5ce88f6e | 582 | |
68782673 BP |
583 | if (nb_bus_decoder) |
584 | nb_bus_decoder(node_id, m); | |
585 | return; | |
586 | } | |
5ce88f6e BP |
587 | break; |
588 | ||
589 | case 0xf: | |
590 | if (TLB_ERROR(ec)) | |
591 | pr_cont("GART Table Walk data error.\n"); | |
592 | else if (BUS_ERROR(ec)) | |
593 | pr_cont("DMA Exclusion Vector Table Walk error.\n"); | |
594 | else | |
f05c41a9 | 595 | goto wrong_mc4_mce; |
68782673 | 596 | return; |
5ce88f6e | 597 | |
05cd667d | 598 | case 0x19: |
980eec8b | 599 | if (boot_cpu_data.x86 == 0x15 || boot_cpu_data.x86 == 0x16) |
05cd667d BP |
600 | pr_cont("Compute Unit Data Error.\n"); |
601 | else | |
f05c41a9 | 602 | goto wrong_mc4_mce; |
68782673 | 603 | return; |
05cd667d | 604 | |
5ce88f6e | 605 | case 0x1c ... 0x1f: |
68782673 | 606 | offset = 13; |
5ce88f6e BP |
607 | break; |
608 | ||
609 | default: | |
f05c41a9 | 610 | goto wrong_mc4_mce; |
68782673 | 611 | } |
5ce88f6e | 612 | |
f05c41a9 | 613 | pr_cont("%s.\n", mc4_mce_desc[xec - offset]); |
5ce88f6e BP |
614 | return; |
615 | ||
f05c41a9 BP |
616 | wrong_mc4_mce: |
617 | pr_emerg(HW_ERR "Corrupted MC4 MCE info?\n"); | |
d93cc222 | 618 | } |
d93cc222 | 619 | |
f05c41a9 | 620 | static void decode_mc5_mce(struct mce *m) |
53bd5fed | 621 | { |
8259a7e5 | 622 | struct cpuinfo_x86 *c = &boot_cpu_data; |
62452882 | 623 | u8 xec = XEC(m->status, xec_mask); |
8259a7e5 BP |
624 | |
625 | if (c->x86 == 0xf || c->x86 == 0x11) | |
f05c41a9 | 626 | goto wrong_mc5_mce; |
fe4ea262 | 627 | |
f05c41a9 | 628 | pr_emerg(HW_ERR "MC5 Error: "); |
8259a7e5 BP |
629 | |
630 | if (xec == 0x0 || xec == 0xc) | |
f05c41a9 | 631 | pr_cont("%s.\n", mc5_mce_desc[xec]); |
8259a7e5 | 632 | else if (xec < 0xd) |
f05c41a9 | 633 | pr_cont("%s parity error.\n", mc5_mce_desc[xec]); |
8259a7e5 | 634 | else |
f05c41a9 | 635 | goto wrong_mc5_mce; |
8259a7e5 BP |
636 | |
637 | return; | |
fe4ea262 | 638 | |
f05c41a9 BP |
639 | wrong_mc5_mce: |
640 | pr_emerg(HW_ERR "Corrupted MC5 MCE info?\n"); | |
53bd5fed BP |
641 | } |
642 | ||
f05c41a9 | 643 | static void decode_mc6_mce(struct mce *m) |
b8f85c47 | 644 | { |
62452882 | 645 | u8 xec = XEC(m->status, xec_mask); |
b8f85c47 | 646 | |
f05c41a9 | 647 | pr_emerg(HW_ERR "MC6 Error: "); |
b8f85c47 BP |
648 | |
649 | switch (xec) { | |
650 | case 0x1: | |
651 | pr_cont("Free List"); | |
652 | break; | |
653 | ||
654 | case 0x2: | |
655 | pr_cont("Physical Register File"); | |
656 | break; | |
657 | ||
658 | case 0x3: | |
659 | pr_cont("Retire Queue"); | |
660 | break; | |
661 | ||
662 | case 0x4: | |
663 | pr_cont("Scheduler table"); | |
664 | break; | |
665 | ||
666 | case 0x5: | |
667 | pr_cont("Status Register File"); | |
668 | break; | |
669 | ||
670 | default: | |
f05c41a9 | 671 | goto wrong_mc6_mce; |
b8f85c47 BP |
672 | break; |
673 | } | |
674 | ||
675 | pr_cont(" parity error.\n"); | |
676 | ||
677 | return; | |
678 | ||
f05c41a9 BP |
679 | wrong_mc6_mce: |
680 | pr_emerg(HW_ERR "Corrupted MC6 MCE info?\n"); | |
b8f85c47 BP |
681 | } |
682 | ||
6337583d | 683 | static inline void amd_decode_err_code(u16 ec) |
d93cc222 | 684 | { |
980eec8b JS |
685 | if (INT_ERROR(ec)) { |
686 | pr_emerg(HW_ERR "internal: %s\n", UU_MSG(ec)); | |
687 | return; | |
688 | } | |
fa7ae8cc BP |
689 | |
690 | pr_emerg(HW_ERR "cache level: %s", LL_MSG(ec)); | |
691 | ||
692 | if (BUS_ERROR(ec)) | |
693 | pr_cont(", mem/io: %s", II_MSG(ec)); | |
694 | else | |
695 | pr_cont(", tx: %s", TT_MSG(ec)); | |
696 | ||
697 | if (MEM_ERROR(ec) || BUS_ERROR(ec)) { | |
698 | pr_cont(", mem-tx: %s", R4_MSG(ec)); | |
699 | ||
700 | if (BUS_ERROR(ec)) | |
701 | pr_cont(", part-proc: %s (%s)", PP_MSG(ec), TO_MSG(ec)); | |
702 | } | |
703 | ||
704 | pr_cont("\n"); | |
549d042d | 705 | } |
549d042d | 706 | |
5ce88f6e BP |
707 | /* |
708 | * Filter out unwanted MCE signatures here. | |
709 | */ | |
710 | static bool amd_filter_mce(struct mce *m) | |
711 | { | |
712 | u8 xec = (m->status >> 16) & 0x1f; | |
713 | ||
714 | /* | |
715 | * NB GART TLB error reporting is disabled by default. | |
716 | */ | |
717 | if (m->bank == 4 && xec == 0x5 && !report_gart_errors) | |
718 | return true; | |
719 | ||
720 | return false; | |
721 | } | |
722 | ||
d5c6770d BP |
723 | static const char *decode_error_status(struct mce *m) |
724 | { | |
725 | if (m->status & MCI_STATUS_UC) { | |
726 | if (m->status & MCI_STATUS_PCC) | |
727 | return "System Fatal error."; | |
728 | if (m->mcgstatus & MCG_STATUS_RIPV) | |
729 | return "Uncorrected, software restartable error."; | |
730 | return "Uncorrected, software containable error."; | |
731 | } | |
732 | ||
733 | if (m->status & MCI_STATUS_DEFERRED) | |
734 | return "Deferred error."; | |
735 | ||
736 | return "Corrected error, no action required."; | |
737 | } | |
738 | ||
9cdeb404 | 739 | int amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data) |
549d042d | 740 | { |
fb253195 | 741 | struct mce *m = (struct mce *)data; |
f89f8388 | 742 | struct cpuinfo_x86 *c = &cpu_data(m->extcpu); |
b0b07a2b | 743 | int ecc; |
549d042d | 744 | |
5ce88f6e BP |
745 | if (amd_filter_mce(m)) |
746 | return NOTIFY_STOP; | |
747 | ||
51966241 BP |
748 | switch (m->bank) { |
749 | case 0: | |
f05c41a9 | 750 | decode_mc0_mce(m); |
51966241 | 751 | break; |
d93cc222 | 752 | |
ab5535e7 | 753 | case 1: |
f05c41a9 | 754 | decode_mc1_mce(m); |
ab5535e7 BP |
755 | break; |
756 | ||
56cad2d6 | 757 | case 2: |
4a73d3de | 758 | decode_mc2_mce(m); |
56cad2d6 BP |
759 | break; |
760 | ||
f9350efd | 761 | case 3: |
f05c41a9 | 762 | decode_mc3_mce(m); |
f9350efd BP |
763 | break; |
764 | ||
51966241 | 765 | case 4: |
f05c41a9 | 766 | decode_mc4_mce(m); |
51966241 BP |
767 | break; |
768 | ||
53bd5fed | 769 | case 5: |
f05c41a9 | 770 | decode_mc5_mce(m); |
53bd5fed BP |
771 | break; |
772 | ||
b8f85c47 | 773 | case 6: |
f05c41a9 | 774 | decode_mc6_mce(m); |
b8f85c47 BP |
775 | break; |
776 | ||
51966241 BP |
777 | default: |
778 | break; | |
b69b29de | 779 | } |
51966241 | 780 | |
d5c6770d BP |
781 | pr_emerg(HW_ERR "Error Status: %s\n", decode_error_status(m)); |
782 | ||
d824c771 BP |
783 | pr_emerg(HW_ERR "CPU:%d (%x:%x:%x) MC%d_STATUS[%s|%s|%s|%s|%s", |
784 | m->extcpu, | |
785 | c->x86, c->x86_model, c->x86_mask, | |
786 | m->bank, | |
787 | ((m->status & MCI_STATUS_OVER) ? "Over" : "-"), | |
788 | ((m->status & MCI_STATUS_UC) ? "UE" : "CE"), | |
789 | ((m->status & MCI_STATUS_MISCV) ? "MiscV" : "-"), | |
790 | ((m->status & MCI_STATUS_PCC) ? "PCC" : "-"), | |
791 | ((m->status & MCI_STATUS_ADDRV) ? "AddrV" : "-")); | |
792 | ||
980eec8b | 793 | if (c->x86 == 0x15 || c->x86 == 0x16) |
d824c771 | 794 | pr_cont("|%s|%s", |
d5c6770d BP |
795 | ((m->status & MCI_STATUS_DEFERRED) ? "Deferred" : "-"), |
796 | ((m->status & MCI_STATUS_POISON) ? "Poison" : "-")); | |
d824c771 BP |
797 | |
798 | /* do the two bits[14:13] together */ | |
799 | ecc = (m->status >> 45) & 0x3; | |
800 | if (ecc) | |
801 | pr_cont("|%sECC", ((ecc == 2) ? "C" : "U")); | |
802 | ||
803 | pr_cont("]: 0x%016llx\n", m->status); | |
804 | ||
805 | if (m->status & MCI_STATUS_ADDRV) | |
806 | pr_emerg(HW_ERR "MC%d_ADDR: 0x%016llx\n", m->bank, m->addr); | |
807 | ||
51966241 | 808 | amd_decode_err_code(m->status & 0xffff); |
fb253195 BP |
809 | |
810 | return NOTIFY_STOP; | |
549d042d | 811 | } |
9cdeb404 | 812 | EXPORT_SYMBOL_GPL(amd_decode_mce); |
f436f8bb | 813 | |
fb253195 BP |
814 | static struct notifier_block amd_mce_dec_nb = { |
815 | .notifier_call = amd_decode_mce, | |
816 | }; | |
817 | ||
f436f8bb IM |
818 | static int __init mce_amd_init(void) |
819 | { | |
bad11e03 BP |
820 | struct cpuinfo_x86 *c = &boot_cpu_data; |
821 | ||
822 | if (c->x86_vendor != X86_VENDOR_AMD) | |
e045c291 BP |
823 | return 0; |
824 | ||
980eec8b | 825 | if (c->x86 < 0xf || c->x86 > 0x16) |
e045c291 BP |
826 | return 0; |
827 | ||
888ab8e6 BP |
828 | fam_ops = kzalloc(sizeof(struct amd_decoder_ops), GFP_KERNEL); |
829 | if (!fam_ops) | |
830 | return -ENOMEM; | |
831 | ||
bad11e03 | 832 | switch (c->x86) { |
888ab8e6 | 833 | case 0xf: |
f05c41a9 BP |
834 | fam_ops->mc0_mce = k8_mc0_mce; |
835 | fam_ops->mc1_mce = k8_mc1_mce; | |
4a73d3de | 836 | fam_ops->mc2_mce = k8_mc2_mce; |
888ab8e6 BP |
837 | break; |
838 | ||
839 | case 0x10: | |
f05c41a9 BP |
840 | fam_ops->mc0_mce = f10h_mc0_mce; |
841 | fam_ops->mc1_mce = k8_mc1_mce; | |
4a73d3de | 842 | fam_ops->mc2_mce = k8_mc2_mce; |
888ab8e6 BP |
843 | break; |
844 | ||
f0157b3a | 845 | case 0x11: |
f05c41a9 BP |
846 | fam_ops->mc0_mce = k8_mc0_mce; |
847 | fam_ops->mc1_mce = k8_mc1_mce; | |
4a73d3de | 848 | fam_ops->mc2_mce = k8_mc2_mce; |
f0157b3a BP |
849 | break; |
850 | ||
9be0bb10 | 851 | case 0x12: |
f05c41a9 BP |
852 | fam_ops->mc0_mce = f12h_mc0_mce; |
853 | fam_ops->mc1_mce = k8_mc1_mce; | |
4a73d3de | 854 | fam_ops->mc2_mce = k8_mc2_mce; |
9be0bb10 BP |
855 | break; |
856 | ||
888ab8e6 | 857 | case 0x14: |
5ce88f6e | 858 | nb_err_cpumask = 0x3; |
980eec8b JS |
859 | fam_ops->mc0_mce = cat_mc0_mce; |
860 | fam_ops->mc1_mce = cat_mc1_mce; | |
4a73d3de | 861 | fam_ops->mc2_mce = k8_mc2_mce; |
888ab8e6 BP |
862 | break; |
863 | ||
2be64bfa BP |
864 | case 0x15: |
865 | xec_mask = 0x1f; | |
f05c41a9 BP |
866 | fam_ops->mc0_mce = f15h_mc0_mce; |
867 | fam_ops->mc1_mce = f15h_mc1_mce; | |
4a73d3de | 868 | fam_ops->mc2_mce = f15h_mc2_mce; |
2be64bfa BP |
869 | break; |
870 | ||
980eec8b JS |
871 | case 0x16: |
872 | xec_mask = 0x1f; | |
873 | fam_ops->mc0_mce = cat_mc0_mce; | |
874 | fam_ops->mc1_mce = cat_mc1_mce; | |
875 | fam_ops->mc2_mce = f16h_mc2_mce; | |
876 | break; | |
877 | ||
888ab8e6 | 878 | default: |
ec3e82d6 | 879 | printk(KERN_WARNING "Huh? What family is it: 0x%x?!\n", c->x86); |
888ab8e6 BP |
880 | kfree(fam_ops); |
881 | return -EINVAL; | |
882 | } | |
883 | ||
9530d608 BP |
884 | pr_info("MCE: In-kernel MCE decoding enabled.\n"); |
885 | ||
3653ada5 | 886 | mce_register_decode_chain(&amd_mce_dec_nb); |
f436f8bb IM |
887 | |
888 | return 0; | |
889 | } | |
890 | early_initcall(mce_amd_init); | |
0d18b2e3 BP |
891 | |
892 | #ifdef MODULE | |
893 | static void __exit mce_amd_exit(void) | |
894 | { | |
3653ada5 | 895 | mce_unregister_decode_chain(&amd_mce_dec_nb); |
888ab8e6 | 896 | kfree(fam_ops); |
0d18b2e3 BP |
897 | } |
898 | ||
899 | MODULE_DESCRIPTION("AMD MCE decoder"); | |
900 | MODULE_ALIAS("edac-mce-amd"); | |
901 | MODULE_LICENSE("GPL"); | |
902 | module_exit(mce_amd_exit); | |
903 | #endif |