Commit | Line | Data |
---|---|---|
a9a753d5 | 1 | /* |
775c503f | 2 | * Freescale MPC85xx Memory Controller kernel module |
a9a753d5 | 3 | * |
c92132f5 CL |
4 | * Parts Copyrighted (c) 2013 by Freescale Semiconductor, Inc. |
5 | * | |
a9a753d5 DJ |
6 | * Author: Dave Jiang <djiang@mvista.com> |
7 | * | |
8 | * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under | |
9 | * the terms of the GNU General Public License version 2. This program | |
10 | * is licensed "as is" without any warranty of any kind, whether express | |
11 | * or implied. | |
12 | * | |
13 | */ | |
14 | #include <linux/module.h> | |
15 | #include <linux/init.h> | |
a9a753d5 DJ |
16 | #include <linux/interrupt.h> |
17 | #include <linux/ctype.h> | |
18 | #include <linux/io.h> | |
19 | #include <linux/mod_devicetable.h> | |
20 | #include <linux/edac.h> | |
60be7551 | 21 | #include <linux/smp.h> |
5a0e3ad6 | 22 | #include <linux/gfp.h> |
a9a753d5 DJ |
23 | |
24 | #include <linux/of_platform.h> | |
25 | #include <linux/of_device.h> | |
a9a753d5 DJ |
26 | #include "edac_module.h" |
27 | #include "edac_core.h" | |
28 | #include "mpc85xx_edac.h" | |
29 | ||
30 | static int edac_dev_idx; | |
0616fb00 | 31 | #ifdef CONFIG_PCI |
a9a753d5 | 32 | static int edac_pci_idx; |
0616fb00 | 33 | #endif |
a9a753d5 DJ |
34 | static int edac_mc_idx; |
35 | ||
36 | static u32 orig_ddr_err_disable; | |
37 | static u32 orig_ddr_err_sbe; | |
38 | ||
39 | /* | |
40 | * PCI Err defines | |
41 | */ | |
42 | #ifdef CONFIG_PCI | |
43 | static u32 orig_pci_err_cap_dr; | |
44 | static u32 orig_pci_err_en; | |
45 | #endif | |
46 | ||
47 | static u32 orig_l2_err_disable; | |
bd1688dc | 48 | #ifdef CONFIG_FSL_SOC_BOOKE |
60be7551 | 49 | static u32 orig_hid1[2]; |
b4846251 | 50 | #endif |
a9a753d5 | 51 | |
a9a753d5 DJ |
52 | /************************ MC SYSFS parts ***********************************/ |
53 | ||
ba004239 MCC |
54 | #define to_mci(k) container_of(k, struct mem_ctl_info, dev) |
55 | ||
56 | static ssize_t mpc85xx_mc_inject_data_hi_show(struct device *dev, | |
57 | struct device_attribute *mattr, | |
a9a753d5 DJ |
58 | char *data) |
59 | { | |
ba004239 | 60 | struct mem_ctl_info *mci = to_mci(dev); |
a9a753d5 DJ |
61 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; |
62 | return sprintf(data, "0x%08x", | |
63 | in_be32(pdata->mc_vbase + | |
64 | MPC85XX_MC_DATA_ERR_INJECT_HI)); | |
65 | } | |
66 | ||
ba004239 MCC |
67 | static ssize_t mpc85xx_mc_inject_data_lo_show(struct device *dev, |
68 | struct device_attribute *mattr, | |
a9a753d5 DJ |
69 | char *data) |
70 | { | |
ba004239 | 71 | struct mem_ctl_info *mci = to_mci(dev); |
a9a753d5 DJ |
72 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; |
73 | return sprintf(data, "0x%08x", | |
74 | in_be32(pdata->mc_vbase + | |
75 | MPC85XX_MC_DATA_ERR_INJECT_LO)); | |
76 | } | |
77 | ||
ba004239 MCC |
78 | static ssize_t mpc85xx_mc_inject_ctrl_show(struct device *dev, |
79 | struct device_attribute *mattr, | |
80 | char *data) | |
a9a753d5 | 81 | { |
ba004239 | 82 | struct mem_ctl_info *mci = to_mci(dev); |
a9a753d5 DJ |
83 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; |
84 | return sprintf(data, "0x%08x", | |
85 | in_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT)); | |
86 | } | |
87 | ||
ba004239 MCC |
88 | static ssize_t mpc85xx_mc_inject_data_hi_store(struct device *dev, |
89 | struct device_attribute *mattr, | |
a9a753d5 DJ |
90 | const char *data, size_t count) |
91 | { | |
ba004239 | 92 | struct mem_ctl_info *mci = to_mci(dev); |
a9a753d5 DJ |
93 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; |
94 | if (isdigit(*data)) { | |
95 | out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_HI, | |
96 | simple_strtoul(data, NULL, 0)); | |
97 | return count; | |
98 | } | |
99 | return 0; | |
100 | } | |
101 | ||
ba004239 MCC |
102 | static ssize_t mpc85xx_mc_inject_data_lo_store(struct device *dev, |
103 | struct device_attribute *mattr, | |
a9a753d5 DJ |
104 | const char *data, size_t count) |
105 | { | |
ba004239 | 106 | struct mem_ctl_info *mci = to_mci(dev); |
a9a753d5 DJ |
107 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; |
108 | if (isdigit(*data)) { | |
109 | out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_LO, | |
110 | simple_strtoul(data, NULL, 0)); | |
111 | return count; | |
112 | } | |
113 | return 0; | |
114 | } | |
115 | ||
ba004239 MCC |
116 | static ssize_t mpc85xx_mc_inject_ctrl_store(struct device *dev, |
117 | struct device_attribute *mattr, | |
118 | const char *data, size_t count) | |
a9a753d5 | 119 | { |
ba004239 | 120 | struct mem_ctl_info *mci = to_mci(dev); |
a9a753d5 DJ |
121 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; |
122 | if (isdigit(*data)) { | |
123 | out_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT, | |
124 | simple_strtoul(data, NULL, 0)); | |
125 | return count; | |
126 | } | |
127 | return 0; | |
128 | } | |
129 | ||
ba004239 MCC |
130 | DEVICE_ATTR(inject_data_hi, S_IRUGO | S_IWUSR, |
131 | mpc85xx_mc_inject_data_hi_show, mpc85xx_mc_inject_data_hi_store); | |
132 | DEVICE_ATTR(inject_data_lo, S_IRUGO | S_IWUSR, | |
133 | mpc85xx_mc_inject_data_lo_show, mpc85xx_mc_inject_data_lo_store); | |
134 | DEVICE_ATTR(inject_ctrl, S_IRUGO | S_IWUSR, | |
135 | mpc85xx_mc_inject_ctrl_show, mpc85xx_mc_inject_ctrl_store); | |
a9a753d5 | 136 | |
917c85b5 TI |
137 | static struct attribute *mpc85xx_dev_attrs[] = { |
138 | &dev_attr_inject_data_hi.attr, | |
139 | &dev_attr_inject_data_lo.attr, | |
140 | &dev_attr_inject_ctrl.attr, | |
141 | NULL | |
142 | }; | |
a9a753d5 | 143 | |
917c85b5 | 144 | ATTRIBUTE_GROUPS(mpc85xx_dev); |
a9a753d5 DJ |
145 | |
146 | /**************************** PCI Err device ***************************/ | |
147 | #ifdef CONFIG_PCI | |
148 | ||
149 | static void mpc85xx_pci_check(struct edac_pci_ctl_info *pci) | |
150 | { | |
151 | struct mpc85xx_pci_pdata *pdata = pci->pvt_info; | |
152 | u32 err_detect; | |
153 | ||
154 | err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR); | |
155 | ||
156 | /* master aborts can happen during PCI config cycles */ | |
157 | if (!(err_detect & ~(PCI_EDE_MULTI_ERR | PCI_EDE_MST_ABRT))) { | |
158 | out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect); | |
159 | return; | |
160 | } | |
161 | ||
162 | printk(KERN_ERR "PCI error(s) detected\n"); | |
163 | printk(KERN_ERR "PCI/X ERR_DR register: %#08x\n", err_detect); | |
164 | ||
165 | printk(KERN_ERR "PCI/X ERR_ATTRIB register: %#08x\n", | |
166 | in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ATTRIB)); | |
167 | printk(KERN_ERR "PCI/X ERR_ADDR register: %#08x\n", | |
168 | in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR)); | |
169 | printk(KERN_ERR "PCI/X ERR_EXT_ADDR register: %#08x\n", | |
170 | in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EXT_ADDR)); | |
171 | printk(KERN_ERR "PCI/X ERR_DL register: %#08x\n", | |
172 | in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DL)); | |
173 | printk(KERN_ERR "PCI/X ERR_DH register: %#08x\n", | |
174 | in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DH)); | |
175 | ||
176 | /* clear error bits */ | |
177 | out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect); | |
178 | ||
179 | if (err_detect & PCI_EDE_PERR_MASK) | |
180 | edac_pci_handle_pe(pci, pci->ctl_name); | |
181 | ||
182 | if ((err_detect & ~PCI_EDE_MULTI_ERR) & ~PCI_EDE_PERR_MASK) | |
183 | edac_pci_handle_npe(pci, pci->ctl_name); | |
184 | } | |
185 | ||
c92132f5 CL |
186 | static void mpc85xx_pcie_check(struct edac_pci_ctl_info *pci) |
187 | { | |
188 | struct mpc85xx_pci_pdata *pdata = pci->pvt_info; | |
189 | u32 err_detect; | |
190 | ||
191 | err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR); | |
192 | ||
193 | pr_err("PCIe error(s) detected\n"); | |
194 | pr_err("PCIe ERR_DR register: 0x%08x\n", err_detect); | |
195 | pr_err("PCIe ERR_CAP_STAT register: 0x%08x\n", | |
196 | in_be32(pdata->pci_vbase + MPC85XX_PCI_GAS_TIMR)); | |
197 | pr_err("PCIe ERR_CAP_R0 register: 0x%08x\n", | |
198 | in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R0)); | |
199 | pr_err("PCIe ERR_CAP_R1 register: 0x%08x\n", | |
200 | in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R1)); | |
201 | pr_err("PCIe ERR_CAP_R2 register: 0x%08x\n", | |
202 | in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R2)); | |
203 | pr_err("PCIe ERR_CAP_R3 register: 0x%08x\n", | |
204 | in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R3)); | |
205 | ||
206 | /* clear error bits */ | |
207 | out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect); | |
208 | } | |
209 | ||
210 | static int mpc85xx_pcie_find_capability(struct device_node *np) | |
211 | { | |
212 | struct pci_controller *hose; | |
213 | ||
214 | if (!np) | |
215 | return -EINVAL; | |
216 | ||
217 | hose = pci_find_hose_for_OF_device(np); | |
218 | ||
219 | return early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP); | |
220 | } | |
221 | ||
a9a753d5 DJ |
222 | static irqreturn_t mpc85xx_pci_isr(int irq, void *dev_id) |
223 | { | |
224 | struct edac_pci_ctl_info *pci = dev_id; | |
225 | struct mpc85xx_pci_pdata *pdata = pci->pvt_info; | |
226 | u32 err_detect; | |
227 | ||
228 | err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR); | |
229 | ||
230 | if (!err_detect) | |
231 | return IRQ_NONE; | |
232 | ||
c92132f5 CL |
233 | if (pdata->is_pcie) |
234 | mpc85xx_pcie_check(pci); | |
235 | else | |
236 | mpc85xx_pci_check(pci); | |
a9a753d5 DJ |
237 | |
238 | return IRQ_HANDLED; | |
239 | } | |
240 | ||
9b3c6e85 | 241 | int mpc85xx_pci_err_probe(struct platform_device *op) |
a9a753d5 DJ |
242 | { |
243 | struct edac_pci_ctl_info *pci; | |
244 | struct mpc85xx_pci_pdata *pdata; | |
f87bd330 | 245 | struct resource r; |
a9a753d5 DJ |
246 | int res = 0; |
247 | ||
f87bd330 | 248 | if (!devres_open_group(&op->dev, mpc85xx_pci_err_probe, GFP_KERNEL)) |
a9a753d5 DJ |
249 | return -ENOMEM; |
250 | ||
251 | pci = edac_pci_alloc_ctl_info(sizeof(*pdata), "mpc85xx_pci_err"); | |
252 | if (!pci) | |
253 | return -ENOMEM; | |
254 | ||
905e75c4 JH |
255 | /* make sure error reporting method is sane */ |
256 | switch (edac_op_state) { | |
257 | case EDAC_OPSTATE_POLL: | |
258 | case EDAC_OPSTATE_INT: | |
259 | break; | |
260 | default: | |
261 | edac_op_state = EDAC_OPSTATE_INT; | |
262 | break; | |
263 | } | |
264 | ||
a9a753d5 DJ |
265 | pdata = pci->pvt_info; |
266 | pdata->name = "mpc85xx_pci_err"; | |
267 | pdata->irq = NO_IRQ; | |
c92132f5 CL |
268 | |
269 | if (mpc85xx_pcie_find_capability(op->dev.of_node) > 0) | |
270 | pdata->is_pcie = true; | |
271 | ||
f87bd330 DJ |
272 | dev_set_drvdata(&op->dev, pci); |
273 | pci->dev = &op->dev; | |
a9a753d5 DJ |
274 | pci->mod_name = EDAC_MOD_STR; |
275 | pci->ctl_name = pdata->name; | |
031d5518 | 276 | pci->dev_name = dev_name(&op->dev); |
a9a753d5 | 277 | |
c92132f5 CL |
278 | if (edac_op_state == EDAC_OPSTATE_POLL) { |
279 | if (pdata->is_pcie) | |
280 | pci->edac_check = mpc85xx_pcie_check; | |
281 | else | |
282 | pci->edac_check = mpc85xx_pci_check; | |
283 | } | |
a9a753d5 DJ |
284 | |
285 | pdata->edac_idx = edac_pci_idx++; | |
286 | ||
a26f95fe | 287 | res = of_address_to_resource(op->dev.of_node, 0, &r); |
f87bd330 | 288 | if (res) { |
a9a753d5 DJ |
289 | printk(KERN_ERR "%s: Unable to get resource for " |
290 | "PCI err regs\n", __func__); | |
291 | goto err; | |
292 | } | |
293 | ||
f87bd330 DJ |
294 | /* we only need the error registers */ |
295 | r.start += 0xe00; | |
296 | ||
66ed3f75 HS |
297 | if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r), |
298 | pdata->name)) { | |
a9a753d5 DJ |
299 | printk(KERN_ERR "%s: Error while requesting mem region\n", |
300 | __func__); | |
301 | res = -EBUSY; | |
302 | goto err; | |
303 | } | |
304 | ||
66ed3f75 | 305 | pdata->pci_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r)); |
a9a753d5 DJ |
306 | if (!pdata->pci_vbase) { |
307 | printk(KERN_ERR "%s: Unable to setup PCI err regs\n", __func__); | |
308 | res = -ENOMEM; | |
309 | goto err; | |
310 | } | |
311 | ||
c92132f5 CL |
312 | if (pdata->is_pcie) { |
313 | orig_pci_err_cap_dr = | |
314 | in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR); | |
315 | out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR, ~0); | |
316 | orig_pci_err_en = | |
317 | in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN); | |
318 | out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, 0); | |
319 | } else { | |
320 | orig_pci_err_cap_dr = | |
321 | in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR); | |
322 | ||
323 | /* PCI master abort is expected during config cycles */ | |
324 | out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR, 0x40); | |
325 | ||
326 | orig_pci_err_en = | |
327 | in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN); | |
328 | ||
329 | /* disable master abort reporting */ | |
330 | out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, ~0x40); | |
331 | } | |
a9a753d5 DJ |
332 | |
333 | /* clear error bits */ | |
334 | out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, ~0); | |
335 | ||
336 | if (edac_pci_add_device(pci, pdata->edac_idx) > 0) { | |
956b9ba1 | 337 | edac_dbg(3, "failed edac_pci_add_device()\n"); |
a9a753d5 DJ |
338 | goto err; |
339 | } | |
340 | ||
341 | if (edac_op_state == EDAC_OPSTATE_INT) { | |
a26f95fe | 342 | pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0); |
f87bd330 | 343 | res = devm_request_irq(&op->dev, pdata->irq, |
c92132f5 | 344 | mpc85xx_pci_isr, |
e245e3b2 | 345 | IRQF_SHARED, |
a9a753d5 DJ |
346 | "[EDAC] PCI err", pci); |
347 | if (res < 0) { | |
348 | printk(KERN_ERR | |
e7d2c215 | 349 | "%s: Unable to request irq %d for " |
a9a753d5 | 350 | "MPC85xx PCI err\n", __func__, pdata->irq); |
f87bd330 | 351 | irq_dispose_mapping(pdata->irq); |
a9a753d5 DJ |
352 | res = -ENODEV; |
353 | goto err2; | |
354 | } | |
355 | ||
356 | printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for PCI Err\n", | |
357 | pdata->irq); | |
358 | } | |
359 | ||
c92132f5 CL |
360 | if (pdata->is_pcie) { |
361 | /* | |
362 | * Enable all PCIe error interrupt & error detect except invalid | |
363 | * PEX_CONFIG_ADDR/PEX_CONFIG_DATA access interrupt generation | |
364 | * enable bit and invalid PEX_CONFIG_ADDR/PEX_CONFIG_DATA access | |
365 | * detection enable bit. Because PCIe bus code to initialize and | |
366 | * configure these PCIe devices on booting will use some invalid | |
367 | * PEX_CONFIG_ADDR/PEX_CONFIG_DATA, edac driver prints the much | |
368 | * notice information. So disable this detect to fix ugly print. | |
369 | */ | |
370 | out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, ~0 | |
371 | & ~PEX_ERR_ICCAIE_EN_BIT); | |
372 | out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR, 0 | |
373 | | PEX_ERR_ICCAD_DISR_BIT); | |
374 | } | |
375 | ||
f87bd330 | 376 | devres_remove_group(&op->dev, mpc85xx_pci_err_probe); |
956b9ba1 | 377 | edac_dbg(3, "success\n"); |
a9a753d5 DJ |
378 | printk(KERN_INFO EDAC_MOD_STR " PCI err registered\n"); |
379 | ||
380 | return 0; | |
381 | ||
382 | err2: | |
f87bd330 | 383 | edac_pci_del_device(&op->dev); |
a9a753d5 DJ |
384 | err: |
385 | edac_pci_free_ctl_info(pci); | |
f87bd330 | 386 | devres_release_group(&op->dev, mpc85xx_pci_err_probe); |
a9a753d5 DJ |
387 | return res; |
388 | } | |
905e75c4 | 389 | EXPORT_SYMBOL(mpc85xx_pci_err_probe); |
a9a753d5 | 390 | |
a9a753d5 DJ |
391 | #endif /* CONFIG_PCI */ |
392 | ||
393 | /**************************** L2 Err device ***************************/ | |
394 | ||
395 | /************************ L2 SYSFS parts ***********************************/ | |
396 | ||
397 | static ssize_t mpc85xx_l2_inject_data_hi_show(struct edac_device_ctl_info | |
398 | *edac_dev, char *data) | |
399 | { | |
400 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; | |
401 | return sprintf(data, "0x%08x", | |
402 | in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI)); | |
403 | } | |
404 | ||
405 | static ssize_t mpc85xx_l2_inject_data_lo_show(struct edac_device_ctl_info | |
406 | *edac_dev, char *data) | |
407 | { | |
408 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; | |
409 | return sprintf(data, "0x%08x", | |
410 | in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO)); | |
411 | } | |
412 | ||
413 | static ssize_t mpc85xx_l2_inject_ctrl_show(struct edac_device_ctl_info | |
414 | *edac_dev, char *data) | |
415 | { | |
416 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; | |
417 | return sprintf(data, "0x%08x", | |
418 | in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL)); | |
419 | } | |
420 | ||
421 | static ssize_t mpc85xx_l2_inject_data_hi_store(struct edac_device_ctl_info | |
422 | *edac_dev, const char *data, | |
423 | size_t count) | |
424 | { | |
425 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; | |
426 | if (isdigit(*data)) { | |
427 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI, | |
428 | simple_strtoul(data, NULL, 0)); | |
429 | return count; | |
430 | } | |
431 | return 0; | |
432 | } | |
433 | ||
434 | static ssize_t mpc85xx_l2_inject_data_lo_store(struct edac_device_ctl_info | |
435 | *edac_dev, const char *data, | |
436 | size_t count) | |
437 | { | |
438 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; | |
439 | if (isdigit(*data)) { | |
440 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO, | |
441 | simple_strtoul(data, NULL, 0)); | |
442 | return count; | |
443 | } | |
444 | return 0; | |
445 | } | |
446 | ||
447 | static ssize_t mpc85xx_l2_inject_ctrl_store(struct edac_device_ctl_info | |
448 | *edac_dev, const char *data, | |
449 | size_t count) | |
450 | { | |
451 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; | |
452 | if (isdigit(*data)) { | |
453 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL, | |
454 | simple_strtoul(data, NULL, 0)); | |
455 | return count; | |
456 | } | |
457 | return 0; | |
458 | } | |
459 | ||
460 | static struct edac_dev_sysfs_attribute mpc85xx_l2_sysfs_attributes[] = { | |
461 | { | |
462 | .attr = { | |
463 | .name = "inject_data_hi", | |
464 | .mode = (S_IRUGO | S_IWUSR) | |
465 | }, | |
466 | .show = mpc85xx_l2_inject_data_hi_show, | |
467 | .store = mpc85xx_l2_inject_data_hi_store}, | |
468 | { | |
469 | .attr = { | |
470 | .name = "inject_data_lo", | |
471 | .mode = (S_IRUGO | S_IWUSR) | |
472 | }, | |
473 | .show = mpc85xx_l2_inject_data_lo_show, | |
474 | .store = mpc85xx_l2_inject_data_lo_store}, | |
475 | { | |
476 | .attr = { | |
477 | .name = "inject_ctrl", | |
478 | .mode = (S_IRUGO | S_IWUSR) | |
479 | }, | |
480 | .show = mpc85xx_l2_inject_ctrl_show, | |
481 | .store = mpc85xx_l2_inject_ctrl_store}, | |
482 | ||
483 | /* End of list */ | |
484 | { | |
485 | .attr = {.name = NULL} | |
486 | } | |
487 | }; | |
488 | ||
489 | static void mpc85xx_set_l2_sysfs_attributes(struct edac_device_ctl_info | |
490 | *edac_dev) | |
491 | { | |
492 | edac_dev->sysfs_attributes = mpc85xx_l2_sysfs_attributes; | |
493 | } | |
494 | ||
495 | /***************************** L2 ops ***********************************/ | |
496 | ||
497 | static void mpc85xx_l2_check(struct edac_device_ctl_info *edac_dev) | |
498 | { | |
499 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; | |
500 | u32 err_detect; | |
501 | ||
502 | err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET); | |
503 | ||
504 | if (!(err_detect & L2_EDE_MASK)) | |
505 | return; | |
506 | ||
507 | printk(KERN_ERR "ECC Error in CPU L2 cache\n"); | |
508 | printk(KERN_ERR "L2 Error Detect Register: 0x%08x\n", err_detect); | |
509 | printk(KERN_ERR "L2 Error Capture Data High Register: 0x%08x\n", | |
510 | in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATAHI)); | |
511 | printk(KERN_ERR "L2 Error Capture Data Lo Register: 0x%08x\n", | |
512 | in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATALO)); | |
513 | printk(KERN_ERR "L2 Error Syndrome Register: 0x%08x\n", | |
514 | in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTECC)); | |
515 | printk(KERN_ERR "L2 Error Attributes Capture Register: 0x%08x\n", | |
516 | in_be32(pdata->l2_vbase + MPC85XX_L2_ERRATTR)); | |
517 | printk(KERN_ERR "L2 Error Address Capture Register: 0x%08x\n", | |
518 | in_be32(pdata->l2_vbase + MPC85XX_L2_ERRADDR)); | |
519 | ||
520 | /* clear error detect register */ | |
521 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, err_detect); | |
522 | ||
523 | if (err_detect & L2_EDE_CE_MASK) | |
524 | edac_device_handle_ce(edac_dev, 0, 0, edac_dev->ctl_name); | |
525 | ||
526 | if (err_detect & L2_EDE_UE_MASK) | |
527 | edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name); | |
528 | } | |
529 | ||
530 | static irqreturn_t mpc85xx_l2_isr(int irq, void *dev_id) | |
531 | { | |
532 | struct edac_device_ctl_info *edac_dev = dev_id; | |
533 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; | |
534 | u32 err_detect; | |
535 | ||
536 | err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET); | |
537 | ||
538 | if (!(err_detect & L2_EDE_MASK)) | |
539 | return IRQ_NONE; | |
540 | ||
541 | mpc85xx_l2_check(edac_dev); | |
542 | ||
543 | return IRQ_HANDLED; | |
544 | } | |
545 | ||
9b3c6e85 | 546 | static int mpc85xx_l2_err_probe(struct platform_device *op) |
a9a753d5 DJ |
547 | { |
548 | struct edac_device_ctl_info *edac_dev; | |
549 | struct mpc85xx_l2_pdata *pdata; | |
550 | struct resource r; | |
551 | int res; | |
552 | ||
553 | if (!devres_open_group(&op->dev, mpc85xx_l2_err_probe, GFP_KERNEL)) | |
554 | return -ENOMEM; | |
555 | ||
556 | edac_dev = edac_device_alloc_ctl_info(sizeof(*pdata), | |
557 | "cpu", 1, "L", 1, 2, NULL, 0, | |
558 | edac_dev_idx); | |
559 | if (!edac_dev) { | |
560 | devres_release_group(&op->dev, mpc85xx_l2_err_probe); | |
561 | return -ENOMEM; | |
562 | } | |
563 | ||
564 | pdata = edac_dev->pvt_info; | |
565 | pdata->name = "mpc85xx_l2_err"; | |
566 | pdata->irq = NO_IRQ; | |
567 | edac_dev->dev = &op->dev; | |
568 | dev_set_drvdata(edac_dev->dev, edac_dev); | |
569 | edac_dev->ctl_name = pdata->name; | |
570 | edac_dev->dev_name = pdata->name; | |
571 | ||
a26f95fe | 572 | res = of_address_to_resource(op->dev.of_node, 0, &r); |
a9a753d5 DJ |
573 | if (res) { |
574 | printk(KERN_ERR "%s: Unable to get resource for " | |
575 | "L2 err regs\n", __func__); | |
576 | goto err; | |
577 | } | |
578 | ||
579 | /* we only need the error registers */ | |
580 | r.start += 0xe00; | |
581 | ||
28f65c11 JP |
582 | if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r), |
583 | pdata->name)) { | |
a9a753d5 DJ |
584 | printk(KERN_ERR "%s: Error while requesting mem region\n", |
585 | __func__); | |
586 | res = -EBUSY; | |
587 | goto err; | |
588 | } | |
589 | ||
28f65c11 | 590 | pdata->l2_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r)); |
a9a753d5 DJ |
591 | if (!pdata->l2_vbase) { |
592 | printk(KERN_ERR "%s: Unable to setup L2 err regs\n", __func__); | |
593 | res = -ENOMEM; | |
594 | goto err; | |
595 | } | |
596 | ||
597 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, ~0); | |
598 | ||
599 | orig_l2_err_disable = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS); | |
600 | ||
601 | /* clear the err_dis */ | |
602 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, 0); | |
603 | ||
604 | edac_dev->mod_name = EDAC_MOD_STR; | |
605 | ||
606 | if (edac_op_state == EDAC_OPSTATE_POLL) | |
607 | edac_dev->edac_check = mpc85xx_l2_check; | |
608 | ||
609 | mpc85xx_set_l2_sysfs_attributes(edac_dev); | |
610 | ||
611 | pdata->edac_idx = edac_dev_idx++; | |
612 | ||
613 | if (edac_device_add_device(edac_dev) > 0) { | |
956b9ba1 | 614 | edac_dbg(3, "failed edac_device_add_device()\n"); |
a9a753d5 DJ |
615 | goto err; |
616 | } | |
617 | ||
618 | if (edac_op_state == EDAC_OPSTATE_INT) { | |
a26f95fe | 619 | pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0); |
a9a753d5 | 620 | res = devm_request_irq(&op->dev, pdata->irq, |
a18c3f16 | 621 | mpc85xx_l2_isr, IRQF_SHARED, |
a9a753d5 DJ |
622 | "[EDAC] L2 err", edac_dev); |
623 | if (res < 0) { | |
624 | printk(KERN_ERR | |
e7d2c215 | 625 | "%s: Unable to request irq %d for " |
a9a753d5 DJ |
626 | "MPC85xx L2 err\n", __func__, pdata->irq); |
627 | irq_dispose_mapping(pdata->irq); | |
628 | res = -ENODEV; | |
629 | goto err2; | |
630 | } | |
631 | ||
632 | printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for L2 Err\n", | |
633 | pdata->irq); | |
634 | ||
635 | edac_dev->op_state = OP_RUNNING_INTERRUPT; | |
636 | ||
637 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, L2_EIE_MASK); | |
638 | } | |
639 | ||
640 | devres_remove_group(&op->dev, mpc85xx_l2_err_probe); | |
641 | ||
956b9ba1 | 642 | edac_dbg(3, "success\n"); |
a9a753d5 DJ |
643 | printk(KERN_INFO EDAC_MOD_STR " L2 err registered\n"); |
644 | ||
645 | return 0; | |
646 | ||
647 | err2: | |
648 | edac_device_del_device(&op->dev); | |
649 | err: | |
650 | devres_release_group(&op->dev, mpc85xx_l2_err_probe); | |
651 | edac_device_free_ctl_info(edac_dev); | |
652 | return res; | |
653 | } | |
654 | ||
2dc11581 | 655 | static int mpc85xx_l2_err_remove(struct platform_device *op) |
a9a753d5 DJ |
656 | { |
657 | struct edac_device_ctl_info *edac_dev = dev_get_drvdata(&op->dev); | |
658 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; | |
659 | ||
956b9ba1 | 660 | edac_dbg(0, "\n"); |
a9a753d5 DJ |
661 | |
662 | if (edac_op_state == EDAC_OPSTATE_INT) { | |
663 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, 0); | |
664 | irq_dispose_mapping(pdata->irq); | |
665 | } | |
666 | ||
667 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, orig_l2_err_disable); | |
668 | edac_device_del_device(&op->dev); | |
669 | edac_device_free_ctl_info(edac_dev); | |
670 | return 0; | |
671 | } | |
672 | ||
1afaa055 | 673 | static const struct of_device_id mpc85xx_l2_err_of_match[] = { |
29d6cf26 KG |
674 | /* deprecate the fsl,85.. forms in the future, 2.6.30? */ |
675 | { .compatible = "fsl,8540-l2-cache-controller", }, | |
676 | { .compatible = "fsl,8541-l2-cache-controller", }, | |
677 | { .compatible = "fsl,8544-l2-cache-controller", }, | |
678 | { .compatible = "fsl,8548-l2-cache-controller", }, | |
679 | { .compatible = "fsl,8555-l2-cache-controller", }, | |
680 | { .compatible = "fsl,8568-l2-cache-controller", }, | |
681 | { .compatible = "fsl,mpc8536-l2-cache-controller", }, | |
682 | { .compatible = "fsl,mpc8540-l2-cache-controller", }, | |
683 | { .compatible = "fsl,mpc8541-l2-cache-controller", }, | |
684 | { .compatible = "fsl,mpc8544-l2-cache-controller", }, | |
685 | { .compatible = "fsl,mpc8548-l2-cache-controller", }, | |
686 | { .compatible = "fsl,mpc8555-l2-cache-controller", }, | |
687 | { .compatible = "fsl,mpc8560-l2-cache-controller", }, | |
688 | { .compatible = "fsl,mpc8568-l2-cache-controller", }, | |
cd1542c8 | 689 | { .compatible = "fsl,mpc8569-l2-cache-controller", }, |
29d6cf26 | 690 | { .compatible = "fsl,mpc8572-l2-cache-controller", }, |
cd1542c8 AV |
691 | { .compatible = "fsl,p1020-l2-cache-controller", }, |
692 | { .compatible = "fsl,p1021-l2-cache-controller", }, | |
a014554e | 693 | { .compatible = "fsl,p2020-l2-cache-controller", }, |
a9a753d5 DJ |
694 | {}, |
695 | }; | |
952e1c66 | 696 | MODULE_DEVICE_TABLE(of, mpc85xx_l2_err_of_match); |
a9a753d5 | 697 | |
00006124 | 698 | static struct platform_driver mpc85xx_l2_err_driver = { |
a9a753d5 DJ |
699 | .probe = mpc85xx_l2_err_probe, |
700 | .remove = mpc85xx_l2_err_remove, | |
701 | .driver = { | |
4018294b | 702 | .name = "mpc85xx_l2_err", |
4018294b GL |
703 | .of_match_table = mpc85xx_l2_err_of_match, |
704 | }, | |
a9a753d5 DJ |
705 | }; |
706 | ||
707 | /**************************** MC Err device ***************************/ | |
708 | ||
dcca7c3d PT |
709 | /* |
710 | * Taken from table 8-55 in the MPC8641 User's Manual and/or 9-61 in the | |
711 | * MPC8572 User's Manual. Each line represents a syndrome bit column as a | |
712 | * 64-bit value, but split into an upper and lower 32-bit chunk. The labels | |
713 | * below correspond to Freescale's manuals. | |
714 | */ | |
715 | static unsigned int ecc_table[16] = { | |
716 | /* MSB LSB */ | |
717 | /* [0:31] [32:63] */ | |
718 | 0xf00fe11e, 0xc33c0ff7, /* Syndrome bit 7 */ | |
719 | 0x00ff00ff, 0x00fff0ff, | |
720 | 0x0f0f0f0f, 0x0f0fff00, | |
721 | 0x11113333, 0x7777000f, | |
722 | 0x22224444, 0x8888222f, | |
723 | 0x44448888, 0xffff4441, | |
724 | 0x8888ffff, 0x11118882, | |
725 | 0xffff1111, 0x22221114, /* Syndrome bit 0 */ | |
726 | }; | |
727 | ||
728 | /* | |
729 | * Calculate the correct ECC value for a 64-bit value specified by high:low | |
730 | */ | |
731 | static u8 calculate_ecc(u32 high, u32 low) | |
732 | { | |
733 | u32 mask_low; | |
734 | u32 mask_high; | |
735 | int bit_cnt; | |
736 | u8 ecc = 0; | |
737 | int i; | |
738 | int j; | |
739 | ||
740 | for (i = 0; i < 8; i++) { | |
741 | mask_high = ecc_table[i * 2]; | |
742 | mask_low = ecc_table[i * 2 + 1]; | |
743 | bit_cnt = 0; | |
744 | ||
745 | for (j = 0; j < 32; j++) { | |
746 | if ((mask_high >> j) & 1) | |
747 | bit_cnt ^= (high >> j) & 1; | |
748 | if ((mask_low >> j) & 1) | |
749 | bit_cnt ^= (low >> j) & 1; | |
750 | } | |
751 | ||
752 | ecc |= bit_cnt << i; | |
753 | } | |
754 | ||
755 | return ecc; | |
756 | } | |
757 | ||
758 | /* | |
759 | * Create the syndrome code which is generated if the data line specified by | |
760 | * 'bit' failed. Eg generate an 8-bit codes seen in Table 8-55 in the MPC8641 | |
761 | * User's Manual and 9-61 in the MPC8572 User's Manual. | |
762 | */ | |
763 | static u8 syndrome_from_bit(unsigned int bit) { | |
764 | int i; | |
765 | u8 syndrome = 0; | |
766 | ||
767 | /* | |
768 | * Cycle through the upper or lower 32-bit portion of each value in | |
769 | * ecc_table depending on if 'bit' is in the upper or lower half of | |
770 | * 64-bit data. | |
771 | */ | |
772 | for (i = bit < 32; i < 16; i += 2) | |
773 | syndrome |= ((ecc_table[i] >> (bit % 32)) & 1) << (i / 2); | |
774 | ||
775 | return syndrome; | |
776 | } | |
777 | ||
778 | /* | |
779 | * Decode data and ecc syndrome to determine what went wrong | |
780 | * Note: This can only decode single-bit errors | |
781 | */ | |
782 | static void sbe_ecc_decode(u32 cap_high, u32 cap_low, u32 cap_ecc, | |
783 | int *bad_data_bit, int *bad_ecc_bit) | |
784 | { | |
785 | int i; | |
786 | u8 syndrome; | |
787 | ||
788 | *bad_data_bit = -1; | |
789 | *bad_ecc_bit = -1; | |
790 | ||
791 | /* | |
792 | * Calculate the ECC of the captured data and XOR it with the captured | |
793 | * ECC to find an ECC syndrome value we can search for | |
794 | */ | |
795 | syndrome = calculate_ecc(cap_high, cap_low) ^ cap_ecc; | |
796 | ||
797 | /* Check if a data line is stuck... */ | |
798 | for (i = 0; i < 64; i++) { | |
799 | if (syndrome == syndrome_from_bit(i)) { | |
800 | *bad_data_bit = i; | |
801 | return; | |
802 | } | |
803 | } | |
804 | ||
805 | /* If data is correct, check ECC bits for errors... */ | |
806 | for (i = 0; i < 8; i++) { | |
807 | if ((syndrome >> i) & 0x1) { | |
808 | *bad_ecc_bit = i; | |
809 | return; | |
810 | } | |
811 | } | |
812 | } | |
813 | ||
2ce39109 YS |
814 | #define make64(high, low) (((u64)(high) << 32) | (low)) |
815 | ||
a9a753d5 DJ |
816 | static void mpc85xx_mc_check(struct mem_ctl_info *mci) |
817 | { | |
818 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; | |
819 | struct csrow_info *csrow; | |
21768639 | 820 | u32 bus_width; |
a9a753d5 DJ |
821 | u32 err_detect; |
822 | u32 syndrome; | |
2ce39109 | 823 | u64 err_addr; |
a9a753d5 DJ |
824 | u32 pfn; |
825 | int row_index; | |
dcca7c3d PT |
826 | u32 cap_high; |
827 | u32 cap_low; | |
828 | int bad_data_bit; | |
829 | int bad_ecc_bit; | |
a9a753d5 DJ |
830 | |
831 | err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT); | |
55e5750b | 832 | if (!err_detect) |
a9a753d5 DJ |
833 | return; |
834 | ||
835 | mpc85xx_mc_printk(mci, KERN_ERR, "Err Detect Register: %#8.8x\n", | |
836 | err_detect); | |
837 | ||
838 | /* no more processing if not ECC bit errors */ | |
839 | if (!(err_detect & (DDR_EDE_SBE | DDR_EDE_MBE))) { | |
840 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect); | |
841 | return; | |
842 | } | |
843 | ||
844 | syndrome = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ECC); | |
21768639 PT |
845 | |
846 | /* Mask off appropriate bits of syndrome based on bus width */ | |
847 | bus_width = (in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG) & | |
848 | DSC_DBW_MASK) ? 32 : 64; | |
849 | if (bus_width == 64) | |
850 | syndrome &= 0xff; | |
851 | else | |
852 | syndrome &= 0xffff; | |
853 | ||
2ce39109 YS |
854 | err_addr = make64( |
855 | in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_EXT_ADDRESS), | |
856 | in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ADDRESS)); | |
a9a753d5 DJ |
857 | pfn = err_addr >> PAGE_SHIFT; |
858 | ||
859 | for (row_index = 0; row_index < mci->nr_csrows; row_index++) { | |
de3910eb | 860 | csrow = mci->csrows[row_index]; |
a9a753d5 DJ |
861 | if ((pfn >= csrow->first_page) && (pfn <= csrow->last_page)) |
862 | break; | |
863 | } | |
864 | ||
dcca7c3d PT |
865 | cap_high = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_DATA_HI); |
866 | cap_low = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_DATA_LO); | |
867 | ||
868 | /* | |
869 | * Analyze single-bit errors on 64-bit wide buses | |
870 | * TODO: Add support for 32-bit wide buses | |
871 | */ | |
872 | if ((err_detect & DDR_EDE_SBE) && (bus_width == 64)) { | |
873 | sbe_ecc_decode(cap_high, cap_low, syndrome, | |
874 | &bad_data_bit, &bad_ecc_bit); | |
875 | ||
876 | if (bad_data_bit != -1) | |
877 | mpc85xx_mc_printk(mci, KERN_ERR, | |
878 | "Faulty Data bit: %d\n", bad_data_bit); | |
879 | if (bad_ecc_bit != -1) | |
880 | mpc85xx_mc_printk(mci, KERN_ERR, | |
881 | "Faulty ECC bit: %d\n", bad_ecc_bit); | |
882 | ||
883 | mpc85xx_mc_printk(mci, KERN_ERR, | |
884 | "Expected Data / ECC:\t%#8.8x_%08x / %#2.2x\n", | |
885 | cap_high ^ (1 << (bad_data_bit - 32)), | |
886 | cap_low ^ (1 << bad_data_bit), | |
887 | syndrome ^ (1 << bad_ecc_bit)); | |
888 | } | |
889 | ||
890 | mpc85xx_mc_printk(mci, KERN_ERR, | |
891 | "Captured Data / ECC:\t%#8.8x_%08x / %#2.2x\n", | |
892 | cap_high, cap_low, syndrome); | |
2ce39109 | 893 | mpc85xx_mc_printk(mci, KERN_ERR, "Err addr: %#8.8llx\n", err_addr); |
a9a753d5 DJ |
894 | mpc85xx_mc_printk(mci, KERN_ERR, "PFN: %#8.8x\n", pfn); |
895 | ||
896 | /* we are out of range */ | |
897 | if (row_index == mci->nr_csrows) | |
898 | mpc85xx_mc_printk(mci, KERN_ERR, "PFN out of range!\n"); | |
899 | ||
900 | if (err_detect & DDR_EDE_SBE) | |
9eb07a7f | 901 | edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, |
ad4d6e23 MCC |
902 | pfn, err_addr & ~PAGE_MASK, syndrome, |
903 | row_index, 0, -1, | |
03f7eae8 | 904 | mci->ctl_name, ""); |
a9a753d5 DJ |
905 | |
906 | if (err_detect & DDR_EDE_MBE) | |
9eb07a7f | 907 | edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, |
ad4d6e23 MCC |
908 | pfn, err_addr & ~PAGE_MASK, syndrome, |
909 | row_index, 0, -1, | |
03f7eae8 | 910 | mci->ctl_name, ""); |
a9a753d5 DJ |
911 | |
912 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect); | |
913 | } | |
914 | ||
915 | static irqreturn_t mpc85xx_mc_isr(int irq, void *dev_id) | |
916 | { | |
917 | struct mem_ctl_info *mci = dev_id; | |
918 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; | |
919 | u32 err_detect; | |
920 | ||
921 | err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT); | |
922 | if (!err_detect) | |
923 | return IRQ_NONE; | |
924 | ||
925 | mpc85xx_mc_check(mci); | |
926 | ||
927 | return IRQ_HANDLED; | |
928 | } | |
929 | ||
9b3c6e85 | 930 | static void mpc85xx_init_csrows(struct mem_ctl_info *mci) |
a9a753d5 DJ |
931 | { |
932 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; | |
933 | struct csrow_info *csrow; | |
084a4fcc | 934 | struct dimm_info *dimm; |
a9a753d5 DJ |
935 | u32 sdram_ctl; |
936 | u32 sdtype; | |
937 | enum mem_type mtype; | |
938 | u32 cs_bnds; | |
939 | int index; | |
940 | ||
941 | sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG); | |
942 | ||
943 | sdtype = sdram_ctl & DSC_SDTYPE_MASK; | |
944 | if (sdram_ctl & DSC_RD_EN) { | |
945 | switch (sdtype) { | |
946 | case DSC_SDTYPE_DDR: | |
947 | mtype = MEM_RDDR; | |
948 | break; | |
949 | case DSC_SDTYPE_DDR2: | |
950 | mtype = MEM_RDDR2; | |
951 | break; | |
b1cfebc9 YS |
952 | case DSC_SDTYPE_DDR3: |
953 | mtype = MEM_RDDR3; | |
954 | break; | |
a9a753d5 DJ |
955 | default: |
956 | mtype = MEM_UNKNOWN; | |
957 | break; | |
958 | } | |
959 | } else { | |
960 | switch (sdtype) { | |
961 | case DSC_SDTYPE_DDR: | |
962 | mtype = MEM_DDR; | |
963 | break; | |
964 | case DSC_SDTYPE_DDR2: | |
965 | mtype = MEM_DDR2; | |
966 | break; | |
b1cfebc9 YS |
967 | case DSC_SDTYPE_DDR3: |
968 | mtype = MEM_DDR3; | |
969 | break; | |
a9a753d5 DJ |
970 | default: |
971 | mtype = MEM_UNKNOWN; | |
972 | break; | |
973 | } | |
974 | } | |
975 | ||
976 | for (index = 0; index < mci->nr_csrows; index++) { | |
977 | u32 start; | |
978 | u32 end; | |
979 | ||
de3910eb MCC |
980 | csrow = mci->csrows[index]; |
981 | dimm = csrow->channels[0]->dimm; | |
084a4fcc | 982 | |
a9a753d5 DJ |
983 | cs_bnds = in_be32(pdata->mc_vbase + MPC85XX_MC_CS_BNDS_0 + |
984 | (index * MPC85XX_MC_CS_BNDS_OFS)); | |
b4846251 IS |
985 | |
986 | start = (cs_bnds & 0xffff0000) >> 16; | |
987 | end = (cs_bnds & 0x0000ffff); | |
a9a753d5 DJ |
988 | |
989 | if (start == end) | |
990 | continue; /* not populated */ | |
991 | ||
b4846251 IS |
992 | start <<= (24 - PAGE_SHIFT); |
993 | end <<= (24 - PAGE_SHIFT); | |
994 | end |= (1 << (24 - PAGE_SHIFT)) - 1; | |
995 | ||
cff9279e PT |
996 | csrow->first_page = start; |
997 | csrow->last_page = end; | |
a895bf8b MCC |
998 | |
999 | dimm->nr_pages = end + 1 - start; | |
084a4fcc MCC |
1000 | dimm->grain = 8; |
1001 | dimm->mtype = mtype; | |
1002 | dimm->dtype = DEV_UNKNOWN; | |
a9a753d5 | 1003 | if (sdram_ctl & DSC_X32_EN) |
084a4fcc MCC |
1004 | dimm->dtype = DEV_X32; |
1005 | dimm->edac_mode = EDAC_SECDED; | |
a9a753d5 DJ |
1006 | } |
1007 | } | |
1008 | ||
9b3c6e85 | 1009 | static int mpc85xx_mc_err_probe(struct platform_device *op) |
a9a753d5 DJ |
1010 | { |
1011 | struct mem_ctl_info *mci; | |
ad4d6e23 | 1012 | struct edac_mc_layer layers[2]; |
a9a753d5 DJ |
1013 | struct mpc85xx_mc_pdata *pdata; |
1014 | struct resource r; | |
1015 | u32 sdram_ctl; | |
1016 | int res; | |
1017 | ||
1018 | if (!devres_open_group(&op->dev, mpc85xx_mc_err_probe, GFP_KERNEL)) | |
1019 | return -ENOMEM; | |
1020 | ||
ad4d6e23 MCC |
1021 | layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; |
1022 | layers[0].size = 4; | |
1023 | layers[0].is_virt_csrow = true; | |
1024 | layers[1].type = EDAC_MC_LAYER_CHANNEL; | |
1025 | layers[1].size = 1; | |
1026 | layers[1].is_virt_csrow = false; | |
b9bc5ddb KP |
1027 | mci = edac_mc_alloc(edac_mc_idx, ARRAY_SIZE(layers), layers, |
1028 | sizeof(*pdata)); | |
a9a753d5 DJ |
1029 | if (!mci) { |
1030 | devres_release_group(&op->dev, mpc85xx_mc_err_probe); | |
1031 | return -ENOMEM; | |
1032 | } | |
1033 | ||
1034 | pdata = mci->pvt_info; | |
1035 | pdata->name = "mpc85xx_mc_err"; | |
1036 | pdata->irq = NO_IRQ; | |
fd687502 | 1037 | mci->pdev = &op->dev; |
a9a753d5 | 1038 | pdata->edac_idx = edac_mc_idx++; |
fd687502 | 1039 | dev_set_drvdata(mci->pdev, mci); |
a9a753d5 DJ |
1040 | mci->ctl_name = pdata->name; |
1041 | mci->dev_name = pdata->name; | |
1042 | ||
a26f95fe | 1043 | res = of_address_to_resource(op->dev.of_node, 0, &r); |
a9a753d5 DJ |
1044 | if (res) { |
1045 | printk(KERN_ERR "%s: Unable to get resource for MC err regs\n", | |
1046 | __func__); | |
1047 | goto err; | |
1048 | } | |
1049 | ||
28f65c11 JP |
1050 | if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r), |
1051 | pdata->name)) { | |
a9a753d5 DJ |
1052 | printk(KERN_ERR "%s: Error while requesting mem region\n", |
1053 | __func__); | |
1054 | res = -EBUSY; | |
1055 | goto err; | |
1056 | } | |
1057 | ||
28f65c11 | 1058 | pdata->mc_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r)); |
a9a753d5 DJ |
1059 | if (!pdata->mc_vbase) { |
1060 | printk(KERN_ERR "%s: Unable to setup MC err regs\n", __func__); | |
1061 | res = -ENOMEM; | |
1062 | goto err; | |
1063 | } | |
1064 | ||
1065 | sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG); | |
1066 | if (!(sdram_ctl & DSC_ECC_EN)) { | |
1067 | /* no ECC */ | |
1068 | printk(KERN_WARNING "%s: No ECC DIMMs discovered\n", __func__); | |
1069 | res = -ENODEV; | |
1070 | goto err; | |
1071 | } | |
1072 | ||
956b9ba1 | 1073 | edac_dbg(3, "init mci\n"); |
a9a753d5 DJ |
1074 | mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_RDDR2 | |
1075 | MEM_FLAG_DDR | MEM_FLAG_DDR2; | |
1076 | mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; | |
1077 | mci->edac_cap = EDAC_FLAG_SECDED; | |
1078 | mci->mod_name = EDAC_MOD_STR; | |
1079 | mci->mod_ver = MPC85XX_REVISION; | |
1080 | ||
1081 | if (edac_op_state == EDAC_OPSTATE_POLL) | |
1082 | mci->edac_check = mpc85xx_mc_check; | |
1083 | ||
1084 | mci->ctl_page_to_phys = NULL; | |
1085 | ||
1086 | mci->scrub_mode = SCRUB_SW_SRC; | |
1087 | ||
a9a753d5 DJ |
1088 | mpc85xx_init_csrows(mci); |
1089 | ||
a9a753d5 DJ |
1090 | /* store the original error disable bits */ |
1091 | orig_ddr_err_disable = | |
1092 | in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE); | |
1093 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE, 0); | |
1094 | ||
1095 | /* clear all error bits */ | |
1096 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, ~0); | |
1097 | ||
917c85b5 | 1098 | if (edac_mc_add_mc_with_groups(mci, mpc85xx_dev_groups)) { |
956b9ba1 | 1099 | edac_dbg(3, "failed edac_mc_add_mc()\n"); |
a9a753d5 DJ |
1100 | goto err; |
1101 | } | |
1102 | ||
1103 | if (edac_op_state == EDAC_OPSTATE_INT) { | |
1104 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN, | |
1105 | DDR_EIE_MBEE | DDR_EIE_SBEE); | |
1106 | ||
1107 | /* store the original error management threshold */ | |
1108 | orig_ddr_err_sbe = in_be32(pdata->mc_vbase + | |
1109 | MPC85XX_MC_ERR_SBE) & 0xff0000; | |
1110 | ||
1111 | /* set threshold to 1 error per interrupt */ | |
1112 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, 0x10000); | |
1113 | ||
1114 | /* register interrupts */ | |
a26f95fe | 1115 | pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0); |
a9a753d5 | 1116 | res = devm_request_irq(&op->dev, pdata->irq, |
60be7551 | 1117 | mpc85xx_mc_isr, |
e245e3b2 | 1118 | IRQF_SHARED, |
a9a753d5 DJ |
1119 | "[EDAC] MC err", mci); |
1120 | if (res < 0) { | |
1121 | printk(KERN_ERR "%s: Unable to request irq %d for " | |
1122 | "MPC85xx DRAM ERR\n", __func__, pdata->irq); | |
1123 | irq_dispose_mapping(pdata->irq); | |
1124 | res = -ENODEV; | |
1125 | goto err2; | |
1126 | } | |
1127 | ||
1128 | printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for MC\n", | |
1129 | pdata->irq); | |
1130 | } | |
1131 | ||
1132 | devres_remove_group(&op->dev, mpc85xx_mc_err_probe); | |
956b9ba1 | 1133 | edac_dbg(3, "success\n"); |
a9a753d5 DJ |
1134 | printk(KERN_INFO EDAC_MOD_STR " MC err registered\n"); |
1135 | ||
1136 | return 0; | |
1137 | ||
1138 | err2: | |
1139 | edac_mc_del_mc(&op->dev); | |
1140 | err: | |
1141 | devres_release_group(&op->dev, mpc85xx_mc_err_probe); | |
1142 | edac_mc_free(mci); | |
1143 | return res; | |
1144 | } | |
1145 | ||
2dc11581 | 1146 | static int mpc85xx_mc_err_remove(struct platform_device *op) |
a9a753d5 DJ |
1147 | { |
1148 | struct mem_ctl_info *mci = dev_get_drvdata(&op->dev); | |
1149 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; | |
1150 | ||
956b9ba1 | 1151 | edac_dbg(0, "\n"); |
a9a753d5 DJ |
1152 | |
1153 | if (edac_op_state == EDAC_OPSTATE_INT) { | |
1154 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN, 0); | |
1155 | irq_dispose_mapping(pdata->irq); | |
1156 | } | |
1157 | ||
1158 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE, | |
1159 | orig_ddr_err_disable); | |
1160 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, orig_ddr_err_sbe); | |
1161 | ||
1162 | edac_mc_del_mc(&op->dev); | |
1163 | edac_mc_free(mci); | |
1164 | return 0; | |
1165 | } | |
1166 | ||
1afaa055 | 1167 | static const struct of_device_id mpc85xx_mc_err_of_match[] = { |
29d6cf26 KG |
1168 | /* deprecate the fsl,85.. forms in the future, 2.6.30? */ |
1169 | { .compatible = "fsl,8540-memory-controller", }, | |
1170 | { .compatible = "fsl,8541-memory-controller", }, | |
1171 | { .compatible = "fsl,8544-memory-controller", }, | |
1172 | { .compatible = "fsl,8548-memory-controller", }, | |
1173 | { .compatible = "fsl,8555-memory-controller", }, | |
1174 | { .compatible = "fsl,8568-memory-controller", }, | |
1175 | { .compatible = "fsl,mpc8536-memory-controller", }, | |
1176 | { .compatible = "fsl,mpc8540-memory-controller", }, | |
1177 | { .compatible = "fsl,mpc8541-memory-controller", }, | |
1178 | { .compatible = "fsl,mpc8544-memory-controller", }, | |
1179 | { .compatible = "fsl,mpc8548-memory-controller", }, | |
1180 | { .compatible = "fsl,mpc8555-memory-controller", }, | |
1181 | { .compatible = "fsl,mpc8560-memory-controller", }, | |
1182 | { .compatible = "fsl,mpc8568-memory-controller", }, | |
5528e229 | 1183 | { .compatible = "fsl,mpc8569-memory-controller", }, |
29d6cf26 | 1184 | { .compatible = "fsl,mpc8572-memory-controller", }, |
b4846251 | 1185 | { .compatible = "fsl,mpc8349-memory-controller", }, |
cd1542c8 AV |
1186 | { .compatible = "fsl,p1020-memory-controller", }, |
1187 | { .compatible = "fsl,p1021-memory-controller", }, | |
a014554e | 1188 | { .compatible = "fsl,p2020-memory-controller", }, |
86f9a433 | 1189 | { .compatible = "fsl,qoriq-memory-controller", }, |
a9a753d5 DJ |
1190 | {}, |
1191 | }; | |
952e1c66 | 1192 | MODULE_DEVICE_TABLE(of, mpc85xx_mc_err_of_match); |
a9a753d5 | 1193 | |
00006124 | 1194 | static struct platform_driver mpc85xx_mc_err_driver = { |
a9a753d5 DJ |
1195 | .probe = mpc85xx_mc_err_probe, |
1196 | .remove = mpc85xx_mc_err_remove, | |
1197 | .driver = { | |
4018294b | 1198 | .name = "mpc85xx_mc_err", |
4018294b GL |
1199 | .of_match_table = mpc85xx_mc_err_of_match, |
1200 | }, | |
a9a753d5 DJ |
1201 | }; |
1202 | ||
bd1688dc | 1203 | #ifdef CONFIG_FSL_SOC_BOOKE |
60be7551 AK |
1204 | static void __init mpc85xx_mc_clear_rfxe(void *data) |
1205 | { | |
1206 | orig_hid1[smp_processor_id()] = mfspr(SPRN_HID1); | |
a94d7b35 | 1207 | mtspr(SPRN_HID1, (orig_hid1[smp_processor_id()] & ~HID1_RFXE)); |
60be7551 | 1208 | } |
b4846251 | 1209 | #endif |
60be7551 | 1210 | |
d54051f1 TR |
1211 | static struct platform_driver * const drivers[] = { |
1212 | &mpc85xx_mc_err_driver, | |
1213 | &mpc85xx_l2_err_driver, | |
1214 | }; | |
1215 | ||
a9a753d5 DJ |
1216 | static int __init mpc85xx_mc_init(void) |
1217 | { | |
1218 | int res = 0; | |
a94d7b35 | 1219 | u32 pvr = 0; |
a9a753d5 DJ |
1220 | |
1221 | printk(KERN_INFO "Freescale(R) MPC85xx EDAC driver, " | |
1222 | "(C) 2006 Montavista Software\n"); | |
1223 | ||
1224 | /* make sure error reporting method is sane */ | |
1225 | switch (edac_op_state) { | |
1226 | case EDAC_OPSTATE_POLL: | |
1227 | case EDAC_OPSTATE_INT: | |
1228 | break; | |
1229 | default: | |
1230 | edac_op_state = EDAC_OPSTATE_INT; | |
1231 | break; | |
1232 | } | |
1233 | ||
d54051f1 | 1234 | res = platform_register_drivers(drivers, ARRAY_SIZE(drivers)); |
a9a753d5 | 1235 | if (res) |
d54051f1 | 1236 | printk(KERN_WARNING EDAC_MOD_STR "drivers fail to register\n"); |
a9a753d5 | 1237 | |
bd1688dc | 1238 | #ifdef CONFIG_FSL_SOC_BOOKE |
a94d7b35 KG |
1239 | pvr = mfspr(SPRN_PVR); |
1240 | ||
1241 | if ((PVR_VER(pvr) == PVR_VER_E500V1) || | |
1242 | (PVR_VER(pvr) == PVR_VER_E500V2)) { | |
1243 | /* | |
1244 | * need to clear HID1[RFXE] to disable machine check int | |
1245 | * so we can catch it | |
1246 | */ | |
1247 | if (edac_op_state == EDAC_OPSTATE_INT) | |
1248 | on_each_cpu(mpc85xx_mc_clear_rfxe, NULL, 0); | |
1249 | } | |
b4846251 | 1250 | #endif |
a9a753d5 DJ |
1251 | |
1252 | return 0; | |
1253 | } | |
1254 | ||
1255 | module_init(mpc85xx_mc_init); | |
1256 | ||
bd1688dc | 1257 | #ifdef CONFIG_FSL_SOC_BOOKE |
60be7551 AK |
1258 | static void __exit mpc85xx_mc_restore_hid1(void *data) |
1259 | { | |
1260 | mtspr(SPRN_HID1, orig_hid1[smp_processor_id()]); | |
1261 | } | |
b4846251 | 1262 | #endif |
60be7551 | 1263 | |
a9a753d5 DJ |
1264 | static void __exit mpc85xx_mc_exit(void) |
1265 | { | |
bd1688dc | 1266 | #ifdef CONFIG_FSL_SOC_BOOKE |
a94d7b35 KG |
1267 | u32 pvr = mfspr(SPRN_PVR); |
1268 | ||
1269 | if ((PVR_VER(pvr) == PVR_VER_E500V1) || | |
1270 | (PVR_VER(pvr) == PVR_VER_E500V2)) { | |
1271 | on_each_cpu(mpc85xx_mc_restore_hid1, NULL, 0); | |
1272 | } | |
a9a753d5 | 1273 | #endif |
d54051f1 | 1274 | platform_unregister_drivers(drivers, ARRAY_SIZE(drivers)); |
a9a753d5 DJ |
1275 | } |
1276 | ||
1277 | module_exit(mpc85xx_mc_exit); | |
1278 | ||
1279 | MODULE_LICENSE("GPL"); | |
1280 | MODULE_AUTHOR("Montavista Software, Inc."); | |
1281 | module_param(edac_op_state, int, 0444); | |
1282 | MODULE_PARM_DESC(edac_op_state, | |
1283 | "EDAC Error Reporting state: 0=Poll, 2=Interrupt"); |