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edac: mpc85xx improve SDRAM error reporting
[deliverable/linux.git] / drivers / edac / mpc85xx_edac.c
CommitLineData
a9a753d5
DJ		 1/*
2 * Freescale MPC85xx Memory Controller kenel module
3 *
4 * Author: Dave Jiang <djiang@mvista.com>
5 *
6 * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 *
11 */
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/slab.h>
15#include <linux/interrupt.h>
16#include <linux/ctype.h>
17#include <linux/io.h>
18#include <linux/mod_devicetable.h>
19#include <linux/edac.h>
60be7551 20#include <linux/smp.h>
a9a753d5
DJ		 21
22#include <linux/of_platform.h>
23#include <linux/of_device.h>
a9a753d5
DJ		 24#include "edac_module.h"
25#include "edac_core.h"
26#include "mpc85xx_edac.h"
27
28static int edac_dev_idx;
0616fb00 29#ifdef CONFIG_PCI
a9a753d5 30static int edac_pci_idx;
0616fb00 31#endif
a9a753d5
DJ		 32static int edac_mc_idx;
33
34static u32 orig_ddr_err_disable;
35static u32 orig_ddr_err_sbe;
36
37/*
38 * PCI Err defines
39 */
40#ifdef CONFIG_PCI
41static u32 orig_pci_err_cap_dr;
42static u32 orig_pci_err_en;
43#endif
44
45static u32 orig_l2_err_disable;
b4846251 46#ifdef CONFIG_MPC85xx
60be7551 47static u32 orig_hid1[2];
b4846251 48#endif
a9a753d5 49
a9a753d5
DJ		 50/************************ MC SYSFS parts ***********************************/
51
52static ssize_t mpc85xx_mc_inject_data_hi_show(struct mem_ctl_info *mci,
53 char *data)
54{
55 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
56 return sprintf(data, "0x%08x",
57 in_be32(pdata->mc_vbase +
58 MPC85XX_MC_DATA_ERR_INJECT_HI));
59}
60
61static ssize_t mpc85xx_mc_inject_data_lo_show(struct mem_ctl_info *mci,
62 char *data)
63{
64 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
65 return sprintf(data, "0x%08x",
66 in_be32(pdata->mc_vbase +
67 MPC85XX_MC_DATA_ERR_INJECT_LO));
68}
69
70static ssize_t mpc85xx_mc_inject_ctrl_show(struct mem_ctl_info *mci, char *data)
71{
72 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
73 return sprintf(data, "0x%08x",
74 in_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT));
75}
76
77static ssize_t mpc85xx_mc_inject_data_hi_store(struct mem_ctl_info *mci,
78 const char *data, size_t count)
79{
80 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
81 if (isdigit(*data)) {
82 out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_HI,
83 simple_strtoul(data, NULL, 0));
84 return count;
85 }
86 return 0;
87}
88
89static ssize_t mpc85xx_mc_inject_data_lo_store(struct mem_ctl_info *mci,
90 const char *data, size_t count)
91{
92 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
93 if (isdigit(*data)) {
94 out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_LO,
95 simple_strtoul(data, NULL, 0));
96 return count;
97 }
98 return 0;
99}
100
101static ssize_t mpc85xx_mc_inject_ctrl_store(struct mem_ctl_info *mci,
102 const char *data, size_t count)
103{
104 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
105 if (isdigit(*data)) {
106 out_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT,
107 simple_strtoul(data, NULL, 0));
108 return count;
109 }
110 return 0;
111}
112
113static struct mcidev_sysfs_attribute mpc85xx_mc_sysfs_attributes[] = {
114 {
115 .attr = {
116 .name = "inject_data_hi",
117 .mode = (S_IRUGO | S_IWUSR)
118 },
119 .show = mpc85xx_mc_inject_data_hi_show,
120 .store = mpc85xx_mc_inject_data_hi_store},
121 {
122 .attr = {
123 .name = "inject_data_lo",
124 .mode = (S_IRUGO | S_IWUSR)
125 },
126 .show = mpc85xx_mc_inject_data_lo_show,
127 .store = mpc85xx_mc_inject_data_lo_store},
128 {
129 .attr = {
130 .name = "inject_ctrl",
131 .mode = (S_IRUGO | S_IWUSR)
132 },
133 .show = mpc85xx_mc_inject_ctrl_show,
134 .store = mpc85xx_mc_inject_ctrl_store},
135
136 /* End of list */
137 {
138 .attr = {.name = NULL}
139 }
140};
141
142static void mpc85xx_set_mc_sysfs_attributes(struct mem_ctl_info *mci)
143{
144 mci->mc_driver_sysfs_attributes = mpc85xx_mc_sysfs_attributes;
145}
146
147/**************************** PCI Err device ***************************/
148#ifdef CONFIG_PCI
149
150static void mpc85xx_pci_check(struct edac_pci_ctl_info *pci)
151{
152 struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
153 u32 err_detect;
154
155 err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR);
156
157 /* master aborts can happen during PCI config cycles */
158 if (!(err_detect & ~(PCI_EDE_MULTI_ERR | PCI_EDE_MST_ABRT))) {
159 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect);
160 return;
161 }
162
163 printk(KERN_ERR "PCI error(s) detected\n");
164 printk(KERN_ERR "PCI/X ERR_DR register: %#08x\n", err_detect);
165
166 printk(KERN_ERR "PCI/X ERR_ATTRIB register: %#08x\n",
167 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ATTRIB));
168 printk(KERN_ERR "PCI/X ERR_ADDR register: %#08x\n",
169 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR));
170 printk(KERN_ERR "PCI/X ERR_EXT_ADDR register: %#08x\n",
171 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EXT_ADDR));
172 printk(KERN_ERR "PCI/X ERR_DL register: %#08x\n",
173 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DL));
174 printk(KERN_ERR "PCI/X ERR_DH register: %#08x\n",
175 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DH));
176
177 /* clear error bits */
178 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect);
179
180 if (err_detect & PCI_EDE_PERR_MASK)
181 edac_pci_handle_pe(pci, pci->ctl_name);
182
183 if ((err_detect & ~PCI_EDE_MULTI_ERR) & ~PCI_EDE_PERR_MASK)
184 edac_pci_handle_npe(pci, pci->ctl_name);
185}
186
187static irqreturn_t mpc85xx_pci_isr(int irq, void *dev_id)
188{
189 struct edac_pci_ctl_info *pci = dev_id;
190 struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
191 u32 err_detect;
192
193 err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR);
194
195 if (!err_detect)
196 return IRQ_NONE;
197
198 mpc85xx_pci_check(pci);
199
200 return IRQ_HANDLED;
201}
202
f87bd330
DJ		 203static int __devinit mpc85xx_pci_err_probe(struct of_device *op,
204 const struct of_device_id *match)
a9a753d5
DJ		 205{
206 struct edac_pci_ctl_info *pci;
207 struct mpc85xx_pci_pdata *pdata;
f87bd330 208 struct resource r;
a9a753d5
DJ		 209 int res = 0;
210
f87bd330 211 if (!devres_open_group(&op->dev, mpc85xx_pci_err_probe, GFP_KERNEL))
a9a753d5
DJ		 212 return -ENOMEM;
213
214 pci = edac_pci_alloc_ctl_info(sizeof(*pdata), "mpc85xx_pci_err");
215 if (!pci)
216 return -ENOMEM;
217
218 pdata = pci->pvt_info;
219 pdata->name = "mpc85xx_pci_err";
220 pdata->irq = NO_IRQ;
f87bd330
DJ		 221 dev_set_drvdata(&op->dev, pci);
222 pci->dev = &op->dev;
a9a753d5
DJ		 223 pci->mod_name = EDAC_MOD_STR;
224 pci->ctl_name = pdata->name;
031d5518 225 pci->dev_name = dev_name(&op->dev);
a9a753d5
DJ		 226
227 if (edac_op_state == EDAC_OPSTATE_POLL)
228 pci->edac_check = mpc85xx_pci_check;
229
230 pdata->edac_idx = edac_pci_idx++;
231
f87bd330
DJ		 232 res = of_address_to_resource(op->node, 0, &r);
233 if (res) {
a9a753d5
DJ		 234 printk(KERN_ERR "%s: Unable to get resource for "
235 "PCI err regs\n", __func__);
236 goto err;
237 }
238
f87bd330
DJ		 239 /* we only need the error registers */
240 r.start += 0xe00;
241
242 if (!devm_request_mem_region(&op->dev, r.start,
243 r.end - r.start + 1, pdata->name)) {
a9a753d5
DJ		 244 printk(KERN_ERR "%s: Error while requesting mem region\n",
245 __func__);
246 res = -EBUSY;
247 goto err;
248 }
249
f87bd330
DJ		 250 pdata->pci_vbase = devm_ioremap(&op->dev, r.start,
251 r.end - r.start + 1);
a9a753d5
DJ		 252 if (!pdata->pci_vbase) {
253 printk(KERN_ERR "%s: Unable to setup PCI err regs\n", __func__);
254 res = -ENOMEM;
255 goto err;
256 }
257
258 orig_pci_err_cap_dr =
259 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR);
260
261 /* PCI master abort is expected during config cycles */
262 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR, 0x40);
263
264 orig_pci_err_en = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN);
265
266 /* disable master abort reporting */
267 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, ~0x40);
268
269 /* clear error bits */
270 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, ~0);
271
272 if (edac_pci_add_device(pci, pdata->edac_idx) > 0) {
273 debugf3("%s(): failed edac_pci_add_device()\n", __func__);
274 goto err;
275 }
276
277 if (edac_op_state == EDAC_OPSTATE_INT) {
f87bd330
DJ		 278 pdata->irq = irq_of_parse_and_map(op->node, 0);
279 res = devm_request_irq(&op->dev, pdata->irq,
a9a753d5
DJ		 280 mpc85xx_pci_isr, IRQF_DISABLED,
281 "[EDAC] PCI err", pci);
282 if (res < 0) {
283 printk(KERN_ERR
284 "%s: Unable to requiest irq %d for "
285 "MPC85xx PCI err\n", __func__, pdata->irq);
f87bd330 286 irq_dispose_mapping(pdata->irq);
a9a753d5
DJ		 287 res = -ENODEV;
288 goto err2;
289 }
290
291 printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for PCI Err\n",
292 pdata->irq);
293 }
294
f87bd330 295 devres_remove_group(&op->dev, mpc85xx_pci_err_probe);
a9a753d5
DJ		 296 debugf3("%s(): success\n", __func__);
297 printk(KERN_INFO EDAC_MOD_STR " PCI err registered\n");
298
299 return 0;
300
301err2:
f87bd330 302 edac_pci_del_device(&op->dev);
a9a753d5
DJ		 303err:
304 edac_pci_free_ctl_info(pci);
f87bd330 305 devres_release_group(&op->dev, mpc85xx_pci_err_probe);
a9a753d5
DJ		 306 return res;
307}
308
f87bd330 309static int mpc85xx_pci_err_remove(struct of_device *op)
a9a753d5 310{
f87bd330 311 struct edac_pci_ctl_info *pci = dev_get_drvdata(&op->dev);
a9a753d5
DJ		 312 struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
313
314 debugf0("%s()\n", __func__);
315
316 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR,
317 orig_pci_err_cap_dr);
318
319 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, orig_pci_err_en);
320
321 edac_pci_del_device(pci->dev);
322
323 if (edac_op_state == EDAC_OPSTATE_INT)
324 irq_dispose_mapping(pdata->irq);
325
326 edac_pci_free_ctl_info(pci);
327
328 return 0;
329}
330
f87bd330
DJ		 331static struct of_device_id mpc85xx_pci_err_of_match[] = {
332 {
333 .compatible = "fsl,mpc8540-pcix",
334 },
335 {
336 .compatible = "fsl,mpc8540-pci",
337 },
338 {},
339};
340
341static struct of_platform_driver mpc85xx_pci_err_driver = {
342 .owner = THIS_MODULE,
343 .name = "mpc85xx_pci_err",
344 .match_table = mpc85xx_pci_err_of_match,
a9a753d5
DJ		 345 .probe = mpc85xx_pci_err_probe,
346 .remove = __devexit_p(mpc85xx_pci_err_remove),
347 .driver = {
f87bd330
DJ		 348 .name = "mpc85xx_pci_err",
349 .owner = THIS_MODULE,
350 },
a9a753d5
DJ		 351};
352
353#endif /* CONFIG_PCI */
354
355/**************************** L2 Err device ***************************/
356
357/************************ L2 SYSFS parts ***********************************/
358
359static ssize_t mpc85xx_l2_inject_data_hi_show(struct edac_device_ctl_info
360 *edac_dev, char *data)
361{
362 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
363 return sprintf(data, "0x%08x",
364 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI));
365}
366
367static ssize_t mpc85xx_l2_inject_data_lo_show(struct edac_device_ctl_info
368 *edac_dev, char *data)
369{
370 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
371 return sprintf(data, "0x%08x",
372 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO));
373}
374
375static ssize_t mpc85xx_l2_inject_ctrl_show(struct edac_device_ctl_info
376 *edac_dev, char *data)
377{
378 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
379 return sprintf(data, "0x%08x",
380 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL));
381}
382
383static ssize_t mpc85xx_l2_inject_data_hi_store(struct edac_device_ctl_info
384 *edac_dev, const char *data,
385 size_t count)
386{
387 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
388 if (isdigit(*data)) {
389 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI,
390 simple_strtoul(data, NULL, 0));
391 return count;
392 }
393 return 0;
394}
395
396static ssize_t mpc85xx_l2_inject_data_lo_store(struct edac_device_ctl_info
397 *edac_dev, const char *data,
398 size_t count)
399{
400 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
401 if (isdigit(*data)) {
402 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO,
403 simple_strtoul(data, NULL, 0));
404 return count;
405 }
406 return 0;
407}
408
409static ssize_t mpc85xx_l2_inject_ctrl_store(struct edac_device_ctl_info
410 *edac_dev, const char *data,
411 size_t count)
412{
413 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
414 if (isdigit(*data)) {
415 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL,
416 simple_strtoul(data, NULL, 0));
417 return count;
418 }
419 return 0;
420}
421
422static struct edac_dev_sysfs_attribute mpc85xx_l2_sysfs_attributes[] = {
423 {
424 .attr = {
425 .name = "inject_data_hi",
426 .mode = (S_IRUGO | S_IWUSR)
427 },
428 .show = mpc85xx_l2_inject_data_hi_show,
429 .store = mpc85xx_l2_inject_data_hi_store},
430 {
431 .attr = {
432 .name = "inject_data_lo",
433 .mode = (S_IRUGO | S_IWUSR)
434 },
435 .show = mpc85xx_l2_inject_data_lo_show,
436 .store = mpc85xx_l2_inject_data_lo_store},
437 {
438 .attr = {
439 .name = "inject_ctrl",
440 .mode = (S_IRUGO | S_IWUSR)
441 },
442 .show = mpc85xx_l2_inject_ctrl_show,
443 .store = mpc85xx_l2_inject_ctrl_store},
444
445 /* End of list */
446 {
447 .attr = {.name = NULL}
448 }
449};
450
451static void mpc85xx_set_l2_sysfs_attributes(struct edac_device_ctl_info
452 *edac_dev)
453{
454 edac_dev->sysfs_attributes = mpc85xx_l2_sysfs_attributes;
455}
456
457/***************************** L2 ops ***********************************/
458
459static void mpc85xx_l2_check(struct edac_device_ctl_info *edac_dev)
460{
461 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
462 u32 err_detect;
463
464 err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET);
465
466 if (!(err_detect & L2_EDE_MASK))
467 return;
468
469 printk(KERN_ERR "ECC Error in CPU L2 cache\n");
470 printk(KERN_ERR "L2 Error Detect Register: 0x%08x\n", err_detect);
471 printk(KERN_ERR "L2 Error Capture Data High Register: 0x%08x\n",
472 in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATAHI));
473 printk(KERN_ERR "L2 Error Capture Data Lo Register: 0x%08x\n",
474 in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATALO));
475 printk(KERN_ERR "L2 Error Syndrome Register: 0x%08x\n",
476 in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTECC));
477 printk(KERN_ERR "L2 Error Attributes Capture Register: 0x%08x\n",
478 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRATTR));
479 printk(KERN_ERR "L2 Error Address Capture Register: 0x%08x\n",
480 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRADDR));
481
482 /* clear error detect register */
483 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, err_detect);
484
485 if (err_detect & L2_EDE_CE_MASK)
486 edac_device_handle_ce(edac_dev, 0, 0, edac_dev->ctl_name);
487
488 if (err_detect & L2_EDE_UE_MASK)
489 edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name);
490}
491
492static irqreturn_t mpc85xx_l2_isr(int irq, void *dev_id)
493{
494 struct edac_device_ctl_info *edac_dev = dev_id;
495 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
496 u32 err_detect;
497
498 err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET);
499
500 if (!(err_detect & L2_EDE_MASK))
501 return IRQ_NONE;
502
503 mpc85xx_l2_check(edac_dev);
504
505 return IRQ_HANDLED;
506}
507
508static int __devinit mpc85xx_l2_err_probe(struct of_device *op,
509 const struct of_device_id *match)
510{
511 struct edac_device_ctl_info *edac_dev;
512 struct mpc85xx_l2_pdata *pdata;
513 struct resource r;
514 int res;
515
516 if (!devres_open_group(&op->dev, mpc85xx_l2_err_probe, GFP_KERNEL))
517 return -ENOMEM;
518
519 edac_dev = edac_device_alloc_ctl_info(sizeof(*pdata),
520 "cpu", 1, "L", 1, 2, NULL, 0,
521 edac_dev_idx);
522 if (!edac_dev) {
523 devres_release_group(&op->dev, mpc85xx_l2_err_probe);
524 return -ENOMEM;
525 }
526
527 pdata = edac_dev->pvt_info;
528 pdata->name = "mpc85xx_l2_err";
529 pdata->irq = NO_IRQ;
530 edac_dev->dev = &op->dev;
531 dev_set_drvdata(edac_dev->dev, edac_dev);
532 edac_dev->ctl_name = pdata->name;
533 edac_dev->dev_name = pdata->name;
534
535 res = of_address_to_resource(op->node, 0, &r);
536 if (res) {
537 printk(KERN_ERR "%s: Unable to get resource for "
538 "L2 err regs\n", __func__);
539 goto err;
540 }
541
542 /* we only need the error registers */
543 r.start += 0xe00;
544
545 if (!devm_request_mem_region(&op->dev, r.start,
546 r.end - r.start + 1, pdata->name)) {
547 printk(KERN_ERR "%s: Error while requesting mem region\n",
548 __func__);
549 res = -EBUSY;
550 goto err;
551 }
552
553 pdata->l2_vbase = devm_ioremap(&op->dev, r.start, r.end - r.start + 1);
554 if (!pdata->l2_vbase) {
555 printk(KERN_ERR "%s: Unable to setup L2 err regs\n", __func__);
556 res = -ENOMEM;
557 goto err;
558 }
559
560 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, ~0);
561
562 orig_l2_err_disable = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS);
563
564 /* clear the err_dis */
565 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, 0);
566
567 edac_dev->mod_name = EDAC_MOD_STR;
568
569 if (edac_op_state == EDAC_OPSTATE_POLL)
570 edac_dev->edac_check = mpc85xx_l2_check;
571
572 mpc85xx_set_l2_sysfs_attributes(edac_dev);
573
574 pdata->edac_idx = edac_dev_idx++;
575
576 if (edac_device_add_device(edac_dev) > 0) {
577 debugf3("%s(): failed edac_device_add_device()\n", __func__);
578 goto err;
579 }
580
581 if (edac_op_state == EDAC_OPSTATE_INT) {
582 pdata->irq = irq_of_parse_and_map(op->node, 0);
583 res = devm_request_irq(&op->dev, pdata->irq,
584 mpc85xx_l2_isr, IRQF_DISABLED,
585 "[EDAC] L2 err", edac_dev);
586 if (res < 0) {
587 printk(KERN_ERR
588 "%s: Unable to requiest irq %d for "
589 "MPC85xx L2 err\n", __func__, pdata->irq);
590 irq_dispose_mapping(pdata->irq);
591 res = -ENODEV;
592 goto err2;
593 }
594
595 printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for L2 Err\n",
596 pdata->irq);
597
598 edac_dev->op_state = OP_RUNNING_INTERRUPT;
599
600 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, L2_EIE_MASK);
601 }
602
603 devres_remove_group(&op->dev, mpc85xx_l2_err_probe);
604
605 debugf3("%s(): success\n", __func__);
606 printk(KERN_INFO EDAC_MOD_STR " L2 err registered\n");
607
608 return 0;
609
610err2:
611 edac_device_del_device(&op->dev);
612err:
613 devres_release_group(&op->dev, mpc85xx_l2_err_probe);
614 edac_device_free_ctl_info(edac_dev);
615 return res;
616}
617
618static int mpc85xx_l2_err_remove(struct of_device *op)
619{
620 struct edac_device_ctl_info *edac_dev = dev_get_drvdata(&op->dev);
621 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
622
623 debugf0("%s()\n", __func__);
624
625 if (edac_op_state == EDAC_OPSTATE_INT) {
626 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, 0);
627 irq_dispose_mapping(pdata->irq);
628 }
629
630 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, orig_l2_err_disable);
631 edac_device_del_device(&op->dev);
632 edac_device_free_ctl_info(edac_dev);
633 return 0;
634}
635
636static struct of_device_id mpc85xx_l2_err_of_match[] = {
29d6cf26
KG		 637/* deprecate the fsl,85.. forms in the future, 2.6.30? */
638 { .compatible = "fsl,8540-l2-cache-controller", },
639 { .compatible = "fsl,8541-l2-cache-controller", },
640 { .compatible = "fsl,8544-l2-cache-controller", },
641 { .compatible = "fsl,8548-l2-cache-controller", },
642 { .compatible = "fsl,8555-l2-cache-controller", },
643 { .compatible = "fsl,8568-l2-cache-controller", },
644 { .compatible = "fsl,mpc8536-l2-cache-controller", },
645 { .compatible = "fsl,mpc8540-l2-cache-controller", },
646 { .compatible = "fsl,mpc8541-l2-cache-controller", },
647 { .compatible = "fsl,mpc8544-l2-cache-controller", },
648 { .compatible = "fsl,mpc8548-l2-cache-controller", },
649 { .compatible = "fsl,mpc8555-l2-cache-controller", },
650 { .compatible = "fsl,mpc8560-l2-cache-controller", },
651 { .compatible = "fsl,mpc8568-l2-cache-controller", },
652 { .compatible = "fsl,mpc8572-l2-cache-controller", },
a014554e 653 { .compatible = "fsl,p2020-l2-cache-controller", },
a9a753d5
DJ		 654 {},
655};
656
657static struct of_platform_driver mpc85xx_l2_err_driver = {
658 .owner = THIS_MODULE,
659 .name = "mpc85xx_l2_err",
660 .match_table = mpc85xx_l2_err_of_match,
661 .probe = mpc85xx_l2_err_probe,
662 .remove = mpc85xx_l2_err_remove,
663 .driver = {
664 .name = "mpc85xx_l2_err",
665 .owner = THIS_MODULE,
666 },
667};
668
669/**************************** MC Err device ***************************/
670
dcca7c3d
PT		 671/*
672 * Taken from table 8-55 in the MPC8641 User's Manual and/or 9-61 in the
673 * MPC8572 User's Manual. Each line represents a syndrome bit column as a
674 * 64-bit value, but split into an upper and lower 32-bit chunk. The labels
675 * below correspond to Freescale's manuals.
676 */
677static unsigned int ecc_table[16] = {
678 /* MSB LSB */
679 /* [0:31] [32:63] */
680 0xf00fe11e, 0xc33c0ff7, /* Syndrome bit 7 */
681 0x00ff00ff, 0x00fff0ff,
682 0x0f0f0f0f, 0x0f0fff00,
683 0x11113333, 0x7777000f,
684 0x22224444, 0x8888222f,
685 0x44448888, 0xffff4441,
686 0x8888ffff, 0x11118882,
687 0xffff1111, 0x22221114, /* Syndrome bit 0 */
688};
689
690/*
691 * Calculate the correct ECC value for a 64-bit value specified by high:low
692 */
693static u8 calculate_ecc(u32 high, u32 low)
694{
695 u32 mask_low;
696 u32 mask_high;
697 int bit_cnt;
698 u8 ecc = 0;
699 int i;
700 int j;
701
702 for (i = 0; i < 8; i++) {
703 mask_high = ecc_table[i * 2];
704 mask_low = ecc_table[i * 2 + 1];
705 bit_cnt = 0;
706
707 for (j = 0; j < 32; j++) {
708 if ((mask_high >> j) & 1)
709 bit_cnt ^= (high >> j) & 1;
710 if ((mask_low >> j) & 1)
711 bit_cnt ^= (low >> j) & 1;
712 }
713
714 ecc |= bit_cnt << i;
715 }
716
717 return ecc;
718}
719
720/*
721 * Create the syndrome code which is generated if the data line specified by
722 * 'bit' failed. Eg generate an 8-bit codes seen in Table 8-55 in the MPC8641
723 * User's Manual and 9-61 in the MPC8572 User's Manual.
724 */
725static u8 syndrome_from_bit(unsigned int bit) {
726 int i;
727 u8 syndrome = 0;
728
729 /*
730 * Cycle through the upper or lower 32-bit portion of each value in
731 * ecc_table depending on if 'bit' is in the upper or lower half of
732 * 64-bit data.
733 */
734 for (i = bit < 32; i < 16; i += 2)
735 syndrome |= ((ecc_table[i] >> (bit % 32)) & 1) << (i / 2);
736
737 return syndrome;
738}
739
740/*
741 * Decode data and ecc syndrome to determine what went wrong
742 * Note: This can only decode single-bit errors
743 */
744static void sbe_ecc_decode(u32 cap_high, u32 cap_low, u32 cap_ecc,
745 int *bad_data_bit, int *bad_ecc_bit)
746{
747 int i;
748 u8 syndrome;
749
750 *bad_data_bit = -1;
751 *bad_ecc_bit = -1;
752
753 /*
754 * Calculate the ECC of the captured data and XOR it with the captured
755 * ECC to find an ECC syndrome value we can search for
756 */
757 syndrome = calculate_ecc(cap_high, cap_low) ^ cap_ecc;
758
759 /* Check if a data line is stuck... */
760 for (i = 0; i < 64; i++) {
761 if (syndrome == syndrome_from_bit(i)) {
762 *bad_data_bit = i;
763 return;
764 }
765 }
766
767 /* If data is correct, check ECC bits for errors... */
768 for (i = 0; i < 8; i++) {
769 if ((syndrome >> i) & 0x1) {
770 *bad_ecc_bit = i;
771 return;
772 }
773 }
774}
775
a9a753d5
DJ		 776static void mpc85xx_mc_check(struct mem_ctl_info *mci)
777{
778 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
779 struct csrow_info *csrow;
21768639 780 u32 bus_width;
a9a753d5
DJ		 781 u32 err_detect;
782 u32 syndrome;
783 u32 err_addr;
784 u32 pfn;
785 int row_index;
dcca7c3d
PT		 786 u32 cap_high;
787 u32 cap_low;
788 int bad_data_bit;
789 int bad_ecc_bit;
a9a753d5
DJ		 790
791 err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT);
55e5750b 792 if (!err_detect)
a9a753d5
DJ		 793 return;
794
795 mpc85xx_mc_printk(mci, KERN_ERR, "Err Detect Register: %#8.8x\n",
796 err_detect);
797
798 /* no more processing if not ECC bit errors */
799 if (!(err_detect & (DDR_EDE_SBE | DDR_EDE_MBE))) {
800 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect);
801 return;
802 }
803
804 syndrome = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ECC);
21768639
PT		 805
806 /* Mask off appropriate bits of syndrome based on bus width */
807 bus_width = (in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG) &
808 DSC_DBW_MASK) ? 32 : 64;
809 if (bus_width == 64)
810 syndrome &= 0xff;
811 else
812 syndrome &= 0xffff;
813
a9a753d5
DJ		 814 err_addr = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ADDRESS);
815 pfn = err_addr >> PAGE_SHIFT;
816
817 for (row_index = 0; row_index < mci->nr_csrows; row_index++) {
818 csrow = &mci->csrows[row_index];
819 if ((pfn >= csrow->first_page) && (pfn <= csrow->last_page))
820 break;
821 }
822
dcca7c3d
PT		 823 cap_high = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_DATA_HI);
824 cap_low = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_DATA_LO);
825
826 /*
827 * Analyze single-bit errors on 64-bit wide buses
828 * TODO: Add support for 32-bit wide buses
829 */
830 if ((err_detect & DDR_EDE_SBE) && (bus_width == 64)) {
831 sbe_ecc_decode(cap_high, cap_low, syndrome,
832 &bad_data_bit, &bad_ecc_bit);
833
834 if (bad_data_bit != -1)
835 mpc85xx_mc_printk(mci, KERN_ERR,
836 "Faulty Data bit: %d\n", bad_data_bit);
837 if (bad_ecc_bit != -1)
838 mpc85xx_mc_printk(mci, KERN_ERR,
839 "Faulty ECC bit: %d\n", bad_ecc_bit);
840
841 mpc85xx_mc_printk(mci, KERN_ERR,
842 "Expected Data / ECC:\t%#8.8x_%08x / %#2.2x\n",
843 cap_high ^ (1 << (bad_data_bit - 32)),
844 cap_low ^ (1 << bad_data_bit),
845 syndrome ^ (1 << bad_ecc_bit));
846 }
847
848 mpc85xx_mc_printk(mci, KERN_ERR,
849 "Captured Data / ECC:\t%#8.8x_%08x / %#2.2x\n",
850 cap_high, cap_low, syndrome);
851 mpc85xx_mc_printk(mci, KERN_ERR, "Err addr: %#8.8x\n", err_addr);
a9a753d5
DJ		 852 mpc85xx_mc_printk(mci, KERN_ERR, "PFN: %#8.8x\n", pfn);
853
854 /* we are out of range */
855 if (row_index == mci->nr_csrows)
856 mpc85xx_mc_printk(mci, KERN_ERR, "PFN out of range!\n");
857
858 if (err_detect & DDR_EDE_SBE)
859 edac_mc_handle_ce(mci, pfn, err_addr & PAGE_MASK,
860 syndrome, row_index, 0, mci->ctl_name);
861
862 if (err_detect & DDR_EDE_MBE)
863 edac_mc_handle_ue(mci, pfn, err_addr & PAGE_MASK,
864 row_index, mci->ctl_name);
865
866 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect);
867}
868
869static irqreturn_t mpc85xx_mc_isr(int irq, void *dev_id)
870{
871 struct mem_ctl_info *mci = dev_id;
872 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
873 u32 err_detect;
874
875 err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT);
876 if (!err_detect)
877 return IRQ_NONE;
878
879 mpc85xx_mc_check(mci);
880
881 return IRQ_HANDLED;
882}
883
884static void __devinit mpc85xx_init_csrows(struct mem_ctl_info *mci)
885{
886 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
887 struct csrow_info *csrow;
888 u32 sdram_ctl;
889 u32 sdtype;
890 enum mem_type mtype;
891 u32 cs_bnds;
892 int index;
893
894 sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG);
895
896 sdtype = sdram_ctl & DSC_SDTYPE_MASK;
897 if (sdram_ctl & DSC_RD_EN) {
898 switch (sdtype) {
899 case DSC_SDTYPE_DDR:
900 mtype = MEM_RDDR;
901 break;
902 case DSC_SDTYPE_DDR2:
903 mtype = MEM_RDDR2;
904 break;
b1cfebc9
YS		 905 case DSC_SDTYPE_DDR3:
906 mtype = MEM_RDDR3;
907 break;
a9a753d5
DJ		 908 default:
909 mtype = MEM_UNKNOWN;
910 break;
911 }
912 } else {
913 switch (sdtype) {
914 case DSC_SDTYPE_DDR:
915 mtype = MEM_DDR;
916 break;
917 case DSC_SDTYPE_DDR2:
918 mtype = MEM_DDR2;
919 break;
b1cfebc9
YS		 920 case DSC_SDTYPE_DDR3:
921 mtype = MEM_DDR3;
922 break;
a9a753d5
DJ		 923 default:
924 mtype = MEM_UNKNOWN;
925 break;
926 }
927 }
928
929 for (index = 0; index < mci->nr_csrows; index++) {
930 u32 start;
931 u32 end;
932
933 csrow = &mci->csrows[index];
934 cs_bnds = in_be32(pdata->mc_vbase + MPC85XX_MC_CS_BNDS_0 +
935 (index * MPC85XX_MC_CS_BNDS_OFS));
b4846251
IS		 936
937 start = (cs_bnds & 0xffff0000) >> 16;
938 end = (cs_bnds & 0x0000ffff);
a9a753d5
DJ		 939
940 if (start == end)
941 continue; /* not populated */
942
b4846251
IS		 943 start <<= (24 - PAGE_SHIFT);
944 end <<= (24 - PAGE_SHIFT);
945 end |= (1 << (24 - PAGE_SHIFT)) - 1;
946
cff9279e
PT		 947 csrow->first_page = start;
948 csrow->last_page = end;
b4846251 949 csrow->nr_pages = end + 1 - start;
a9a753d5
DJ		 950 csrow->grain = 8;
951 csrow->mtype = mtype;
952 csrow->dtype = DEV_UNKNOWN;
953 if (sdram_ctl & DSC_X32_EN)
954 csrow->dtype = DEV_X32;
955 csrow->edac_mode = EDAC_SECDED;
956 }
957}
958
959static int __devinit mpc85xx_mc_err_probe(struct of_device *op,
960 const struct of_device_id *match)
961{
962 struct mem_ctl_info *mci;
963 struct mpc85xx_mc_pdata *pdata;
964 struct resource r;
965 u32 sdram_ctl;
966 int res;
967
968 if (!devres_open_group(&op->dev, mpc85xx_mc_err_probe, GFP_KERNEL))
969 return -ENOMEM;
970
971 mci = edac_mc_alloc(sizeof(*pdata), 4, 1, edac_mc_idx);
972 if (!mci) {
973 devres_release_group(&op->dev, mpc85xx_mc_err_probe);
974 return -ENOMEM;
975 }
976
977 pdata = mci->pvt_info;
978 pdata->name = "mpc85xx_mc_err";
979 pdata->irq = NO_IRQ;
980 mci->dev = &op->dev;
981 pdata->edac_idx = edac_mc_idx++;
982 dev_set_drvdata(mci->dev, mci);
983 mci->ctl_name = pdata->name;
984 mci->dev_name = pdata->name;
985
986 res = of_address_to_resource(op->node, 0, &r);
987 if (res) {
988 printk(KERN_ERR "%s: Unable to get resource for MC err regs\n",
989 __func__);
990 goto err;
991 }
992
993 if (!devm_request_mem_region(&op->dev, r.start,
994 r.end - r.start + 1, pdata->name)) {
995 printk(KERN_ERR "%s: Error while requesting mem region\n",
996 __func__);
997 res = -EBUSY;
998 goto err;
999 }
1000
1001 pdata->mc_vbase = devm_ioremap(&op->dev, r.start, r.end - r.start + 1);
1002 if (!pdata->mc_vbase) {
1003 printk(KERN_ERR "%s: Unable to setup MC err regs\n", __func__);
1004 res = -ENOMEM;
1005 goto err;
1006 }
1007
1008 sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG);
1009 if (!(sdram_ctl & DSC_ECC_EN)) {
1010 /* no ECC */
1011 printk(KERN_WARNING "%s: No ECC DIMMs discovered\n", __func__);
1012 res = -ENODEV;
1013 goto err;
1014 }
1015
1016 debugf3("%s(): init mci\n", __func__);
1017 mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_RDDR2 |
1018 MEM_FLAG_DDR | MEM_FLAG_DDR2;
1019 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
1020 mci->edac_cap = EDAC_FLAG_SECDED;
1021 mci->mod_name = EDAC_MOD_STR;
1022 mci->mod_ver = MPC85XX_REVISION;
1023
1024 if (edac_op_state == EDAC_OPSTATE_POLL)
1025 mci->edac_check = mpc85xx_mc_check;
1026
1027 mci->ctl_page_to_phys = NULL;
1028
1029 mci->scrub_mode = SCRUB_SW_SRC;
1030
1031 mpc85xx_set_mc_sysfs_attributes(mci);
1032
1033 mpc85xx_init_csrows(mci);
1034
a9a753d5
DJ		 1035 /* store the original error disable bits */
1036 orig_ddr_err_disable =
1037 in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE);
1038 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE, 0);
1039
1040 /* clear all error bits */
1041 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, ~0);
1042
1043 if (edac_mc_add_mc(mci)) {
1044 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
1045 goto err;
1046 }
1047
1048 if (edac_op_state == EDAC_OPSTATE_INT) {
1049 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN,
1050 DDR_EIE_MBEE | DDR_EIE_SBEE);
1051
1052 /* store the original error management threshold */
1053 orig_ddr_err_sbe = in_be32(pdata->mc_vbase +
1054 MPC85XX_MC_ERR_SBE) & 0xff0000;
1055
1056 /* set threshold to 1 error per interrupt */
1057 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, 0x10000);
1058
1059 /* register interrupts */
1060 pdata->irq = irq_of_parse_and_map(op->node, 0);
1061 res = devm_request_irq(&op->dev, pdata->irq,
60be7551
AK		 1062 mpc85xx_mc_isr,
1063 IRQF_DISABLED | IRQF_SHARED,
a9a753d5
DJ		 1064 "[EDAC] MC err", mci);
1065 if (res < 0) {
1066 printk(KERN_ERR "%s: Unable to request irq %d for "
1067 "MPC85xx DRAM ERR\n", __func__, pdata->irq);
1068 irq_dispose_mapping(pdata->irq);
1069 res = -ENODEV;
1070 goto err2;
1071 }
1072
1073 printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for MC\n",
1074 pdata->irq);
1075 }
1076
1077 devres_remove_group(&op->dev, mpc85xx_mc_err_probe);
1078 debugf3("%s(): success\n", __func__);
1079 printk(KERN_INFO EDAC_MOD_STR " MC err registered\n");
1080
1081 return 0;
1082
1083err2:
1084 edac_mc_del_mc(&op->dev);
1085err:
1086 devres_release_group(&op->dev, mpc85xx_mc_err_probe);
1087 edac_mc_free(mci);
1088 return res;
1089}
1090
1091static int mpc85xx_mc_err_remove(struct of_device *op)
1092{
1093 struct mem_ctl_info *mci = dev_get_drvdata(&op->dev);
1094 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
1095
1096 debugf0("%s()\n", __func__);
1097
1098 if (edac_op_state == EDAC_OPSTATE_INT) {
1099 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN, 0);
1100 irq_dispose_mapping(pdata->irq);
1101 }
1102
1103 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE,
1104 orig_ddr_err_disable);
1105 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, orig_ddr_err_sbe);
1106
1107 edac_mc_del_mc(&op->dev);
1108 edac_mc_free(mci);
1109 return 0;
1110}
1111
1112static struct of_device_id mpc85xx_mc_err_of_match[] = {
29d6cf26
KG		 1113/* deprecate the fsl,85.. forms in the future, 2.6.30? */
1114 { .compatible = "fsl,8540-memory-controller", },
1115 { .compatible = "fsl,8541-memory-controller", },
1116 { .compatible = "fsl,8544-memory-controller", },
1117 { .compatible = "fsl,8548-memory-controller", },
1118 { .compatible = "fsl,8555-memory-controller", },
1119 { .compatible = "fsl,8568-memory-controller", },
1120 { .compatible = "fsl,mpc8536-memory-controller", },
1121 { .compatible = "fsl,mpc8540-memory-controller", },
1122 { .compatible = "fsl,mpc8541-memory-controller", },
1123 { .compatible = "fsl,mpc8544-memory-controller", },
1124 { .compatible = "fsl,mpc8548-memory-controller", },
1125 { .compatible = "fsl,mpc8555-memory-controller", },
1126 { .compatible = "fsl,mpc8560-memory-controller", },
1127 { .compatible = "fsl,mpc8568-memory-controller", },
1128 { .compatible = "fsl,mpc8572-memory-controller", },
b4846251 1129 { .compatible = "fsl,mpc8349-memory-controller", },
a014554e 1130 { .compatible = "fsl,p2020-memory-controller", },
a9a753d5
DJ		 1131 {},
1132};
1133
1134static struct of_platform_driver mpc85xx_mc_err_driver = {
1135 .owner = THIS_MODULE,
1136 .name = "mpc85xx_mc_err",
1137 .match_table = mpc85xx_mc_err_of_match,
1138 .probe = mpc85xx_mc_err_probe,
1139 .remove = mpc85xx_mc_err_remove,
1140 .driver = {
1141 .name = "mpc85xx_mc_err",
1142 .owner = THIS_MODULE,
1143 },
1144};
1145
b4846251 1146#ifdef CONFIG_MPC85xx
60be7551
AK		 1147static void __init mpc85xx_mc_clear_rfxe(void *data)
1148{
1149 orig_hid1[smp_processor_id()] = mfspr(SPRN_HID1);
1150 mtspr(SPRN_HID1, (orig_hid1[smp_processor_id()] & ~0x20000));
1151}
b4846251 1152#endif
60be7551 1153
a9a753d5
DJ		 1154static int __init mpc85xx_mc_init(void)
1155{
1156 int res = 0;
1157
1158 printk(KERN_INFO "Freescale(R) MPC85xx EDAC driver, "
1159 "(C) 2006 Montavista Software\n");
1160
1161 /* make sure error reporting method is sane */
1162 switch (edac_op_state) {
1163 case EDAC_OPSTATE_POLL:
1164 case EDAC_OPSTATE_INT:
1165 break;
1166 default:
1167 edac_op_state = EDAC_OPSTATE_INT;
1168 break;
1169 }
1170
1171 res = of_register_platform_driver(&mpc85xx_mc_err_driver);
1172 if (res)
1173 printk(KERN_WARNING EDAC_MOD_STR "MC fails to register\n");
1174
1175 res = of_register_platform_driver(&mpc85xx_l2_err_driver);
1176 if (res)
1177 printk(KERN_WARNING EDAC_MOD_STR "L2 fails to register\n");
1178
1179#ifdef CONFIG_PCI
f87bd330 1180 res = of_register_platform_driver(&mpc85xx_pci_err_driver);
a9a753d5
DJ		 1181 if (res)
1182 printk(KERN_WARNING EDAC_MOD_STR "PCI fails to register\n");
1183#endif
1184
b4846251 1185#ifdef CONFIG_MPC85xx
a9a753d5
DJ		 1186 /*
1187 * need to clear HID1[RFXE] to disable machine check int
1188 * so we can catch it
1189 */
60be7551
AK		 1190 if (edac_op_state == EDAC_OPSTATE_INT)
1191 on_each_cpu(mpc85xx_mc_clear_rfxe, NULL, 0);
b4846251 1192#endif
a9a753d5
DJ		 1193
1194 return 0;
1195}
1196
1197module_init(mpc85xx_mc_init);
1198
b4846251 1199#ifdef CONFIG_MPC85xx
60be7551
AK		 1200static void __exit mpc85xx_mc_restore_hid1(void *data)
1201{
1202 mtspr(SPRN_HID1, orig_hid1[smp_processor_id()]);
1203}
b4846251 1204#endif
60be7551 1205
a9a753d5
DJ		 1206static void __exit mpc85xx_mc_exit(void)
1207{
b4846251 1208#ifdef CONFIG_MPC85xx
60be7551 1209 on_each_cpu(mpc85xx_mc_restore_hid1, NULL, 0);
b4846251 1210#endif
a9a753d5 1211#ifdef CONFIG_PCI
f87bd330 1212 of_unregister_platform_driver(&mpc85xx_pci_err_driver);
a9a753d5
DJ		 1213#endif
1214 of_unregister_platform_driver(&mpc85xx_l2_err_driver);
1215 of_unregister_platform_driver(&mpc85xx_mc_err_driver);
1216}
1217
1218module_exit(mpc85xx_mc_exit);
1219
1220MODULE_LICENSE("GPL");
1221MODULE_AUTHOR("Montavista Software, Inc.");
1222module_param(edac_op_state, int, 0444);
1223MODULE_PARM_DESC(edac_op_state,
1224 "EDAC Error Reporting state: 0=Poll, 2=Interrupt");
Linux kernel - Deliverables
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