[deliverable/linux.git] / drivers / edac / r82600_edac.c

/*
 * Radisys 82600 Embedded chipset Memory Controller kernel module
 * (C) 2005 EADS Astrium
 * This file may be distributed under the terms of the
 * GNU General Public License.
 *
 * Written by Tim Small <tim@buttersideup.com>, based on work by Thayne
 * Harbaugh, Dan Hollis <goemon at anime dot net> and others.
 *
 * $Id: edac_r82600.c,v 1.1.2.6 2005/10/05 00:43:44 dsp_llnl Exp $
 *
 * Written with reference to 82600 High Integration Dual PCI System
 * Controller Data Book:
 * http://www.radisys.com/files/support_downloads/007-01277-0002.82600DataBook.pdf
 * references to this document given in []
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/slab.h>
#include "edac_mc.h"

#define R82600_REVISION	" Ver: 2.0.1 " __DATE__
#define EDAC_MOD_STR	"r82600_edac"

#define r82600_printk(level, fmt, arg...) \
	edac_printk(level, "r82600", fmt, ##arg)

#define r82600_mc_printk(mci, level, fmt, arg...) \
	edac_mc_chipset_printk(mci, level, "r82600", fmt, ##arg)

/* Radisys say "The 82600 integrates a main memory SDRAM controller that
 * supports up to four banks of memory. The four banks can support a mix of
 * sizes of 64 bit wide (72 bits with ECC) Synchronous DRAM (SDRAM) DIMMs,
 * each of which can be any size from 16MB to 512MB. Both registered (control
 * signals buffered) and unbuffered DIMM types are supported. Mixing of
 * registered and unbuffered DIMMs as well as mixing of ECC and non-ECC DIMMs
 * is not allowed. The 82600 SDRAM interface operates at the same frequency as
 * the CPU bus, 66MHz, 100MHz or 133MHz."
 */

#define R82600_NR_CSROWS 4
#define R82600_NR_CHANS  1
#define R82600_NR_DIMMS  4

#define R82600_BRIDGE_ID  0x8200

/* Radisys 82600 register addresses - device 0 function 0 - PCI bridge */
#define R82600_DRAMC	0x57	/* Various SDRAM related control bits
				 * all bits are R/W
				 *
				 * 7    SDRAM ISA Hole Enable
				 * 6    Flash Page Mode Enable
				 * 5    ECC Enable: 1=ECC 0=noECC
				 * 4    DRAM DIMM Type: 1=
				 * 3    BIOS Alias Disable
				 * 2    SDRAM BIOS Flash Write Enable
				 * 1:0  SDRAM Refresh Rate: 00=Disabled
				 *          01=7.8usec (256Mbit SDRAMs)
				 *          10=15.6us 11=125usec
				 */

#define R82600_SDRAMC	0x76	/* "SDRAM Control Register"
				 * More SDRAM related control bits
				 * all bits are R/W
				 *
				 * 15:8 Reserved.
				 *
				 * 7:5  Special SDRAM Mode Select
				 *
				 * 4    Force ECC
				 *
				 *        1=Drive ECC bits to 0 during
				 *          write cycles (i.e. ECC test mode)
				 *
				 *        0=Normal ECC functioning
				 *
				 * 3    Enhanced Paging Enable
				 *
				 * 2    CAS# Latency 0=3clks 1=2clks
				 *
				 * 1    RAS# to CAS# Delay 0=3 1=2
				 *
				 * 0    RAS# Precharge     0=3 1=2
				 */

#define R82600_EAP	0x80	/* ECC Error Address Pointer Register
				 *
				 * 31    Disable Hardware Scrubbing (RW)
				 *        0=Scrub on corrected read
				 *        1=Don't scrub on corrected read
				 *
				 * 30:12 Error Address Pointer (RO)
				 *        Upper 19 bits of error address
				 *
				 * 11:4  Syndrome Bits (RO)
				 *
				 * 3     BSERR# on multibit error (RW)
				 *        1=enable 0=disable
				 *
				 * 2     NMI on Single Bit Eror (RW)
				 *        1=NMI triggered by SBE n.b. other
				 *          prerequeists
				 *        0=NMI not triggered
				 *
				 * 1     MBE (R/WC)
				 *        read 1=MBE at EAP (see above)
				 *        read 0=no MBE, or SBE occurred first
				 *        write 1=Clear MBE status (must also
				 *          clear SBE)
				 *        write 0=NOP
				 *
				 * 1     SBE (R/WC)
				 *        read 1=SBE at EAP (see above)
				 *        read 0=no SBE, or MBE occurred first
				 *        write 1=Clear SBE status (must also
				 *          clear MBE)
				 *        write 0=NOP
				 */

#define R82600_DRBA	0x60	/* + 0x60..0x63 SDRAM Row Boundry Address
				 *  Registers
				 *
				 * 7:0  Address lines 30:24 - upper limit of
				 * each row [p57]
				 */

struct r82600_error_info {
	u32 eapr;
};

static unsigned int disable_hardware_scrub = 0;

static void r82600_get_error_info (struct mem_ctl_info *mci,
		struct r82600_error_info *info)
{
	struct pci_dev *pdev;

	pdev = to_pci_dev(mci->dev);
	pci_read_config_dword(pdev, R82600_EAP, &info->eapr);

	if (info->eapr & BIT(0))
		/* Clear error to allow next error to be reported [p.62] */
		pci_write_bits32(pdev, R82600_EAP,
				((u32) BIT(0) & (u32) BIT(1)),
				((u32) BIT(0) & (u32) BIT(1)));

	if (info->eapr & BIT(1))
		/* Clear error to allow next error to be reported [p.62] */
		pci_write_bits32(pdev, R82600_EAP,
				((u32) BIT(0) & (u32) BIT(1)),
				((u32) BIT(0) & (u32) BIT(1)));
}

static int r82600_process_error_info (struct mem_ctl_info *mci,
		struct r82600_error_info *info, int handle_errors)
{
	int error_found;
	u32 eapaddr, page;
	u32 syndrome;

	error_found = 0;

	/* bits 30:12 store the upper 19 bits of the 32 bit error address */
	eapaddr = ((info->eapr >> 12) & 0x7FFF) << 13;
	/* Syndrome in bits 11:4 [p.62]       */
	syndrome = (info->eapr >> 4) & 0xFF;

	/* the R82600 reports at less than page *
	 * granularity (upper 19 bits only)     */
	page = eapaddr >> PAGE_SHIFT;

	if (info->eapr & BIT(0)) {  /* CE? */
		error_found = 1;

		if (handle_errors)
			edac_mc_handle_ce(mci, page, 0,  /* not avail */
					syndrome,
					edac_mc_find_csrow_by_page(mci, page),
					0,  /* channel */
					mci->ctl_name);
	}

	if (info->eapr & BIT(1)) {  /* UE? */
		error_found = 1;

		if (handle_errors)
			/* 82600 doesn't give enough info */
			edac_mc_handle_ue(mci, page, 0,
				edac_mc_find_csrow_by_page(mci, page),
				mci->ctl_name);
	}

	return error_found;
}

static void r82600_check(struct mem_ctl_info *mci)
{
	struct r82600_error_info info;

	debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
	r82600_get_error_info(mci, &info);
	r82600_process_error_info(mci, &info, 1);
}

static inline int ecc_enabled(u8 dramcr)
{
	return dramcr & BIT(5);
}

static void r82600_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
		u8 dramcr)
{
	struct csrow_info *csrow;
	int index;
	u8 drbar;  /* SDRAM Row Boundry Address Register */
	u32 row_high_limit, row_high_limit_last;
	u32 reg_sdram, ecc_on, row_base;

	ecc_on = ecc_enabled(dramcr);
	reg_sdram = dramcr & BIT(4);
	row_high_limit_last = 0;

	for (index = 0; index < mci->nr_csrows; index++) {
		csrow = &mci->csrows[index];

		/* find the DRAM Chip Select Base address and mask */
		pci_read_config_byte(pdev, R82600_DRBA + index, &drbar);

		debugf1("%s() Row=%d DRBA = %#0x\n", __func__, index, drbar);

		row_high_limit = ((u32) drbar << 24);
/*		row_high_limit = ((u32)drbar << 24) | 0xffffffUL; */

		debugf1("%s() Row=%d, Boundry Address=%#0x, Last = %#0x\n",
			__func__, index, row_high_limit, row_high_limit_last);

		/* Empty row [p.57] */
		if (row_high_limit == row_high_limit_last)
			continue;

		row_base = row_high_limit_last;

		csrow->first_page = row_base >> PAGE_SHIFT;
		csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1;
		csrow->nr_pages = csrow->last_page - csrow->first_page + 1;
		/* Error address is top 19 bits - so granularity is      *
		 * 14 bits                                               */
		csrow->grain = 1 << 14;
		csrow->mtype = reg_sdram ? MEM_RDDR : MEM_DDR;
		/* FIXME - check that this is unknowable with this chipset */
		csrow->dtype = DEV_UNKNOWN;

		/* Mode is global on 82600 */
		csrow->edac_mode = ecc_on ? EDAC_SECDED : EDAC_NONE;
		row_high_limit_last = row_high_limit;
	}
}

static int r82600_probe1(struct pci_dev *pdev, int dev_idx)
{
	struct mem_ctl_info *mci;
	u8 dramcr;
	u32 eapr;
	u32 scrub_disabled;
	u32 sdram_refresh_rate;
	struct r82600_error_info discard;

	debugf0("%s()\n", __func__);
	pci_read_config_byte(pdev, R82600_DRAMC, &dramcr);
	pci_read_config_dword(pdev, R82600_EAP, &eapr);
	scrub_disabled = eapr & BIT(31);
	sdram_refresh_rate = dramcr & (BIT(0) | BIT(1));
	debugf2("%s(): sdram refresh rate = %#0x\n", __func__,
		sdram_refresh_rate);
	debugf2("%s(): DRAMC register = %#0x\n", __func__, dramcr);
	mci = edac_mc_alloc(0, R82600_NR_CSROWS, R82600_NR_CHANS);

	if (mci == NULL)
		return -ENOMEM;

	debugf0("%s(): mci = %p\n", __func__, mci);
	mci->dev = &pdev->dev;
	mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_DDR;
	mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
	/* FIXME try to work out if the chip leads have been used for COM2
	 * instead on this board? [MA6?] MAYBE:
	 */

	/* On the R82600, the pins for memory bits 72:65 - i.e. the   *
	 * EC bits are shared with the pins for COM2 (!), so if COM2  *
	 * is enabled, we assume COM2 is wired up, and thus no EDAC   *
	 * is possible.                                               */
	mci->edac_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;

	if (ecc_enabled(dramcr)) {
		if (scrub_disabled)
			debugf3("%s(): mci = %p - Scrubbing disabled! EAP: "
				"%#0x\n", __func__, mci, eapr);
	} else
		mci->edac_cap = EDAC_FLAG_NONE;

	mci->mod_name = EDAC_MOD_STR;
	mci->mod_ver = R82600_REVISION;
	mci->ctl_name = "R82600";
	mci->edac_check = r82600_check;
	mci->ctl_page_to_phys = NULL;
	r82600_init_csrows(mci, pdev, dramcr);
	r82600_get_error_info(mci, &discard);  /* clear counters */

	/* Here we assume that we will never see multiple instances of this
	 * type of memory controller.  The ID is therefore hardcoded to 0.
	 */
	if (edac_mc_add_mc(mci,0)) {
		debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
		goto fail;
	}

	/* get this far and it's successful */

	if (disable_hardware_scrub) {
		debugf3("%s(): Disabling Hardware Scrub (scrub on error)\n",
			__func__);
		pci_write_bits32(pdev, R82600_EAP, BIT(31), BIT(31));
	}

	debugf3("%s(): success\n", __func__);
	return 0;

fail:
	edac_mc_free(mci);
	return -ENODEV;
}

/* returns count (>= 0), or negative on error */
static int __devinit r82600_init_one(struct pci_dev *pdev,
		const struct pci_device_id *ent)
{
	debugf0("%s()\n", __func__);

	/* don't need to call pci_device_enable() */
	return r82600_probe1(pdev, ent->driver_data);
}

static void __devexit r82600_remove_one(struct pci_dev *pdev)
{
	struct mem_ctl_info *mci;

	debugf0("%s()\n", __func__);

	if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
		return;

	edac_mc_free(mci);
}

static const struct pci_device_id r82600_pci_tbl[] __devinitdata = {
	{
		PCI_DEVICE(PCI_VENDOR_ID_RADISYS, R82600_BRIDGE_ID)
	},
	{
		0,
	}	/* 0 terminated list. */
};

MODULE_DEVICE_TABLE(pci, r82600_pci_tbl);

static struct pci_driver r82600_driver = {
	.name = EDAC_MOD_STR,
	.probe = r82600_init_one,
	.remove = __devexit_p(r82600_remove_one),
	.id_table = r82600_pci_tbl,
};

static int __init r82600_init(void)
{
	return pci_register_driver(&r82600_driver);
}

static void __exit r82600_exit(void)
{
	pci_unregister_driver(&r82600_driver);
}

module_init(r82600_init);
module_exit(r82600_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Tim Small <tim@buttersideup.com> - WPAD Ltd. "
	"on behalf of EADS Astrium");
MODULE_DESCRIPTION("MC support for Radisys 82600 memory controllers");

module_param(disable_hardware_scrub, bool, 0644);
MODULE_PARM_DESC(disable_hardware_scrub,
		 "If set, disable the chipset's automatic scrub for CEs");
Commit	Line	Data
2f768af7 AC	1	/*
	2	* Radisys 82600 Embedded chipset Memory Controller kernel module
	3	* (C) 2005 EADS Astrium
	4	* This file may be distributed under the terms of the
	5	* GNU General Public License.
	6	*
	7	* Written by Tim Small <tim@buttersideup.com>, based on work by Thayne
	8	* Harbaugh, Dan Hollis <goemon at anime dot net> and others.
	9	*
	10	* $Id: edac_r82600.c,v 1.1.2.6 2005/10/05 00:43:44 dsp_llnl Exp $
	11	*
	12	* Written with reference to 82600 High Integration Dual PCI System
	13	* Controller Data Book:
	14	* http://www.radisys.com/files/support_downloads/007-01277-0002.82600DataBook.pdf
	15	* references to this document given in []
	16	*/
	17
2f768af7 AC	18	#include <linux/module.h>
2f768af7 AC	19	#include <linux/init.h>
2f768af7 AC	20	#include <linux/pci.h>
2f768af7 AC	21	#include <linux/pci_ids.h>
2f768af7	22	#include <linux/slab.h>
2f768af7 AC	23	#include "edac_mc.h"
2f768af7 AC	24
929a40ec DT	25	#define R82600_REVISION " Ver: 2.0.1 " __DATE__
929a40ec DT	26	#define EDAC_MOD_STR "r82600_edac"
37f04581	27
537fba28	28	#define r82600_printk(level, fmt, arg...) \
e7ecd891	29	edac_printk(level, "r82600", fmt, ##arg)
537fba28 DP	30
537fba28 DP	31	#define r82600_mc_printk(mci, level, fmt, arg...) \
e7ecd891	32	edac_mc_chipset_printk(mci, level, "r82600", fmt, ##arg)
537fba28	33
2f768af7 AC	34	/* Radisys say "The 82600 integrates a main memory SDRAM controller that
	35	* supports up to four banks of memory. The four banks can support a mix of
	36	* sizes of 64 bit wide (72 bits with ECC) Synchronous DRAM (SDRAM) DIMMs,
	37	* each of which can be any size from 16MB to 512MB. Both registered (control
	38	* signals buffered) and unbuffered DIMM types are supported. Mixing of
	39	* registered and unbuffered DIMMs as well as mixing of ECC and non-ECC DIMMs
	40	* is not allowed. The 82600 SDRAM interface operates at the same frequency as
	41	* the CPU bus, 66MHz, 100MHz or 133MHz."
	42	*/
	43
	44	#define R82600_NR_CSROWS 4
	45	#define R82600_NR_CHANS 1
	46	#define R82600_NR_DIMMS 4
	47
	48	#define R82600_BRIDGE_ID 0x8200
	49
	50	/* Radisys 82600 register addresses - device 0 function 0 - PCI bridge */
	51	#define R82600_DRAMC 0x57 /* Various SDRAM related control bits
	52	* all bits are R/W
	53	*
	54	* 7 SDRAM ISA Hole Enable
	55	* 6 Flash Page Mode Enable
	56	* 5 ECC Enable: 1=ECC 0=noECC
	57	* 4 DRAM DIMM Type: 1=
	58	* 3 BIOS Alias Disable
	59	* 2 SDRAM BIOS Flash Write Enable
	60	* 1:0 SDRAM Refresh Rate: 00=Disabled
	61	* 01=7.8usec (256Mbit SDRAMs)
	62	* 10=15.6us 11=125usec
	63	*/
	64
	65	#define R82600_SDRAMC 0x76 /* "SDRAM Control Register"
	66	* More SDRAM related control bits
	67	* all bits are R/W
	68	*
	69	* 15:8 Reserved.
	70	*
	71	* 7:5 Special SDRAM Mode Select
	72	*
	73	* 4 Force ECC
	74	*
	75	* 1=Drive ECC bits to 0 during
	76	* write cycles (i.e. ECC test mode)
	77	*
	78	* 0=Normal ECC functioning
	79	*
	80	* 3 Enhanced Paging Enable
	81	*
	82	* 2 CAS# Latency 0=3clks 1=2clks
	83	*
	84	* 1 RAS# to CAS# Delay 0=3 1=2
	85	*
	86	* 0 RAS# Precharge 0=3 1=2
	87	*/
	88
	89	#define R82600_EAP 0x80 /* ECC Error Address Pointer Register
	90	*
	91	* 31 Disable Hardware Scrubbing (RW)
	92	* 0=Scrub on corrected read
	93	* 1=Don't scrub on corrected read
	94	*
	95	* 30:12 Error Address Pointer (RO)
	96	* Upper 19 bits of error address
	97	*
98	* 11:4 Syndrome Bits (RO)
99	*
100	* 3 BSERR# on multibit error (RW)
101	* 1=enable 0=disable
102	*
103	* 2 NMI on Single Bit Eror (RW)
104	* 1=NMI triggered by SBE n.b. other
105	* prerequeists
106	* 0=NMI not triggered
107	*
108	* 1 MBE (R/WC)
109	* read 1=MBE at EAP (see above)
110	* read 0=no MBE, or SBE occurred first
111	* write 1=Clear MBE status (must also
112	* clear SBE)
113	* write 0=NOP
114	*
115	* 1 SBE (R/WC)
116	* read 1=SBE at EAP (see above)
117	* read 0=no SBE, or MBE occurred first
118	* write 1=Clear SBE status (must also
119	* clear MBE)
120	* write 0=NOP
121	*/
122
123	#define R82600_DRBA 0x60 /* + 0x60..0x63 SDRAM Row Boundry Address
124	* Registers
125	*
126	* 7:0 Address lines 30:24 - upper limit of
127	* each row [p57]
128	*/
129
130	struct r82600_error_info {
131	u32 eapr;
132	};
133
2f768af7 AC	134	static unsigned int disable_hardware_scrub = 0;
2f768af7 AC	135
2f768af7 AC	136	static void r82600_get_error_info (struct mem_ctl_info *mci,
	137	struct r82600_error_info *info)
	138	{
37f04581 DT	139	struct pci_dev *pdev;
	140
	141	pdev = to_pci_dev(mci->dev);
	142	pci_read_config_dword(pdev, R82600_EAP, &info->eapr);
2f768af7 AC	143
	144	if (info->eapr & BIT(0))
	145	/* Clear error to allow next error to be reported [p.62] */
37f04581	146	pci_write_bits32(pdev, R82600_EAP,
e7ecd891 DP	147	((u32) BIT(0) & (u32) BIT(1)),
e7ecd891 DP	148	((u32) BIT(0) & (u32) BIT(1)));
2f768af7 AC	149
	150	if (info->eapr & BIT(1))
	151	/* Clear error to allow next error to be reported [p.62] */
37f04581	152	pci_write_bits32(pdev, R82600_EAP,
e7ecd891 DP	153	((u32) BIT(0) & (u32) BIT(1)),
e7ecd891 DP	154	((u32) BIT(0) & (u32) BIT(1)));
2f768af7 AC	155	}
2f768af7 AC	156
2f768af7 AC	157	static int r82600_process_error_info (struct mem_ctl_info *mci,
	158	struct r82600_error_info *info, int handle_errors)
	159	{
	160	int error_found;
	161	u32 eapaddr, page;
	162	u32 syndrome;
	163
	164	error_found = 0;
	165
	166	/* bits 30:12 store the upper 19 bits of the 32 bit error address */
	167	eapaddr = ((info->eapr >> 12) & 0x7FFF) << 13;
	168	/* Syndrome in bits 11:4 [p.62] */
	169	syndrome = (info->eapr >> 4) & 0xFF;
	170
	171	/* the R82600 reports at less than page *
	172	* granularity (upper 19 bits only) */
	173	page = eapaddr >> PAGE_SHIFT;
	174
e7ecd891	175	if (info->eapr & BIT(0)) { /* CE? */
2f768af7 AC	176	error_found = 1;
	177
	178	if (handle_errors)
e7ecd891 DP	179	edac_mc_handle_ce(mci, page, 0, /* not avail */
	180	syndrome,
	181	edac_mc_find_csrow_by_page(mci, page),
	182	0, /* channel */
	183	mci->ctl_name);
2f768af7 AC	184	}
2f768af7 AC	185
e7ecd891	186	if (info->eapr & BIT(1)) { /* UE? */
2f768af7 AC	187	error_found = 1;
	188
	189	if (handle_errors)
	190	/* 82600 doesn't give enough info */
	191	edac_mc_handle_ue(mci, page, 0,
e7ecd891 DP	192	edac_mc_find_csrow_by_page(mci, page),
e7ecd891 DP	193	mci->ctl_name);
2f768af7 AC	194	}
	195
	196	return error_found;
	197	}
	198
	199	static void r82600_check(struct mem_ctl_info *mci)
	200	{
	201	struct r82600_error_info info;
	202
537fba28	203	debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
2f768af7 AC	204	r82600_get_error_info(mci, &info);
	205	r82600_process_error_info(mci, &info, 1);
	206	}
	207
13189525	208	static inline int ecc_enabled(u8 dramcr)
2f768af7	209	{
13189525 DT	210	return dramcr & BIT(5);
	211	}
	212
	213	static void r82600_init_csrows(struct mem_ctl_info mci, struct pci_dev pdev,
	214	u8 dramcr)
	215	{
	216	struct csrow_info *csrow;
2f768af7	217	int index;
13189525 DT	218	u8 drbar; /* SDRAM Row Boundry Address Register */
	219	u32 row_high_limit, row_high_limit_last;
	220	u32 reg_sdram, ecc_on, row_base;
	221
	222	ecc_on = ecc_enabled(dramcr);
	223	reg_sdram = dramcr & BIT(4);
	224	row_high_limit_last = 0;
	225
	226	for (index = 0; index < mci->nr_csrows; index++) {
	227	csrow = &mci->csrows[index];
	228
	229	/* find the DRAM Chip Select Base address and mask */
	230	pci_read_config_byte(pdev, R82600_DRBA + index, &drbar);
	231
	232	debugf1("%s() Row=%d DRBA = %#0x\n", __func__, index, drbar);
	233
	234	row_high_limit = ((u32) drbar << 24);
	235	/* row_high_limit = ((u32)drbar << 24) \| 0xffffffUL; */
	236
	237	debugf1("%s() Row=%d, Boundry Address=%#0x, Last = %#0x\n",
	238	__func__, index, row_high_limit, row_high_limit_last);
	239
	240	/* Empty row [p.57] */
	241	if (row_high_limit == row_high_limit_last)
	242	continue;
	243
	244	row_base = row_high_limit_last;
	245
	246	csrow->first_page = row_base >> PAGE_SHIFT;
	247	csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1;
	248	csrow->nr_pages = csrow->last_page - csrow->first_page + 1;
	249	/* Error address is top 19 bits - so granularity is *
	250	* 14 bits */
	251	csrow->grain = 1 << 14;
	252	csrow->mtype = reg_sdram ? MEM_RDDR : MEM_DDR;
	253	/* FIXME - check that this is unknowable with this chipset */
	254	csrow->dtype = DEV_UNKNOWN;
	255
	256	/* Mode is global on 82600 */
	257	csrow->edac_mode = ecc_on ? EDAC_SECDED : EDAC_NONE;
	258	row_high_limit_last = row_high_limit;
	259	}
	260	}
	261
	262	static int r82600_probe1(struct pci_dev *pdev, int dev_idx)
	263	{
	264	struct mem_ctl_info *mci;
2f768af7	265	u8 dramcr;
2f768af7 AC	266	u32 eapr;
	267	u32 scrub_disabled;
	268	u32 sdram_refresh_rate;
749ede57	269	struct r82600_error_info discard;
2f768af7	270
537fba28	271	debugf0("%s()\n", __func__);
2f768af7 AC	272	pci_read_config_byte(pdev, R82600_DRAMC, &dramcr);
2f768af7 AC	273	pci_read_config_dword(pdev, R82600_EAP, &eapr);
2f768af7 AC	274	scrub_disabled = eapr & BIT(31);
2f768af7 AC	275	sdram_refresh_rate = dramcr & (BIT(0) \| BIT(1));
537fba28 DP	276	debugf2("%s(): sdram refresh rate = %#0x\n", __func__,
537fba28 DP	277	sdram_refresh_rate);
537fba28	278	debugf2("%s(): DRAMC register = %#0x\n", __func__, dramcr);
2f768af7 AC	279	mci = edac_mc_alloc(0, R82600_NR_CSROWS, R82600_NR_CHANS);
2f768af7 AC	280
13189525 DT	281	if (mci == NULL)
13189525 DT	282	return -ENOMEM;
2f768af7	283
537fba28	284	debugf0("%s(): mci = %p\n", __func__, mci);
37f04581	285	mci->dev = &pdev->dev;
2f768af7	286	mci->mtype_cap = MEM_FLAG_RDDR \| MEM_FLAG_DDR;
2f768af7	287	mci->edac_ctl_cap = EDAC_FLAG_NONE \| EDAC_FLAG_EC \| EDAC_FLAG_SECDED;
e7ecd891 DP	288	/* FIXME try to work out if the chip leads have been used for COM2
	289	* instead on this board? [MA6?] MAYBE:
	290	*/
2f768af7 AC	291
	292	/* On the R82600, the pins for memory bits 72:65 - i.e. the *
	293	* EC bits are shared with the pins for COM2 (!), so if COM2 *
	294	* is enabled, we assume COM2 is wired up, and thus no EDAC *
	295	* is possible. */
	296	mci->edac_cap = EDAC_FLAG_NONE \| EDAC_FLAG_EC \| EDAC_FLAG_SECDED;
e7ecd891	297
13189525	298	if (ecc_enabled(dramcr)) {
2f768af7	299	if (scrub_disabled)
537fba28 DP	300	debugf3("%s(): mci = %p - Scrubbing disabled! EAP: "
537fba28 DP	301	"%#0x\n", __func__, mci, eapr);
2f768af7 AC	302	} else
	303	mci->edac_cap = EDAC_FLAG_NONE;
	304
680cbbbb	305	mci->mod_name = EDAC_MOD_STR;
37f04581	306	mci->mod_ver = R82600_REVISION;
2f768af7 AC	307	mci->ctl_name = "R82600";
	308	mci->edac_check = r82600_check;
	309	mci->ctl_page_to_phys = NULL;
13189525	310	r82600_init_csrows(mci, pdev, dramcr);
749ede57	311	r82600_get_error_info(mci, &discard); /* clear counters */
2f768af7	312
2d7bbb91 DT	313	/* Here we assume that we will never see multiple instances of this
	314	* type of memory controller. The ID is therefore hardcoded to 0.
	315	*/
	316	if (edac_mc_add_mc(mci,0)) {
537fba28	317	debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
2f768af7 AC	318	goto fail;
	319	}
	320
	321	/* get this far and it's successful */
	322
2f768af7	323	if (disable_hardware_scrub) {
537fba28 DP	324	debugf3("%s(): Disabling Hardware Scrub (scrub on error)\n",
537fba28 DP	325	__func__);
37f04581	326	pci_write_bits32(pdev, R82600_EAP, BIT(31), BIT(31));
2f768af7 AC	327	}
2f768af7 AC	328
537fba28	329	debugf3("%s(): success\n", __func__);
2f768af7 AC	330	return 0;
	331
	332	fail:
13189525 DT	333	edac_mc_free(mci);
13189525 DT	334	return -ENODEV;
2f768af7 AC	335	}
	336
	337	/* returns count (>= 0), or negative on error */
	338	static int __devinit r82600_init_one(struct pci_dev *pdev,
e7ecd891	339	const struct pci_device_id *ent)
2f768af7	340	{
537fba28	341	debugf0("%s()\n", __func__);
2f768af7 AC	342
	343	/* don't need to call pci_device_enable() */
	344	return r82600_probe1(pdev, ent->driver_data);
	345	}
	346
2f768af7 AC	347	static void __devexit r82600_remove_one(struct pci_dev *pdev)
	348	{
	349	struct mem_ctl_info *mci;
	350
537fba28	351	debugf0("%s()\n", __func__);
2f768af7	352
37f04581	353	if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
18dbc337 DP	354	return;
	355
	356	edac_mc_free(mci);
2f768af7 AC	357	}
2f768af7 AC	358
2f768af7	359	static const struct pci_device_id r82600_pci_tbl[] __devinitdata = {
e7ecd891 DP	360	{
	361	PCI_DEVICE(PCI_VENDOR_ID_RADISYS, R82600_BRIDGE_ID)
	362	},
	363	{
	364	0,
	365	} /* 0 terminated list. */
2f768af7 AC	366	};
	367
	368	MODULE_DEVICE_TABLE(pci, r82600_pci_tbl);
	369
2f768af7	370	static struct pci_driver r82600_driver = {
680cbbbb	371	.name = EDAC_MOD_STR,
2f768af7 AC	372	.probe = r82600_init_one,
	373	.remove = __devexit_p(r82600_remove_one),
	374	.id_table = r82600_pci_tbl,
	375	};
	376
da9bb1d2	377	static int __init r82600_init(void)
2f768af7 AC	378	{
	379	return pci_register_driver(&r82600_driver);
	380	}
	381
2f768af7 AC	382	static void __exit r82600_exit(void)
	383	{
	384	pci_unregister_driver(&r82600_driver);
	385	}
	386
2f768af7 AC	387	module_init(r82600_init);
	388	module_exit(r82600_exit);
	389
2f768af7 AC	390	MODULE_LICENSE("GPL");
2f768af7 AC	391	MODULE_AUTHOR("Tim Small <tim@buttersideup.com> - WPAD Ltd. "
e7ecd891	392	"on behalf of EADS Astrium");
2f768af7 AC	393	MODULE_DESCRIPTION("MC support for Radisys 82600 memory controllers");
	394
	395	module_param(disable_hardware_scrub, bool, 0644);
	396	MODULE_PARM_DESC(disable_hardware_scrub,
	397	"If set, disable the chipset's automatic scrub for CEs");