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c03e017c CC |
1 | /* |
2 | * rt8973a.h | |
3 | * | |
4 | * Copyright (c) 2014 Samsung Electronics Co., Ltd | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License as published by the | |
8 | * Free Software Foundation; either version 2 of the License, or (at your | |
9 | * option) any later version. | |
10 | */ | |
11 | ||
12 | #ifndef __LINUX_EXTCON_RT8973A_H | |
13 | #define __LINUX_EXTCON_RT8973A_H | |
14 | ||
15 | enum rt8973a_types { | |
16 | TYPE_RT8973A, | |
17 | }; | |
18 | ||
19 | /* RT8973A registers */ | |
20 | enum rt8973A_reg { | |
21 | RT8973A_REG_DEVICE_ID = 0x1, | |
22 | RT8973A_REG_CONTROL1, | |
23 | RT8973A_REG_INT1, | |
24 | RT8973A_REG_INT2, | |
25 | RT8973A_REG_INTM1, | |
26 | RT8973A_REG_INTM2, | |
27 | RT8973A_REG_ADC, | |
28 | RT8973A_REG_RSVD_1, | |
29 | RT8973A_REG_RSVD_2, | |
30 | RT8973A_REG_DEV1, | |
31 | RT8973A_REG_DEV2, | |
32 | RT8973A_REG_RSVD_3, | |
33 | RT8973A_REG_RSVD_4, | |
34 | RT8973A_REG_RSVD_5, | |
35 | RT8973A_REG_RSVD_6, | |
36 | RT8973A_REG_RSVD_7, | |
37 | RT8973A_REG_RSVD_8, | |
38 | RT8973A_REG_RSVD_9, | |
39 | RT8973A_REG_MANUAL_SW1, | |
40 | RT8973A_REG_MANUAL_SW2, | |
41 | RT8973A_REG_RSVD_10, | |
42 | RT8973A_REG_RSVD_11, | |
43 | RT8973A_REG_RSVD_12, | |
44 | RT8973A_REG_RSVD_13, | |
45 | RT8973A_REG_RSVD_14, | |
46 | RT8973A_REG_RSVD_15, | |
47 | RT8973A_REG_RESET, | |
48 | ||
49 | RT8973A_REG_END, | |
50 | }; | |
51 | ||
52 | /* Define RT8973A MASK/SHIFT constant */ | |
53 | #define RT8973A_REG_DEVICE_ID_VENDOR_SHIFT 0 | |
54 | #define RT8973A_REG_DEVICE_ID_VERSION_SHIFT 3 | |
55 | #define RT8973A_REG_DEVICE_ID_VENDOR_MASK (0x7 << RT8973A_REG_DEVICE_ID_VENDOR_SHIFT) | |
56 | #define RT8973A_REG_DEVICE_ID_VERSION_MASK (0x1f << RT8973A_REG_DEVICE_ID_VERSION_SHIFT) | |
57 | ||
58 | #define RT8973A_REG_CONTROL1_INTM_SHIFT 0 | |
59 | #define RT8973A_REG_CONTROL1_AUTO_CONFIG_SHIFT 2 | |
60 | #define RT8973A_REG_CONTROL1_I2C_RST_EN_SHIFT 3 | |
61 | #define RT8973A_REG_CONTROL1_SWITCH_OPEN_SHIFT 4 | |
62 | #define RT8973A_REG_CONTROL1_CHGTYP_SHIFT 5 | |
63 | #define RT8973A_REG_CONTROL1_USB_CHD_EN_SHIFT 6 | |
64 | #define RT8973A_REG_CONTROL1_ADC_EN_SHIFT 7 | |
65 | #define RT8973A_REG_CONTROL1_INTM_MASK (0x1 << RT8973A_REG_CONTROL1_INTM_SHIFT) | |
66 | #define RT8973A_REG_CONTROL1_AUTO_CONFIG_MASK (0x1 << RT8973A_REG_CONTROL1_AUTO_CONFIG_SHIFT) | |
67 | #define RT8973A_REG_CONTROL1_I2C_RST_EN_MASK (0x1 << RT8973A_REG_CONTROL1_I2C_RST_EN_SHIFT) | |
68 | #define RT8973A_REG_CONTROL1_SWITCH_OPEN_MASK (0x1 << RT8973A_REG_CONTROL1_SWITCH_OPEN_SHIFT) | |
69 | #define RT8973A_REG_CONTROL1_CHGTYP_MASK (0x1 << RT8973A_REG_CONTROL1_CHGTYP_SHIFT) | |
70 | #define RT8973A_REG_CONTROL1_USB_CHD_EN_MASK (0x1 << RT8973A_REG_CONTROL1_USB_CHD_EN_SHIFT) | |
71 | #define RT8973A_REG_CONTROL1_ADC_EN_MASK (0x1 << RT8973A_REG_CONTROL1_ADC_EN_SHIFT) | |
72 | ||
73 | #define RT9873A_REG_INTM1_ATTACH_SHIFT 0 | |
74 | #define RT9873A_REG_INTM1_DETACH_SHIFT 1 | |
75 | #define RT9873A_REG_INTM1_CHGDET_SHIFT 2 | |
76 | #define RT9873A_REG_INTM1_DCD_T_SHIFT 3 | |
77 | #define RT9873A_REG_INTM1_OVP_SHIFT 4 | |
78 | #define RT9873A_REG_INTM1_CONNECT_SHIFT 5 | |
79 | #define RT9873A_REG_INTM1_ADC_CHG_SHIFT 6 | |
80 | #define RT9873A_REG_INTM1_OTP_SHIFT 7 | |
81 | #define RT9873A_REG_INTM1_ATTACH_MASK (0x1 << RT9873A_REG_INTM1_ATTACH_SHIFT) | |
82 | #define RT9873A_REG_INTM1_DETACH_MASK (0x1 << RT9873A_REG_INTM1_DETACH_SHIFT) | |
83 | #define RT9873A_REG_INTM1_CHGDET_MASK (0x1 << RT9873A_REG_INTM1_CHGDET_SHIFT) | |
84 | #define RT9873A_REG_INTM1_DCD_T_MASK (0x1 << RT9873A_REG_INTM1_DCD_T_SHIFT) | |
85 | #define RT9873A_REG_INTM1_OVP_MASK (0x1 << RT9873A_REG_INTM1_OVP_SHIFT) | |
86 | #define RT9873A_REG_INTM1_CONNECT_MASK (0x1 << RT9873A_REG_INTM1_CONNECT_SHIFT) | |
87 | #define RT9873A_REG_INTM1_ADC_CHG_MASK (0x1 << RT9873A_REG_INTM1_ADC_CHG_SHIFT) | |
88 | #define RT9873A_REG_INTM1_OTP_MASK (0x1 << RT9873A_REG_INTM1_OTP_SHIFT) | |
89 | ||
90 | #define RT9873A_REG_INTM2_UVLO_SHIFT 1 | |
91 | #define RT9873A_REG_INTM2_POR_SHIFT 2 | |
92 | #define RT9873A_REG_INTM2_OTP_FET_SHIFT 3 | |
93 | #define RT9873A_REG_INTM2_OVP_FET_SHIFT 4 | |
94 | #define RT9873A_REG_INTM2_OCP_LATCH_SHIFT 5 | |
95 | #define RT9873A_REG_INTM2_OCP_SHIFT 6 | |
96 | #define RT9873A_REG_INTM2_OVP_OCP_SHIFT 7 | |
97 | #define RT9873A_REG_INTM2_UVLO_MASK (0x1 << RT9873A_REG_INTM2_UVLO_SHIFT) | |
98 | #define RT9873A_REG_INTM2_POR_MASK (0x1 << RT9873A_REG_INTM2_POR_SHIFT) | |
99 | #define RT9873A_REG_INTM2_OTP_FET_MASK (0x1 << RT9873A_REG_INTM2_OTP_FET_SHIFT) | |
100 | #define RT9873A_REG_INTM2_OVP_FET_MASK (0x1 << RT9873A_REG_INTM2_OVP_FET_SHIFT) | |
101 | #define RT9873A_REG_INTM2_OCP_LATCH_MASK (0x1 << RT9873A_REG_INTM2_OCP_LATCH_SHIFT) | |
102 | #define RT9873A_REG_INTM2_OCP_MASK (0x1 << RT9873A_REG_INTM2_OCP_SHIFT) | |
103 | #define RT9873A_REG_INTM2_OVP_OCP_MASK (0x1 << RT9873A_REG_INTM2_OVP_OCP_SHIFT) | |
104 | ||
105 | #define RT8973A_REG_ADC_SHIFT 0 | |
106 | #define RT8973A_REG_ADC_MASK (0x1f << RT8973A_REG_ADC_SHIFT) | |
107 | ||
108 | #define RT8973A_REG_DEV1_OTG_SHIFT 0 | |
109 | #define RT8973A_REG_DEV1_SDP_SHIFT 2 | |
110 | #define RT8973A_REG_DEV1_UART_SHIFT 3 | |
111 | #define RT8973A_REG_DEV1_CAR_KIT_TYPE1_SHIFT 4 | |
112 | #define RT8973A_REG_DEV1_CDPORT_SHIFT 5 | |
113 | #define RT8973A_REG_DEV1_DCPORT_SHIFT 6 | |
114 | #define RT8973A_REG_DEV1_OTG_MASK (0x1 << RT8973A_REG_DEV1_OTG_SHIFT) | |
115 | #define RT8973A_REG_DEV1_SDP_MASK (0x1 << RT8973A_REG_DEV1_SDP_SHIFT) | |
116 | #define RT8973A_REG_DEV1_UART_MASK (0x1 << RT8973A_REG_DEV1_UART_SHIFT) | |
117 | #define RT8973A_REG_DEV1_CAR_KIT_TYPE1_MASK (0x1 << RT8973A_REG_DEV1_CAR_KIT_TYPE1_SHIFT) | |
118 | #define RT8973A_REG_DEV1_CDPORT_MASK (0x1 << RT8973A_REG_DEV1_CDPORT_SHIFT) | |
119 | #define RT8973A_REG_DEV1_DCPORT_MASK (0x1 << RT8973A_REG_DEV1_DCPORT_SHIFT) | |
120 | #define RT8973A_REG_DEV1_USB_MASK (RT8973A_REG_DEV1_SDP_MASK \ | |
121 | | RT8973A_REG_DEV1_CDPORT_MASK) | |
122 | ||
123 | #define RT8973A_REG_DEV2_JIG_USB_ON_SHIFT 0 | |
124 | #define RT8973A_REG_DEV2_JIG_USB_OFF_SHIFT 1 | |
125 | #define RT8973A_REG_DEV2_JIG_UART_ON_SHIFT 2 | |
126 | #define RT8973A_REG_DEV2_JIG_UART_OFF_SHIFT 3 | |
127 | #define RT8973A_REG_DEV2_JIG_USB_ON_MASK (0x1 << RT8973A_REG_DEV2_JIG_USB_ON_SHIFT) | |
128 | #define RT8973A_REG_DEV2_JIG_USB_OFF_MASK (0x1 << RT8973A_REG_DEV2_JIG_USB_OFF_SHIFT) | |
129 | #define RT8973A_REG_DEV2_JIG_UART_ON_MASK (0x1 << RT8973A_REG_DEV2_JIG_UART_ON_SHIFT) | |
130 | #define RT8973A_REG_DEV2_JIG_UART_OFF_MASK (0x1 << RT8973A_REG_DEV2_JIG_UART_OFF_SHIFT) | |
131 | ||
132 | #define RT8973A_REG_MANUAL_SW1_DP_SHIFT 2 | |
133 | #define RT8973A_REG_MANUAL_SW1_DM_SHIFT 5 | |
134 | #define RT8973A_REG_MANUAL_SW1_DP_MASK (0x7 << RT8973A_REG_MANUAL_SW1_DP_SHIFT) | |
135 | #define RT8973A_REG_MANUAL_SW1_DM_MASK (0x7 << RT8973A_REG_MANUAL_SW1_DM_SHIFT) | |
136 | #define DM_DP_CON_SWITCH_OPEN 0x0 | |
137 | #define DM_DP_CON_SWITCH_USB 0x1 | |
138 | #define DM_DP_CON_SWITCH_UART 0x3 | |
139 | #define DM_DP_SWITCH_OPEN ((DM_DP_CON_SWITCH_OPEN << RT8973A_REG_MANUAL_SW1_DP_SHIFT) \ | |
140 | | (DM_DP_CON_SWITCH_OPEN << RT8973A_REG_MANUAL_SW1_DM_SHIFT)) | |
141 | #define DM_DP_SWITCH_USB ((DM_DP_CON_SWITCH_USB << RT8973A_REG_MANUAL_SW1_DP_SHIFT) \ | |
142 | | (DM_DP_CON_SWITCH_USB << RT8973A_REG_MANUAL_SW1_DM_SHIFT)) | |
143 | #define DM_DP_SWITCH_UART ((DM_DP_CON_SWITCH_UART << RT8973A_REG_MANUAL_SW1_DP_SHIFT) \ | |
144 | | (DM_DP_CON_SWITCH_UART << RT8973A_REG_MANUAL_SW1_DM_SHIFT)) | |
145 | ||
146 | #define RT8973A_REG_MANUAL_SW2_FET_ON_SHIFT 0 | |
147 | #define RT8973A_REG_MANUAL_SW2_JIG_ON_SHIFT 2 | |
148 | #define RT8973A_REG_MANUAL_SW2_BOOT_SW_SHIFT 3 | |
149 | #define RT8973A_REG_MANUAL_SW2_FET_ON_MASK (0x1 << RT8973A_REG_MANUAL_SW2_FET_ON_SHIFT) | |
150 | #define RT8973A_REG_MANUAL_SW2_JIG_ON_MASK (0x1 << RT8973A_REG_MANUAL_SW2_JIG_ON_SHIFT) | |
151 | #define RT8973A_REG_MANUAL_SW2_BOOT_SW_MASK (0x1 << RT8973A_REG_MANUAL_SW2_BOOT_SW_SHIFT) | |
152 | #define RT8973A_REG_MANUAL_SW2_FET_ON 0 | |
153 | #define RT8973A_REG_MANUAL_SW2_FET_OFF 0x1 | |
154 | #define RT8973A_REG_MANUAL_SW2_JIG_OFF 0 | |
155 | #define RT8973A_REG_MANUAL_SW2_JIG_ON 0x1 | |
156 | #define RT8973A_REG_MANUAL_SW2_BOOT_SW_ON 0 | |
157 | #define RT8973A_REG_MANUAL_SW2_BOOT_SW_OFF 0x1 | |
158 | ||
159 | #define RT8973A_REG_RESET_SHIFT 0 | |
160 | #define RT8973A_REG_RESET_MASK (0x1 << RT8973A_REG_RESET_SHIFT) | |
161 | #define RT8973A_REG_RESET 0x1 | |
162 | ||
163 | /* RT8973A Interrupts */ | |
164 | enum rt8973a_irq { | |
165 | /* Interrupt1*/ | |
166 | RT8973A_INT1_ATTACH, | |
167 | RT8973A_INT1_DETACH, | |
168 | RT8973A_INT1_CHGDET, | |
169 | RT8973A_INT1_DCD_T, | |
170 | RT8973A_INT1_OVP, | |
171 | RT8973A_INT1_CONNECT, | |
172 | RT8973A_INT1_ADC_CHG, | |
173 | RT8973A_INT1_OTP, | |
174 | ||
175 | /* Interrupt2*/ | |
176 | RT8973A_INT2_UVLO, | |
177 | RT8973A_INT2_POR, | |
178 | RT8973A_INT2_OTP_FET, | |
179 | RT8973A_INT2_OVP_FET, | |
180 | RT8973A_INT2_OCP_LATCH, | |
181 | RT8973A_INT2_OCP, | |
182 | RT8973A_INT2_OVP_OCP, | |
183 | ||
184 | RT8973A_NUM, | |
185 | }; | |
186 | ||
187 | #define RT8973A_INT1_ATTACH_MASK BIT(0) | |
188 | #define RT8973A_INT1_DETACH_MASK BIT(1) | |
189 | #define RT8973A_INT1_CHGDET_MASK BIT(2) | |
190 | #define RT8973A_INT1_DCD_T_MASK BIT(3) | |
191 | #define RT8973A_INT1_OVP_MASK BIT(4) | |
192 | #define RT8973A_INT1_CONNECT_MASK BIT(5) | |
193 | #define RT8973A_INT1_ADC_CHG_MASK BIT(6) | |
194 | #define RT8973A_INT1_OTP_MASK BIT(7) | |
195 | #define RT8973A_INT2_UVLOT_MASK BIT(0) | |
196 | #define RT8973A_INT2_POR_MASK BIT(1) | |
197 | #define RT8973A_INT2_OTP_FET_MASK BIT(2) | |
198 | #define RT8973A_INT2_OVP_FET_MASK BIT(3) | |
199 | #define RT8973A_INT2_OCP_LATCH_MASK BIT(4) | |
200 | #define RT8973A_INT2_OCP_MASK BIT(5) | |
201 | #define RT8973A_INT2_OVP_OCP_MASK BIT(6) | |
202 | ||
203 | #endif /* __LINUX_EXTCON_RT8973A_H */ |