Commit | Line | Data |
---|---|---|
c781c06d KH |
1 | /* |
2 | * Copyright (C) 2005-2007 Kristian Hoegsberg <krh@bitplanet.net> | |
3038e353 KH |
3 | * |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software Foundation, | |
16 | * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
17 | */ | |
18 | ||
e8ca9702 | 19 | #include <linux/bug.h> |
459f7923 SR |
20 | #include <linux/completion.h> |
21 | #include <linux/crc-itu-t.h> | |
3038e353 | 22 | #include <linux/device.h> |
459f7923 | 23 | #include <linux/errno.h> |
77c9a5da SR |
24 | #include <linux/firewire.h> |
25 | #include <linux/firewire-constants.h> | |
e8ca9702 SR |
26 | #include <linux/jiffies.h> |
27 | #include <linux/kernel.h> | |
459f7923 | 28 | #include <linux/kref.h> |
e8ca9702 | 29 | #include <linux/list.h> |
459f7923 | 30 | #include <linux/module.h> |
6a5033be | 31 | #include <linux/mutex.h> |
e8ca9702 | 32 | #include <linux/spinlock.h> |
e8ca9702 SR |
33 | #include <linux/workqueue.h> |
34 | ||
60063497 | 35 | #include <linux/atomic.h> |
e8ca9702 | 36 | #include <asm/byteorder.h> |
459f7923 | 37 | |
77c9a5da | 38 | #include "core.h" |
3038e353 | 39 | |
cb7c96da | 40 | int fw_compute_block_crc(__be32 *block) |
8e85973e SR |
41 | { |
42 | int length; | |
43 | u16 crc; | |
44 | ||
45 | length = (be32_to_cpu(block[0]) >> 16) & 0xff; | |
46 | crc = crc_itu_t(0, (u8 *)&block[1], length * 4); | |
47 | *block |= cpu_to_be32(crc); | |
48 | ||
49 | return length; | |
50 | } | |
51 | ||
6a5033be | 52 | static DEFINE_MUTEX(card_mutex); |
3038e353 KH |
53 | static LIST_HEAD(card_list); |
54 | ||
55 | static LIST_HEAD(descriptor_list); | |
56 | static int descriptor_count; | |
57 | ||
fe242579 | 58 | static __be32 tmp_config_rom[256]; |
e300839d SR |
59 | /* ROM header, bus info block, root dir header, capabilities = 7 quadlets */ |
60 | static size_t config_rom_length = 1 + 4 + 1 + 1; | |
fe242579 | 61 | |
a77754a7 KH |
62 | #define BIB_CRC(v) ((v) << 0) |
63 | #define BIB_CRC_LENGTH(v) ((v) << 16) | |
64 | #define BIB_INFO_LENGTH(v) ((v) << 24) | |
edd5bdaf | 65 | #define BIB_BUS_NAME 0x31333934 /* "1394" */ |
a77754a7 KH |
66 | #define BIB_LINK_SPEED(v) ((v) << 0) |
67 | #define BIB_GENERATION(v) ((v) << 4) | |
68 | #define BIB_MAX_ROM(v) ((v) << 8) | |
69 | #define BIB_MAX_RECEIVE(v) ((v) << 12) | |
70 | #define BIB_CYC_CLK_ACC(v) ((v) << 16) | |
71 | #define BIB_PMC ((1) << 27) | |
72 | #define BIB_BMC ((1) << 28) | |
73 | #define BIB_ISC ((1) << 29) | |
74 | #define BIB_CMC ((1) << 30) | |
edd5bdaf SR |
75 | #define BIB_IRMC ((1) << 31) |
76 | #define NODE_CAPABILITIES 0x0c0083c0 /* per IEEE 1394 clause 8.3.2.6.5.2 */ | |
3038e353 | 77 | |
dd5eeb99 CL |
78 | /* |
79 | * IEEE-1394 specifies a default SPLIT_TIMEOUT value of 800 cycles (100 ms), | |
80 | * but we have to make it longer because there are many devices whose firmware | |
81 | * is just too slow for that. | |
82 | */ | |
83 | #define DEFAULT_SPLIT_TIMEOUT (2 * 8000) | |
84 | ||
6044565a SR |
85 | #define CANON_OUI 0x000085 |
86 | ||
e300839d | 87 | static void generate_config_rom(struct fw_card *card, __be32 *config_rom) |
3038e353 KH |
88 | { |
89 | struct fw_descriptor *desc; | |
8e85973e | 90 | int i, j, k, length; |
3038e353 | 91 | |
c781c06d KH |
92 | /* |
93 | * Initialize contents of config rom buffer. On the OHCI | |
5e20c282 SR |
94 | * controller, block reads to the config rom accesses the host |
95 | * memory, but quadlet read access the hardware bus info block | |
96 | * registers. That's just crack, but it means we should make | |
2cc489c2 | 97 | * sure the contents of bus info block in host memory matches |
c781c06d KH |
98 | * the version stored in the OHCI registers. |
99 | */ | |
3038e353 | 100 | |
8e85973e SR |
101 | config_rom[0] = cpu_to_be32( |
102 | BIB_CRC_LENGTH(4) | BIB_INFO_LENGTH(4) | BIB_CRC(0)); | |
edd5bdaf | 103 | config_rom[1] = cpu_to_be32(BIB_BUS_NAME); |
8e85973e | 104 | config_rom[2] = cpu_to_be32( |
a77754a7 KH |
105 | BIB_LINK_SPEED(card->link_speed) | |
106 | BIB_GENERATION(card->config_rom_generation++ % 14 + 2) | | |
107 | BIB_MAX_ROM(2) | | |
108 | BIB_MAX_RECEIVE(card->max_receive) | | |
edd5bdaf | 109 | BIB_BMC | BIB_ISC | BIB_CMC | BIB_IRMC); |
8e85973e SR |
110 | config_rom[3] = cpu_to_be32(card->guid >> 32); |
111 | config_rom[4] = cpu_to_be32(card->guid); | |
3038e353 KH |
112 | |
113 | /* Generate root directory. */ | |
edd5bdaf | 114 | config_rom[6] = cpu_to_be32(NODE_CAPABILITIES); |
8e85973e SR |
115 | i = 7; |
116 | j = 7 + descriptor_count; | |
3038e353 KH |
117 | |
118 | /* Generate root directory entries for descriptors. */ | |
119 | list_for_each_entry (desc, &descriptor_list, link) { | |
937f6879 | 120 | if (desc->immediate > 0) |
8e85973e SR |
121 | config_rom[i++] = cpu_to_be32(desc->immediate); |
122 | config_rom[i] = cpu_to_be32(desc->key | (j - i)); | |
3038e353 KH |
123 | i++; |
124 | j += desc->length; | |
125 | } | |
126 | ||
127 | /* Update root directory length. */ | |
8e85973e | 128 | config_rom[5] = cpu_to_be32((i - 5 - 1) << 16); |
3038e353 KH |
129 | |
130 | /* End of root directory, now copy in descriptors. */ | |
131 | list_for_each_entry (desc, &descriptor_list, link) { | |
8e85973e SR |
132 | for (k = 0; k < desc->length; k++) |
133 | config_rom[i + k] = cpu_to_be32(desc->data[k]); | |
3038e353 KH |
134 | i += desc->length; |
135 | } | |
136 | ||
137 | /* Calculate CRCs for all blocks in the config rom. This | |
138 | * assumes that CRC length and info length are identical for | |
139 | * the bus info block, which is always the case for this | |
140 | * implementation. */ | |
e175569c | 141 | for (i = 0; i < j; i += length + 1) |
cb7c96da | 142 | length = fw_compute_block_crc(config_rom + i); |
3038e353 | 143 | |
e300839d | 144 | WARN_ON(j != config_rom_length); |
3038e353 KH |
145 | } |
146 | ||
53dca511 | 147 | static void update_config_roms(void) |
3038e353 KH |
148 | { |
149 | struct fw_card *card; | |
3038e353 KH |
150 | |
151 | list_for_each_entry (card, &card_list, link) { | |
e300839d SR |
152 | generate_config_rom(card, tmp_config_rom); |
153 | card->driver->set_config_rom(card, tmp_config_rom, | |
154 | config_rom_length); | |
3038e353 KH |
155 | } |
156 | } | |
157 | ||
e300839d SR |
158 | static size_t required_space(struct fw_descriptor *desc) |
159 | { | |
160 | /* descriptor + entry into root dir + optional immediate entry */ | |
161 | return desc->length + 1 + (desc->immediate > 0 ? 1 : 0); | |
162 | } | |
163 | ||
53dca511 | 164 | int fw_core_add_descriptor(struct fw_descriptor *desc) |
3038e353 KH |
165 | { |
166 | size_t i; | |
e300839d | 167 | int ret; |
3038e353 | 168 | |
c781c06d KH |
169 | /* |
170 | * Check descriptor is valid; the length of all blocks in the | |
3038e353 | 171 | * descriptor has to add up to exactly the length of the |
c781c06d KH |
172 | * block. |
173 | */ | |
3038e353 KH |
174 | i = 0; |
175 | while (i < desc->length) | |
176 | i += (desc->data[i] >> 16) + 1; | |
177 | ||
178 | if (i != desc->length) | |
66dea3e5 | 179 | return -EINVAL; |
3038e353 | 180 | |
6a5033be | 181 | mutex_lock(&card_mutex); |
3038e353 | 182 | |
e300839d SR |
183 | if (config_rom_length + required_space(desc) > 256) { |
184 | ret = -EBUSY; | |
185 | } else { | |
186 | list_add_tail(&desc->link, &descriptor_list); | |
187 | config_rom_length += required_space(desc); | |
937f6879 | 188 | descriptor_count++; |
e300839d SR |
189 | if (desc->immediate > 0) |
190 | descriptor_count++; | |
191 | update_config_roms(); | |
192 | ret = 0; | |
193 | } | |
3038e353 | 194 | |
6a5033be | 195 | mutex_unlock(&card_mutex); |
3038e353 | 196 | |
e300839d | 197 | return ret; |
3038e353 | 198 | } |
c76acec6 | 199 | EXPORT_SYMBOL(fw_core_add_descriptor); |
3038e353 | 200 | |
53dca511 | 201 | void fw_core_remove_descriptor(struct fw_descriptor *desc) |
3038e353 | 202 | { |
6a5033be | 203 | mutex_lock(&card_mutex); |
3038e353 KH |
204 | |
205 | list_del(&desc->link); | |
e300839d | 206 | config_rom_length -= required_space(desc); |
3038e353 | 207 | descriptor_count--; |
937f6879 KH |
208 | if (desc->immediate > 0) |
209 | descriptor_count--; | |
3038e353 KH |
210 | update_config_roms(); |
211 | ||
6a5033be | 212 | mutex_unlock(&card_mutex); |
3038e353 | 213 | } |
c76acec6 | 214 | EXPORT_SYMBOL(fw_core_remove_descriptor); |
3038e353 | 215 | |
02d37bed SR |
216 | static int reset_bus(struct fw_card *card, bool short_reset) |
217 | { | |
218 | int reg = short_reset ? 5 : 1; | |
219 | int bit = short_reset ? PHY_BUS_SHORT_RESET : PHY_BUS_RESET; | |
220 | ||
221 | return card->driver->update_phy_reg(card, reg, 0, bit); | |
222 | } | |
223 | ||
224 | void fw_schedule_bus_reset(struct fw_card *card, bool delayed, bool short_reset) | |
225 | { | |
226 | /* We don't try hard to sort out requests of long vs. short resets. */ | |
227 | card->br_short = short_reset; | |
228 | ||
229 | /* Use an arbitrary short delay to combine multiple reset requests. */ | |
230 | fw_card_get(card); | |
105e53f8 | 231 | if (!queue_delayed_work(fw_workqueue, &card->br_work, |
6ea9e7bb | 232 | delayed ? DIV_ROUND_UP(HZ, 100) : 0)) |
02d37bed SR |
233 | fw_card_put(card); |
234 | } | |
235 | EXPORT_SYMBOL(fw_schedule_bus_reset); | |
236 | ||
237 | static void br_work(struct work_struct *work) | |
238 | { | |
239 | struct fw_card *card = container_of(work, struct fw_card, br_work.work); | |
240 | ||
241 | /* Delay for 2s after last reset per IEEE 1394 clause 8.2.1. */ | |
242 | if (card->reset_jiffies != 0 && | |
e71084af | 243 | time_before64(get_jiffies_64(), card->reset_jiffies + 2 * HZ)) { |
105e53f8 | 244 | if (!queue_delayed_work(fw_workqueue, &card->br_work, 2 * HZ)) |
02d37bed SR |
245 | fw_card_put(card); |
246 | return; | |
247 | } | |
248 | ||
249 | fw_send_phy_config(card, FW_PHY_CONFIG_NO_NODE_ID, card->generation, | |
250 | FW_PHY_CONFIG_CURRENT_GAP_COUNT); | |
251 | reset_bus(card, card->br_short); | |
252 | fw_card_put(card); | |
253 | } | |
254 | ||
cbae787c | 255 | static void allocate_broadcast_channel(struct fw_card *card, int generation) |
6104ee92 | 256 | { |
cbae787c SR |
257 | int channel, bandwidth = 0; |
258 | ||
e91b2787 CL |
259 | if (!card->broadcast_channel_allocated) { |
260 | fw_iso_resource_manage(card, generation, 1ULL << 31, | |
f30e6d3e | 261 | &channel, &bandwidth, true); |
e91b2787 CL |
262 | if (channel != 31) { |
263 | fw_notify("failed to allocate broadcast channel\n"); | |
264 | return; | |
265 | } | |
7889b60e | 266 | card->broadcast_channel_allocated = true; |
6104ee92 | 267 | } |
e91b2787 CL |
268 | |
269 | device_for_each_child(card->device, (void *)(long)generation, | |
270 | fw_device_set_broadcast_channel); | |
6104ee92 | 271 | } |
6104ee92 | 272 | |
83db801c KH |
273 | static const char gap_count_table[] = { |
274 | 63, 5, 7, 8, 10, 13, 16, 18, 21, 24, 26, 29, 32, 35, 37, 40 | |
275 | }; | |
276 | ||
53dca511 | 277 | void fw_schedule_bm_work(struct fw_card *card, unsigned long delay) |
0fa1986f | 278 | { |
0fa1986f | 279 | fw_card_get(card); |
02d37bed | 280 | if (!schedule_delayed_work(&card->bm_work, delay)) |
0fa1986f JF |
281 | fw_card_put(card); |
282 | } | |
283 | ||
02d37bed | 284 | static void bm_work(struct work_struct *work) |
19a15b93 | 285 | { |
02d37bed | 286 | struct fw_card *card = container_of(work, struct fw_card, bm_work.work); |
10389536 | 287 | struct fw_device *root_device, *irm_device; |
cbae787c | 288 | struct fw_node *root_node; |
250b2b6d | 289 | int root_id, new_root_id, irm_id, bm_id, local_id; |
cbae787c | 290 | int gap_count, generation, grace, rcode; |
25b1c3d8 | 291 | bool do_reset = false; |
62305823 SR |
292 | bool root_device_is_running; |
293 | bool root_device_is_cmc; | |
10389536 | 294 | bool irm_is_1394_1995_only; |
6044565a | 295 | bool keep_this_irm; |
f30e6d3e | 296 | __be32 transaction_data[2]; |
19a15b93 | 297 | |
ae948011 | 298 | spin_lock_irq(&card->lock); |
15803478 | 299 | |
cbae787c | 300 | if (card->local_node == NULL) { |
ae948011 | 301 | spin_unlock_irq(&card->lock); |
0fa1986f | 302 | goto out_put_card; |
15803478 | 303 | } |
19a15b93 KH |
304 | |
305 | generation = card->generation; | |
10389536 | 306 | |
cbae787c SR |
307 | root_node = card->root_node; |
308 | fw_node_get(root_node); | |
15803478 | 309 | root_device = root_node->data; |
62305823 SR |
310 | root_device_is_running = root_device && |
311 | atomic_read(&root_device->state) == FW_DEVICE_RUNNING; | |
312 | root_device_is_cmc = root_device && root_device->cmc; | |
10389536 SR |
313 | |
314 | irm_device = card->irm_node->data; | |
315 | irm_is_1394_1995_only = irm_device && irm_device->config_rom && | |
316 | (irm_device->config_rom[2] & 0x000000f0) == 0; | |
317 | ||
6044565a SR |
318 | /* Canon MV5i works unreliably if it is not root node. */ |
319 | keep_this_irm = irm_device && irm_device->config_rom && | |
320 | irm_device->config_rom[3] >> 8 == CANON_OUI; | |
321 | ||
cbae787c SR |
322 | root_id = root_node->node_id; |
323 | irm_id = card->irm_node->node_id; | |
324 | local_id = card->local_node->node_id; | |
e1dc7cab | 325 | |
e71084af CL |
326 | grace = time_after64(get_jiffies_64(), |
327 | card->reset_jiffies + DIV_ROUND_UP(HZ, 8)); | |
e1dc7cab | 328 | |
7e0e314f CL |
329 | if ((is_next_generation(generation, card->bm_generation) && |
330 | !card->bm_abdicate) || | |
931c4834 | 331 | (card->bm_generation != generation && grace)) { |
c781c06d KH |
332 | /* |
333 | * This first step is to figure out who is IRM and | |
931c4834 KH |
334 | * then try to become bus manager. If the IRM is not |
335 | * well defined (e.g. does not have an active link | |
336 | * layer or does not responds to our lock request, we | |
337 | * will have to do a little vigilante bus management. | |
338 | * In that case, we do a goto into the gap count logic | |
339 | * so that when we do the reset, we still optimize the | |
340 | * gap count. That could well save a reset in the | |
c781c06d KH |
341 | * next generation. |
342 | */ | |
931c4834 | 343 | |
cbae787c SR |
344 | if (!card->irm_node->link_on) { |
345 | new_root_id = local_id; | |
10389536 SR |
346 | fw_notify("%s, making local node (%02x) root.\n", |
347 | "IRM has link off", new_root_id); | |
348 | goto pick_me; | |
349 | } | |
350 | ||
6044565a | 351 | if (irm_is_1394_1995_only && !keep_this_irm) { |
10389536 SR |
352 | new_root_id = local_id; |
353 | fw_notify("%s, making local node (%02x) root.\n", | |
354 | "IRM is not 1394a compliant", new_root_id); | |
931c4834 KH |
355 | goto pick_me; |
356 | } | |
357 | ||
f30e6d3e SR |
358 | transaction_data[0] = cpu_to_be32(0x3f); |
359 | transaction_data[1] = cpu_to_be32(local_id); | |
931c4834 | 360 | |
ae948011 | 361 | spin_unlock_irq(&card->lock); |
931c4834 | 362 | |
1e119fa9 JF |
363 | rcode = fw_run_transaction(card, TCODE_LOCK_COMPARE_SWAP, |
364 | irm_id, generation, SCODE_100, | |
365 | CSR_REGISTER_BASE + CSR_BUS_MANAGER_ID, | |
f30e6d3e | 366 | transaction_data, 8); |
931c4834 | 367 | |
1e119fa9 JF |
368 | if (rcode == RCODE_GENERATION) |
369 | /* Another bus reset, BM work has been rescheduled. */ | |
15803478 | 370 | goto out; |
931c4834 | 371 | |
f30e6d3e | 372 | bm_id = be32_to_cpu(transaction_data[0]); |
cbae787c | 373 | |
250b2b6d SR |
374 | spin_lock_irq(&card->lock); |
375 | if (rcode == RCODE_COMPLETE && generation == card->generation) | |
376 | card->bm_node_id = | |
377 | bm_id == 0x3f ? local_id : 0xffc0 | bm_id; | |
378 | spin_unlock_irq(&card->lock); | |
cbae787c | 379 | |
250b2b6d | 380 | if (rcode == RCODE_COMPLETE && bm_id != 0x3f) { |
cbae787c SR |
381 | /* Somebody else is BM. Only act as IRM. */ |
382 | if (local_id == irm_id) | |
383 | allocate_broadcast_channel(card, generation); | |
384 | ||
15803478 | 385 | goto out; |
6104ee92 | 386 | } |
931c4834 | 387 | |
bda3b8a1 CL |
388 | if (rcode == RCODE_SEND_ERROR) { |
389 | /* | |
390 | * We have been unable to send the lock request due to | |
391 | * some local problem. Let's try again later and hope | |
392 | * that the problem has gone away by then. | |
393 | */ | |
394 | fw_schedule_bm_work(card, DIV_ROUND_UP(HZ, 8)); | |
395 | goto out; | |
396 | } | |
397 | ||
ae948011 | 398 | spin_lock_irq(&card->lock); |
1e119fa9 | 399 | |
6044565a | 400 | if (rcode != RCODE_COMPLETE && !keep_this_irm) { |
c781c06d KH |
401 | /* |
402 | * The lock request failed, maybe the IRM | |
931c4834 KH |
403 | * isn't really IRM capable after all. Let's |
404 | * do a bus reset and pick the local node as | |
c781c06d KH |
405 | * root, and thus, IRM. |
406 | */ | |
cbae787c | 407 | new_root_id = local_id; |
10389536 SR |
408 | fw_notify("%s, making local node (%02x) root.\n", |
409 | "BM lock failed", new_root_id); | |
931c4834 KH |
410 | goto pick_me; |
411 | } | |
412 | } else if (card->bm_generation != generation) { | |
c781c06d | 413 | /* |
e1dc7cab SR |
414 | * We weren't BM in the last generation, and the last |
415 | * bus reset is less than 125ms ago. Reschedule this job. | |
c781c06d | 416 | */ |
ae948011 | 417 | spin_unlock_irq(&card->lock); |
e1dc7cab | 418 | fw_schedule_bm_work(card, DIV_ROUND_UP(HZ, 8)); |
15803478 | 419 | goto out; |
931c4834 KH |
420 | } |
421 | ||
c781c06d KH |
422 | /* |
423 | * We're bus manager for this generation, so next step is to | |
931c4834 | 424 | * make sure we have an active cycle master and do gap count |
c781c06d KH |
425 | * optimization. |
426 | */ | |
931c4834 | 427 | card->bm_generation = generation; |
19a15b93 | 428 | |
15803478 | 429 | if (root_device == NULL) { |
c781c06d KH |
430 | /* |
431 | * Either link_on is false, or we failed to read the | |
432 | * config rom. In either case, pick another root. | |
433 | */ | |
cbae787c | 434 | new_root_id = local_id; |
62305823 | 435 | } else if (!root_device_is_running) { |
c781c06d KH |
436 | /* |
437 | * If we haven't probed this device yet, bail out now | |
438 | * and let's try again once that's done. | |
439 | */ | |
ae948011 | 440 | spin_unlock_irq(&card->lock); |
15803478 | 441 | goto out; |
62305823 | 442 | } else if (root_device_is_cmc) { |
c781c06d | 443 | /* |
c374ab42 CL |
444 | * We will send out a force root packet for this |
445 | * node as part of the gap count optimization. | |
c781c06d | 446 | */ |
931c4834 | 447 | new_root_id = root_id; |
83db801c | 448 | } else { |
c781c06d KH |
449 | /* |
450 | * Current root has an active link layer and we | |
19a15b93 | 451 | * successfully read the config rom, but it's not |
c781c06d KH |
452 | * cycle master capable. |
453 | */ | |
cbae787c | 454 | new_root_id = local_id; |
83db801c KH |
455 | } |
456 | ||
931c4834 | 457 | pick_me: |
24d40125 SR |
458 | /* |
459 | * Pick a gap count from 1394a table E-1. The table doesn't cover | |
460 | * the typically much larger 1394b beta repeater delays though. | |
461 | */ | |
462 | if (!card->beta_repeaters_present && | |
15803478 SR |
463 | root_node->max_hops < ARRAY_SIZE(gap_count_table)) |
464 | gap_count = gap_count_table[root_node->max_hops]; | |
83db801c KH |
465 | else |
466 | gap_count = 63; | |
467 | ||
c781c06d | 468 | /* |
25b1c3d8 SR |
469 | * Finally, figure out if we should do a reset or not. If we have |
470 | * done less than 5 resets with the same physical topology and we | |
c781c06d KH |
471 | * have either a new root or a new gap count setting, let's do it. |
472 | */ | |
19a15b93 | 473 | |
931c4834 KH |
474 | if (card->bm_retries++ < 5 && |
475 | (card->gap_count != gap_count || new_root_id != root_id)) | |
25b1c3d8 | 476 | do_reset = true; |
19a15b93 | 477 | |
ae948011 | 478 | spin_unlock_irq(&card->lock); |
19a15b93 | 479 | |
83db801c KH |
480 | if (do_reset) { |
481 | fw_notify("phy config: card %d, new root=%x, gap_count=%d\n", | |
931c4834 KH |
482 | card->index, new_root_id, gap_count); |
483 | fw_send_phy_config(card, new_root_id, generation, gap_count); | |
02d37bed | 484 | reset_bus(card, true); |
cbae787c | 485 | /* Will allocate broadcast channel after the reset. */ |
c374ab42 | 486 | goto out; |
19a15b93 | 487 | } |
6104ee92 | 488 | |
c374ab42 CL |
489 | if (root_device_is_cmc) { |
490 | /* | |
491 | * Make sure that the cycle master sends cycle start packets. | |
492 | */ | |
f30e6d3e | 493 | transaction_data[0] = cpu_to_be32(CSR_STATE_BIT_CMSTR); |
c374ab42 CL |
494 | rcode = fw_run_transaction(card, TCODE_WRITE_QUADLET_REQUEST, |
495 | root_id, generation, SCODE_100, | |
496 | CSR_REGISTER_BASE + CSR_STATE_SET, | |
f30e6d3e | 497 | transaction_data, 4); |
c374ab42 CL |
498 | if (rcode == RCODE_GENERATION) |
499 | goto out; | |
19a15b93 | 500 | } |
6104ee92 | 501 | |
c374ab42 CL |
502 | if (local_id == irm_id) |
503 | allocate_broadcast_channel(card, generation); | |
504 | ||
15803478 | 505 | out: |
15803478 | 506 | fw_node_put(root_node); |
0fa1986f JF |
507 | out_put_card: |
508 | fw_card_put(card); | |
19a15b93 KH |
509 | } |
510 | ||
53dca511 SR |
511 | void fw_card_initialize(struct fw_card *card, |
512 | const struct fw_card_driver *driver, | |
513 | struct device *device) | |
3038e353 | 514 | { |
bbf19db3 | 515 | static atomic_t index = ATOMIC_INIT(-1); |
3038e353 | 516 | |
bbf19db3 | 517 | card->index = atomic_inc_return(&index); |
5e20c282 | 518 | card->driver = driver; |
3038e353 | 519 | card->device = device; |
5e20c282 SR |
520 | card->current_tlabel = 0; |
521 | card->tlabel_mask = 0; | |
dd5eeb99 CL |
522 | card->split_timeout_hi = DEFAULT_SPLIT_TIMEOUT / 8000; |
523 | card->split_timeout_lo = (DEFAULT_SPLIT_TIMEOUT % 8000) << 19; | |
524 | card->split_timeout_cycles = DEFAULT_SPLIT_TIMEOUT; | |
525 | card->split_timeout_jiffies = | |
526 | DIV_ROUND_UP(DEFAULT_SPLIT_TIMEOUT * HZ, 8000); | |
3038e353 | 527 | card->color = 0; |
e534fe16 | 528 | card->broadcast_channel = BROADCAST_CHANNEL_INITIAL; |
3038e353 | 529 | |
459f7923 SR |
530 | kref_init(&card->kref); |
531 | init_completion(&card->done); | |
5e20c282 | 532 | INIT_LIST_HEAD(&card->transaction_list); |
bf54e146 | 533 | INIT_LIST_HEAD(&card->phy_receiver_list); |
3038e353 | 534 | spin_lock_init(&card->lock); |
3038e353 KH |
535 | |
536 | card->local_node = NULL; | |
537 | ||
02d37bed SR |
538 | INIT_DELAYED_WORK(&card->br_work, br_work); |
539 | INIT_DELAYED_WORK(&card->bm_work, bm_work); | |
3038e353 KH |
540 | } |
541 | EXPORT_SYMBOL(fw_card_initialize); | |
542 | ||
53dca511 SR |
543 | int fw_card_add(struct fw_card *card, |
544 | u32 max_receive, u32 link_speed, u64 guid) | |
3038e353 | 545 | { |
e1eff7a3 | 546 | int ret; |
3038e353 KH |
547 | |
548 | card->max_receive = max_receive; | |
549 | card->link_speed = link_speed; | |
550 | card->guid = guid; | |
551 | ||
6a5033be | 552 | mutex_lock(&card_mutex); |
3038e353 | 553 | |
e300839d SR |
554 | generate_config_rom(card, tmp_config_rom); |
555 | ret = card->driver->enable(card, tmp_config_rom, config_rom_length); | |
b171e204 SR |
556 | if (ret == 0) |
557 | list_add_tail(&card->link, &card_list); | |
558 | ||
559 | mutex_unlock(&card_mutex); | |
e1eff7a3 SR |
560 | |
561 | return ret; | |
3038e353 KH |
562 | } |
563 | EXPORT_SYMBOL(fw_card_add); | |
564 | ||
c781c06d | 565 | /* |
d645f4da SR |
566 | * The next few functions implement a dummy driver that is used once a card |
567 | * driver shuts down an fw_card. This allows the driver to cleanly unload, | |
568 | * as all IO to the card will be handled (and failed) by the dummy driver | |
569 | * instead of calling into the module. Only functions for iso context | |
570 | * shutdown still need to be provided by the card driver. | |
20802224 SR |
571 | * |
572 | * .read/write_csr() should never be called anymore after the dummy driver | |
573 | * was bound since they are only used within request handler context. | |
574 | * .set_config_rom() is never called since the card is taken out of card_list | |
575 | * before switching to the dummy driver. | |
c781c06d | 576 | */ |
3038e353 | 577 | |
02d37bed | 578 | static int dummy_read_phy_reg(struct fw_card *card, int address) |
3038e353 | 579 | { |
02d37bed | 580 | return -ENODEV; |
3038e353 KH |
581 | } |
582 | ||
53dca511 SR |
583 | static int dummy_update_phy_reg(struct fw_card *card, int address, |
584 | int clear_bits, int set_bits) | |
3038e353 KH |
585 | { |
586 | return -ENODEV; | |
587 | } | |
588 | ||
53dca511 | 589 | static void dummy_send_request(struct fw_card *card, struct fw_packet *packet) |
3038e353 | 590 | { |
18d0cdfd | 591 | packet->callback(packet, card, RCODE_CANCELLED); |
3038e353 KH |
592 | } |
593 | ||
53dca511 | 594 | static void dummy_send_response(struct fw_card *card, struct fw_packet *packet) |
3038e353 | 595 | { |
18d0cdfd | 596 | packet->callback(packet, card, RCODE_CANCELLED); |
3038e353 KH |
597 | } |
598 | ||
53dca511 | 599 | static int dummy_cancel_packet(struct fw_card *card, struct fw_packet *packet) |
730c32f5 KH |
600 | { |
601 | return -ENOENT; | |
602 | } | |
603 | ||
53dca511 SR |
604 | static int dummy_enable_phys_dma(struct fw_card *card, |
605 | int node_id, int generation) | |
3038e353 KH |
606 | { |
607 | return -ENODEV; | |
608 | } | |
609 | ||
20802224 SR |
610 | static struct fw_iso_context *dummy_allocate_iso_context(struct fw_card *card, |
611 | int type, int channel, size_t header_size) | |
612 | { | |
613 | return ERR_PTR(-ENODEV); | |
614 | } | |
615 | ||
616 | static int dummy_start_iso(struct fw_iso_context *ctx, | |
617 | s32 cycle, u32 sync, u32 tags) | |
618 | { | |
619 | return -ENODEV; | |
620 | } | |
621 | ||
622 | static int dummy_set_iso_channels(struct fw_iso_context *ctx, u64 *channels) | |
623 | { | |
624 | return -ENODEV; | |
625 | } | |
626 | ||
627 | static int dummy_queue_iso(struct fw_iso_context *ctx, struct fw_iso_packet *p, | |
628 | struct fw_iso_buffer *buffer, unsigned long payload) | |
629 | { | |
630 | return -ENODEV; | |
631 | } | |
632 | ||
13882a82 CL |
633 | static void dummy_flush_queue_iso(struct fw_iso_context *ctx) |
634 | { | |
635 | } | |
636 | ||
d645f4da | 637 | static const struct fw_card_driver dummy_driver_template = { |
20802224 SR |
638 | .read_phy_reg = dummy_read_phy_reg, |
639 | .update_phy_reg = dummy_update_phy_reg, | |
640 | .send_request = dummy_send_request, | |
641 | .send_response = dummy_send_response, | |
642 | .cancel_packet = dummy_cancel_packet, | |
643 | .enable_phys_dma = dummy_enable_phys_dma, | |
644 | .allocate_iso_context = dummy_allocate_iso_context, | |
645 | .start_iso = dummy_start_iso, | |
646 | .set_iso_channels = dummy_set_iso_channels, | |
647 | .queue_iso = dummy_queue_iso, | |
13882a82 | 648 | .flush_queue_iso = dummy_flush_queue_iso, |
3038e353 KH |
649 | }; |
650 | ||
53dca511 | 651 | void fw_card_release(struct kref *kref) |
459f7923 SR |
652 | { |
653 | struct fw_card *card = container_of(kref, struct fw_card, kref); | |
654 | ||
655 | complete(&card->done); | |
656 | } | |
657 | ||
53dca511 | 658 | void fw_core_remove_card(struct fw_card *card) |
3038e353 | 659 | { |
d645f4da SR |
660 | struct fw_card_driver dummy_driver = dummy_driver_template; |
661 | ||
ecab4133 MB |
662 | card->driver->update_phy_reg(card, 4, |
663 | PHY_LINK_ACTIVE | PHY_CONTENDER, 0); | |
02d37bed | 664 | fw_schedule_bus_reset(card, false, true); |
3038e353 | 665 | |
6a5033be | 666 | mutex_lock(&card_mutex); |
e747a5c0 | 667 | list_del_init(&card->link); |
6a5033be | 668 | mutex_unlock(&card_mutex); |
3038e353 | 669 | |
d645f4da SR |
670 | /* Switch off most of the card driver interface. */ |
671 | dummy_driver.free_iso_context = card->driver->free_iso_context; | |
672 | dummy_driver.stop_iso = card->driver->stop_iso; | |
3038e353 KH |
673 | card->driver = &dummy_driver; |
674 | ||
3038e353 | 675 | fw_destroy_nodes(card); |
459f7923 SR |
676 | |
677 | /* Wait for all users, especially device workqueue jobs, to finish. */ | |
678 | fw_card_put(card); | |
679 | wait_for_completion(&card->done); | |
8a2d9ed3 | 680 | |
1e8afea1 | 681 | WARN_ON(!list_empty(&card->transaction_list)); |
3038e353 KH |
682 | } |
683 | EXPORT_SYMBOL(fw_core_remove_card); |